ON NVD5490NL Single nâ channel power mosfet Datasheet

NVD5490NL
Power MOSFET
60 V, 64 mW, 17 A, Single N−Channel
Features
•
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
High Current Capability
Avalanche Energy Specified
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
RDS(on)
V(BR)DSS
ID
64 mW @ 10 V
60 V
17 A
85 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain Current RqJC (Notes 1 & 3)
Power Dissipation RqJC
(Note 1)
Continuous Drain Current RqJA (Notes 1, 2 &
3)
Power Dissipation RqJA
(Notes 1 & 2)
Pulsed Drain Current
TC = 25°C
Steady
State
Symbol
Value
Unit
VDSS
60
V
VGS
"20
V
ID
17
A
TC = 100°C
TC = 25°C
Steady
State
ID
A
5.0
PD
1.7
IDM
71
A
TA = 25°C
IDmaxpkg
30
A
TJ, Tstg
−55 to
175
°C
IS
41
A
EAS
41
mJ
TL
260
°C
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 30 V, VGS = 10 V,
IL(pk) = 9.0 A, L = 1.0 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
1 2
W
3.4
TA = 25°C, tp = 10 ms
Operating Junction and Storage Temperature
4
3.0
TA = 100°C
Current Limited by
Package (Note 3)
S (3)
W
49
24
TA = 100°C
TA = 25°C
N−Channel
G (1)
12
PD
TC = 100°C
TA = 25°C
D (2,4)
DPAK
CASE 369AA
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENT
4
Drain
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
2
1 Drain 3
Gate Source
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction−to−Case − Steady State (Drain)
RqJC
3.1
°C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
44
1. The entire application environment impacts the thermal resistance values
shown, they are not constants and are only valid for the particular conditions
noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2012
November, 2012 − Rev. 1
1
3
YWW
54
90NLG
Parameter
Y
WW
5490L
G
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
NVD5490NL/D
NVD5490NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
V(BR)DSS
VGS = 0 V, ID = 250 mA
60
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
VGS = 0 V,
VDS = 60 V
V
TJ = 25°C
1.0
TJ = 125°C
10
mA
IGSS
VDS = 0 V, VGS = "20 V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250 mA
2.5
V
Drain−to−Source On Resistance
RDS(on)
VGS = 10 V, ID = 9 A
46
64
mW
VGS = 4.5 V, ID = 9 A
66
85
VDS = 15 V, ID = 20 A
15
S
365
pF
"100
nA
ON CHARACTERISTICS (Note 4)
Forward Transconductance
gFS
1.5
CHARGES, CAPACITANCES & GATE RESISTANCE
Ciss
Input Capacitance
Output Capacitance
Coss
Reverse Transfer Capacitance
Total Gate Charge
Crss
QG(TOT)
Threshold Gate Charge
VDS = 48 V,
ID = 9 A
91
46
VGS = 4.5 V
7.8
VGS = 10 V
14
QG(TH)
nC
0.4
nC
1.5
nC
5.4
nC
RG
7
W
td(on)
9.4
ns
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Gate Resistance
VGS = 0 V, f = 1.0 MHz,
VDS = 25 V
VDS = 48 V, ID = 9 A
VGS = 10 V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(off)
VDS = 48 V, VGS = 4.5 V,
ID = 9 A, RG = 10 W
57
24
tf
35
td(on)
6.7
tr
17
td(off)
VDS = 48 V, VGS = 10 V,
ID = 9 A, RG = 10 W
tf
ns
34
34
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
trr
Charge Time
ta
Discharge Time
tb
Reverse Recovery Stored Charge
VGS = 0 V,
IS = 9 A
TJ = 25°C
0.97
TJ = 125°C
0.87
25
IS = 20.5 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms
QRR
http://onsemi.com
2
V
ns
20
5.0
27
4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
5. Switching characteristics are independent of operating junction temperatures.
1.2
nC
NVD5490NL
TYPICAL CHARACTERISTICS
VDS ≥ 5 V
VGS = 4.5 V
VGS = 10 V
20
VGS = 4.0 V
15
VGS = 3.6 V
10
5
VGS = 3.0 V
0
1
2
3
4
5
20
15
10
TJ = 25°C
5
TJ = 100°C
2
TJ = −55°C
3
4
5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.13
0.12
ID = 17 A
TJ = 25°C
0.11
0.10
0.09
0.08
0.07
0.06
0.05
0.04
25
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
30
VGS = 7.5 V
ID, DRAIN CURRENT (A)
25
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (Normalized)
TJ = 25°C
4
5
6
7
8
9
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
0.10
TJ = 25°C
0.09
VGS = 4.5 V
0.08
0.07
0.06
VGS = 10 V
0.05
0.04
5
10
15
20
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100,000
2.5
VGS = 0 V
ID = 9 A
VGS = 10 V
TJ = 175°C
10,000
2.0
IDSS, LEAKAGE (nA)
ID, DRAIN CURRENT (A)
30
1000
1.5
1.0
0.5
−50 −25
0
25
50
75
100
125
150
TJ = 125°C
100
10
175
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
http://onsemi.com
3
60
NVD5490NL
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
10
C, CAPACITANCE (pF)
VGS = 0 V
TJ = 25°C
600
Ciss
400
Coss
200
Crss
0
0
10
20
30
40
8
6
4
0
5
10
15
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
IS, SOURCE CURRENT (A)
30
tr
tf
td(off)
td(on)
1
10
VGS = 0 V
TJ = 25°C
25
20
15
10
5
0
100
0
0.5
1.0
1.5
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
VGS = 10 V
Single Pulse
TC = 25°C
1 mS
100 mS
EAS, SINGLE PULSE DRAIN−TO−
SOURCE AVALANCHE ENERGY (mJ)
t, TIME (ns)
ID, DRAIN CURRENT (A)
0
Figure 7. Capacitance Variation
10
10 mS
10 mS
dc
1
0.1
RDS(on) Limit
Thermal Limit
Package Limit
0.01
0.001
VDS = 48 V
ID = 9 A
TJ = 25°C
Qg, TOTAL GATE CHARGE (nC)
100
10
Qgd
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VDD = 48 V
ID = 9 A
VGS = 4.5 V
100
Qgs
2
1000
1
QT
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
800
0.1
1
10
100
25
ID = 17 A
20
15
10
5
0
25
50
75
100
125
150
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
http://onsemi.com
4
175
NVD5490NL
TYPICAL CHARACTERISTICS
10
R(t) (°C/W)
50% Duty Cycle
1 20%
10%
5%
2%
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
ORDERING INFORMATION
Order Number
NVD5490NLT4G
Package
Shipping†
DPAK
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
5
NVD5490NL
PACKAGE DIMENSIONS
DPAK
CASE 369AA
ISSUE B
A
E
b3
c2
B
Z
D
1
L4
A
4
L3
b2
e
2
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
H
DETAIL A
3
c
b
0.005 (0.13)
M
H
C
L2
GAUGE
PLANE
C
L
SEATING
PLANE
A1
L1
DETAIL A
ROTATED 905 CW
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
6.17
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
6
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NVD5490NL/D
Similar pages