CAT28F001 Licensed Intel second source 1 Megabit CMOS Boot Block Flash Memory FEATURES ■ Deep Powerdown Mode ■ Fast Read Access Time: 70/90/120/150 ns ■ On-Chip Address and Data Latches ■ Blocked Architecture ■ ■ ■ ■ ■ ■ ■ ■ — One 8 KB Boot Block w/ Lock Out • Top or Bottom Locations — Two 4 KB Parameter Blocks — One 112 KB Main Block Low Power CMOS Operation 12.0V ± 5% Programming and Erase Voltage Automated Program & Erase Algorithms High Speed Programming Commercial, Industrial and Automotive Temperature Ranges ■ ■ — 0.05 µA ICC Typical — 0.8 µA IPP Typical Hardware Data Protection Electronic Signature 100,000 Program/Erase Cycles and 10 Year Data Retention JEDEC Standard Pinouts: — 32 pin DIP — 32 pin PLCC — 32 pin TSOP Reset/Deep Power Down Mode DESCRIPTION The CAT28F001 is a high speed 128K X 8 bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after sale code updates. The CAT28F001 is designed with a signature mode which allows the user to identify the IC manufacturer and device type. The CAT28F001 is also designed with onChip Address Latches, Data Latches, Programming and Erase Algorithms. The CAT28F001 has a blocked architecture with one 8 KB Boot Block, two 4 KB Parameter Blocks and one 112 KB Main Block. The Boot Block section can be at the top or bottom of the memory map and includes a reprogramming write lock out feature to guarantee data integrity. It is designed to contain secure code which will bring up the system minimally and download code to other locations of CAT28F001. The CAT28F001 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 32-pin plastic DIP, PLCC or TSOP packages. BLOCK DIAGRAM I/O0–I/O7 ADDRESS COUNTER I/O BUFFERS WRITE STATE MACHINE ERASE VOLTAGE SWITCH STATUS REGISTER RP WE PROGRAM VOLTAGE SWITCH CE, OE LOGIC DATA LATCH SENSE AMP COMPARATOR COMMAND REGISTER A0–A16 VOLTAGE VERIFY SWITCH ADDRESS LATCH CE OE Y-GATING Y-DECODER X-DECODER 8K-BYTE BOOT BLOCK 4K-BYTE PARAMETER BLOCK 4K-BYTE PARAMETER BLOCK 112K-BYTE MAIN BLOCK 28F001 F01 © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. 25071-00 2/98 F-1 1 CAT28F001 PIN CONFIGURATION PLCC Package (N) 1 2 3 32 31 30 VCC WE RP A12 A7 A6 4 29 5 6 7 28 27 26 A14 A13 A8 A9 8 25 9 10 11 24 23 22 A0 I/O0 I/O1 I/O2 12 21 13 14 15 20 19 18 I/O7 I/O6 I/O5 I/O4 VSS 16 17 I/O3 A11 OE A10 CE 5 6 7 29 28 27 A4 A3 8 26 9 10 25 24 A2 A1 A0 I/O0 A14 A13 A8 A9 A11 OE 23 A10 22 F02CE 28F001 11 12 13 21 14 15 16 17 18 19 20 I/O1 I/O2 VSS I/O3 A5 A4 A3 A2 A1 4 3 2 1 32 31 30 A7 A6 A5 I/O7 I/O4 I/O5 I/O6 VPP A16 A15 A12 A15 A16 VPP VCC WE RP DIP Package (P) TSOP Package (Standard Pinout) (T) A11 A9 A8 A13 A14 RP WE VCC VPP A16 A15 A12 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 PIN FUNCTIONS Pin Name Type Function A0–A16 Input Address Inputs for memory addressing I/O0–I/O7 I/O Data Input/Output CE Input Chip Enable OE Input Output Enable WE Input Write Enable VCC Voltage Supply VSS Ground VPP Program/Erase Voltage Supply RP Input Doc. No. 25071-00 2/98 F-1 28F001 F03 Power Down 2 CAT28F001 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................... –55°C to +95°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(1) ........... –2.0V to +VCC + 2.0V (Except A9, RP, OE, VCC and VPP) Voltage on Pin A9, RP AND OE with Respect to Ground(1) ................... –2.0V to +13.5V VPP with Respect to Ground during Program/Erase(1) .............. –2.0V to +14.0V VCC with Respect to Ground(1) ............ –2.0V to +7.0V Package Power Dissipation Capability (TA = 25°C) .................................. 1.0 W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND (3) Parameter Endurance Min. Max. Units Test Method 100K Cycles/Byte MIL-STD-883, Test Method 1033 10 Years MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 TDR(3) Data Retention VZAP(3) ESD Susceptibility 2000 Volts ILTH(3)(4) Latch-Up 100 mA JEDEC Standard 17 CAPACITANCE TA = 25°C, f = 1.0 MHz Limits Symbol CIN(3) COUT (3) CVPP(3) Test Min Max. Units Conditions Input Pin Capacitance 8 pF VIN = 0V Output Pin Capacitance 12 pF VOUT = 0V VPP Supply Capacitance 25 pF VPP = 0V Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. 3 Doc. No. 25071-00 2/98 F-1 CAT28F001 D.C. OPERATING CHARACTERISTICS VCC = +5V ±10%, unless otherwise specified Limits Symbol Parameter Min. Max. Unit Test Conditions ILI Input Leakage Current ±1.0 µA VIN = VCC or VSS VCC = 5.5V ILO Output Leakage Current ±10 µA VOUT = VCC or VSS, VCC = 5.5V ISB1 VCC Standby Current CMOS 100 µA CE = VCC ±0.2V = RP VCC = 5.5V ISB2 VCC Standby Current TTL 1.5 mA CE = RP = VIH, VCC = 5.5V IPPD VPP Deep Powerdown Current 1.0 µA RP = GND±0.2V ICC1 VCC Active Read Current 30 mA VCC = 5.5V, CE = VIL, IOUT = 0mA, f = 8 MHz ICC2(1) VCC Programming Current 20 mA VCC = 5.5V, Programming in Progress ICC3(1) VCC Erase Current 20 mA VCC = 5.5V, Erase in Progress IPPS VPP Standby Current ±10 200 µA µA VPP < VCC VPP > VCC IPP1 VPP Read Current 200 µA VPP = VPPH IPP2(1) VPP Programming Current 30 mA VPP = VPPH, Programming in Progress IPP3(1) VPP Erase Current 30 mA VPP = VPPH, Erase in Progress VIL Input Low Level 0.8 V VOL Output Low Level 0.45 V VIH Input High Level 2.0 VCC+0.5 V VOH Output High Level 2.4 VID A9 Signature Voltage 11.5 IID –0.5 IOL = 5.8mA, VCC = 4.5V V IOH = 2.5mA, VCC = 4.5V 13.0 V A9 = VID A9 Signature Current 500 µA A9 = VID ICCD VCC Deep Powerdown Current 1.0 µA RP = GND±0.2V ICCES VCC Erase Suspend Current 10 mA Erase Suspended CE = VIH IPPES VPP Erase Suspend Current 300 µA Erase Suspended VPP=VPPH Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. 25071-00 2/98 F-1 4 CAT28F001 SUPPLY CHARACTERISTICS Limits Symbol Parameter Min Max. Unit VLKO VCC Erase/Write Lock Voltage 2.5 V VCC VCC Supply Voltage 4.5 5.5 V VPPL VPP During Read Operations 0 6.5 V VPPH VPP During Erase/Program 11.4 12.6 V VHH RP, OE Unlock Voltage 11.4 12.6 V A.C. CHARACTERISTICS, Read Operation VCC = +5V ±10%, unless otherwise specified JEDEC Symbol 28F001-70(8) 28F001-90(7) Standard Symbol Parameter Min. Max. Min. Max. 28F001-15(7) Min. Min. Max. Unit tRC Read Cycle Time tELQV tCE CE Access Time 70 90 120 150 ns tAVQV tACC Address Access Time 70 90 120 150 ns tGLQV tOE OE Access Time 27 35 50 55 ns - tOH Output Hold from Address OE/CE Change 0 0 0 0 ns tGLQX tOLZ(1)(6) OE to Output in Low-Z 0 0 0 0 ns tELQX tLZ(1)(6) CE to Output in Low-Z 0 0 0 0 ns tGHQZ tDF(1)(2) OE High to Output High-Z 30 30 30 30 ns tEHQZ tHZ(1)(2) CE High to Output High-Z 55 35 55 55 ns tPHQV tPWH RP High to Output Delay 600 600 600 600 ns 70 Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5) INPUT PULSE LEVELS 0.8 V REFERENCE POINTS 1.5 V 0.0 V 5108 FHD F03 Testing Load Circuit (example) Testing Load Circuit (example) 1.3V 5108 FHD F03A 1.3V 1N914 1N914 3.3K DEVICE UNDER TEST ns 3.0 V REFERENCE POINTS 0.45 V 150 Figure 2. Highspeed A.C. Testing Input/Output Waveform(3)(4)(5) 2.0 V INPUT PULSE LEVELS 120 Max. tAVAV 2.4 V 90 28F001-12(7) 3.3K DEVICE UNDER TEST OUT CL = 100 pF CL INCLUDES JIG CAPACITANCE OUT CL = 30 pF CL INCLUDES JIG CAPACITANCE 5108 FHD F05 5108 FHD F04 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer. (3) Input Rise and Fall Times (10% to 90%) < 10 ns. (4) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V. (5) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V. (6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid. (7) For load and reference points, see Fig. 1 (8) For load and reference points, see Fig. 2 5 Doc. No. 25071-00 2/98 F-1 CAT28F001 A.C. CHARACTERISTICS, Program/Erase Operation VCC = +5V ±10% JEDEC Standard Symbol Symbol 28F001-70 Parameter Min. Max. 28F001-90 Min. Max. 28F001-12 Min. Max. 28F001-15 Min. Max. Unit tAVAV tWC Write Cycle Time 70 90 120 150 ns tAVWH tAS Address Setup to WE Going High 35 40 40 40 ns tWHAX tAH Address Hold Time from WE Going High 10 10 10 10 ns tDVWH tDS Data Setup Time to WE Going High 35 40 40 40 ns tWHDX tDH Data Hold Time from WE Going High 10 10 10 10 ns tELWL tCS CE Setup Time to WE Going Low 0 0 0 0 ns tWHEH tCH CE Hold Time from WE Going High 0 0 0 0 ns tWLWH tWP WE Pulse Width 35 40 40 40 ns tWHWL tWPH WE High Pulse Width 10 10 10 10 ns tWHGL — Write Recovery Time Before Read 0 0 0 0 µs tPHWL tPS(1) RP High Recovery to WE Going Low 480 480 480 480 ns tPHHWH tPHS(1) RP VHH Setup to WE Going High 100 100 100 100 ns tVPWH tVPS(1) VPP Setup to WE Going High 100 100 100 100 ns tWHQV1 — Duration of Programming Operations 15 15 15 15 µs tWHQV2 — Duration of Erase Operations (Boot) 1.3 1.3 1.3 1.3 Sec tWHQV3 — Duration of Erase Operations (Parameter) 1.3 1.3 1.3 1.3 Sec tWHQV4 — Duration of Erase Operations (Main) 3 3 3 3 Sec tQVVL tVPH(1) VPP Hold from Valid Status Reg Data 0 0 0 0 ns tQVPH tPHH(1) RP VHH Hold from Status Reg Data 0 0 0 0 ns tPHBR(1) — Boot Block Relock Delay tGHHWL — OE VHH Setup to WE Going Low 480 480 480 480 ns tWHGH — OE VHH Hold from WE High 480 480 480 480 ns 100 100 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. 25071-00 2/98 F-1 6 100 100 ns CAT28F001 ERASE AND PROGRAMMING PERFORMANCE 28F001-70 Parameter Min. 28F001-90 Typ. Max. Boot Block Erase Time 2.10 Boot Block Program Time 28F001-12 Max. 14.9 2.10 0.15 0.52 0.15 Parameter Block Erase Time 2.10 14.6 2.10 14.6 2.10 14.6 2.10 14.6 Sec Parameter Block Program Time 0.07 0.26 0.07 0.26 0.07 0.26 0.07 0.26 Sec Main Block Erase Time 3.80 20.9 3.80 20.9 3.80 20.9 3.80 20.9 Sec Main Block Program Time 2.10 7.34 2.10 7.34 2.10 7.34 2.10 7.34 Sec 10.10 65 10.10 65 10.10 65 10.10 65 Sec 2.39 8.38 2.39 8.38 2.39 8.38 2.39 8.38 Sec Notes Chip Program Time Min. 28F001-15 Typ. Chip Erase Time Min. Typ. Max. 14.9 2.10 0.52 0.15 Min. Typ. Max. Unit 14.9 2.10 14.9 Sec 0.52 0.15 0.52 Sec FUNCTION TABLE(1) Pins Mode RP CE OE WE VPP I/O Read VIH VIL VIL VIH X DOUT Output Disable VIH VIL VIH VIH X High-Z Standby VIH VIH X X X High-Z Signature (MFG) VIH VIL VIL VIH X 31H A0 = VIL, A9 = 12V Signature (Device) VIH VIL VIL VIH X 94H-28F001T 95H-28F001B A0 = VIH, A9 = 12V Write Cycle VIH VIL VIH VIL X DIN During Write Cycle Deep Power Down VIL X X X X HIGH-Z WRITE COMMAND TABLE Commands are written into the command register in one or two write cycles. Write cycles also internally latch addresses and data required for programming and erase operations. Mode First Bus Cycle Operation Address DIN Operation Second Bus Cycle Address DIN DOUT Read Array/Reset Write X FFH Program Setup/ Program Write AIN 40H 10H Write AIN Read Status Reg. Write X 70H Read X Clear Status Reg. Write X 50H Erase Setup/Erase Confirm Write Block ad 20H Write Block ad D0H Erase Suspend/ Erase Resume Write X B0H Write X D0H Read Sig (Mfg) Write X 90H Read 0000H 31H Read Sig (Dev) Write X 90H Read 0001H 94H-28F001T 95H-28F001B DIN St. Reg. Data Note: (1) Logic Levels: X = Logic ‘Do not care’ (VIH, VIL, VPPL, VPPH) 7 Doc. No. 25071-00 2/98 F-1 CAT28F001 READ OPERATIONS Read Mode applying the required high voltage on address pin A9 while the other address line are held at VIL. The CAT28F001 memory can be read from any of its Blocks (Boot Block, Main Block or Parameter Block), Status Register and Signature Information by sending the Read Command Mode to the Command Register. A Read cycle from address 0000H retrieves the binary code for the IC manufacturer on outputs I/O7 to I/O0: CAT28F001 automatically resets to Read Array mode upon initial device power up or after exit from deep power down. A Read operation is performed with both CE and OE low and with RP and OE high. Vpp can be either high or low. The data retrieved from the I/O pins reflects the contents of the memory location corresponding to the state of the 17 address pins. The respective timing waveforms for the read operation are shown in Figure 3. Refer to the AC Read characteristics for specific timing parameters. Catalyst Code = 0011 0001 (31H) A Read cycle from address 0001H retrieves the binary code for the device on outputs I/O7 to I/O0: CAT28F001T = 1001 0100 (94H) CAT28F001B = 1001 0101 (95H) Standby Mode With CE at a logic-high level, the CAT28F001 is placed in a standby mode where most of the device circuitry is disabled, thereby substantially reducing power consumption. The outputs are placed in a high-impendance state independent of the OE status. Signature Mode The signature mode allows the user to identify the IC manufacturer and the type of the device while the device resides in the target system. This mode can be activated in either of two ways; through the conventional method of applying a high voltage (12V) to address pin A9 or by sending an instruction to the command register (see Write Operations). Deep Power-Down When RP is at logic-low level, the CAT28F001 is placed in a Deep Power-Down mode where all the device circuitry are disabled, thereby reducing the power consumption to 0.25µW. The conventional method is entered as a regular read mode by driving the CE and OE low (with WE high), and Figure 3. A.C. Timing for Read Operation POWER UP STANDBY DEVICE AND ADDRESS SELECTION ADDRESSES OUPUTS ENABLED DATA VALID STANDBY POWER DOWN ADDRESS STABLE tAVAV (tRC) CE (E) tEHQZ OE (G) tGHQZ (tDF) tGLQV (tOE) WE (W) tELQV (tCE) tOH tGLQX (tOLZ) tELQX (tLZ) HIGH-Z HIGH-Z DATA (I/O) OUTPUT VALID tAVQV (tACC) tPHQV (tPWH) RP (P) 28F001 F05 Doc. No. 25071-00 2/98 F-1 8 CAT28F001 block erasure. During the first write cycle, a Command 20H (Erase Setup) is first written to the Command Register, followed by the Command D0H (Erase Confirm). These commands require both appropriate command data and an address within Block to be erased. Also, Block erasure can only occur when VPP= VPPH. WRITE OPERATIONS The following operations are initiated by observing the sequence specified in the Write Command Table. Read Array The device can be put into a Read Array Mode by initiating a write cycle with FFH on the data bus. The device is also in a standard Read Array Mode after the initial device power up and when comes out of the Deep Power-Down mode. Block preconditioning, erase and verify are all handled internally by the Write State Machine, invisible to the system. After receiving the two command erase sequence the CAT28F001 automatically outputs Status Register data when read (Fig.5). The CPU can detect the completion of the erase event by checking if the SR.7 of the Status Register is set. Signature Mode An alternative method for reading device signature (see Read Operations Signature Mode), is initiated by writing the code 90H into the command register. A read cycle from address 0000H with CE and OE low (and WE high) will output the device signature. SR.5 will indicate whether the erase was successful. If an erase error is detected, the Status Register should be cleared. The device will be in the Status Register Read Mode until another command is issued. Catalyst Code = Catalyst Code = 0011 0001 (31H) ERASE SUSPEND/ERASE RESUME The Erase Suspend Command allows erase sequence interruption in order to read data from another block of memory. Once the erase sequence is started, writing the Erase Suspend command (B0H) to the Command Register requests that the WSM suspend the erase sequence at a predetermined point in the erase algorithm. The CAT28F001 continues to output Status Register data when read, after the Erase Suspend command is written to it. Polling the WSM Status and Erase Suspend Status bits will determine when the erase operation has been suspended (both will be set to “1s”). A Read cycle from address 0001H retrieves the binary code for the device on outputs I/O7 to I/O0: CAT28F001T = 1001 0100 (94H) CAT28F001B = 1001 0101 (95H) To terminate the operations, it is necessary to write another valid command into the register. STATUS REGISTER The device may now be given a Read ARRAY Command, which allows any locations 'not within the block being erased' to be read. Also, you can either perform a Read Status Register or resume the Erase Operation by sending Erase Resume (D0H), at which time the WSM will continue with the erase sequence. The Erase Suspend Status and WSM Status bits of the Status Register will be cleared. The 28F001 contains an 8-bit Status Register. The Status Register is polled to check for write or erase completion or any related errors. The Status Register may be read at any time by issuing a Read Status Register (70H) command. All subsequent read operations output data from the Status Register, until another valid command is issued. The contents of the Status Register are latched on the falling edge of OE or CE , whichever occurs last in the read cycle. OE or CE must be toggled to VIH before further reads to update the status register latch. PROGRAM SETUP/PROGRAM COMMANDS Programming is executed by a two-write sequence. The program Setup command (40H) is written to the Command Register, followed by a second write specifying the address and data (latched on the rising edge of WE) to be programmed. The WSM then takes over, controlling the program and verify algorithms internally. After the two-command program sequence is written to it, the CAT28F001 automatically outputs Status Register data when read (see figure 4; Byte Program Flowchart). The CPU can detect the completion of the program event by analyzing the WSM Status bit of the Status Register. Only the Read Status Register Command is valid while programming is active. The Erase Status (SR.5) and Program Status (SR.4) are set to 1 by the WSM and can only be reset issuing Clear Status Register (50H) These two bits can be polled for failures, thus allowing more flexibility to the designer when using the CAT28F001. Also, VPP Status (SR.3) when set to 1 must be reset by system software before any further byte programs or block erases are attempted. ERASE SETUP/ERASE CONFIRM Erase is executed one block at a time, initiated by a two cycle command sequence. The two cycle command sequence provides added security against accidental 9 Doc. No. 25071-00 2/98 F-1 CAT28F001 WSMS ESS ES PS VPPS R R R 7 6 5 4 3 2 1 0 SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Erase Suspended 0 = Erase in Progress/Completed SR.5 = ERASE STATUS 1 = Error in Block Erasure 0 = Successful Block Erase SR.4 = PROGRAM STATUS 1 = Error in Byte Program 0 = Successful Byte Program SR.3 = VPP STATUS 1 = VPP Low Detect; Operation Abort 0 = VPP Okay SR.2 -SR.0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use and should be masked out when polling the Status Register. NOTES: The Write State Machine Status Bit must first be checked to determine program or erase completion, before the Program or Erase Status bits are checked for success. If the Program AND Erase Status bits are set to “1s” during an erase attempt, an improper command sequence was entered. Attempt the operation again. If VPP low status is detected, the Status Register must be cleared before another program or erase operation is attempted. The VPP Status bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates the VPP level only after the program or erase command sequences have been entered and informs the system if VPP has not been switched on. The VPP Status bit is not guaranteed to report accurate feedback between VPPL and VPPH. When the Status Register indicates that programming is complete, the Program Status bit should be checked. If program error is detected, the Status Register should be cleared. The internal WSM verify only detects errors for “1s” that do not successfully program to “0s”. The Command Register remains in Read Status Register mode until further commands are issued to it. bits will be set to “1”. When issuing the Erase Setup and Erase Confirm commands, they should be written to an address within the address range of the block to be erased. Figure 5 shows a system software flowchart for block erase. The entire sequence is performed with VPP at VPPH. Abort occurs when RP transitions to VIL, or VPP drops to VPPL. Although the WSM is halted, byte data is partially programmed or Block data is partially erased at the location where it was aborted. Block erasure or a repeat of byte programming will initialize this data to a known value. If erase/byte program is attempted while VPP = VPPL, the Status bit (SR.5/SR.4) will be set to “1”. Erase/Program attempts while VPPL < VPP < VPPH produce spurious results and should not be attempted. EMBEDDED ALGORITHMS The CAT28F001 integrates the Quick Pulse programming algorithm on-chip, using the Command Register, Status Register and Write State Machine (WSM). Onchip integration dramatically simplifies system software and provides processor-like interface timings to the Command and Status Registers. WSM operation, internal program verify, and VPP high voltage presence are monitored and reported via appropriate Status Register bits. Figure 4 shows a system software flowchart for device programming. BOOT BLOCK PROGRAM AND ERASE The boot block is intended to contain secure code which will minimally bring up a system and control programming and erase of other blocks of the device, if needed. Therefore, additional “lockout” protection is provided to guarantee data integrity. Boot block program and erase operations are enabled through high voltage VHH on either RP or OE, and the normal program and erase command sequences are used. Reference the AC Waveforms for Program/Erase. As above, the Quick Erase algorithm is now implemented internally, including all preconditioning of block data. WSM operation, erase verify and VPP high voltage presence are monitored and reported through the Status Register. Additionally, if a command other than Erase Confirm is written to the device after Erase Setup has been written, both the Erase Status and Program Status Doc. No. 25071-00 2/98 F-1 If boot block program or erase is attempted while RP is at VIH, either the Program Status or Erase Status bit will be set to “1”, reflective of the operation being attempted and indicating boot block lock. Program/erase attempts while VIH < RP < VHH produce spurious results and should not be attempted. 10 CAT28F001 IN-SYSTEM OPERATION For on-board programming, the RP pin is the most convenient means of altering the boot block. Before issuing Program or Erase confirms commands, RP must transition to VHH. Hold RP at this high voltage throughout the program or erase interval (until after Status Register confirm of successful completion). At this time, it can return to VIH or VIL. Figure 4 Byte Programming Flowchart START Bus Operation Command Comments WRITE 40H, BYTE ADDRESS Write Program Setup Data = 40H Address = Bytes to be Programmed WRITE BYTE ADDRESS/DATA Write Program Data to be programmed Address = Byte to be Programmed READ STATUS REGISTER Read Status Register Data. Toggle OE or CE to update Status Register Check SR.7 Standby 1 = Ready, 0 = Busy NO SR.7 = 1? Repeat for subsequent bytes. YES FULL STATUS CHECK IF DESIRED Full Status check can be done after each byte or after a sequence of bytes. Write FFH after the last byte programming operation to reset the device to Read Array Mode. BYTE PROGRAM COMPLETED FULL STATUS CHECK PROCEDURE STATUS REGISTER DATA READ (SEE ABOVE) Bus Operation SR.3 = 0? Command Comments NO VPP RANGE ERROR Standby Check SR.3 1 = VPP Low Detect NO BYTE PROGRAM ERROR Standby Check SR.3 1 = Byte Program Error YES SR.4 = 0? YES BYTE PROGRAM SUCCESSFUL SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. SR.3 is only cleared by the Clear Status Register Command, in case where multiple bytes are programmed before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. 11 Doc. No. 25071-00 2/98 F-1 CAT28F001 Figure 5 Block Erase Flowchart START Bus Operation Command Comments WRITE 20H, BLOCK ADDRESS Write Erase Setup Data = 20H Address = Within Block to be erased WRITE D0H BLOCK ADDRESS Write Erase Data - D0H Address = Within Block to be erased READ STATUS REGISTER Read Status Register Data. Toggle OE or CE to update Status Register Standby Check SR.7 1 = Ready, 0 = Busy ERASE SUSPEND LOOP NO SR.7 = 1? NO SUSPEND ERASE? YES YES Repeat for subsequent blocks. FULL STATUS CHECK IF DESIRED Full Status check can be done after each block or after a sequence of blocks. Write FFH after the last block erase operation to reset the device to Read Array Mode. BLOCK ERASE COMPLETED FULL STATUS CHECK PROCEDURE STATUS REGISTER DATA READ (SEE ABOVE) SR.3 = 0? NO Bus Operation VPP RANGE ERROR Command Comments Standby Check SR.3 1 = VPP Low Detect Standby Check SR.4 Both 1 = Command Sequence Error Standby Check SR.5 1 = Block Erase Error YES SR.4,5 = 1? YES COMMAND SEQUENCE ERROR NO SR.5 = 0? BLOCK ERASE SUCCESSFUL NO BLOCK ERASE ERROR SR.3 MUST be cleared, if set during a erase attempt, before further attempts are allowed by the Write State Machine. SR.3 is only cleared by the Clear Status Register Command, in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Doc. No. 25071-00 2/98 F-1 12 CAT28F001 Figure 6 Block Erase Suspend/Resume Flowchart START Bus Operation Command Comments Write Data = B0H WRITE B0H READ STATUS REGISTER SR.7 = 1? Erase Suspend Standby/ Ready Read Status Register Check SR.7 1 = Ready, 0 = Busy Toggle OE or CE to Update Status Register Standby Check SR.6 1 = Suspended NO YES SR.6 = 1? NO ERASE HAS COMPLETED YES Write Read Array Data = FFH WRITE FFH Read DONE READING? Read array data from block other than that being erased. NO YES Write Erase Resume Data = D0H WRITE D0H CONTINUE ERASE 13 Doc. No. 25071-00 2/98 F-1 CAT28F001 Figure 7. A.C. Timing for Program/Erase Operation VCC POWER-UP & STANDBY WRITE WRITE PROGRAM OR VALID ADDRESS & DATA (PROGRAM) AUTOMATED PROGRAM ERASE SETUP COMMAND OR ERASE DELAY OR ERASE CONFIRM COMMAND READ STATUS REGISTER DATA WRITE READ ARRAY COMMAND VIH ADDRESSES (A) AIN VIL AIN tAVWH tAVAV tWHAX VIH CE (E) VIL tELWL tWHEH tWHGL VIH OE (G) VIL tWHQV 1, 2, 3, 4 tWHWL VIH WE (W) VIL VIH tWLWH tWHDX tDVWH HIGH Z DATA (I/O) DIN VIL VHH RP (P) VALID SRD DIN tPHWL tPHHWH DIN tQVPH 6.5V VIH VIL VPPH VPP (V) tVPWH tQVVL VPPL VIH VIL 28F001 F09 POWER UP/DOWN PROTECTION POWER SUPPLY DECOUPLING The CAT28F001 offers protection against inadvertent programming during VPP and VCC power transitions. When powering up the device there is no power-on sequencing necessary. In other words, VPP and VCC may power up in any order. Additionally VPP may be hardwired to VPPH independent of the state of VCC and any power up/down cycling. The internal command register of the CAT28F001 is reset to the Read Mode on power up. To reduce the effect of transient power supply voltage spikes, it is good practice to use a 0.1µF ceramic capacitor between VCC and VSS and VPP and VSS. These high-frequency capacitors should be placed as close as possible to the device for optimum decoupling. Doc. No. 25071-00 2/98 F-1 14 CAT28F001 ALTERNATE CE-CONTROLLED WRITES VCC = +5V ±10%, unless otherwise specified JEDEC Standard Symbol Symbol 28F001-70 Parameter Min. Max. 28F001-90 Min. Max. 28F001-12 Min. Max. 28F001-15 Min. Max. Unit tAVAV tWC Write Cycle Time 70 90 120 150 ns tAVEH tAS Address Setup to CE Going High 35 40 40 40 ns tEHAX tAH Address Hold Time from CE Going High 10 10 10 10 ns tDVEH tDS Data Setup Time to CE Going High 35 40 40 40 ns tEHDX tDH Data Hold Time from CE Going High 10 10 10 10 ns tWLEL tWS WE Setup Time to CE Going Low 0 0 0 0 ns tEHWH tWH WE Hold Time from CE Going High 0 0 0 0 ns tELEH tCP CE Pulse Width 35 40 40 40 ns tEHEL tEPH CE High Pulse Width 10 10 10 10 ns tEHGL — Write Recovery Time Before Read 0 0 0 0 µs tPHEL tPS(1) RP High Recovery to CE Going Low 480 480 480 480 ns tPHHEH tPHS(1) RP VHH Setup to CE Going High 100 100 100 100 ns tVPEH tVPS(1) VPP Setup to CE Going High 100 100 100 100 ns tEHQV1 — Duration of Programming Operations 15 15 15 15 µs tEHQV2 — Duration of Erase Operations (Boot) 1.3 1.3 1.3 1.3 Sec tEHQV3 — Duration of Erase Operations (Parameter) 1.3 1.3 1.3 1.3 Sec tEHQV4 — Duration of Erase Operations (Main) 3 3 3 3 Sec tQVVL tVPH(1) VPP Hold from Valid Status Reg Data 0 0 0 0 ns tQVPH tPHH(1) RP VHH Hold from Status Reg Data 0 0 0 0 ns tPHBR(1) — Boot Block Relock Delay tGHHWL — OE VHH Setup to WE Going Low 480 480 480 480 ns tWHGH — OE VHH Hold from WE High 480 480 480 480 ns 100 100 100 100 ns Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. 15 Doc. No. 25071-00 2/98 F-1 CAT28F001 Figure 8. Alternate Boot Block Access Method Using OE WRITE PROGRAM OR ERASE SETUP COMMAND OE WRITE VALID ADDRESS AND DATA (PROGRAM) OR ERASE CONFIRM COMMAND AUTOMATED PROGRAM OR ERASE DELAY READ STATUS REGISTER DATA VHH VIH VIL tWHGH tGHHWL VIH VIL WE VIH DATA DIN VIL VALID SR DATA DIN Figure 9. Alternate AC Waveform for Write Operations VCC POWER-UP & STANDBY WRITE WRITE PROGRAM OR VALID ADDRESS & DATA (PROGRAM) AUTOMATED PROGRAM ERASE SETUP COMMAND OR ERASE DELAY OR ERASE CONFIRM COMMAND READ STATUS REGISTER DATA WRITE READ ARRAY COMMAND VIH ADDRESSES AIN VIL AIN tAVEH tAVAV tEHAX VIH WE (W) VIL tWLEL tEHWH tEHGL VIH OE (a) VIL tEHQV 1, 2, 3, 4 tEHEL VIH CE (E) VIL VIH tELEH tDVEH tEHDX HIGH Z DATA I/O DIN VIL VHH RP (P) VALID SRD DIN tPHEL tPHHEH tQVPH tVPEH tQVVL 6.5V VIH VIL VPPH VPP (V) VPPL VIH VIL Doc. No. 25071-00 2/98 F-1 16 DIN CAT28F001 ORDERING INFORMATION Prefix CAT Optional Company ID Device # 28F001 Product Number Suffix P -90 I Temperature Range Blank = Commercial (0˚ - 70˚C) I = Industrial (-40˚ - 85˚C) A = Automotive (-40˚ - 105˚C)* Package N: PLCC P: PDIP T: TSOP (8mmx20mm) B Boot Block B: Bottom T: Top T Tape & Reel T: 500/Reel Speed 70: 70ns 90: 90 ns 12: 120 ns 15: 150 ns 28F001 F12 * -40˚ to +125˚C is available upon request Note: (1) The device used in the above example is a CAT28F001PI-90BT (PDIP, Industrial Temperature, 90ns access time, Bottom Boot Block, Tape & Reel) 17 Doc. No. 25071-00 2/98 F-1 CAT28F001 Doc. No. 25071-00 2/98 F-1 18