TI1 OPA322AQDBVRQ1 20-mhz, low-noise, 1.8-v, rri/o, cmos operational amplifier Datasheet

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OPA322-Q1
OPA2322-Q1
OPA4322-Q1
SLOS856B – JUNE 2013 – REVISED MAY 2017
OPAx322-Q1 20-MHz, Low-Noise, 1.8-V, RRI/O,
CMOS Operational Amplifier
1
•
•
1
•
•
•
•
•
•
•
•
•
•
Features
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H3A
– Device CDM ESD Classification Level C5
Gain Bandwidth: 20 MHz
Low Noise: 8.5 nV√Hz at 1 kHz
Slew Rate: 10 V/μs
Low THD+N: 0.0005%
Rail-to-Rail I/O
Offset Voltage: 2 mV (Maximum)
Supply Voltage: 1.8 V to 5.5 V
Supply Current:
– Single-Supply Current: 1.6 mA/ch
– Dual-Supply Current: 1.5 mA/ch
– Quad-Supply Current: 1.4 mA/ch
Unity-Gain Stable
Small Packages:
– SOT-23, VSSOP, TSSOP
The combination of very-low noise (8.5 nV√Hz at 1
kHz), high-gain bandwidth (20 MHz), and fast slew
rate (10 V/μs) make the OPAx322-Q1 family ideal for
a wide range of applications, including signal
conditioning and sensor amplification requiring high
gains. Featuring low THD+N, the OPAx322-Q1 family
is also excellent for consumer audio applications,
particularly for single-supply systems.
The OPA322-Q1 (single version) is available in 5-pin
SOT-23 package, while the OPA2322-Q1 (dual
version) is offered in a 8-pin VSSOP package. The
OPA4322-Q1 (quad version) is available in a 14-pin
TSSOP package. All versions are specified for
operation from –40°C to +125°C.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
OPA322-Q1
SOT-23 (5)
2.90 mm × 1.60 mm
OPA2322-Q1
VSSOP (8)
3.00 mm × 3.00 mm
OPA4322-Q1
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Zero-Crossover Rail-to-Rail Input Stage
Eliminates Distortion
1
0.8
•
•
•
•
•
•
•
•
Applications
Automotive
Sensor Signal Conditioning
Consumer Audio
Multi-Pole Active Filters
Control-Loop Amplifiers
Communications
Security
Scanners
0.6
Offset Voltage (mV)
2
0.4
0.2
0
-0.2
-0.4
-0.6
Representative Units
VS = ±2.75 V
-0.8
-1
-3
-2
-1
0
1
2
3
Common-Mode Voltage (V)
3 Description
The OPAx322-Q1 series consists of single-, dual-,
and quad-channel CMOS operational amplifiers
featuring low noise and rail-to-rail inputs and outputs
optimized for low-power, single-supply applications.
Specified over a wide supply range from 1.8 V to 5.5
V, the low quiescent current of only 1.5 mA per
channel makes these devices well-suited for powersensitive applications.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA322-Q1
OPA2322-Q1
OPA4322-Q1
SLOS856B – JUNE 2013 – REVISED MAY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
7
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
7
7
8
8
8
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information: OPA322-Q1 ............................
Thermal Information: OPA2322-Q1 ..........................
Thermal Information: OPA4322-Q1 ..........................
Electrical Characteristics...........................................
Typical Characteristics........................................ 11
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 16
4
8.4 Device Functional Modes........................................ 20
9
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application .................................................. 22
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example ................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
26
26
26
26
27
27
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 28
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2013) to Revision B
Page
•
Updated data sheet text to the latest documentation and translation standards ................................................................... 1
•
Deleted "x" device marking and "with shutdown" from document title .................................................................................. 1
•
Deleted "Shutdown: 0.1 µA/ch" from Features list ................................................................................................................ 1
•
Deleted SON package from Features list .............................................................................................................................. 1
•
Deleted OPA322S-Q1, OPA2322S-Q1, OPA4322S-Q1 devices from data sheet ................................................................ 1
•
Changed single-supply current from 1.5 mA/ch to 1.6 mA/ch in Features section ................................................................ 1
•
Changed quad-supply current from 1.5 ma/ch to 1.4 ma/ch in Features section ................................................................. 1
•
Deleted "x" device marking, 6-pin SOT-23, 16-pin TSSOP, 10-pin VSSOP, 8-pin SOIC, 8-pin SON packages and
shutdown text from Description section ................................................................................................................................. 1
•
Deleted OPA322S-Q1, OPA2322S-Q1, and OPA4322S-Q1 devices from Device Information table .................................. 1
•
Deleted 8-pin SOIC and 8-pin SON packages from Device Information table ...................................................................... 1
•
Deleted OPA322S-Q1 pinout drawing and pin table information in Pin Configuration and Functions section ..................... 4
•
Deleted OPA2322-Q1 DRG package pinout drawing in Pin Configuration and Functions section........................................ 4
•
Deleted OPA2322S-Q1 pinout drawing and table information in Pin Configuration and Functions section ......................... 4
•
Deleted OPA4322S-Q1 pinout drawing and table information in Pin Configuration and Functions section ......................... 4
•
Updated OPA2322-Q1 pinout tables in Pin Configuration and Functions section ................................................................ 5
•
Updated OPA4322-Q1 pinout table in Pin Configuration and Functions section .................................................................. 6
•
Deleted Operating Temperature, TA values from Absolute Maximum Ratings table.............................................................. 7
•
Added automotive ESD Ratings table to the Specifications section ...................................................................................... 7
•
Added Recommended Operating Conditions table to the Specifications section .................................................................. 7
•
Deleted OPA322S-Q1 Thermal Information table ................................................................................................................. 8
•
Deleted OPA2322S-Q1 D and DRG package Thermal Information values ........................................................................... 8
•
Deleted OPA2322S-Q1 Thermal Information table values .................................................................................................... 8
•
Deleted OPA4322S-Q1 Thermal Information table values .................................................................................................... 8
2
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Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: OPA322-Q1 OPA2322-Q1 OPA4322-Q1
OPA322-Q1
OPA2322-Q1
OPA4322-Q1
www.ti.com
SLOS856B – JUNE 2013 – REVISED MAY 2017
Revision History (continued)
•
Deleted shutdown information from Electrical Characteristics table ..................................................................................... 9
•
Changed typical input voltage noise value from 2.8 to 4.5 µVPP in Electrical Characteristics table ...................................... 9
•
Deleted repeating Open-Loop Gain test conditions in Electrical Characteristics table ......................................................... 9
•
Deleted Figure 26, Figure 27, Figure 28, and Figure 29 from Typical Characteristics section ........................................... 11
•
Updated x-axis of Figure 2 .................................................................................................................................................. 11
•
Updated x-axis of Figure 5 .................................................................................................................................................. 11
•
Added Detailed Description section and Functional Block Diagram .................................................................................... 16
•
Added Feature Description section ..................................................................................................................................... 16
•
Deleted shutdown text in Feature Description section ........................................................................................................ 16
•
Deleted text regarding the unity-gain stability of the OPAx322-Q1 in 1-nF capacitive loads Capacitive Load and
Stability section .................................................................................................................................................................... 18
•
Added Device Functional Modes section ............................................................................................................................ 20
•
Deleted shutdown text in Device Functional Modes section ............................................................................................... 20
•
Changed FilterPro™ link in Application Information section ............................................................................................... 21
•
Updated Figure 35 ............................................................................................................................................................... 22
•
Added Power Supply Recommendations section ............................................................................................................... 23
•
Added Layout section .......................................................................................................................................................... 24
•
Deleted Leadless DFN Package subsection in Layout section ........................................................................................... 24
•
Updated Figure 37 (Layout Example)................................................................................................................................... 24
•
Deleted OPA322S-Q1, OPA2322S-Q1, and OPA4322S-Q1 devices from Related Links table.......................................... 26
Changes from Original (June 2013) to Revision A
•
Page
Changed document status to Production Data ...................................................................................................................... 1
Copyright © 2013–2017, Texas Instruments Incorporated
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3
OPA322-Q1
OPA2322-Q1
OPA4322-Q1
SLOS856B – JUNE 2013 – REVISED MAY 2017
www.ti.com
5 Pin Configuration and Functions
OPA322-Q1 DBV Package
5-Pin SOT-23
Top View
OUT
1
V-
2
+IN
3
5
V+
4
-IN
Pin Functions: OPA322-Q1
PIN
NAME
NO.
–IN
4
+IN
OUT
I/O
DESCRIPTION
I
Inverting input
3
I
Noninverting input
1
O
Output
V–
2
—
Negative (lowest) power supply
V+
5
—
Positive (highest) power supply
4
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Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: OPA322-Q1 OPA2322-Q1 OPA4322-Q1
OPA322-Q1
OPA2322-Q1
OPA4322-Q1
www.ti.com
SLOS856B – JUNE 2013 – REVISED MAY 2017
OPA2322-Q1 DGK Packages
8-Pin VSSOP
Top View
OUT A
-IN A
1
2
+IN A
3
V-
4
A
B
8
V+
7
OUT B
6
-IN B
5
+IN B
Pin Functions: OPA2322-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative (lowest) power supply
V+
8
—
Positive (highest) power supply
Copyright © 2013–2017, Texas Instruments Incorporated
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5
OPA322-Q1
OPA2322-Q1
OPA4322-Q1
SLOS856B – JUNE 2013 – REVISED MAY 2017
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OPA4322-Q1 PW Package
14-Pin TSSOP
Top View
OUT A
1
14 OUT D
A
D
13 -IN D
-IN A
2
+IN A
3
12 +IN D
V+
4
11 V-
+IN B
5
10 +IN C
-IN B
6
OUT B
7
B
C
9
-IN C
8
OUT C
Pin Functions: OPA4322-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
–IN C
9
I
Inverting input, channel C
+IN C
10
I
Noninverting input, channel C
–IN D
13
I
Inverting input, channel D
+IN D
12
I
Noninverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V–
11
—
Negative (lowest) power supply
V+
4
—
Positive (highest) power supply
6
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OPA2322-Q1
OPA4322-Q1
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SLOS856B – JUNE 2013 – REVISED MAY 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage, VS = (V+) – (V–)
Voltage
Signal input pins
Signal input pins (2)
Current
(2)
(3)
UNIT
6
V
(V–) – 0.5
(V+) + 0.5
V
–10
10
mA
150
°C
150
°C
Output short-circuit (3)
Temperature
(1)
(2)
MAX
Continuous
Junction, TJ
Storage, Tstg
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must
be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
Electrostatic discharge
(1)
UNIT
±4000
Charged-device model (CDM), per AEC Q100-011
V
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VS
Specified voltage
1.8
5.5
V
TA
Specified temperature
–40
125
°C
Copyright © 2013–2017, Texas Instruments Incorporated
UNIT
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7
OPA322-Q1
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OPA4322-Q1
SLOS856B – JUNE 2013 – REVISED MAY 2017
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6.4 Thermal Information: OPA322-Q1
OPA322-Q1
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
219.3
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
107.5
°C/W
RθJB
Junction-to-board thermal resistance
57.5
°C/W
ψJT
Junction-to-top characterization parameter
7.4
°C/W
ψJB
Junction-to-board characterization parameter
56.9
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2322-Q1
OPA2322-Q1
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
174.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
43.9
°C/W
RθJB
Junction-to-board thermal resistance
95
°C/W
ψJT
Junction-to-top characterization parameter
2
°C/W
ψJB
Junction-to-board characterization parameter
93.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4322-Q1
OPA4322-Q1
THERMAL METRIC
(1)
PW (TSSOP)
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
109.8
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
34.9
°C/W
RθJB
Junction-to-board thermal resistance
52.5
°C/W
ψJT
Junction-to-top characterization parameter
2.2
°C/W
ψJB
Junction-to-board characterization parameter
51.8
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
—
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
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OPA322-Q1
OPA2322-Q1
OPA4322-Q1
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SLOS856B – JUNE 2013 – REVISED MAY 2017
6.7 Electrical Characteristics
at VS = 1.8 V to 5.5 V, or ±0.9 V to ±2.75 V, TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, VOUT = VS / 2, (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.5
2
mV
1.8
6
μV/°C
TA = 25°C
10
50
TA = –40°C to 125°C
20
65
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
vs temperature
VS = 5.5 V
PSR
vs power supply
VS = 1.8 V to 5.5 V
Channel separation
at 1 kHz
130
μV/V
dB
INPUT VOLTAGE
VCM
Common-mode voltage
range
CMRR
Common-mode rejection
ratio
(V–) – 0.1
(V–) – 0.1 V < VCM < (V+) + 0.1 V
TA = 25°C
90
TA = –40°C to 125°C
90
(V+) + 0.1
100
V
dB
INPUT BIAS CURRENT
TA = 25°C
IB
Input bias current
±0.2
±50
OPA322-Q1:
TA = –40°C to 125°C
±800
OPA2322-Q1:
TA = –40°C to 125°C
±400
OPA4322-Q1:
TA = –40°C to 125°C
±400
pA
TA = 25°C
IOS
Input offset current
±10
TA = –40°C to 85°C
±0.2
±10
TA = –40°C to 85°C
±50
TA = –40°C to 125°C
±400
pA
NOISE
Input voltage noise
en
Input voltage noise density
in
Input current noise density
f = 0.1 Hz to 10 Hz
4.5
f = 1 kHz
8.5
f = 10 kHz
7
f = 1 kHz
0.6
μVPP
nV/√Hz
fA/√Hz
INPUT CAPACITANCE
Differential
5
pF
Common-mode
4
pF
130
dB
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
0.1 V < VO < (V+) – 0.1 V
RL = 10 kΩ
PM
Phase margin
VS = 5 V
CL = 50 pF
47
°
100
FREQUENCY RESPONSE
GBP
Gain bandwidth product
VS = 5 V
CL = 50 pF, unity gain
20
MHz
SR
Slew rate
VS = 5 V
CL = 50 pF, G = 1
10
V/μs
tS
Settling time
Overload recovery time
THD+N
(1)
Total harmonic distortion +
noise (1)
VS = 5 V
CL = 50 pF, to 0.1%, 2-V step, G = 1
0.25
VS = 5 V
CL = 50 pF, to 0.01%, 2-V step, G = 1
0.32
VS = 5 V
CL = 50 pF
VIN × G > VS
100
μs
VS = 5 V
CL = 50 pF
VO = 4 VPP, G = 1, f = 10 kHz
RL = 10 kΩ
0.0005%
VS = 5 V, CL = 50 pF, VO = 2 VPP, G = 1, f = 10 kHz
RL = 600 Ω
0.0011%
ns
Third-order filter; bandwidth = 80 kHz at –3 dB
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Electrical Characteristics (continued)
at VS = 1.8 V to 5.5 V, or ±0.9 V to ±2.75 V, TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, VOUT = VS / 2, (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10
20
UNIT
OUTPUT
VO
Voltage output (swing from
both rails)
RL = 10 kΩ
ISC
Short-circuit current
VS = 5.5 V
CL
Capacitive load drive
RO
Open-loop output resistance
TA = 25°C
TA = –40°C to 125°C
30
±65
mV
mA
See Typical Characteristics
IO = 0 mA
f = 1 MHz
90
Ω
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current per
amplifier
Power-on time
10
1.8
OPA322-Q1:
IO = 0 mA
VS = 5.5 V
TA = 25°C
OPA2322-Q1:
IO = 0 mA
VS = 5.5 V
TA = 25°C
OPA4322-Q1:
IO = 0 mA
VS = 5.5 V
TA = 25°C
1.9
1.5
1.75
TA = –40°C to 125°C
V
2
TA = –40°C to 125°C
1.85
1.4
TA = –40°C to 125°C
mA
1.65
1.75
VS+ = 0 V to 5 V, to 90% IQ level
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5.5
1.6
28
μs
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SLOS856B – JUNE 2013 – REVISED MAY 2017
7 Typical Characteristics
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
-40
120
100
-60
115
80
-80
60
-100
40
-120
20
-140
Gain (dB)
120
Gain
Phase
0
10
110
105
100
95
-160
-20
1
Open-Loop Gain (dB)
125
RL = 10 kW, 50 pF
VS = ±2.5 V
Phase (°)
-20
140
100
1k
10k
100k
1M
10M
90
-180
100M
85
-40
Frequency (Hz)
6
0.8
5
0.4
0.2
0
-0.2
-0.4
-0.6
80
100
120
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2
1
0
-1
-2
-3
IB+
IBIOS
-5
-6
2.9
2.7
3
-4
IBIB+
-0.8
-3 -2.5 -2 -1.5 -1 -0.5 0
Supply Voltage (±V)
1
1.5
IOS
IB+
IB-
0
20
40
60
Temperature (°C)
80
100
Figure 5. Input Bias Current vs Temperature
Copyright © 2013–2017, Texas Instruments Incorporated
2.5
3
1.6
1.55
1.5
1.45
1.4
+125°C
+85°C
1.35
+25°C
-40°C
1.3
-20
2
Figure 4. Input Bias Current
vs Common-Mode Voltage
Quiescent Current (mA/Ch)
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
-100
-40
0.5
Common-Mode Voltage (V)
Figure 3. Input Bias Current vs Supply Voltage
Input Bias Current (pA)
20
40
60
Temperature (°C)
4
0.6
-1
0
Figure 2. Open-Loop Gain vs Temperature
1
Input Bias Current (pA)
Input Bias Current (pA)
Figure 1. Open-Loop Gain and Phase vs Frequency
-20
120
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
Figure 6. Quiescent Current vs Supply Voltage Per Amplifier
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Typical Characteristics (continued)
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
1
14
0.8
0.6
Offset Voltage (mV)
Number of Amplifiers (%)
12
10
8
6
4
0.4
0.2
0
-0.2
-0.4
-0.6
2
Representative Units
VS = ±2.75 V
-0.8
-1
1.5
1.1
1.3
0.9
0.5
0.7
0.1
0.3
-0.1
-0.3
-0.7
-0.5
-1.1
-0.9
-1.3
-1.5
0
-3
-2
3
2
6
VS = 1.8 V to 5.5 V
5
4
3
100
Voltage (mV)
Voltage Noise (nV/ÖHz)
1
Figure 8. Offset Voltage vs Common-Mode Voltage
Figure 7. Offset Voltage Production Histogram
1000
0
-1
Common-Mode Voltage (V)
Offset Voltage (mV)
10
2
1
0
-1
-2
-3
1
-4
10
100
1k
10 k
1M
100 k
0
1
2
3
4
Frequency (Hz)
Figure 9. Input Voltage Noise Spectral Density
vs Frequency
60
20
G = 10 V/V
0
40
8
10
9
VS = 5.5 V
RL = 10 kΩ
CL = 50 pF
G = 100 V/V
20
G = 10 V/V
0
G = 1 V/V
12
7
60
VS = 1.8 V
RL = 10 kΩ
CL = 50 pF
G = 100 V/V
-20
10 k
6
Figure 10. 0.1-Hz to 10-Hz Input Voltage Noise
Gain (dB)
Gain (dB)
40
5
Time (s)
100 k
G = 1 V/V
1M
10 M
100 M
-20
10 k
100 k
1M
10 M
Frequency (Hz)
Frequency (Hz)
Figure 11. Closed-Loop Gain vs Frequency
Figure 12. Closed-Loop Gain vs Frequency
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100 M
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Typical Characteristics (continued)
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
6
3
5.5 VS
2
4
Output Voltage (V)
Output Voltage (VPP)
5
3.3 VS
3
2
1
-40°C
+25°C
+125°C
0
-1
1.8 VS
1
-2
RL = 10 kW
CL = 50 pF
VS = ±2.75 V
0
10 k
-3
100 k
10 M
1M
10
0
20
30
Frequency (Hz)
40
50
Figure 13. Maximum Output Voltage vs Frequency
70
80
Figure 14. Output Voltage Swing vs Output Current
1000
70
G = 1, VS = 1.8 V
VS = ±2.75 V
60
G = 1, VS = 5.5 V
G = 10, VS = 1.8 V
50
Overshoot (%)
Impedance (W)
60
Output Current (mA)
100
G = 10, VS = 5.5 V
40
30
20
10
0
10
1
10
100
1k
10 k
100 k
1M
10 M 100 M
500
0
1000
Frequency (Hz)
0.1
0.01
Load = 600 W
0.001
Frequency = 10 kHz
VS = ±2.5 V
G = +1 V/V
Load = 10 kW
0.1
2000
2500
3000
Figure 16. Small-Signal Overshoot
vs Load Capacitance
Total Harmonic Distortion and Noise (%)
Total Harmonic Distortion and Noise (%)
Figure 15. Open-Loop Output Impedance
vs Frequency
0.0001
0.01
1500
Capacitive Load (pF)
1
10
0.1
Frequency = 10 kHz
VIN = 2 VPP
VS = ±2.5 V
G = +1 V/V
0.01
Load = 600 W
0.001
Load = 10 kW
0.0001
10
100
1k
Figure 17. THD+N vs Amplitude
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10 k
100 k
Frequency (Hz)
VIN (VPP)
Figure 18. THD+N vs Frequency
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Typical Characteristics (continued)
0
0.1
Frequency = 10 kHz
VIN = 4 VPP
VS = ±2.5 V
G = 1 V/V
VS = ±2.75 V
-20
Channel Separation (dB)
Total Harmonic Distortion and Noise (%)
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
0.01
Load = 600 W
0.001
-60
-80
-100
-120
Load = 10 kW
0.0001
-40
-140
10
100
1k
1k
100 k
10 k
10 k
100 k
1M
10 M
100 M
Frequency (Hz)
Frequency (Hz)
Figure 19. THD+N vs Frequency
Figure 20. Channel Separation
vs Frequency (Dual-Channel)
12
0.1
CL = 50 pF
Gain = 1
VS = ±2.75 V
VIN = 100 mVPP
0.075
11.5
Voltage (V)
Slew Rate (V/ms)
0.05
11
Rise
10.5
Fall
10
0.025
0
-0.025
-0.05
9.5
VOUT
VIN
-0.075
9
-0.1
1.6
2
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2
5.6
-0.8
-0.4
0
0.4
Supply Voltage (V)
1.5
0.075
VIN
Gain = -1
VS = ±2.75 V
VIN = 100 mVPP
Voltage (V)
Voltage (V)
Gain = 1
VS = ±2.75 V
VIN = 2 VPP
1
0.05
0
1.6
1.2
Figure 22. Small-Signal Step Response
Figure 21. Slew Rate vs Supply Voltage
0.1
0.025
0.8
Time (ms)
-0.025
0.5
VOUT
0
-0.5
-0.05
-0.1
-1.6
-1
VOUT
VIN
-0.075
-1.5
-1.2
-0.8
-0.4
0
0.4
0.8
-0.4
0
Time (ms)
Figure 23. Small-Signal Step Response
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0.4
0.8
1.2
1.6
Time (ms)
Figure 24. Large-Signal Step Response vs Time
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Typical Characteristics (continued)
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
Common-Mode Rejection Ratio,
Power-Supply Rejection Ratio (dB)
120
100
80
60
40
20
PSRR
CMRR
0
100
1k
10k
100k
1M
Frequency (Hz)
Figure 25. CMRR and PSRR vs Frequency
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8 Detailed Description
8.1 Overview
The OPAx322-Q1 family of operational amplifiers (op amps) are high-speed precision amplifiers well-suited to
drive 12-, 14-, and 16-bit analog-to-digital converters. Low-output impedance with flat frequency characteristics
and zero-crossover distortion circuitry enable high linearity over the full input common-mode range, achieving
true rail-to-rail input from a 1.8-V to 5.5-V single-supply.
8.2 Functional Block Diagram
V+
Low Noise Charge
Pump
Bias Circuitry
+IN
-IN
OUT
Input Stage Load
Bias Circuitry
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8.3 Feature Description
8.3.1 Operating Voltage
The OPAx322-Q1 series op amps are unity-gain stable and can operate on a single-supply voltage (1.8 V to 5.5
V), or a split-supply voltage (±0.9 V to ±2.75 V), which makes the op amps highly versatile and easy to use. The
power-supply pins must have local bypass ceramic capacitors (typically 0.001 μF to 0.1 μF). These amplifiers are
fully specified from 1.8 V to 5.5 V and over the extended temperature range from –40°C to +125°C. Parameters
that can exhibit variance with regard to operating voltage or temperature are presented in Typical Characteristics.
8.3.2 Input and ESD Protection
The OPAx322-Q1 incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of
input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit input overdrive protection, as long as
the current is limited to 10 mA as stated in Absolute Maximum Ratings. Many input signals are inherently currentlimited to less than 10 mA; therefore, a limiting resistor is not required. Figure 26 shows how a series input
resistor (RS) may be added to the driven input to limit the input current. The added resistor contributes thermal
noise at the amplifier input and the value must be kept to the minimum in noise-sensitive applications.
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Feature Description (continued)
V+
IOVERLOAD
10 mA, maximum
VOUT
OPA322-Q1
VIN
RS
Copyright © 2016, Texas Instruments Incorporated
Figure 26. Input Current Protection
8.3.3 Phase Reversal
The OPAx322-Q1 family of op amps are designed to be immune to phase reversal when the input pins exceed
the supply voltages, which provides further in-system stability and predictability. Figure 27 shows the input
voltage exceeding the supply voltage without any phase reversal.
4
VIN
VS = ±2.5 V
3
Voltage (V)
2
VOUT
1
0
-1
-2
-3
-4
-500
-250
0
250
500
750
1000
Time (ms)
Figure 27. No Phase Reversal
8.3.4 Feedback Capacitor Improves Response
For optimum settling time and stability with high-impedance feedback networks, it may be necessary to add a
feedback capacitor across the feedback resistor (RF), as shown in Figure 28. This capacitor compensates for the
zero created by the feedback network impedance and the OPAx322-Q1 input capacitance (and any parasitic
layout capacitance). The effect becomes more significant with higher impedance networks.
CF
RIN
RF
VIN
V+
CIN
RIN ´ CIN = RF ´ CF
OPA322-Q1
VOUT
CL
CIN
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NOTE: Where CIN is equal to the OPAx322-Q1 input capacitance (approximately 9 pF) plus any parasitic layout capacitance.
Figure 28. Feedback Capacitor Improves Dynamic Performance
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Feature Description (continued)
For the circuit shown in Figure 28, the value of the variable feedback capacitor must be selected so that the input
resistance times the input capacitance of the OPAx322-Q1 (typically 9 pF) plus the estimated parasitic layout
capacitance equals the feedback capacitor times the feedback resistor with Equation 1.
RIN × CIN = RF × CF
where
•
CIN is equal to the OPAx322-Q1 input capacitance (sum of differential and common-mode) plus the layout
capacitance
(1)
The capacitor value can be adjusted until optimum performance is obtained.
8.3.5 EMI Susceptibility and Input Filtering
Operational amplifiers vary in susceptibility to electromagnetic interference (EMI). If conducted EMI enters the
device, the DC offset observed at the amplifier output may shift from the nominal value while EMI is present. This
shift is a result of signal rectification associated with the internal semiconductor junctions. While all operational
amplifier pin functions can be affected by EMI, the input pins are likely to be the most susceptible. The OPAx322Q1 operational amplifier family incorporates an internal input low-pass filter that reduces the amplifier response
to EMI. Both common-mode and differential mode filtering are provided by the input filter. The filter is designed
for a cutoff frequency of approximately 580 MHz (–3 dB), with a roll-off of 20 dB per decade.
8.3.6 Output Impedance
The open-loop output impedance of the OPAx322-Q1 common-source output stage is approximately 90 Ω. When
the op amp is connected with feedback, the loop gain significantly reduces this value. For each decade rise in
the closed-loop gain, the loop gain is reduced by the same amount, which results in a tenfold increase in
effective output impedance. While the OPAx322-Q1 output impedance remains flat over a wide frequency range.
At higher frequencies the output impedance rises as the open-loop gain of the op amp drops. However, at these
frequencies the output becomes capacitive as a result of parasitic capacitance. This characteristic prevents the
output impedance from becoming too high, which can cause stability problems when driving large capacitive
loads. As mentioned previously, the OPAx322-Q1 has excellent capacitive load drive capability for an op amp
with a bandwidth of this value.
8.3.7 Capacitive Load and Stability
The OPAx322-Q1 is designed to be used in applications where driving a capacitive load is required. As with all
op amps, there may be specific instances where the OPAx322-Q1 can become unstable. The particular op amp
circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing
whether an amplifier is stable in operation. An op amp in the unity-gain (1-V/V) buffer configuration and driving a
capacitive load exhibits a greater tendency to become unstable than an amplifier operating at a higher noise
gain. The capacitive load, in conjunction with the op amp output resistance, creates a pole within the feedback
loop that degrades the phase margin.
The equivalent series resistance (ESR) of some very large capacitors (CL > 1 µF) is sufficient to alter the phase
characteristics in the feedback loop so the amplifier remains stable. Increasing the amplifier closed-loop gain
allows the amplifier to drive increasingly larger capacitance. This increased capability is evident when observing
the overshoot response of the amplifier at higher voltage gains, as shown in Figure 29. One technique for
increasing the capacitive load drive capability of the amplifier operating in unity gain is to insert a small resistor
(RS, typically 10-Ω to 20-Ω) in series with the output, as shown in Figure 30.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. A possible
problem with this technique is that a voltage divider is created with the added series resistor and any resistor
connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output that
reduces the output swing. However, the error contributed by the voltage divider may be insignificant. For
example, with a load resistance of RL = 10 kΩ and RS = 20 Ω, the gain error is approximately 0.2%. When RL
decreases to 600 Ω (which the OPAx322-Q1 is able to drive), the error increases to 7.5%.
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Feature Description (continued)
70
G = 1, VS = 1.8 V
60
G = 1, VS = 5.5 V
G = 10, VS = 1.8 V
Overshoot (%)
50
G = 10, VS = 5.5 V
40
30
20
10
0
0
500
1000
1500
2000
3000
2500
Capacitive Load (pF)
Figure 29. Small-Signal Overshoot vs Capacitive Load (100-mVPP Output Step)
V+
RS
VOUT
OPA322-Q1
VIN
10 W to
20 W
RL
CL
Copyright © 2016, Texas Instruments Incorporated
Figure 30. Improving Capacitive Load Drive
8.3.8 Overload Recovery Time
Overload recovery time is the time required for the output of the amplifier to come out of saturation and recover
to the linear region. Overload recovery is particularly important in applications where small signals must be
amplified in the presence of large transients. Figure 31 and Figure 32 show the positive and negative overload
recovery times of the OPAx322-Q1, respectively. In both cases, the time elapsed before the OPAx322-Q1 comes
out of saturation is less than 100 ns. The symmetry between the positive and negative recovery times allows
excellent signal rectification without distortion of the output signal.
spacer
3
2.5
Output
0.5
Input
2
0
1.5
-0.5
Voltage (V)
Voltage (V)
1
VS = ±2.75 V
G = -10
1
0.5
0
-1
-1.5
-2
Input
Output
-0.5
VS = ±2.75 V
G = -10
-2.5
-1
9.75
10
10.25
10.5
10.75
11
-3
9.75
10
10.25
Time (250 ns/div)
Figure 31. Positive Recovery Time
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10.5
10.75
11
Time (250 ns/div)
Figure 32. Negative Recovery Time
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8.4 Device Functional Modes
The OPAx322-Q1 family of operational amplifiers are operational when power-supply voltages between 1.8 V to
5.5 V are applied.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPAx322-Q1 family offers outstanding DC and AC performance. These devices operate up to a 5.5-V power
supply and offer ultra-low input bias current and 20-MHz bandwidth. These features make the OPAx322-Q1
family a robust operational amplifier for both battery-powered and industrial applications.
9.1.1 Active Filter
The OPAx322-Q1 is well-suited for active filter applications that require a wide bandwidth, fast slew rate, lownoise, single-supply operational amplifier. Figure 33 shows a 500-kHz, second-order, low-pass filter using the
multiple-feedback (MFB) topology. The components are selected to provide a maximally flat Butterworth
response. Beyond the cutoff frequency, roll-off is –40 dB/dec. The Butterworth response is ideal for applications
that require predictable gain characteristics, such as the anti-aliasing filter used in front of an ADC.
One point to observe when considering the MFB filter is that the output is inverted relative to the input. If this
inversion is not required (or not desired) a noninverting output can be achieved through one of these options:
1. Adding an inverting amplifier
2. Adding an additional second-order MFB stage
3. Using a noninverting filter topology, such as the Sallen-Key (shown in Figure 34).
MFB, Sallen-Key, low-pass, and high-pass filter synthesis is quickly accomplished using TI’s FilterPro™ program.
This software is available as a free download at www.ti.com.
R3
549 W
C2
150 pF
R1
549 W
R2
1.24 kW
V+
VIN
C1
1 nF
OPA322-Q1
VOUT
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Figure 33. Second-Order, Butterworth, 500-kHz Low-Pass Filter
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Application Information (continued)
220 pF
V+
1.8 kW
19.5 kW
150 kW
VIN = 1 VRMS
47 pF OPA322-Q1
3.3 nF
VOUT
VCopyright © 2016, Texas Instruments Incorporated
Figure 34. OPAx322-Q1 Configured as a Three-Pole, 20-kHz, Sallen-Key Filter
9.2 Typical Application
2.25 k
2.25 k
1 nF
1.13 k
Input
±
Output
OPA322-Q1
4 nF
+
Copyright © 2017, Texas Instruments Incorporated
Figure 35. Second-Order, Low-Pass Filter Schematic
9.2.1 Design Requirements
•
Gain = 1 V/V
•
•
Low-pass cutoff frequency = 50 kHz
–40-db/dec filter response
•
Maintain less than 3-dB gain peaking in the gain versus frequency response
9.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Equation 2. Use Equation 2
to calculate the voltage transfer function.
1 R1R3C2C5
Output
s
2
Input
s
s C2 1 R1 1 R3 1 R4 1 R3R4C2C5
(2)
This circuit produces a signal inversion. For this circuit, the gain at DC and the low-pass cutoff frequency are
calculated by Equation 3.
R4
Gain
R1
fC
1
2S
1 R3R 4 C2C5
(3)
®
Software tools are readily available to simplify filter design. WEBENCH Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH® Filter Designer allows the user to create
optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor
partners.
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Typical Application (continued)
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows the
user to design, optimize, and simulate complete multistage active filter solutions within minutes.
9.2.3 Application Curve
20
Gain (db)
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 36. OPAx322-Q1 Second-Order, 50-kHz, Low-Pass Filter
10 Power Supply Recommendations
The OPAx322-Q1 family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications
apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in Typical Characteristics.
CAUTION
Supply voltages larger than 6 V can permanently damage the device; see the Absolute
Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see Layout.
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11 Layout
11.1 Layout Guidelines
The OPAx322-Q1 is a wideband amplifier. To realize the full operational performance of the device, follow good
high-frequency printed-circuit board (PCB) layout practices. The bypass capacitors must be connected between
each supply pin and ground as close as possible to the device. The bypass capacitor traces must be designed
for minimum inductance.
11.2 Layout Example
GND
Use a low-ESR,
ceramic bypass
capacitor.
VS+
VOUT
VS±
V+
OUT
V±
Use a low-ESR,
ceramic bypass
capacitor.
GND
VIN
RG
+IN
Run the input traces
as far away from
the supply lines
as possible.
GND
±IN
RF
Place components
close to the device
and to each other to
reduce parasitic
errors.
Copyright © 2017, Texas Instruments Incorporated
Figure 37. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
12.1.2.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a
range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
12.1.2.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount devices. The
evaluation tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT23-6, SOT23-5
and SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used with
terminal strips or may be wired directly to existing circuits.
12.1.2.3 Universal Operational Amplifier EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of device package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, VSSOP, TSSOP and SOT-23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own devices. TI recommends
requesting several op amp device samples when ordering the Universal Op Amp EVM.
12.1.2.4 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
12.1.2.5 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The
WEBENCH® Filter Designer allows the user to create optimized filter designs using a selection of TI operational
amplifiers and passive components from TI's vendor partners.
Copyright © 2013–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: OPA322-Q1 OPA2322-Q1 OPA4322-Q1
25
OPA322-Q1
OPA2322-Q1
OPA4322-Q1
SLOS856B – JUNE 2013 – REVISED MAY 2017
www.ti.com
Device Support (continued)
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows the
user to design, optimize, and simulate complete multistage active filter solutions within minutes.
12.2 Documentation Support
12.2.1 Related Documentation
The following documents are relevant to using the OPAx322x-Q1 family, and recommended for reference. All are
available for download at www.ti.com unless otherwise noted.
• QFN/SON PCB Attachment(SLVA271)
• Quad Flatpack No-Lead Logic Packages (SCBA017)
• OPA322, OPA2322, OPA4322 EMIR Immunity Performance (SBOT005)
• FilterPro™ User's Guide (SBFA001)
• AFE for Transient Recorder and Digital Fault Recorder Using High-Speed ADCs and Differential Amplifiers
(TIDUAT7)
• Reference Design for Interfacing Current Output Hall Sensors and CTs With Differential ADCs/MCUs
(TIDUA57A)
• Single-Ended Signal Conditioning Circuit for Current and Voltage Measurement Using Fluxgate Sensors
(TIDU585)
• Differential Signal Conditioning Circuit for Current and Voltage Measurement Using Fluxgate Sensors
(TIDU569)
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA322-Q1
Click here
Click here
Click here
Click here
Click here
OPA2322-Q1
Click here
Click here
Click here
Click here
Click here
OPA4322-Q1
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
26
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: OPA322-Q1 OPA2322-Q1 OPA4322-Q1
OPA322-Q1
OPA2322-Q1
OPA4322-Q1
www.ti.com
SLOS856B – JUNE 2013 – REVISED MAY 2017
12.6 Trademarks
FilterPro, TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
is a trademark of ~ Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2013–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: OPA322-Q1 OPA2322-Q1 OPA4322-Q1
27
OPA322-Q1
OPA2322-Q1
OPA4322-Q1
SLOS856B – JUNE 2013 – REVISED MAY 2017
www.ti.com
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: OPA322-Q1 OPA2322-Q1 OPA4322-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
3-May-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2322AQDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OVDQ
OPA322AQDBVRQ1
PREVIEW
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
19AD
OPA4322AQPWQ1
PREVIEW
TSSOP
PW
14
90
TBD
Call TI
Call TI
-40 to 125
OPA4322AQPWRQ1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
4322AQ1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-May-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA2322-Q1, OPA4322-Q1 :
• Catalog: OPA2322, OPA4322
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-May-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
OPA2322AQDGKRQ1
VSSOP
DGK
OPA322AQDBVRQ1
SOT-23
OPA4322AQPWRQ1
TSSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
8
2500
330.0
DBV
5
3000
PW
14
2000
B0
(mm)
K0
(mm)
P1
(mm)
12.4
5.3
3.4
1.4
8.0
178.0
9.0
3.3
3.2
1.4
330.0
12.4
6.9
5.6
1.6
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
12.0
Q1
4.0
8.0
Q3
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-May-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2322AQDGKRQ1
VSSOP
DGK
8
2500
366.0
364.0
50.0
OPA322AQDBVRQ1
SOT-23
DBV
5
3000
180.0
180.0
18.0
OPA4322AQPWRQ1
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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