ESDAXLC4-1BF3 Single line extra low capacitance TVS Features ■ Stand-off voltage 3 V ■ Ultra low capacitance 0.3 pF on a wide frequency spectrum, 200 to 3000 MHz ■ Bidirectional device ■ Low clamping factor VCL/VBR ■ Fast response time ■ Very thin package: 0.36 mm max ■ Low leakage current Flip Chip (2 bumps) Complies with the following standards ■ Figure 1. Schematic diagram (top view) IEC 61000-4-2 level 4 Applications Where transient over voltage protection and electrical overstress protection in sensitive equipment is required, such as: ■ Computers ■ Printers ■ Communication systems ■ Cellular phone handsets and accessories ■ Video equipment Portable equipment Description The ESDAXLC4-1BF3 is a single line Transil™ diode designed specifically for the protection of integrated circuits into portable equipment and miniaturized electronics devices subject to ESD and EOS transient over voltages. Packaged in WLCSP, it minimizes PCB consumption. TM: Transil is a trademark of STMicroelectronics May 2011 Doc ID 018522 Rev 2 1/10 www.st.com 10 Characteristics ESDAXLC4-1BF3 1 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Value Unit VPP Peak pulse voltage: IEC61000-4-2 contact discharge PPP Peak pulse power dissipation (8/20 µs) (1) Tj initial = Tamb 55 W IPP Repetitive peak pulse current (8/20 µs) Tj initial = Tamb 3 A Tj Junction temperature - 55 to +125 °C Storage temperature range - 65 to +150 °C 260 °C Tstg Maximum lead temperature for soldering during 10 s TL kV 8 1. For a surge greater than the maximum values, the diode will fail in short-circuit Figure 2. Electrical characteristics (definitions) Symbol VRM VBR VCL IRM Cline Table 2. Parameter Stand-off voltage Breakdown voltage Clamping voltage Leakage current @ VRM Line capacitance Electrical characteristics (values, Tamb = 25 °C) Symbol Test condition Min. Typ. Max. Unit VBR IR = 1 mA 4 5.5 - V IRM VRM = 3 V - - 50 nA VCL IPP (8/20 µs) = 1 A - - 10 V Cline F = [200 MHz -3000] MHz, VR = 0 V DC, Vosc = 30 m VRMS - 0.3 0.4 pF 2/10 Doc ID 018522 Rev 2 ESDAXLC4-1BF3 Figure 3. 1200 Characteristics Junction capacitance versus reverse applied voltage (typical values) Figure 4. C(pF) 400 F=1 Mhz Vosc = 30 mVRMS Vr = 0V Tj = 25 °C 1000 Junction capacitance versus frequencies (typical values) C(pF) F = 20 MHz –3 GHz Vosc = 30 mVRMS Vr = 0 V Tj = 25 °C 300 800 200 600 400 100 200 VR(V) 0 0 Figure 5. 1 2 3 4 F(MHz) 0 0 5 500 S21 attenuation measurement result Figure 6. 100 1000 1500 2000 2500 3000 Variation of leakage current versus junction temperature (typical values) IR(nA) VR = VRM = 3 V 1 Tj(°C) 0 25 Figure 7. ESD response to IEC61000-4-2 (+8 kV contact discharge) Figure 8. 50 V/div 50 75 100 125 150 ESD response to IEC61000-4-2 (-8 kV contact discharge) 50 V/div C2 C2 20 ns/div Doc ID 018522 Rev 2 20 ns/div 3/10 Ordering information scheme ESDAXLC4-1BF3 2 Ordering information scheme Figure 9. Ordering information scheme ESDA ESD array Extra low capacitance Breakdown voltage 14V2 = 14.2 Volt min. Number of lines 1 = 1 line Type B = Bi-directional Package F = Flip Chip x = 3: lead-free, pitch = 400 µm, bump height = 255 µm 4/10 Doc ID 018522 Rev 2 XLC 4 - 1 B F3 ESDAXLC4-1BF3 Package information ● Epoxy meets UL94,V0 ● Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 10. Package dimensions 0.69 mm ±30 µm 0.36 mm ±45 µm 0.37 mm ±15 µm 0.40 mm ±40 µm 0.50 mm ±30 µm 3 Package information Figure 11. Marking X Doc ID 018522 Rev 2 5/10 PCB recommendations ESDAXLC4-1BF3 Figure 12. Flip Chip tape and reel specification Ø 1.55 ± 0.05 4.0 ± 0.1 1.75 ± 0.1 2.0 ± 0.05 3.5 ±- 0.05 0.75 ± 0.05 8.0 ± 0.3 0.20 ± 0.05 0.57 ± 0.05 0.43 ± 0.1 All dimensions in mm 2.0 ± 0.1 User direction of unreeling 4 PCB recommendations 4.1 Design For optimum electrical performance and highly reliable solder joints, STMicroelectronics recommends the PCB design recommendations listed in Table 3. Table 3. PCB design recommendations for solder bar pitch 400 µm For NSMD PCB non solder mask defined Note: 6/10 Oblong pad: 370 x 180 µm – Micro via SSBU allowed – Micro via SBU to be avoided – Micro via SBU filled (under qualification) Track: – Only one track per pad – Maximum track width = 100 µm Track layout must be symmetrical to the die axis (to homogenize stress and welding attraction during reflow assembly) For SMD PCB solder mask defined Oblong pad: – Micro via SSBU allowed – Micro via SBU to be avoided – Micro via SBU filled (under qualification) PCB Pad Finishing Cu – Ni (2-6 µm) - Au (0.2 µm max) A gold layer finishing on the PCB pad that is too thick (0.2 µm maximum) is not recommended (low joint reliability). Doc ID 018522 Rev 2 ESDAXLC4-1BF3 PCB recommendations To optimize the natural self centering effect of CSP on the PCB, PCB pad positioning and size have to be properly designed (see Figure 13) Micro vias An alternative to routing on the top surface is to route out on buried layers. To achieve this, the pads are connected to the lower layers using micro vias. Only SSBU via technology is approved. Figure 13. Solder mask opening 450 µm 370 µm 370 µm 180 µm 255 µm 180 µm 100 µm Non solder mask defined Doc ID 018522 Rev 2 Solder mask defined 7/10 PCB recommendations 4.2 ESDAXLC4-1BF3 Assembly For chip scale package mounting on the PCB, STMicroelectronics recommends the use of a solder stencil aperture of 330 x 330 µm² maximum and a typical stencil thickness of 75 or 80 µm. Chip scale packages are fully compatible with the use of near eutectic 95.5 Sn, 4 Ag, 0.5 Cu solder paste with no-clean flux. ST's recommendations for chip scale package board mounting are illustrated on the soldering reflow profile shown in Figure 14. Figure 14. ST ECOPACK® recommended soldering reflow profile for PCB mounting Temperature (°C) 260°C max 255°C 220°C 180°C 125 °C 2°C/s recommended 2°C/s recommended 6°C/s max 6°C/s max 3°C/s max 3°C/s max 0 0 1 2 3 4 5 10-30 sec 90 to 150 sec 6 7 Time (min) 90 sec max Dwell time in the soldering zone (with temperature higher than 220 °C) has to be kept as short as possible to prevent component and substrate damages. Peak temperature must not exceed 260 °C. Controlled atmosphere (N2 or N2H2) is recommended during the whole reflow, especially above 150 °C. Chip scale packages are able to withstand three times the previous recommended reflow profile in order to be compatible with a double reflow when SMDs are mounted on both sides of the PCB and one additional repair. A maximum of three soldering reflows are allowed for these lead-free packages (with repair step included). The use of a no-clean flux is highly recommended to avoid any cleaning operation. To prevent any bump cracks, ultrasonic cleaning methods are not recommended. 8/10 Doc ID 018522 Rev 2 ESDAXLC4-1BF3 5 Ordering information Table 4. 6 Ordering information Ordering information Order code Marking Package Weight Base qty Delivery mode ESDAXLC4-1BF3 L Flip Chip 0.37 mg 15 000 Tape and reel 7” Revision history Table 5. Document revision history Date Revision Changes 03-Mar-2011 1 Initial release. 12-May-2011 2 Updated features, Table 1, Figure 9 and Figure 11. Doc ID 018522 Rev 2 9/10 ESDAXLC4-1BF3 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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