FEDL610Q793-02 Issue Date: Jan. 26, 2015 ML610Q793 8-bit Microcontroller for Sensor Control ■ General Description The ML610Q793 is a high-performance 8-bit low power microcontroller optimized for sensor hub, that integrates LAPIS Semiconductor’s original high-performance 8-bit CPU core with a 16-bit multiplier/divider co-processor, 64 KByte flash memory, 4 KByte RAM, multiple interfaces for various sensors and host interfaces with 8KByte logging RAM in small footprint package. The ML610Q793 is an ideal sensor hub microcontroller for smart phone to separate various sensors off from its application processor and control them effectively for reducing total system power consumption. ■ Features ● CPU —8-bit RISC CPU (CPU name: uX-U8/100) —16-bit length instruction system —Minimum instruction execution time 30.5 us (32.768 kHz system clock) 0.25 us (4.096 MHz system clock) —Built-in coprocessor for multiplication, division, and multiply-accumulate operations Multiplication (Input: 16-bit x 16-bit, Output: 32-bit) Division (Input: 32-bit/16-bit, Output: 32-bit) Multiply-accumulate (Input: 16-bit x 16-bit + 32-bit, Output: 32-bit) ● Internal memory —64KByte Flash ROM (32KWord x 16-bit) —4KByte SRAM (4KWord x 8-bit) ● Interrupt controller —Non-maskable interrupt: 1 source —Maskable interrupt: 29 sources Number of internal sources: 13 (Timer: 6, ADC: 1, SPI: 1, I2C: 1, HOSTIF: 1, Arithmetic circuit: 1, UART: 1, SIO: 1) Number of external sources: 16 ● Timer —8 bits timer x 6 ch (also 16 bits x 3ch configuration is available by using Timer 0 and 1, Timer 2 and 3, or Timer 4 and 5) —Watchdog timer (WDT) x 1ch ● Serial interface —SPI interface with master function x 1ch —I2C interface with master function x 1ch —UART interface (two-wire, full duplex communication) x 1ch —SIO interface (two-wire, half-duplex communication) x 1ch ● Host interface —Serial interface with slave function (SPI/I2C selectable) x 1ch —Host processor interrupt —8KByte RAM for logging 1/24 FEDL610Q793-02 ML610Q793 ● General-purpose I/O port —8-bit input/output port x 2ch —5-bit input/output port x 1ch ● A/D converter —12-bit successive approximation type A/D converter x 3ch ● Arithmetic circuit —Root operation (Input: 18 bit, Output: 19 bit) ● Power consumption control function —CPU operation mode Supports high frequency operation and low frequency operation —HALT mode Supports the HALT mode for stopping CPU only Returning for HALT mode : 77usec ● Input clock —32.768 kHz (External clock input) ● Power supply voltage —Analog section:(using ADC) 2.5V to 3.6V (not using ADC) 1.7V to 1.9V —Digital I/O section: 1.7V to 1.9V —Digital core section: 1.7V to 1.9V ● Power consumption —High-speed operation (4.096MHz): 0.93mA —HALT Mode: 0.6uA ● Operating frequency —High-speed clock: —Low-speed clock: 4.096 MHz 32.768kHz ● Operating temperature —Ambient temperature: -30°C to +85°C (FLASH erase/programming -30°C to +60°C) ● Package —48-pin WL-CSP (S-UFLGA48-3.06x2.96-0.40-W) 2/24 FEDL610Q793-02 ML610Q793 ■ Block Diagram DVDD DGND AVDD AGND VDDL PA0_EXI00*1, PA1_EXI01*1, PA2_EXI02*1, PA3_EXI03*1, *1 *1 PA4_EXI04 , PA5_EXI05 , PA6_EXI06*1, PA7_EXI07*1, *1 *1 PB0_EXI08 , PB1_EXI09 , *1 PB2_EXI10 , PB3_EXI11*1, *1 *1 PB4_EXI12 , PB5_EXI13 , *1 PB6_EXI14 , PB7_EXI15*1 PA0_EXI00*1, PA1_EXI01*1, *1 *1 PA2_EXI02 , PA3_EXI03 , PA4_EXI04*1, PA5_EXI05*1, *1 *1 PA6_EXI06 , PA7_EXI07 , *1 PB0_EXI08 , PB1_EXI09*1, *1 *1 PB2_EXI10 , PB3_EXI11 , *1 PB4_EXI12 , PB5_EXI13*1, *1 *1 PB6_EXI14 , PB7_EXI15 *2 PC0_INT_S , PC1, *3 *3 PC2_RXD0 , PC3_TXD0 , PC4 Program Memory (Flash) 64KB Coprocessor HOST IF (RAM8KB) (SPI / I2C) RAM 4KB Interrupt Controller SPI (Master) General-purpose I/O Port 8-bit 2ch 5-bit 1ch I2C (Master) Successive ADC 12-bit 3ch Timer 8-bit 6ch Arithmetic Circuit I2C_SPISEL SDO_SDA_S SDI_SA1_S SCS_SA0_S SCLK_SCL_S *2 PC0_INT_S SDO_M SDI_M SCS_M SCLK_M SDA_M SCL_M ADC_IN0 ADC_IN1 ADC_IN2 VREF Asynchronous SIO 1ch PC2_RXD0*3 PC3_TXD0*3 UART 1ch PB6_EXI14*3 PB7_EXI15*3 WDT XT PB3_EXI11 Clock Controller RESET_N Reset Controller VDDX*4 *4 XTN *1 *2 *3 *4 CPU (uX-U8/100) On Chip ICE PLL Test *4 VPP TEST1 TEST0 Shared by the interrupt pins and the general-purpose I/O port Shared by the interrupt output pin of the host interface and the general-purpose I/O port Shared by the UART/Asynchronous SIO transmit/receive pins and the general-purpose I/O port Leave this pin open in ML610Q793 3/24 FEDL610Q793-02 ML610Q793 ■ Pin Configuration DGND DVDD SDA_M PA2_EXI02 PA5_EXI05 PB0_EXI08 PB3_EXI11 7 AVDD VDDX VDDL PA1_EXI01 PA4_EXI04 PA7_EXI07 PB2_EXI10 6 ADC_IN1 AGND SCL_M PA0_EXI00 PA3_EXI03 PB1_EXI09 VPP 5 ADC_IN2 VREF ADC_IN0 PC1 PA6_EXI06 PB7_EXI15 PC2_RXD0 4 XTN TEST0 PC4 SCS_SA0_S SDI_M PB4_EXI12 3 XT TEST1 SDO_SDA_S SDI_SA1_S SCS_M PB6_EXI14 PC3_TXD0 2 I2C_SPISEL RESET_N SCLK_SCL_S SDO_M SCLK_M PC0_INT_S PB5_EXI13 1 G F E D C B A 48-pin WL-CSP Package(S-UFLGA48-3.06x2.96-0.40-W) (Bottom View) 4/24 FEDL610Q793-02 ML610Q793 ■ List of Pins PIN Symbol Input/output Polarity Function F5 AGND — — Analog GND G6 AVDD — — Analog power supply G7 DGND — — Digital IO/core GND No. F7 DVDD — — Digital I/O power supply E6 VDDL — — Digital core power supply F6 VDDX — — Test pin（open） G1 I2C_SPISEL I — E2 SDO_SDA_S IO — Selects the interface with the host I2C interface when I2C_SPISEL = 1 SPI interface when I2C_SPISEL = 0 SDA of I2C slave interface when I2C_SPISEL = 1 O — I — SDO of SPI slave interface when I2C_SPISEL = 0 (This signal status is Hi-Z except for output data. ) I2C slave address when I2C_SPISEL = 1 I — SDI of SPI slave interface when I2C_SPISEL = 0 I — I2C slave address when I2C_SPISEL = 1 I Positive SCS of SPI slave interface when I2C_SPISEL = 0 I — SCL of I2C slave interface when I2C_SPISEL = 1 I — SCLK of SPI slave interface when I2C_SPISEL = 0 D2 D3 E1 SDI_SA1_S SCS_SA0_S SCLK_SCL_S E7 SDA_M IO — SDA of I2C master interface E5 SCL_M O — SCL of I2C master interface D1 SDO_M O — SDO of SPI master interface C3 SDI_M I — SDI of SPI master interface C2 SCS_M O Positive SCS of SPI master interface C1 SCLK_M O — SCLK of SPI master interface G4 ADC_IN2 I — Successive ADC input 2 G5 ADC_IN1 I — Successive ADC input 1 E4 ADC_IN0 I — Successive ADC input 0 F4 VREF I — Successive ADC reference voltage input B1 PC0_INT_S IO — General-purpose input/output port for the primary function O Negative Interrupt output for host interface for the secondary function General-purpose input/output port D4 PC1 IO — A4 PC2_RXD0 IO — General-purpose input/output port for the primary function I — Asynchronous SIO receive data for the secondary function IO — General-purpose input/output port for the primary function O — Asynchronous SIO transmit data for the secondary function A2 PC3_TXD0 E3 PC4 IO — General-purpose input/output port D5 PA0_EXI00 IO — General-purpose input/output port/external interrupt input D6 PA1_EXI01 IO — General-purpose input/output port/external interrupt input D7 PA2_EXI02 IO — General-purpose input/output port/external interrupt input C5 PA3_EXI03 IO — General-purpose input/output port/external interrupt input C6 PA4_EXI04 IO — General-purpose input/output port/external interrupt input C7 PA5_EXI05 IO — General-purpose input/output port/external interrupt input C4 PA6_EXI06 IO — General-purpose input/output port/external interrupt input B6 PA7_EXI07 IO — General-purpose input/output port/external interrupt input B7 PB0_EXI08 IO — General-purpose input/output port/external interrupt input B5 PB1_EXI09 IO — General-purpose input/output port/external interrupt input A6 PB2_EXI10 IO — General-purpose input/output port/external interrupt input 5/24 FEDL610Q793-02 ML610Q793 A7 PB3_EXI11 IO — General-purpose input/output port/external interrupt input O — 32.768kHz clock for output A3 PB4_EXI12 IO — General-purpose input/output port/external interrupt input A1 PB5_EXI13 IO — General-purpose input/output port/external interrupt input B2 PB6_EXI14 IO — General-purpose input/output port/external interrupt input for the primary function I — UART receive data for the secondary function IO — General-purpose input/output port/external interrupt input for the primary function O — UART transmit data for the secondary function System reset input B4 ■ PB7_EXI15 F1 RESET_N I Negative G2 XT I — G3 XTN — — Test pin（open） External clock input A5 VPP — — Test pin（open） F2 TEST1 I — Test pin F3 TEST0 I — Test pin/remap pin (for firmware update) Termination of Unused Pins Pin VPP open. VDDX open. XTN open. TEST0 open. TEST1 open. PA0PA7 Recommended pin termination open. (refer to Note). PB0PB7 open. (refer to Note). PC0PC4 open. (refer to Note). ADC_IN02 open. VREF open. SDA_M, SCL_M open. SDO_M, SCS_M, SCLK_M SDI_M SCLK_SCL_S, SCS_SA0_S, SDI_SA1_S, SDO_SDA_S open. Connect this pin to a pull-down resistor. Apply low level to I2C_SPISEL pin, and connect these pins to a pull-down resistor. [Note:] The supply current flow may become excessively large if the pins of unused input ports and input/output ports are left open with the high impedance input setting. It is recommended to set those ports to input mode with a pull-down resistor, input mode with a pull-up resistor, or output mode by setting the port control register. 6/24 FEDL610Q793-02 ML610Q793 ■ Host Interface The ML610Q793 controls various sensors via the host interface. The host interface provides selectable I2C/SPI interface and interrupt signals to the host processor, and includes an 8-bit register address space and an 8-KByte FIFO. ● Register Map Address Name Symbol (Byte) R/W Size Initial Value CFG R/W 8 00H Write Read 00H 80H Configuration register 01H 81H Sensor interrupt mask register 0 INTMSK0 R/W 8 FFH Sensor interrupt mask register 1 INTMSK1 R/W 8 FFH — — — — 02H 82H 03H~ 83H~ 07H 87H 08H 88H Operation status register STATUS R/— 8 FEH 09H 89H Sensor interrupt request register 0 INTREQ0 R/— 8 00H reserved 0AH 8AH Sensor interrupt request register 1 INTREQ1 R/— 8 00H 0BH 8BH Error code register 0 ERROR0 R/— 8 00H Error code register 1 ERROR1 R/— 8 00H — — — — 0CH 8CH 0DH~ 8DH~ 0FH 8FH 10H 90H Command register 0 CMD0 R/W 8 00H 11H 91H Command register 1 CMD1 R/W 8 00H 12H 92H Parameter register 0 PRM0 R/W 8 00H 13H 93H Parameter register 1 PRM1 R/W 8 00H 14H 94H Parameter register 2 PRM2 R/W 8 00H 15H 95H Parameter register 3 PRM3 R/W 8 00H 16H 96H Parameter register 4 PRM4 R/W 8 00H 17H 97H Parameter register 5 PRM5 R/W 8 00H 18H 98H Parameter register 6 PRM6 R/W 8 00H 19H 99H Parameter register 7 PRM7 R/W 8 00H 1AH 9AH Parameter register 8 PRM8 R/W 8 00H 1BH 9BH Parameter register 9 PRM9 R/W 8 00H 1CH 9CH Parameter register A PRMA R/W 8 00H 1DH 9DH Parameter register B PRMB R/W 8 00H 1EH 9EH Parameter register C PRMC R/W 8 00H 1FH 9FH Command entry register ENT R/W 8 00H 20H A0H Result register 00 RSLT00 R/— 8 00H 21H A1H Result register 01 RSLT01 R/— 8 00H 22H A2H Result register 02 RSLT02 R/— 8 00H 23H A3H Result register 03 RSLT03 R/— 8 00H 24H A4H Result register 04 RSLT04 R/— 8 00H 25H A5H Result register 05 RSLT05 R/— 8 00H 26H A6H Result register 06 RSLT06 R/— 8 00H 27H A7H Result register 07 RSLT07 R/— 8 00H 28H A8H Result register 08 RSLT08 R/— 8 00H 29H A9H Result register 09 RSLT09 R/— 8 00H 2AH AAH Result register 0A RSLT0A R/— 8 00H 2BH ABH Result register 0B RSLT0B R/— 8 00H 2CH ACH Result register 0C RSLT0C R/— 8 00H 2DH ADH Result register 0D RSLT0D R/— 8 00H reserved 7/24 FEDL610Q793-02 ML610Q793 2EH AEH Result register 0E RSLT0E R/— 8 00H 2FH AFH Result register 0F RSLT0F R/— 8 00H 30H B0H Result register 10 RSLT10 R/— 8 00H 31H B1H Result register 11 RSLT11 R/— 8 00H 32H B2H Result register 12 RSLT12 R/— 8 00H 33H B3H Result register 13 RSLT13 R/— 8 00H 34H B4H Result register 14 RSLT14 R/— 8 00H 35H B5H Result register 15 RSLT15 R/— 8 00H 36H B6H Result register 16 RSLT16 R/— 8 00H 37H B7H Result register 17 RSLT17 R/— 8 00H 38H B8H Result register 18 RSLT18 R/— 8 00H 39H B9H Result register 19 RSLT19 R/— 8 00H 3AH BAH Result register 1A RSLT1A R/— 8 00H 3BH BBH Result register 1B RSLT1B R/— 8 00H 3CH BCH Result register 1C RSLT1C R/— 8 00H 3DH BDH Result register 1D RSLT1D R/— 8 00H 3EH BEH Result register 1E RSLT1E R/— 8 00H 3FH BFH Result register 1F RSLT1F R/— 8 00H 40H C0H Result register 20 RSLT20 R/W 8 Undefined 41H~ C1H~ 7FH FFH — — — — reserved 8/24 FEDL610Q793-02 ML610Q793 ● Configuration Register CFG 7 6 5 4 3 2 1 0 CFG REGMD SPI3M — — — INTLVL — — R/W Initial Value R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 REGMD: Sets the access mode of the serial interface (I2C/SPI). Set to "0" to increment the internal address by 1 each time a 1-byte data is transmitted/received. Set to "1" to fix the address to the same address. The Result register 20 is not intended. In addition, there is prohibition that set to “0” to this register and read successively for Result register “IF” to “20”. SPI3M: If the host interface is set "SPI" (apply low level to I2C_SPISEL pin), sets the interface type(3-wires or 4-wires) of SPI communication. Set to "0" for 4-wires mode, or set to "1" for 3-wires mode. INTLVL: Sets the interrupt level. Set to "0" for pulse output, or set to "1" for level output. ● Sensor Interrupt Mask Register INTMSK0, INTMSK1 7 6 5 4 3 2 1 0 INTMSK0 MSK0[7] MSK0[6] MSK0[5] MSK0[4] MSK0[3] MSK0[2] MSK0[1] MSK0[0] R/W Initial Value R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 INTMSK1 MSK1[7] MSK1[6] MSK1[5] MSK1[4] MSK1[3] MSK1[2] MSK1[1] MSK1[0] R/W Initial Value R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 MSK0[7:0]: Masks the interrupt notification to the host processor by the sensor interrupt request register (INTREQ0). Set to "1" to mask the interrupt notification by REQ0[n] bit of INTREQ0.Set to "0" not to mask the interrupt notification. MSK1[7:0]: Masks the interrupt notification to the host processor by the sensor interrupt request register (INTREQ1). Set to "1" to mask the interrupt notification by REQ1[n] bit of INTREQ1.Set to "0" not to mask the interrupt notification. 9/24 FEDL610Q793-02 ML610Q793 ● Operation Status Register STATUS 7 6 5 4 3 2 1 0 STATUS ST[7] ST[6] ST[5] ST[4] ST[3] ST[2] ST[1] ST[0] R/W Initial Value R/— R/— R/— R/— R/— R/— R/— R/— 1 1 1 1 1 1 1 0 ST[n](N=7 to 0): Indicates the status of sensor measurement. Read successively for STAUS, INTREQ0, INTREQ1 by address increments mode. ● Sensor Interrupt Request Register INTREQn (n = 0, 1) 7 6 5 4 3 2 1 0 INTREQn REQn [7] REQn [6] REQn [5] REQn [4] REQn [3] REQn [2] REQn [1] REQn [0] R/W Initial Value R/— R/— R/— R/— R/— R/— R/— R/— 0 0 0 0 0 0 0 0 REQn[7:0]: Indicates the interrupt source to the host processor. Each bit of this register is cleared by being read by the host processor. Read successively for INTREQ0, INTREQ1 by address increments mode. ＊ In competition clear by the reading from a host processor and write from the CPU occurs, Writing from the CPU may not be reflected in this register. Therefore controls so that access of the CPU and access of the host processor do not compete. In cases the competition is non avoidable, refer to [ML610Q793 SDK sensor control software manuals]. Provide Software avoiding competition for Software Development Kit [SDK]. ● Error Code Register ERROR n (n = 0, 1) 7 6 5 4 3 2 1 0 ERRORn ERn [7] ERn [6] ERn [5] ERn [4] ERn [3] ERn [2] ERn [1] ERn [0] R/W Initial Value R/— R/— R/— R/— R/— R/— R/— R/— 0 0 0 0 0 0 0 0 ER n[7:0]: Indicates the ERROR Code of host processor. ● Command Register CMDn (n = 0, 1) 7 6 5 4 3 2 1 0 CMDn CMDn[7] CMDn[6] CMDn[5] CMDn[4] CMDn[3] CMDn[2] CMDn[1] CMDn[0] R/W Initial Value R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 CMDn[7:0]: This register sets the measurement conditions of sensors and inputs commands such as measurement start/stop. 10/24 FEDL610Q793-02 ML610Q793 ● Parameter Register PRMn (n = 0 to 9, A to C) 7 6 5 4 3 2 1 0 PRMn PRMn[7] PRMn [6] PRMn [5] PRMn [4] PRMn [3] PRMn [2] PRMn [1] PRMn [0] R/W Initial Value R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 PRMn[7:0]: This register sets the parameters of commands. ● Command Entry Register ENT 7 6 5 4 3 2 1 0 ENT — — — — — — — ENT R/W Initial Value R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 ENT: After a command is set, set this bit "1" to notify the CPU of the command. When the CPU receives the command, this bit is cleared. ● Result Register RSLT n (n = 00 to 1F) 7 6 5 4 3 2 1 0 RSLTn RSLTn[7] RSLTn [6] RSLTn [5] RSLTn [4] RSLTn [3] RSLTn [2] RSLTn [1] RSLTn [0] R/W Initial Value R/— R/— R/— R/— R/— R/— R/— R/— 0 0 0 0 0 0 0 0 RSLTn[7:0]: This register indicates the processing result. ● Result Register RSLT20 7 6 5 4 3 2 1 0 RSLT20 RSLT20[7] RSLT20 [6] RSLT20 [5] RSLT20 [4] RSLT20 [3] RSLT20 [2] RSLT20 [1] RSLT20 [0] R/W Initial Value R/— R/— R/— R/— R/— R/— R/— R/— X X X X X X X X RSLT20[7:0]: This register indicates the processing result. As this register has a FIFO structure, read data with the given size. This register can be written from a host processor only when using firmware update software which SDK offers. For details. please refer to a [ML610Q793 SDK firmware updates software manuals]. 11/24 FEDL610Q793-02 ML610Q793 ■ Absolute Maximum Ratings Parameter Power supply voltage (Digital I/O) Power supply voltage (Digital CORE) Power supply voltage (Analog) Input voltage Output current Power dissipation Storage temperature ■ VDDL VDDA VIN IOUT PD TSTG Condition Rating Ta = 25°C 0.3 to +4.6 Ta = 25°C 0.3 to +3.6 Ta = 25°C 0.3 to +4.6 Ta = 25°C Ta = 25°C Ta = 25°C 0.3 to VDD+0.3 12 to +11 0.9 55 to +150 (DGND=AGND=0V) Unit V mA W °C Recommended Operation Conditions Parameter Power supply voltage (Digital I/O) Power supply voltage (Digital CORE) ■ Symbol VDD (DGND=AGND=0V) Max. Unit Symbol Condition Min. Typ. VDD 1.7 1.8 1.9 VDDL 1.7 1.8 1.9 Used ADC 2.5 3.3 3.6 Unused ADC 1.7 1.8 1.9 V Power supply voltage (Analog) VDDA Analog reference voltage VREF 2.5 VDDA Auto transient response (VDDL) Vout mV Clock input frequency fCLK 32.441 32.768 33.095 kHz normal operation -30 25 +85 Ambient temperature Ta FLASH erase/write operation -30 25 +60 °C Operating Conditions of Flash Memory Parameter Symbol Operating temperature TOP Power supply voltage Rewrite count Data retention VDDL CEP YDR Condition read operation erase/write operation Range -30 to +85 -30 to +60 1.7 to 1.9 (DGND=AGND=0V) Unit °C V cycles years 12/24 FEDL610Q793-02 ML610Q793 ■ Electrical Characteristics ● DC Characteristics (1/2) ● DC Characteristics (2/2) (DVDD = VDDL = AVDD = 1.7 to 1.9V, DGND = AGND = 0V, Ta = -30 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit Power consumption CPU stop IDD2 0.6 16.5 µA (HALT) *1,*2 Power consumption CPU 32 kHz operation IDD3 7.5 25 µA (Low-speed operation) *1,*2 Power consumption CPU 4 MHz operation IDD4-1 0.93 1.3 mA (High-speed operation 1) *2 Power consumption CPU 4 MHz operation IDD4-2 1.5 2.3 mA (High-speed operation 2) *3 *1 The low-speed clock operates, and only the high-speed clock (PLL) stops *2 The successive approximation type ADC stops *3 The successive approximation type ADC operates with AVDD=2.5V to 3.6V Parameter Output voltage 1 (SDA_M,SCL_M) Output leakage 1 (SDA_M,SCL_M) Output voltage 2 (Excluding SDA_M and SCL_M) Output leakage 2 (Excluding SDA_M and SCL_M) Input current 1 (RESET_N, TEST1) Input current 2 (TEST0) Input current 3 (Excluding RESET_N, TEST1, and TEST0) (DVDD = AVDD = 1.7 to 1.9V, DGND = AGND = 0V, Ta = -30 to +85°C) Symbol Condition Min. Typ. Max. Unit VOH1 V VOL1 IOL1 = +0.5mA 0.5 IOOH1 µA VOL=0V IOOL1 -1 (in high-impedance state) DVDD VOH2 IOH=-0.5mA - 0.5 V VOL2 IOL= 0.5mA 0.5 IOOH2 IOOL2 IIH1 IIL1 IIH2 IIL2 IIH3 IIL3 IIH3Z IIL3Z VOH= DVDD (in high-impedance state) VOL= 0V (in high-impedance state) VIH1=DVDD VIL1 = 0V VIH1=DVDD VIL1 = 0V VIH1 = DVDD(pull-down) VIL1 = 0V (pull-up) VIH1=DVDD (in high-impedance state) VIL1=0V (in high-impedance state) - - 1 -1 - - -600 2 -1 2 -200 -300 300 30 -30 1 -2 600 200 -2 - - 1 -1 - - µA VIH1 - DVDD 0.7 - - VIL1 - - - DVDD 0.3 Input voltage µA µA µA V 13/24 FEDL610Q793-02 ML610Q793 ● AC Characteristics (Clock) (Unless otherwise specified, DVDD = VDDL = 1.7 to 1.9V, DGND = AGND = 0V, Ta = -30 to +85°C) Rating Parameter Symbol Condition Unit Max. Min. Typ. Typ. Typ. Input clock frequency 32.768 kHz fCLK -1% +1% Typ. Typ. Input clock 15.259 TCLKH µs -1% +1% High pulse width Typ. Typ. Input clock 15.259 µs TCLKL -1% +1% Low pulse width No variable power supply 4.096 3.99 4.20 MHｚ System clock frequency fSYSCLK 4.096 3.89 4.30 MHz VRPL mV TCLK＊ TCLKH *TCLK = 1/fCLK TCLKL XT （Clock input pin） TSYSCLK＊ *TSYSCLK = 1/fSYSCLK SYSCLK （Inside system clock） ● AC Characteristics (Reset) (Unless otherwise specified, DVDD = VDDL = 1.7 to 1.9V, DGND = AGND = 0V, Ta = -30 to +85°C) Rating Parameter Symbol Condition Unit Max. Min. Typ. Power-on VDD – RESET_N ― 200 PRST1 assertion period µs Reset pulse width PRST2 ― 200 Reset noise elimination ― 0.3 PNRST pulse width VIL1 RESET_N VIL1 VIL1 PRST2 PRST1 VIL1 VIL1 PNRST 0.9×VDD DVDD 0.1×VDD 14/24 FEDL610Q793-02 ML610Q793 ● AC Characteristics (External Interrupt) (Unless otherwise specified, DVDD = VDDL = 1.7 to 1.9V, DGND = AGND = 0V, Ta = -30 to +85°C) Parameter Symbol External interrupt disable period TNUL Rating Condition Min. Typ. Max. 76.8 ¯ 106.8 Unit Interrupt: Enabled (MIE = 1), CPU: NOP operation s System clock: 32.768kHz PA0 to PA7 PB0 to PB7 (Rising-edge interrupt mode) tNUL PA0 to PA7 PB0 to PB7 (Falling-edge interrupt mode) tonal PA0 to PA7 PB0 to PB7 (Both-edge interrupt mode) ● tNUL AC Characteristics (UART/SIO) (Unless otherwise specified, DVDD = VDDL = 1.7 to 1.9V, DGND = AGND = 0V, Ta = -30 to +85°C) Parameter Symbol Condition Transmit baud rate tTBRT ¯ Receive baud rate tRBRT ¯ Rating Min. Typ. Max. ¯ BRT*1 ¯ 1 BRT* -3% Unit s 1 BRT*1 BRT* +3% s 1 * : UART：Baud rate period set with the UART baud rate dividing register (LSB/MSB). SIO：Baud rate period set with the UART0 baud rate register (UA0BRTL,H) and the UART0 mode register 0 (UA0MOD0). tTBRT UART：PB7_EXI15 SIO：PC3_TXD0 tRBRT UART：PB6_EXI14 SIO：PC2_RXD0 15/24 FEDL610Q793-02 ML610Q793 ● AC Characteristics (Host Interface: I2C Slave Interface) (Unless otherwise specified, DVDD = VDDL = 1.7 to 1.9, DGND = AGND = 0V, Ta = -30 to +85°C) Parameter Symbol Condition SCL clock frequency fSCL Rating Unit Min. Typ. Max. 0 400 kHz tHD:STA 0.6 s SCL ”L” level time tLOW 1.3 s SCL ”H” level time tHIGH 0.6 s tSU:STA 0.6 s SDA hold time tHD:DAT 0 ns SDA setup time tSU:DAT 0.1 s tSU:STO 0.6 s tBUF 1.3 s SCL hold time (start/restart condition) SCL setup time (restart condition) SDA setup time (stop condition) Bus-free time Restart condition Start condition Stop condition SDA (SDO_SDA_S) SCL (SCLK_SCL_S) tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF 16/24 FEDL610Q793-02 ML610Q793 ● AC Characteristics (Host Interface: SPI Slave Interface) (Unless otherwise specified, DVDD = VDDL = 1.7 to 1.9, DGND = AGND = 0V, Ta = -30 to +85°C) Parameter Symbol Condition SCLK input cycle tSCYC SCLK input pulse width Rating Unit Min. Typ. Max. ¯ 0.5 ¯ ¯ s tSW ¯ 0.2 ¯ ¯ s tCS1 ¯ 80 ¯ ¯ ns tCS2 ¯ 80 ¯ ¯ ns tCH1 ¯ 80 ¯ ¯ ns tCH2 ¯ 80 ¯ ¯ ns SCS input pulse width tCW ¯ 90 ¯ ¯ ns SDO output delay time tSD ¯ ¯ ¯ 240 ns SDI input setup time tSS ¯ 80 ¯ ¯ ns SDI input hold time tSH ¯ 80 ¯ ¯ ns SCS setup time SCS hold time tSCYC tSW tSW SCLK (SCLK_SCLK_S) tCS1 SCLK (SCLK_SCLK_S) tCS2 tSS tSH SDI (SDI_SA1_S) tSD SDO (SDO_SDA_S) tCH2 SCS (SCS_SA0_S) tCH1 tCW 17/24 FEDL610Q793-02 ML610Q793 ● AC Characteristics (SPI Master Interface) (Unless otherwise specified, DVDD = VDDL = 1.7 to 1.9, DGND = AGND = 0V, Ta = -30 to +85°C) Parameter Symbol Condition SCLK_M output cycle tSCYC ¯ SCLK_M output pulse width tSW ¯ SDO_M output delay time tSD SDI_M input setup time SDI_M input hold time Rating Unit Min. Typ. Max. ¯ SCLK*1 ¯ SCLK*1 SCLK*1 SCLK*1 ×0.4 ×0.5 ×0.6 ¯ ¯ ¯ 240 ns tSS ¯ 240 ¯ ¯ ns tSH ¯ 80 ¯ ¯ ns s s *1: Internal clock cycle selected by the interface register tSCYC tSW tSW SCLK_M tSD tSD SDO_M tSS tSH SDI_M 18/24 FEDL610Q793-02 ML610Q793 ● AC Characteristics (I2C Master Interface: Standard Mode 100 kHz) (Unless otherwise specified, DVDD = VDDL = 1.7 to 1.9, DGND = AGND = 0V, Ta = -30 to +85°C) Parameter Symbol Condition SCL clock frequency fSCL tHD:STA Rating Unit Min. Typ. Max. 0 100 kHz 4.0 s SCL hold time (start/restart condition) SCL ”L” level time tLOW 4.7 s SCL ”H” level time tHIGH 4.0 s tSU:STA 4.7 s SDA hold time tHD:DAT 0 s SDA setup time tSU:DAT 0.25 s tSU:STO 4.0 s tBUF 4.7 s SCL setup time (restart condition) SDA setup time (stop condition) Bus-free time ● AC Characteristics (I2C Master Interface: Fast Mode 400 kHz) (Unless otherwise specified, DVDD = VDDL = 1.7 to 1.9, DGND = AGND = 0V, Ta = -30 to +85°C) Parameter Symbol Condition SCL_M clock frequency fSCL Rating Unit Min. Typ. Max. 0 400 kHz tHD:STA 0.6 s SCL_M ”L” level time tLOW 1.3 s SCL_M ”H” level time tHIGH 0.6 s tSU:STA 0.6 s SDA_M hold time tHD:DAT 0 s SDA_M setup time tSU:DAT 0.1 s tSU:STO 0.6 s tBUF 1.3 s SCL_M hold time (start/restart condition) SCL_M setup time (restart condition) SDA_M setup time (stop condition) Bus-free time Start condition Restart condition Stop condition SDA_M SCL_M tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF 19/24 FEDL610Q793-02 ML610Q793 ● Electrical Characteristics of Successive Approximation Type A/D Converter (Unless otherwise specified, DVDD=VDDL=1.7to1.9V, AVDD=2.5to3.6V, DGND=AGND=0V, Ta=-30to+85°C) Parameter Symbol Condition Resolution n Integral non-linearity error margin INL Rating Min. Typ. Max. ¯ ¯ ¯ 12 2.7VVREF3.6V -4 ¯ +4 Unit bit 2.5VVREF2.7V -6 ¯ +6 2.7VVREF3.6V -3 ¯ +3 2.5VVREF2.7V -5 ¯ +5 VOFF ¯ -6 ¯ +6 Full-scale error FSE ¯ -6 ¯ +6 Reference voltage VREF ¯ 2.5 ¯ VDDA V Conversion time tCONV At high-speed operation ¯ 112 ¯ φ/CH Differential non-linearity error margin DNL Zero-scale error LSB φ: Cycle of high-speed clock 20/24 FEDL610Q793-02 ML610Q793 ■ Power-On / Power-Off Procedures Keep the power-on and power-off procedures of DVDD, VDDL supply at the same time. And DVDD, VDDL supply indetical voltage. Keep the power-on procedures of DVDD(VDDL), AVDD supply at the same time. Or DVDD(VDDL) supply voltage before AVDD. And AVDD supply voltage within 50 msec, after DVDD(VDDL) supply voltage. The timing restrictions are shown as following. 5 msec or less DVDD、 VDDL 2sec or more 30mV or less 0.9*DVDD 0.1*DVDD 0sec or more , 50 msec or less 5 msec or less AVDD 2sec or more 30mV or less 0.9*AVDD 0.1*AVDD 21/24 FEDL610Q793-02 ML610Q793 ■ Package Dimensions Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact our responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 22/24 FEDL610Q793-02 ML610Q793 ■ Revision History Page Document No. Issue Date Previous Edition New Edition Description PEDL610Q793-01 2012.12.10 ― ― Preliminary first edition issued FEDL610Q793-01 2013.6.12 ― ― First edition issued 5 6 5 6 VDDX,XTN,VPP pin(open) 6 6 notation of open change 6 6 Delete of RESET_N from Termination of Unused Pins 7 7 change from includes an 8-bit and a 16-bit register address … to 8-bit register address 7 7 RSLT00,02,04,06,08,0A,0C,0E,10,12,14,16,18,1 A,1C,1E size change from 8/16 to 8 9 9 Sensor Interrupt Mask Register, correction of errors. 12 12 Recommended Operation Conditions Vref Min change from 2.2 to 2.5 13 13 DC Characteristics (2/2) correction of errors 14 14 fCLK, TCLKH, TCLKL changed Min/Max Spec 14 14 Add the standard of power-on VDD – RESET_N assertion period. 17 17 AC Characteristics (SPI Slave Interface), correction of errors. 20 20 Voltage setting, correction of errors. 21 21 Add the standard of power-on / power-off procedures. FEDL610Q793-02 2015.1.26 function change with test 23/24 FEDL610Q793-02 ML610Q793 NOTES No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. 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