FEDR36V04G54B-002-01 Issue Date: Oct.01, 2008 MR36V04G54B 128M–Word 32–Bit Page Mode P2ROM PIN CONFIGURATION (TOP VIEW) FEATURES · 128Mx32 or 256Mx16-bit electrically switchable configuration · Page size of 8-word x 32-Bit or 16-word x 16-Bit · 3.0 V to 3.6 V power supply · Random Access time........... 105 ns MAX · Page Access time ................ 25 ns MAX · Operating current ................ 100 mA MAX · Standby current ................... 85 mA MAX · Input/Output TTL compatible · Three-state output PACKAGES ·70-pin plastic SSOP (P-SSOP70-500-0.80-EK-MC) P2ROM ADVANCED TECHNOLOGY P2ROM stands for Production Programmed ROM. This exclusive LAPIS Semiconductor technology utilizes factory test equipment for programming the customers code into the P2ROM prior to final production testing. Advancements in this technology allows production costs to be equivalent to MASKROM and has many advantages and added benefits over the other non-volatile technologies, which include the following; · Short lead time, since the P2ROM is programmed at the final stage of the production process, a large P2ROM inventory "bank system" of un-programmed packaged products are maintained to provide an aggressive lead-time and minimize liability as a custom product. · No mask charge, since P2ROMs do not utilize a custom mask for storing customer code, no mask charges apply. · No additional programming charge, unlike Flash and OTP that require additional programming and handling costs, the P2ROM already has the code loaded at the factory with minimal effect on the production throughput. The cost is included in the unit price. · Custom Marking is available at no additional charge. Vcc 1 70 D28 Vss 2 69 D20 A24 3 68 D12 A23 4 67 D4 A22 5 66 D29 A21 6 65 D21 A20 7 64 D13 A19 8 63 D5 A18 9 62 D30 A17 10 61 D22 A16 11 60 D14 A15 12 59 D6 A14 13 58 D31/A-1 A25 14 57 D23 CE# 15 56 D15 A13 16 55 D7 A12 17 54 OE# A11 18 53 A26 Vcc 19 52 A0 Vss 20 51 Vcc A1 21 50 WORD# A2 22 49 Vss A3 23 48 D0 A4 24 47 D8 A5 25 46 D16 A6 26 45 D24 A7 27 44 D1 A8 28 43 D9 A9 29 42 D17 A10 30 41 D25 Vss 31 40 Vcc D27 32 39 D2 D19 33 38 D10 D11 34 37 D18 D3 35 36 D26 70-pin SSOP 1/9 FEDR36V04G54B-002-01 MR36V04G54B / P2ROM BLOCK DIAGRAM A-1 Column Decoder Address Buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 Row Decoder × 16/× 32 Switch CE# OE# CE OE WORD# Memory Cell Matrix 128M × 32-Bit or 256M × 16-Bit Multiplexer & Sense Amp. Output Buffer D0 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 D1 D3 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D25 D27 D29 D31 In16-bit output mode, these pins are placed in a high-Z state and pin D31 functions as the A-1 address pin. PIN DESCRIPTIONS Pin name A0 to A26 D31/ A–1 D0 to D30 CE# OE# WORD# VCC VSS Functions Address inputs Data outputs /Address -1 input Data outputs Chip enable input Output enable input Word -Byte select input Power supply voltage Ground 2/9 FEDR36V04G54B-002-01 MR36V04G54B / P2ROM FUNCTION TABLE Mode CE# OE# WORD# Read (32-Bit) Read (16-Bit) Output disable L L L L L H H H L H L H L Standby VCC D0 to D15 D16 to D30 DOUT DOUT 3.3 V Hi–Z D31/A-1 DOUT L/H Hi–Z Hi–Z : Don’t Care (H or L) ABSOLUTE MAXIMUM RATINGS Parameter Operating temperature under bias Storage temperature Input voltage Output voltage Power supply voltage Output short circuit current Power dissipation per package Symbol Ta Tstg VI VO VCC Ios PD Condition — relative to VSS — Ta=25C Value 0 to 70 –55 to 125 –0.5 to VCC+0.5 –0.5 to VCC+0.5 –0.5 to 4.6 10 1.0 Unit C C V V V mA W RECOMMENDED OPERATING CONDITIONS Parameter VCC power supply voltage Input “H” level Input “L” level Symbol VCC VIH VIL Condition VCC = 3.0 to 3.6 V Min. 3.0 2.2 –0.5 Typ. — — — (Ta = 0 to 70C) Max. Unit 3.6 V VCC+0.5 V 0.6 V Voltage is relative to VSS. : VCC+1.5V(Max.) when pulse width of overshoot is less than 10ns. : -1.5V(Min.) when pulse width of undershoot is less than 10ns. PIN CAPACITANCE Parameter Input(except Word#) Output Symbol CIN1 COUT Condition VI = 0 V VO = 0 V Min. — — (VCC = 3.3 V, Ta = 25C, f = 1 MHz) Typ. Max. Unit — 20 pF — 20 pF 3/9 FEDR36V04G54B-002-01 MR36V04G54B / P2ROM ELECTRICAL CHARACTERISTICS DC Characteristics Parameter Input leakage current Output leakage current VCC power supply current (Standby) Symbol ILI ILO ICCSC VCC power supply current (Read) ICCA1 Input “H” level Input “L” level Output “H” level Output “L” level VIH VIL VOH VOL Condition VI = 0 to VCC VO = 0 to VCC CE# = VCC=3.6V Add.=VCC CE# = VIL OE# = VIH tc = 200 ns — — IOH = –2 mA IOL = 2 mA Min. — — Typ. — — Max. 20 20 Unit A A — — 85 mA — — 100 mA 2.2 –0.5 2.4 — — — — — VCC+0.5 0.6 — 0.4 V V V V Voltage is relative to VSS. : VCC+1.5V(Max.) when pulse width of overshoot is less than 10ns. : -1.5V(Min.) when pulse width of undershoot is less than 10ns. AC Characteristics Parameter Address cycle time Address access time Address skew time CE Address skew time Page cycle time Page access time CE# access time OE# access time Symbol tC tACC tASK TCSK tPC tPAC tCE tOE tCHZ tOHZ tOH Output disable time Output hold time Condition — — — — — CE# = OE# = VIL OE# = VIL CE# = VIL OE# = VIL CE# = VIL CE# = OE# = VIL Min. 105 — — — 25 — — — 0 0 0 (VCC = 3.3 V ± 0.3 V, Ta = 0 to 70C) Max. Unit — ns 105 ns 10 ns 10 ns — ns 25 ns 105 ns 25 ns 20 ns 20 ns — ns Measurement conditions Input signal level--------------------------------- 0 V/3 V Input timing reference level ------------------- 1/2Vcc Output load --------------------------------------- 50 pF Output timing reference level----------------- 1/2Vcc Output load Output 50 pF (Including scope and jig) 4/9 FEDR36V04G54B-002-01 MR36V04G54B / P2ROM TIMING CHART (READ CYCLE) Random Access Mode Read Cycle tC tC Address tOH tASK tCE tACC CE# tCHZ tOE tOH OE# tOHZ tACC Valid Data Dout Valid Data Hi-Z Hi-Z Page Access Mode Read Cycle tC A3 to A26 tPC tPC A-1 to A2 (X16 mode) A0 to A2 (X32 mode) tCE tOH CE# tCSK tOE tCHZ OE# tACC tPAC tPAC tOHZ Dout Hi-Z Hi-Z 5/9 FEDR36V04G54B-002-01 MR36V04G54B / P2ROM POWER ON CHARACTERISTICS Parameter VCC set up time Power on sequence hold time Power off hold time Symbol tvset tposh tvpoff Condition — — — Min. 5 1 1 (VCC = 3.3 V ± 0.3 V, Ta = 0 to 70C) Max. Unit 270 us — ms — ms TIMING CHART (POWER ON) Don’t power-on Unavailable tvpoff VCC LEVEL = 3.0 V tposh LEVEL=VSS VCC 0.1V tvset Note: A start-up delay of 1ms is required after power-on. If you power-off VCC, you must wait 1ms to power-on. CE# must be HIGH while VCC power on sequence. 6/9 FEDR36V04G54B-002-01 MR36V04G54B / P2ROM PACKAGE DIMENSIONS (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 7/9 FEDR36V04G54B-002-01 MR36V04G54B / P2ROM REVISION HISTORY Page Document No. Date Previous Edition Current Edition FEDR36V04G54B-02-01 Sep. 03 2008 – – Final edition 1 FEDR36V04G54B-002-01 Oct. 1, 2008 – – Changed company logo and name to OKI SEMICONDUCTOR Description 8/9 FEDR36V04G54B-002-01 MR36V04G54B / P2ROM NOTICE No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from LAPIS Semiconductor upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties. 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