MB9AA40NB Series
32-bit ARM® Cortex®-M3
FM3 Microcontroller
The MB9AA40NB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power
consumption mode and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and
SRAM, and have peripheral functions such as various timers, ADCs, LCDC and Communication Interfaces (UART, CSIO, I 2C). The
products which are described in this data sheet are placed into TYPE6 product categories in FM3 Family Peripheral Manual.
Features
Supports external RDY function
32-bit ARM Cortex-M3 Core
*: MB9AFA41LB, FA42LB and FA44LB do not support External
Bus Interface.
Processor version: r2p1
Up to 40 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
LCD Controller (LCDC)
Up to 40 SEG × 8 COM
8 COM or 4 COM mode can be selected.
Built-in internal dividing resistor
LCD drive power supply (bias) pin (VV4 to VV0)
On-chip Memories
With blinking function
[Flash memory]
Multi-function Serial Interface (Max 8 channels)
Dual operation Flash memory
Dual
Operation Flash memory has the upper bank and the
lower bank.
So, this series could implement erase, write and read
operations for each bank simultaneously.
Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank
+ 16 Kbytes lower bank)
Work area: 32 Kbytes (lower bank)
Read cycle: 0 wait-cycle
4 channels with 16steps×9-bit FIFO (ch.4 to ch.7), 4
channels without FIFO (ch.0 to ch.3)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
I2 C
Security function for code protection
[UART]
Full-duplex double buffer
[SRAM]
Selection with or without parity supported
This Series on-chip SRAM is composed of two independent
SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus
and D-code bus of Cortex-M3 core. SRAM1 is connected to
System bus.
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control* : Automatically control the
transmission by CTS/RTS (only ch.4)
SRAM0: Up to 16 Kbytes
Various error detection functions available (parity errors,
SRAM1: Up to 16 Kbytes
framing errors, and overrun errors)
External Bus Interface
Supports SRAM, NOR Flash memory device
Up to 8 chip selects
*: MB9AFA41LB, FA42LB and FA44LB do not support
Hardware Flow control.
8-/16-bit Data width
[CSIO]
Full-duplex double buffer
Up to 25-bit Address bit
Built-in dedicated baud rate generator
Maximum area size: Up to 256 Mbytes
Overrun error detection function available
Supports Address/Data multiplex
Cypress Semiconductor Corporation
Document Number: 002-05633 Rev *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 1, 2017
MB9AA40NB Series
[I2C]
Dual Timer (32-/16-bit Down Counter)
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
DMA Controller (8 channels)
The DMA Controller has an independent bus from the CPU, so
CPU and DMA Controller can process simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Free-running
Periodic (=Reload)
One-shot
Transfer address area: 32-bit (4 Gbytes)
HDMI-CEC/Remote Control Receiver (Up to 2
channels)
Transfer mode: Block transfer/Burst transfer/Demand
HDMI-CEC transmitter
transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 24 channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 2units
Conversion time: 2.0 μs @ 2.7 V to 3.6 V
Priority conversion available (priority at 2 levels)
Header
block automatic transmission by judging Signal
free
Generating status interrupt by detecting Arbitration lost
Generating START, EOM, ACK automatically to output
CEC transmission by setting 1 byte data
Generating transmission status interrupt when transmitting
1 block (1 byte data and EOM/ACK)
HDMI-CEC receiver
Automatic
Line
ACK reply function available
error detection function available
Remote control receiver
4
bytes reception buffer
code detection function available
Repeat
Scanning conversion mode
Real-time clock (RTC)
Built-in FIFO for conversion data storage (for SCAN
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
conversion: 16steps, for Priority conversion: 4steps)
Base Timer (Max 8channels)
Operation mode is selectable from the followings for each
channel.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Watch Counter
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for external bus or peripherals. Moreover, the
port relocate function is built in. It can set which I/O port the
peripheral function can be allocated to.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
The Watch counter is used for wake up from sleep and timer
mode.
Interval timer: up to 64s (Max) @ Sub Clock : 32.768 kHz
External Interrupt Controller Unit
Up to 16 external interrupt input pins
Include one non-maskable interrupt (NMI) input pin
Up to 83 fast general-purpose I/O Ports@100 pin Package
Some ports are 5 V tolerant I/O.
See Pin Description to confirm the corresponding pins.
Document Number: 002-05633 Rev *B
Page 2 of 131
MB9AA40NB Series
Watchdog Timer (2 channels)
Clock Super Visor (CSV)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
This series consists of two different watchdogs, a Hardware
watchdog and a Software watchdog.
External clock failure (clock stop) is detected, reset is
The Hardware watchdog timer is clocked by the built-in
low-speed CR oscillator. Therefore, the Hardware watchdog is
active in any low-power consumption modes except RTC, Stop,
Deep Standby RTC, Deep Standby Stop modes.
External frequency anomaly is detected, interrupt or reset is
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
asserted.
asserted.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage that has been
set, Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Six low-power consumption modes supported.
Sleep
Clock and Reset
Timer
[Clocks]
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillator, and Main PLL).
Main Clock:
4 MHz to 48 MHz
Sub Clock:
32.768 kHz
Built-in high-speed CR Clock:
4 MHz
Built-in low-speed CR Clock:
100 kHz
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power-on reset
RTC
Stop
Deep Standby RTC (selectable between keeping the value of
RAM and not)
Deep Standby Stop (selectable between keeping the value of
RAM and not)
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM)*
*: MB9AFA41LB/MB, FA42LB/MB and FA44LB/MB support
only SWJ-DP.
Software reset
Unique ID
Watchdog timers reset
Unique value of the device (41-bit) is set.
Low-voltage detection reset
Power Supply
Clock super visor reset
Wide range voltage:
VCC = 1.65 V to 3.6 V
VCC = 2.2 V to 3.6 V (when LCDC is used)
Document Number: 002-05633 Rev *B
Page 3 of 131
MB9AA40NB Series
Contents
1. Product Lineup .................................................................................................................................................................. 6
2. Packages ........................................................................................................................................................................... 7
3. Pin Assignment ................................................................................................................................................................. 8
4. List of Pin Functions....................................................................................................................................................... 15
5. I/O Circuit Type................................................................................................................................................................ 41
6. Handling Precautions ..................................................................................................................................................... 48
7. Handling Devices ............................................................................................................................................................ 52
8. Block Diagram ................................................................................................................................................................. 55
9. Memory Size .................................................................................................................................................................... 56
10. Memory Map .................................................................................................................................................................... 57
11. Pin Status in Each CPU State ........................................................................................................................................ 60
12. Electrical Characteristics ............................................................................................................................................... 71
12.1 Absolute Maximum Ratings ......................................................................................................................................... 71
12.2 Recommended Operating Conditions.......................................................................................................................... 72
12.3 DC Characteristics....................................................................................................................................................... 72
12.3.1 Current rating ............................................................................................................................................................... 73
12.3.2 Pin Characteristics ....................................................................................................................................................... 77
12.4 LCD Characteristics..................................................................................................................................................... 78
12.5 AC Characteristics ....................................................................................................................................................... 79
12.5.1 Main Clock Input Characteristics .................................................................................................................................. 79
12.5.2 Sub Clock Input Characteristics ................................................................................................................................... 80
12.5.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 80
12.5.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL) .................................................. 81
12.5.5 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock
of the Main PLL) ........................................................................................................................................................... 81
12.5.6 Reset Input Characteristics .......................................................................................................................................... 82
12.5.7 Power-on Reset Timing................................................................................................................................................ 82
12.5.8 External Bus Timing ..................................................................................................................................................... 83
12.5.9 Base Timer Input Timing .............................................................................................................................................. 90
12.5.10 CSIO/UART Timing .................................................................................................................................................. 91
12.5.11 External Input Timing ................................................................................................................................................ 99
12.5.12 I2C Timing ............................................................................................................................................................... 100
12.5.13 ETM Timing ............................................................................................................................................................ 101
12.5.14 JTAG Timing ........................................................................................................................................................... 102
12.6 12-bit A/D Converter .................................................................................................................................................. 103
12.7 Low-Voltage Detection Characteristics ...................................................................................................................... 106
12.7.1 Low-Voltage Detection Reset ..................................................................................................................................... 106
12.7.2 Interrupt of Low-Voltage Detection ............................................................................................................................. 107
12.8 Flash Memory Write/Erase Characteristics ............................................................................................................... 108
12.8.1 Write / Erase time....................................................................................................................................................... 108
12.8.2 Write cycles and data hold time ................................................................................................................................. 108
12.9 Return Time from Low-Power Consumption Mode .................................................................................................... 109
12.9.1 Return Factor: Interrupt/WKUP .................................................................................................................................. 109
12.9.2 Return Factor: Reset .................................................................................................................................................. 111
13. Ordering Information .................................................................................................................................................... 113
14. Package Dimensions .................................................................................................................................................... 115
15. Errata.............................................................................................................................................................................. 124
16. Major Changes .............................................................................................................................................................. 128
Document Number: 002-05633 Rev *B
Page 4 of 131
MB9AA40NB Series
Document History ............................................................................................................................................................... 130
Sales, Solutions, and Legal Information ........................................................................................................................... 131
Document Number: 002-05633 Rev *B
Page 5 of 131
MB9AA40NB Series
1. Product Lineup
Memory size
Product name
On-chip
Flash
memory
On-chip
SRAM
MB9AFA41LB/MB/NB
MB9AFA42LB/MB/NB
MB9AFA44LB/MB/NB
Main area
64 Kbytes
128 Kbytes
256 Kbytes
Work area
32 Kbytes
32 Kbytes
32 Kbytes
SRAM0
8 Kbytes
8 Kbytes
16 Kbytes
SRAM1
8 Kbytes
8 Kbytes
16 Kbytes
Total
16 Kbytes
16 Kbytes
32 Kbytes
Function
Product name
Pin count
MB9AFA41LB
MB9AFA42LB
MB9AFA44LB
MB9AFA41MB
MB9AFA42MB
MB9AFA44MB
MB9AFA41NB
MB9AFA42NB
MB9AFA44NB
64
80/96
Cortex-M3
40 MHz
1.65 V to 3.6 V
8 ch.
Addr: 21-bit (Max)
R/W Data: 8-bit (Max)
CS: 4 (Max)
Support: SRAM, NOR
Flash memory
100/112
CPU
Freq.
Power supply voltage range
DMAC
External Bus Interface
LCD Controller
Multi-function Serial Interface
(UART/CSIO/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
Dual Timer
HDMI-CEC/ Remote Control
Receiver
Real-Time Clock
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
High-speed
Built-in CR
Low-speed
Debug Function
Unique ID
-
20 SEG × 8 COM
(Max)
Addr: 25-bit (Max)
R/W Data: 8-/16-bit (Max)
CS: 8 (Max)
Support: SRAM,
NOR Flash memory
33 SEG × 8 COM
40 SEG × 8 COM
(Max)
(Max)
8 ch. (Max)
ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO
8 ch. (Max)
1 unit
2 ch. (Max)
1 unit
1 unit
Yes
1 ch. (SW) + 1 ch. (HW)
8 pins (Max) +
11 pins (Max) +
NMI × 1
NMI × 1
51 pins (Max)
66 pins (Max)
12 ch. (2 units)
17 ch. (2 units)
Yes
2 ch.
4 MHz
100 kHz
SWJ-DP
Yes
16 pins (Max) +
NMI × 1
83 pins (Max)
24 ch. (2 units)
SWJ-DP/ETM
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See Electrical Characteristics AC Characteristics Built-in CR Oscillation Characteristics for accuracy of built-in CR.
Document Number: 002-05633 Rev *B
Page 6 of 131
MB9AA40NB Series
2. Packages
Product name
Package
LQFP:
LQFP:
QFN:
LQFP:
LQFP:
BGA:
LQFP:
QFP:
BGA:
LQD064 (0.5 mm pitch)
LQG064 (0.65 mm pitch)
VNC064 (0.5 mm pitch)
LQH080 (0.5 mm pitch)
LQJ080 (0.65 mm pitch)
FDG096 (0.5 mm pitch)
LQI100 (0.5 mm pitch)
PQH100 (0.65 mm pitch)
LBC112 (0.8 mm pitch)
MB9AFA41LB
MB9AFA42LB
MB9AFA44LB
-
-
-
-
MB9AFA41MB
MB9AFA42MB
MB9AFA44MB
-
MB9AFA41NB
MB9AFA42NB
MB9AFA44NB
-
: Supported
Note:
−
See Package Dimensions for detailed information on each package.
Document Number: 002-05633 Rev *B
Page 7 of 131
MB9AA40NB Series
3. Pin Assignment
LQI100
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1/MRDY_1
P61/SOT5_0/TIOB2_2/SEG00
P62/SCK5_0/ADTG_3/SEG01/MOEX_1
P63/INT03_0/SEG02/MWEX_1
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P0E/CTS4_0/TIOB3_2/SEG03/MDQM1_1
P0D/RTS4_0/TIOA3_2/SEG04/MDQM0_1
P0C/SCK4_0/TIOA6_1/MALE_1
P0B/SOT4_0/TIOB6_1/MCSX0_1
P0A/SIN4_0/INT00_2/MCSX1_1
P09/TRACECLK/TIOB0_2/RTS4_2/SEG05/MCSX2_1
P08/AN23/TRACED3/TIOA0_2/CTS4_2/SEG06/MCSX3_1
P07/AN22/TRACED2/ADTG_0/SCK4_2/SEG07/MCLKOUT_1
P06/AN21/TRACED1/TIOB5_2/SOT4_2/INT01_1/SEG08/MCSX4_1
P05/AN20/TRACED0/TIOA5_2/SIN4_2/INT00_1/SEG09/MCSX5_1
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_1
P01/TCK/SWCLK
P00/TRSTX/MCSX7_1
VCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
(TOP VIEW)
VCC
1
75
VSS
P50/INT00_0/SIN3_1/VV4/MADATA00_1
2
74
P20/AN19/INT05_0/CROUT_0/SEG10/MAD24_1
P51/INT01_0/SOT3_1/VV3/MADATA01_1
3
73
P21/AN18/SIN0_0/INT06_1/WKUP2/SEG11
P52/INT02_0/SCK3_1/VV2/MADATA02_1
4
72
P22/AN17/SOT0_0/TIOB7_1/SEG12
P53/SIN6_0/TIOA1_2/INT07_2/VV1/MADATA03_1
5
71
P23/AN16/SCK0_0/TIOA7_1/SEG13
P54/SOT6_0/TIOB1_2/VV0/MADATA04_1
6
70
P1F/AN15/ADTG_5/MAD23_1
P55/SCK6_0/ADTG_1/SEG39/MADATA05_1
7
69
P1E/AN14/RTS4_1/SEG14/MAD22_1
P56/INT08_2/SEG38/MADATA06_1
8
68
P1D/AN13/CTS4_1/SEG15/MAD21_1
P30/TIOB0_1/INT03_2/COM7/MADATA07_1
9
67
P1C/AN12/SCK4_1/SEG16/MAD20_1
P31/TIOB1_1/SCK6_1/INT04_2/COM6/MADATA08_1
10
66
P1B/AN11/SOT4_1/SEG17/MAD19_1
P32/TIOB2_1/SOT6_1/INT05_2/COM5/MADATA09_1
11
65
P1A/AN10/SIN4_1/INT05_1/SEG18/MAD18_1
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/COM4/MADATA10_1
12
64
P19/AN09/SCK2_2/SEG19/MAD17_1
P34/TIOB4_1/MADATA11_1
13
63
P18/AN08/SOT2_2/SEG20/MAD16_1
P35/TIOB5_1/INT08_1/MADATA12_1
14
62
AVSS
LQFP - 100
P36/SIN5_2/INT09_1/MADATA13_1
15
61
AVRH
P37/SOT5_2/INT10_1/MADATA14_1
16
60
AVCC
P38/SCK5_2/INT11_1/MADATA15_1
17
59
P17/AN07/SIN2_2/INT04_1/SEG21/MAD15_1
P39/ADTG_2/COM3
18
58
P16/AN06/SCK0_1/SEG22/MAD14_1
P3A/TIOA0_1/RTCCO_2/SUBOUT_2/COM2
19
57
P15/AN05/SOT0_1/SEG23/MAD13_1
P3B/TIOA1_1/COM1
20
56
P14/AN04/SIN0_1/INT03_1/SEG24/MAD12_1
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
C
VSS
VCC
P46/X0A
P47/X1A
INITX
P48/INT14_1/SIN3_2/SEG32/MAD02_1
P49/TIOB0_0/SOT3_2/SEG31/MAD03_1
P4A/TIOB1_0/SCK3_2/SEG30/MAD04_1
P4B/TIOB2_0/SEG29/MAD05_1
P4C/TIOB3_0/SCK7_1/CEC0/MAD06_1
P4D/TIOB4_0/SOT7_1/MAD07_1
P4E/TIOB5_0/INT06_2/SIN7_1/MAD08_1
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
VCC
P45/TIOA5_0/SEG33/MAD01_1
51
31
25
P44/TIOA4_0/SEG34/MAD00_1
P10/AN00/SEG28
VSS
30
52
P43/TIOA3_0/ADTG_7
24
29
P11/AN01/SIN1_1/INT02_1/WKUP1/SEG27/MAD09_1
P3F/TIOA5_1/SEG35
P42/TIOA2_0
53
28
23
27
P12/AN02/SOT1_1/SEG26/MAD10_1
P3E/TIOA4_1/SEG36
26
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/SEG25/MAD11_1
54
VCC
55
22
P41/TIOA1_0/INT13_1
21
P40/TIOA0_0/INT12_1
P3C/TIOA2_1/COM0
P3D/TIOA3_1/SEG37
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05633 Rev *B
Page 8 of 131
MB9AA40NB Series
PQH100
P50/INT00_0/SIN3_1/VV4/MADATA00_1
VCC
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1/MRDY_1
P61/SOT5_0/TIOB2_2/SEG00
P62/SCK5_0/ADTG_3/SEG01/MOEX_1
P63/INT03_0/SEG02/MWEX_1
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P0E/CTS4_0/TIOB3_2/SEG03/MDQM1_1
P0D/RTS4_0/TIOA3_2/SEG04/MDQM0_1
P0C/SCK4_0/TIOA6_1/MALE_1
P0B/SOT4_0/TIOB6_1/MCSX0_1
P0A/SIN4_0/INT00_2/MCSX1_1
P09/TRACECLK/TIOB0_2/RTS4_2/SEG05/MCSX2_1
P08/AN23/TRACED3/TIOA0_2/CTS4_2/SEG06/MCSX3_1
P07/AN22/TRACED2/ADTG_0/SCK4_2/SEG07/MCLKOUT_1
P06/AN21/TRACED1/TIOB5_2/SOT4_2/INT01_1/SEG08/MCSX4_1
P05/AN20/TRACED0/TIOA5_2/SIN4_2/INT00_1/SEG09/MCSX5_1
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_1
P01/TCK/SWCLK
P00/TRSTX/MCSX7_1
VCC
VSS
P20/AN19/INT05_0/CROUT_0/SEG10/MAD24_1
P21/AN18/SIN0_0/INT06_1/WKUP2/SEG11
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
(TOP VIEW)
P51/INT01_0/SOT3_1/VV3/MADATA01_1
81
50
P22/AN17/SOT0_0/TIOB7_1/SEG12
P52/INT02_0/SCK3_1/VV2/MADATA02_1
82
49
P23/AN16/SCK0_0/TIOA7_1/SEG13
P53/SIN6_0/TIOA1_2/INT07_2/VV1/MADATA03_1
83
48
P1F/AN15/ADTG_5/MAD23_1
P54/SOT6_0/TIOB1_2/VV0/MADATA04_1
84
47
P1E/AN14/RTS4_1/SEG14/MAD22_1
P55/SCK6_0/ADTG_1/SEG39/MADATA05_1
85
46
P1D/AN13/CTS4_1/SEG15/MAD21_1
P56/INT08_2/SEG38/MADATA06_1
86
45
P1C/AN12/SCK4_1/SEG16/MAD20_1
P30/TIOB0_1/INT03_2/COM7/MADATA07_1
87
44
P1B/AN11/SOT4_1/SEG17/MAD19_1
P31/TIOB1_1/SCK6_1/INT04_2/COM6/MADATA08_1
88
43
P1A/AN10/SIN4_1/INT05_1/SEG18/MAD18_1
42
P19/AN09/SCK2_2/SEG19/MAD17_1
41
P18/AN08/SOT2_2/SEG20/MAD16_1
P32/TIOB2_1/SOT6_1/INT05_2/COM5/MADATA09_1
89
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/COM4/MADATA10_1
90
P34/TIOB4_1/MADATA11_1
91
40
AVSS
P35/TIOB5_1/INT08_1/MADATA12_1
92
39
AVRH
P36/SIN5_2/INT09_1/MADATA13_1
93
38
AVCC
P37/SOT5_2/INT10_1/MADATA14_1
94
37
P17/AN07/SIN2_2/INT04_1/SEG21/MAD15_1
P38/SCK5_2/INT11_1/MADATA15_1
95
36
P16/AN06/SCK0_1/SEG22/MAD14_1
P39/ADTG_2/COM3
96
35
P15/AN05/SOT0_1/SEG23/MAD13_1
P3A/TIOA0_1/RTCCO_2/SUBOUT_2/COM2
97
34
P14/AN04/SIN0_1/INT03_1/SEG24/MAD12_1
P3B/TIOA1_1/COM1
98
33
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/SEG25/MAD11_1
P3C/TIOA2_1/COM0
99
32
P12/AN02/SOT1_1/SEG26/MAD10_1
P3D/TIOA3_1/SEG37
100
31
P11/AN01/SIN1_1/INT02_1/WKUP1/SEG27/MAD09_1
28
29
30
VSS
VCC
P10/AN00/SEG28
24
PE0/MD1
27
23
PE3/X1
22
P4D/TIOB4_0/SOT7_1/MAD07_1
P4E/TIOB5_0/INT06_2/SIN7_1/MAD08_1
26
21
P4C/TIOB3_0/SCK7_1/CEC0/MAD06_1
25
20
P4B/TIOB2_0/SEG29/MAD05_1
MD0
19
P4A/TIOB1_0/SCK3_2/SEG30/MAD04_1
PE2/X0
18
12
VSS
P49/TIOB0_0/SOT3_2/SEG31/MAD03_1
11
C
17
10
P45/TIOA5_0/SEG33/MAD01_1
16
9
P44/TIOA4_0/SEG34/MAD00_1
INITX
8
P43/TIOA3_0/ADTG_7
P48/INT14_1/SIN3_2/SEG32/MAD02_1
7
P42/TIOA2_0
15
6
P41/TIOA1_0/INT13_1
P47/X1A
5
P40/TIOA0_0/INT12_1
14
4
VCC
13
3
VSS
VCC
2
P3F/TIOA5_1/SEG35
P46/X0A
1
P3E/TIOA4_1/SEG36
QFP - 100
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05633 Rev *B
Page 9 of 131
MB9AA40NB Series
LQH080/ LQJ080
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1/MRDY_1
P61/SOT5_0/TIOB2_2/SEG00
P62/SCK5_0/ADTG_3/SEG01/MOEX_1
P63/INT03_0/SEG02/MWEX_1
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P0E/CTS4_0/TIOB3_2/SEG03/MDQM1_1
P0D/RTS4_0/TIOA3_2/SEG04/MDQM0_1
P0C/SCK4_0/TIOA6_1/MALE_1
P0B/SOT4_0/TIOB6_1/MCSX0_1
P0A/SIN4_0/INT00_2/MCSX1_1
P07/AN22/ADTG_0/SEG07/MCLKOUT_1
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_1
P01/TCK/SWCLK
P00/TRSTX/MCSX7_1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
(TOP VIEW)
VCC
1
60
P20/AN19/INT05_0/CROUT_0/SEG10/MAD24_1
P50/INT00_0/SIN3_1/VV4/MADATA00_1
2
59
P21/AN18/SIN0_0/INT06_1/WKUP2/SEG11
P51/INT01_0/SOT3_1/VV3/MADATA01_1
3
58
P22/AN17/SOT0_0/TIOB7_1/SEG12
P52/INT02_0/SCK3_1/VV2/MADATA02_1
4
57
P23/AN16/SCK0_0/TIOA7_1/SEG13
P53/SIN6_0/TIOA1_2/INT07_2/VV1/MADATA03_1
5
56
P1B/AN11/SOT4_1/SEG17/MAD19_1
P54/SOT6_0/TIOB1_2/VV0/MADATA04_1
6
55
P1A/AN10/SIN4_1/INT05_1/SEG18/MAD18_1
P55/SCK6_0/ADTG_1/SEG39/MADATA05_1
7
54
P19/AN09/SCK2_2/SEG19/MAD17_1
P56/INT08_2/SEG38/MADATA06_1
8
53
P18/AN08/SOT2_2/SEG20/MAD16_1
P30/TIOB0_1/INT03_2/COM7/MADATA07_1
9
52
AVSS
P31/TIOB1_1/SCK6_1/INT04_2/COM6/MADATA08_1
10
51
AVRH
P32/TIOB2_1/SOT6_1/INT05_2/COM5/MADATA09_1
11
50
AVCC
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/COM4/MADATA10_1
12
49
P17/AN07/SIN2_2/INT04_1/SEG21/MAD15_1
P39/ADTG_2/COM3
13
48
P16/AN06/SCK0_1/SEG22/MAD14_1
P3A/TIOA0_1/RTCCO_2/SUBOUT_2/COM2
14
47
P15/AN05/SOT0_1/SEG23/MAD13_1
P3B/TIOA1_1/COM1
15
46
P14/AN04/SIN0_1/INT03_1/SEG24/MAD12_1
P3C/TIOA2_1/COM0
16
45
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/SEG25/MAD11_1
P3D/TIOA3_1/SEG37
17
44
P12/AN02/SOT1_1/SEG26/MAD10_1
P3E/TIOA4_1/SEG36
18
43
P11/AN01/SIN1_1/INT02_1/WKUP1/SEG27/MAD09_1
P3F/TIOA5_1/SEG35
19
42
P10/AN00/SEG28
VSS
20
41
VCC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P44/TIOA4_0/SEG34/MAD00_1
P45/TIOA5_0/SEG33/MAD01_1
C
VSS
VCC
P46/X0A
P47/X1A
INITX
P48/INT14_1/SIN3_2/SEG32/MAD02_1
P49/TIOB0_0/SOT3_2/SEG31/MAD03_1
P4A/TIOB1_0/SCK3_2/SEG30/MAD04_1
P4B/TIOB2_0/SEG29/MAD05_1
P4C/TIOB3_0/SCK7_1/CEC0/MAD06_1
P4D/TIOB4_0/SOT7_1/MAD07_1
P4E/TIOB5_0/INT06_2/SIN7_1/MAD08_1
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 80
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05633 Rev *B
Page 10 of 131
MB9AA40NB Series
LQD064/ LQG064
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1
P61/SOT5_0/TIOB2_2/SEG00
P62/SCK5_0/ADTG_3/SEG01
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P0C/SCK4_0/TIOA6_1
P0B/SOT4_0/TIOB6_1
P0A/SIN4_0/INT00_2
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(TOP VIEW)
VCC
1
48
P21/AN18/SIN0_0/INT06_1/WKUP2/SEG11
P50/INT00_0/SIN3_1/VV4
2
47
P22/AN17/SOT0_0/TIOB7_1/SEG12
P51/INT01_0/SOT3_1
3
46
P23/AN16/SCK0_0/TIOA7_1/SEG13
P52/INT02_0/SCK3_1
4
45
P19/AN09/SCK2_2/SEG19
P30/TIOB0_1/INT03_2/COM7
5
44
P18/AN08/SOT2_2/SEG20
P31/TIOB1_1/SCK6_1/INT04_2/COM6
6
43
AVSS
P32/TIOB2_1/SOT6_1/INT05_2/COM5
7
42
AVRH
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/COM4
8
41
AVCC
P39/ADTG_2/COM3
9
40
P17/AN07/SIN2_2/INT04_1/SEG21
P3A/TIOA0_1/RTCCO_2/SUBOUT_2/COM2
10
39
P15/AN05/SEG23
P3B/TIOA1_1/COM1
11
38
P14/AN04/INT03_1/SEG24
P3C/TIOA2_1/COM0
12
37
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/SEG25
P3D/TIOA3_1/SEG37
13
36
P12/AN02/SOT1_1/SEG26
P3E/TIOA4_1/SEG36
14
35
P11/AN01/SIN1_1/INT02_1/WKUP1/SEG27
P3F/TIOA5_1/SEG35
15
34
P10/AN00/SEG28
VSS
16
33
VCC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0/SEG31
P4A/TIOB1_0/SEG30
P4B/TIOB2_0/SEG29
P4C/TIOB3_0/SCK7_1/CEC0
P4D/TIOB4_0/SOT7_1
P4E/TIOB5_0/INT06_2/SIN7_1
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 64
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05633 Rev *B
Page 11 of 131
MB9AA40NB Series
VNC064
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1
P61/SOT5_0/TIOB2_2/SEG00
P62/SCK5_0/ADTG_3/SEG01
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P0C/SCK4_0/TIOA6_1
P0B/SOT4_0/TIOB6_1
P0A/SIN4_0/INT00_2
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(TOP VIEW)
VCC
1
48
P21/AN18/SIN0_0/INT06_1/WKUP2/SEG11
P50/INT00_0/SIN3_1/VV4
2
47
P22/AN17/SOT0_0/TIOB7_1/SEG12
P51/INT01_0/SOT3_1
3
46
P23/AN16/SCK0_0/TIOA7_1/SEG13
P52/INT02_0/SCK3_1
4
45
P19/AN09/SCK2_2/SEG19
P30/TIOB0_1/INT03_2/COM7
5
44
P18/AN08/SOT2_2/SEG20
P31/TIOB1_1/SCK6_1/INT04_2/COM6
6
43
AVSS
P32/TIOB2_1/SOT6_1/INT05_2/COM5
7
42
AVRH
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/COM4
8
41
AVCC
P39/ADTG_2/COM3
9
40
P17/AN07/SIN2_2/INT04_1/SEG21
P3A/TIOA0_1/RTCCO_2/SUBOUT_2/COM2
10
39
P15/AN05/SEG23
P3B/TIOA1_1/COM1
11
38
P14/AN04/INT03_1/SEG24
P3C/TIOA2_1/COM0
12
37
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/SEG25
P3D/TIOA3_1/SEG37
13
36
P12/AN02/SOT1_1/SEG26
P3E/TIOA4_1/SEG36
14
35
P11/AN01/SIN1_1/INT02_1/WKUP1/SEG27
P3F/TIOA5_1/SEG35
15
34
P10/AN00/SEG28
VSS
16
33
VCC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0/SEG31
P4A/TIOB1_0/SEG30
P4B/TIOB2_0/SEG29
P4C/TIOB3_0/SCK7_1/CEC0
P4D/TIOB4_0/SOT7_1
P4E/TIOB5_0/INT06_2/SIN7_1
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
QFN - 64
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05633 Rev *B
Page 12 of 131
MB9AA40NB Series
LBC112
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
VSS
P81
P80
VCC
P0E
P0B
AN22
TMS/
SWDIO
TRSTX
VCC
VSS
B
VCC
VSS
P52
P61
P0F
P0C
AN23
TDO/
SWO
TCK/
SWCLK
VSS
TDI
C
P50
P51
VSS
P60
P62
P0D
P09
AN20
VSS
AN19
AN18
D
P53
P54
P55
VSS
P56
P63
P0A
VSS
AN21
AN16
AN15
E
P30
P31
P32
P33
Index
AN17
AN14
AN12
AN11
F
P34
P35
P36
P39
AN13
AN10
AN09
AVRH
G
P37
P38
P3A
P3D
AN08
AN07
AN06
AVSS
H
P3B
P3C
P3E
VSS
P44
P4C
AN05
VSS
AN04
AN03
AVCC
J
VCC
P3F
VSS
P40
P43
P49
P4D
AN02
VSS
AN01
AN00
K
VCC
VSS
X1A
INITX
P42
P48
P4B
P4E
MD1
VSS
VCC
L
VSS
C
X0A
VSS
P41
P45
P4A
MD0
X0
X1
VSS
PFBGA - 112
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05633 Rev *B
Page 13 of 131
MB9AA40NB Series
FDG096
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
VSS
P81
P80
VCC
VSS
P0F
VSS
AN22
TMS/
SWDIO
TRSTX
VSS
B
VCC
VSS
P52
P61
P63
P0D
P0C
TDO/
SWO
TCK/
SWCLK
VSS
TDI
C
P50
P51
VSS
P60
P62
P0E
P0B
P0A
VSS
AN19
AN18
D
P53
P54
P55
Index
AN17
AN16
VSS
E
P56
P30
P31
AN11
AN10
AN09
F
VSS
VSS
VSS
AN08
AN07
AVRH
G
P32
P33
P39
AN06
AN05
AVSS
H
P3A
P3B
P3C
AN04
AN03
AVCC
J
P3D
P3E
VSS
P3F
P48
P4A
P4D
AN02
VSS
AN01
AN00
K
VCC
VSS
X1A
INITX
P45
P49
P4C
P4E
MD1
VSS
VCC
L
VSS
C
X0A
VSS
P44
VSS
P4B
MD0
X0
X1
VSS
PFBGA - 96
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05633 Rev *B
Page 14 of 131
MB9AA40NB Series
4. List of Pin Functions
List of Pin Numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
LQFP-100
QFP-100
BGA-112
LQFP-80
BGA-96
1
79
B1
1
B1
2
80
C1
2
C1
LQFP-64
QFN-64
1
2
-
3
81
C2
3
C2
-
-
-
-
-
-
3
4
82
B3
4
B3
-
-
-
-
-
-
4
5
83
D1
5
D1
-
6
84
D2
6
D2
-
Document Number: 002-05633 Rev *B
Pin Name
VCC
P50
INT00_0
SIN3_1
VV4
MADATA00_1
P51
INT01_0
SOT3_1
(SDA3_1)
VV3
MADATA01_1
P51
INT01_0
SOT3_1
(SDA3_1)
P52
INT02_0
SCK3_1
(SCL3_1)
VV2
MADATA02_1
P52
INT02_0
SCK3_1
(SCL3_1)
P53
SIN6_0
TIOA1_2
INT07_2
VV1
MADATA03_1
P54
SOT6_0
(SDA6_0)
TIOB1_2
VV0
MADATA04_1
I/O Circuit
Type
Pin State
Type
-
J
Y
J
Y
E
L
J
Y
E
L
J
Y
J
X
Page 15 of 131
MB9AA40NB Series
Pin No
LQFP-100
QFP-100
BGA-112
LQFP-80
LQFP-64
QFN-64
BGA-96
7
85
D3
7
D3
-
8
86
D5
8
E1
-
9
87
E1
9
E2
5
-
10
88
E2
10
E3
6
-
11
89
E3
11
G1
7
-
12
90
E4
12
G2
8
13
91
F1
-
-
-
14
92
F2
-
-
-
Document Number: 002-05633 Rev *B
Pin Name
P55
SCK6_0
(SCL6_0)
ADTG_1
SEG39
MADATA05_1
P56
INT08_2
SEG38
MADATA06_1
P30
TIOB0_1
INT03_2
COM7
MADATA07_1
P31
TIOB1_1
SCK6_1
(SCL6_1)
INT04_2
COM6
MADATA08_1
P32
TIOB2_1
SOT6_1
(SDA6_1)
INT05_2
COM5
MADATA09_1
P33
INT04_0
TIOB3_1
SIN6_1
ADTG_6
COM4
MADATA10_1
P34
TIOB4_1
MADATA11_1
P35
TIOB5_1
INT08_1
MADATA12_1
I/O Circuit
Type
Pin State
Type
K
U
K
V
K
V
K
V
K
V
K
V
E
K
E
L
Page 16 of 131
MB9AA40NB Series
Pin No
LQFP-100
QFP-100
BGA-112
LQFP-80
LQFP-64
QFN-64
BGA-96
15
93
F3
-
-
-
-
-
-
-
F1
F2
F3
-
16
94
G1
-
-
-
17
95
G2
-
-
-
18
96
F4
13
G3
9
19
97
G3
14
H1
10
20
98
H1
15
H2
11
21
99
H2
16
H3
12
22
100
G4
17
J1
13
-
-
B2
-
B2
-
23
1
H3
18
J2
14
24
2
J2
19
J4
15
25
26
3
4
L1
J1
20
-
L1
-
16
-
Document Number: 002-05633 Rev *B
Pin Name
P36
SIN5_2
INT09_1
MADATA13_1
VSS
VSS
VSS
P37
SOT5_2
(SDA5_2)
INT10_1
MADATA14_1
P38
SCK5_2
(SCL5_2)
INT11_1
MADATA15_1
P39
ADTG_2
COM3
P3A
TIOA0_1
RTCCO_2
SUBOUT_2
COM2
P3B
TIOA1_1
COM1
P3C
TIOA2_1
COM0
P3D
TIOA3_1
SEG37
VSS
P3E
TIOA4_1
SEG36
P3F
TIOA5_1
SEG35
VSS
VCC
I/O Circuit
Type
Pin State
Type
E
L
-
E
L
E
L
K
U
K
U
K
U
K
U
K
U
K
U
K
U
-
Page 17 of 131
MB9AA40NB Series
Pin No
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-112
LQFP-80
BGA-96
27
5
J4
-
-
-
28
6
L5
-
-
-
29
7
K5
-
-
-
30
8
J5
-
-
-
31
9
H5
21
L5
-
32
10
L6
22
K5
-
33
34
35
11
12
13
K2
J3
H4
L2
L4
K1
23
24
25
K2
J3
L6
L2
L4
K1
17
18
36
14
L3
26
L3
19
37
15
K3
27
K3
20
38
16
K4
28
K4
21
39
17
K6
29
J5
-
22
40
18
J6
30
K6
-
Document Number: 002-05633 Rev *B
Pin Name
P40
TIOA0_0
INT12_1
P41
TIOA1_0
INT13_1
P42
TIOA2_0
P43
TIOA3_0
ADTG_7
P44
TIOA4_0
SEG34
MAD00_1
P45
TIOA5_0
SEG33
MAD01_1
VSS
VSS
VSS
VSS
C
VSS
VCC
P46
X0A
P47
X1A
INITX
P48
INT14_1
SIN3_2
SEG32
MAD02_1
P49
TIOB0_0
SEG31
SOT3_2
(SDA3_2)
MAD03_1
I/O Circuit
Type
Pin State
Type
E
L
E
L
E
K
E
K
K
U
K
U
D
F
D
G
B
C
K
V
K
U
Page 18 of 131
MB9AA40NB Series
Pin No
LQFP-100
QFP-100
BGA-112
LQFP-80
LQFP-64
QFN-64
BGA-96
23
41
19
L7
31
J6
-
42
20
K7
32
L7
24
-
43
21
H6
33
K7
25
-
44
22
J7
34
J7
26
-
45
23
K8
35
K8
27
46
24
K9
36
K9
28
47
25
L8
37
L8
29
48
26
L9
38
L9
30
49
27
L10
39
L10
31
50
28
L11
40
L11
32
51
29
K11
41
K11
33
52
30
J11
42
J11
34
53
31
J10
43
J10
35
-
Document Number: 002-05633 Rev *B
Pin Name
P4A
TIOB1_0
SEG30
SCK3_2
(SCL3_2)
MAD04_1
P4B
TIOB2_0
SEG29
MAD05_1
P4C
TIOB3_0
SCK7_1
(SCL7_1)
CEC0
MAD06_1
P4D
TIOB4_0
SOT7_1
(SDA7_1)
MAD07_1
P4E
TIOB5_0
INT06_2
SIN7_1
MAD08_1
MD1
PE0
MD0
X0
PE2
X1
PE3
VSS
VCC
P10
AN00
SEG28
P11
AN01
SIN1_1
INT02_1
I/O Circuit
Type
Pin State
Type
K
U
K
U
I*
S
I*
K
I*
L
C
E
G
D
A
A
A
B
L
W
L
R
WKUP1
SEG27
MAD09_1
Page 19 of 131
MB9AA40NB Series
Pin No
LQFP-100
QFP-100
BGA-112
LQFP-80
LQFP-64
QFN-64
BGA-96
54
32
J8
44
J8
-
-
K10
J9
-
K10
J9
55
33
H10
45
H10
36
-
37
-
38
56
34
H9
46
H9
-
39
57
35
H7
47
G10
-
58
36
G10
48
G9
59
37
G9
49
F10
60
61
62
38
39
40
H11
F11
G11
50
51
52
H11
F11
G11
Document Number: 002-05633 Rev *B
-
40
41
42
43
Pin Name
P12
AN02
SOT1_1
(SDA1_1)
SEG26
MAD10_1
VSS
VSS
P13
AN03
SCK1_1
(SCL1_1)
RTCCO_1
SEG25
SUBOUT_1
MAD11_1
P14
AN04
INT03_1
SEG24
SIN0_1
MAD12_1
P15
AN05
SEG23
SOT0_1
(SDA0_1)
MAD13_1
P16
AN06
SCK0_1
(SCL0_1)
SEG22
MAD14_1
P17
AN07
SIN2_2
INT04_1
SEG21
MAD15_1
AVCC
AVRH
AVSS
I/O Circuit
Type
Pin State
Type
L
W
-
L
W
L
N
L
W
L
W
L
N
-
Page 20 of 131
MB9AA40NB Series
Pin No
LQFP-100
63
QFP-100
41
BGA-112
G8
LQFP-80
53
LQFP-64
QFN-64
BGA-96
F9
44
-
45
64
42
F10
54
E11
-
-
H8
-
-
-
65
43
F9
55
E10
-
66
44
E11
56
E9
-
67
45
E10
-
-
-
68
46
F8
-
-
-
69
47
E9
-
-
-
70
48
D11
-
-
-
Document Number: 002-05633 Rev *B
Pin Name
P18
AN08
SOT2_2
(SDA2_2)
SEG20
MAD16_1
P19
AN09
SCK2_2
(SCL2_2)
SEG19
MAD17_1
VSS
P1A
AN10
SIN4_1
INT05_1
SEG18
MAD18_1
P1B
AN11
SOT4_1
(SDA4_1)
SEG17
MAD19_1
P1C
AN12
SCK4_1
(SCL4_1)
SEG16
MAD20_1
P1D
AN13
CTS4_1
SEG15
MAD21_1
P1E
AN14
RTS4_1
SEG14
MAD22_1
P1F
AN15
ADTG_5
MAD23_1
I/O Circuit
Type
Pin State
Type
L
W
L
W
-
L
N
L
W
L
W
L
W
L
W
F
M
Page 21 of 131
MB9AA40NB Series
Pin No
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-112
LQFP-80
BGA-96
-
-
B10
C9
-
-
B10
C9
D11
-
71
49
D10
57
D10
46
72
50
E8
58
D9
47
73
51
C11
59
C11
48
74
52
C10
60
C10
-
75
76
53
54
A11
A10
-
A11
-
-
77
55
A9
61
A10
49
-
78
56
B9
62
B9
79
57
B11
63
B11
50
51
-
80
58
A8
64
A9
52
81
59
B8
65
B8
53
Document Number: 002-05633 Rev *B
Pin Name
VSS
VSS
VSS
P23
AN16
SCK0_0
(SCL0_0)
TIOA7_1
SEG13
P22
AN17
SOT0_0
(SDA0_0)
TIOB7_1
SEG12
P21
AN18
SIN0_0
INT06_1
WKUP2
SEG11
P20
AN19
INT05_0
CROUT_0
SEG10
MAD24_1
VSS
VCC
P00
TRSTX
MCSX7_1
P01
TCK
SWCLK
P02
TDI
MCSX6_1
P03
TMS
SWDIO
P04
TDO
SWO
I/O Circuit
Type
Pin State
Type
-
L
W
L
W
L
R
L
N
E
J
E
J
E
J
E
J
E
J
Page 22 of 131
MB9AA40NB Series
Pin No
LQFP-100
QFP-100
BGA-112
LQFP-80
LQFP-64
QFN-64
BGA-96
82
60
C8
-
-
-
-
-
D8
-
-
-
83
61
D9
-
-
-
66
A8
84
62
A7
-
-
-
-
-
-
-
A7
-
85
63
B7
-
-
-
86
64
C7
-
-
-
87
65
D7
67
C8
54
-
Document Number: 002-05633 Rev *B
Pin Name
P05
AN20
TRACED0
TIOA5_2
SIN4_2
INT00_1
SEG09
MCSX5_1
VSS
P06
AN21
TRACED1
TIOB5_2
SOT4_2
(SDA4_2)
INT01_1
SEG08
MCSX4_1
P07
AN22
ADTG_0
SEG07
MCLKOUT_1
TRACED2
SCK4_2
(SCL4_2)
VSS
P08
AN23
TRACED3
TIOA0_2
CTS4_2
SEG06
MCSX3_1
P09
TRACECLK
TIOB0_2
RTS4_2
SEG05
MCSX2_1
P0A
SIN4_0
INT00_2
MCSX1_1
I/O Circuit
Type
Pin State
Type
L
Q
-
L
Q
L
P
-
L
P
K
O
I*
L
Page 23 of 131
MB9AA40NB Series
Pin No
LQFP-100
88
QFP-100
66
BGA-112
A6
LQFP-80
68
LQFP-64
QFN-64
BGA-96
C7
55
56
89
67
B6
69
B7
-
-
D4
C3
-
C3
-
90
68
C6
70
B6
-
91
69
A5
71
C6
-
-
-
-
-
A5
-
92
70
B5
72
A6
57
93
71
D6
73
B5
-
94
72
C5
74
C5
58
-
95
73
B4
Document Number: 002-05633 Rev *B
75
B4
59
Pin Name
P0B
SOT4_0
(SDA4_0)
TIOB6_1
MCSX0_1
P0C
SCK4_0
(SCL4_0)
TIOA6_1
MALE_1
VSS
VSS
P0D
RTS4_0
TIOA3_2
SEG04
MDQM0_1
P0E
CTS4_0
TIOB3_2
SEG03
MDQM1_1
VSS
P0F
NMIX
CROUT_1
RTCCO_0
SUBOUT_0
WKUP0
P63
INT03_0
SEG02
MWEX_1
P62
SCK5_0
(SCL5_0)
ADTG_3
SEG01
MOEX_1
P61
SOT5_0
(SDA5_0)
TIOB2_2
SEG00
I/O Circuit
Type
Pin State
Type
I*
K
I*
K
-
K
U
K
U
-
E
I
K
V
K
U
K
U
Page 24 of 131
MB9AA40NB Series
Pin No
LQFP-100
96
QFP-100
74
97
75
98
76
99
77
100
78
*: 5 V tolerant I/O
BGA-112
C4
A4
A3
A2
A1
Document Number: 002-05633 Rev *B
LQFP-80
76
77
78
79
80
BGA-96
C4
A4
A3
A2
A1
LQFP-64
QFN-64
60
61
62
63
64
Pin Name
P60
SIN5_0
TIOA2_2
INT15_1
WKUP3
CEC1
MRDY_1
VCC
P80
P81
VSS
I/O Circuit
Type
Pin State
Type
I*
T
H
H
-
H
H
-
Page 25 of 131
MB9AA40NB Series
List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
Pin
Function
Pin Name
ADC
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
Function Description
A/D converter external trigger
input pin
A/D converter analog input pin.
ANxx describes ADC ch.xx.
Document Number: 002-05633 Rev *B
LQFP100
QFP100
BGA112
LQFP80
84
7
18
94
70
12
30
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
71
72
73
74
82
83
84
85
62
85
96
72
48
90
8
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
49
50
51
52
60
61
62
63
A7
D3
F4
C5
D11
E4
J5
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
D10
E8
C11
C10
C8
D9
A7
B7
66
7
13
74
12
42
43
44
45
46
47
48
49
53
54
55
56
57
58
59
60
66
-
BGA96
A8
D3
G3
C5
G2
J11
J10
J8
H10
H9
G10
G9
F10
F9
E11
E10
E9
D10
D9
C11
C10
A8
-
LQFP/
QFN64
9
58
8
34
35
36
37
38
39
40
44
45
46
47
48
-
Page 26 of 131
MB9AA40NB Series
Pin No
Pin
Function
Base
Timer
0
Base
Timer
1
Base
Timer
2
Base
Timer
3
Base
Timer
4
Base
Timer
5
Base
Timer
6
Base
Timer
7
Pin Name
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_1
TIOB6_1
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
Function Description
QFP100
BGA112
LQFP80
Base timer ch.6 TIOA pin
27
19
85
40
9
86
28
20
5
41
10
6
29
21
96
42
11
95
30
22
90
43
12
91
31
23
44
13
32
24
82
45
14
83
89
5
97
63
18
87
64
6
98
83
19
88
84
7
99
74
20
89
73
8
100
68
21
90
69
9
1
22
91
10
2
60
23
92
61
67
J4
G3
B7
J6
E1
C7
L5
H1
D1
L7
E2
D2
K5
H2
C4
K7
E3
B4
J5
G4
C6
H6
E4
A5
H5
H3
J7
F1
L6
J2
C8
K8
F2
D9
B6
14
30
9
15
5
31
10
6
16
76
32
11
75
17
70
33
12
71
21
18
34
22
19
35
69
H1
K6
E2
H2
D1
J6
E3
D2
H3
C4
L7
G1
B4
J1
B6
K7
G2
C6
L5
J2
J7
K5
J4
K8
B7
10
22
5
11
23
6
12
60
24
7
59
13
25
8
14
26
15
27
56
Base timer ch.6 TIOB pin
88
66
A6
68
C7
55
71
72
-
49
50
-
D10
E8
-
57
58
-
D10
D9
-
46
47
-
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Document Number: 002-05633 Rev *B
BGA96
LQFP/
QFN64
LQFP100
Page 27 of 131
MB9AA40NB Series
Pin No
Pin
Function
Pin Name
SWCLK
SWDIO
Debugger
SWO
TCK
TDI
TDO
TMS
External
Bus
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRSTX
MAD00_1
MAD01_1
MAD02_1
MAD03_1
MAD04_1
MAD05_1
MAD06_1
MAD07_1
MAD08_1
MAD09_1
MAD10_1
MAD11_1
MAD12_1
MAD13_1
MAD14_1
MAD15_1
MAD16_1
MAD17_1
MAD18_1
MAD19_1
MAD20_1
MAD21_1
MAD22_1
MAD23_1
MAD24_1
Function Description
Serial wire debug interface
clock input pin
Serial wire debug interface
data input / output pin
Serial wire viewer output pin
JTAG test clock input pin
JTAG test data input pin
JTAG debug data output pin
JTAG test mode state
input/output pin
Trace CLK output pin of ETM
Trace data output pins of ETM
JTAG test reset input pin
External bus interface address
bus
Document Number: 002-05633 Rev *B
BGA96
LQFP/
QFN64
LQFP100
QFP100
BGA112
LQFP80
78
56
B9
62
B9
50
80
58
A8
64
A9
52
81
78
79
81
59
56
57
59
B8
B9
B11
B8
65
62
63
65
B8
B9
B11
B8
53
50
51
53
80
58
A8
64
A9
52
86
82
83
84
85
77
31
32
39
40
41
42
43
44
45
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
64
60
61
62
63
55
9
10
17
18
19
20
21
22
23
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
C7
C8
D9
A7
B7
A9
H5
L6
K6
J6
L7
K7
H6
J7
K8
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
C10
61
21
22
29
30
31
32
33
34
35
43
44
45
46
47
48
49
53
54
55
56
60
A10
L5
K5
J5
K6
J6
L7
K7
J7
K8
J10
J8
H10
H9
G10
G9
F10
F9
E11
E10
E9
C10
49
-
Page 28 of 131
MB9AA40NB Series
Pin No
Pin
Function
Pin Name
MCSX0_1
MCSX1_1
MCSX2_1
MCSX3_1
MCSX4_1
MCSX5_1
MCSX6_1
MCSX7_1
MDQM0_1
MDQM1_1
MOEX_1
MWEX_1
External
Bus
MADATA00_1
MADATA01_1
MADATA02_1
MADATA03_1
MADATA04_1
MADATA05_1
MADATA06_1
MADATA07_1
MADATA08_1
MADATA09_1
MADATA10_1
MADATA11_1
MADATA12_1
MADATA13_1
MADATA14_1
MADATA15_1
MALE_1
MRDY_1
MCLKOUT_1
Function Description
External bus interface chip
select output pin
External bus interface byte
mask signal output pin
External bus interface read
enable signal for SRAM
External bus interface write
enable signal for SRAM
External bus interface data bus
Address Latch enable signal
for multiplex
External RDY input signal
External bus clock output pin
Document Number: 002-05633 Rev *B
LQFP/
QFN64
LQFP100
QFP100
BGA112
LQFP80
BGA96
88
87
86
85
83
82
79
77
90
91
66
65
64
63
61
60
57
55
68
69
A6
D7
C7
B7
D9
C8
B11
A9
C6
A5
68
67
63
61
70
71
C7
C8
B11
A10
B6
C6
-
94
72
C5
74
C5
-
93
71
D6
73
B5
-
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
C1
C2
B3
D1
D2
D3
D5
E1
E2
E3
E4
F1
F2
F3
G1
G2
2
3
4
5
6
7
8
9
10
11
12
-
C1
C2
B3
D1
D2
D3
E1
E2
E3
G1
G2
-
-
89
67
B6
69
B7
-
96
84
74
62
C4
A7
76
66
C4
A8
-
Page 29 of 131
MB9AA40NB Series
Pin No
Pin
Function
External
Interrupt
Pin Name
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT02_0
INT02_1
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_1
INT06_2
INT07_2
INT08_1
INT08_2
INT09_1
INT10_1
INT11_1
INT12_1
INT13_1
INT14_1
INT15_1
NMIX
Function Description
External interrupt request 00
input pin
External interrupt request 01
input pin
External interrupt request 02
input pin
External interrupt request 03
input pin
External interrupt request 04
input pin
External interrupt request 05
input pin
External interrupt request 06
input pin
External interrupt request 07
input pin
External interrupt request 08
input pin
External interrupt request 09
input pin
External interrupt request 10
input pin
External interrupt request 11
input pin
External interrupt request 12
input pin
External interrupt request 13
input pin
External interrupt request 14
input pin
External interrupt request 15
input pin
Non-Maskable Interrupt input
pin
Document Number: 002-05633 Rev *B
LQFP/
QFN64
LQFP100
QFP100
BGA112
LQFP80
BGA96
2
82
87
3
83
4
53
93
56
9
12
59
10
74
65
11
73
45
80
60
65
81
61
82
31
71
34
87
90
37
88
52
43
89
51
23
C1
C8
D7
C2
D9
B3
J10
D6
H9
E1
E4
G9
E2
C10
F9
E3
C11
K8
2
67
3
4
43
73
46
9
12
49
10
60
55
11
59
35
C1
C8
C2
B3
J10
B5
H9
E2
G2
F10
E3
C10
E10
G1
C11
K8
2
54
3
4
35
38
5
8
40
6
7
48
27
5
83
D1
5
D1
-
14
8
92
86
F2
D5
8
E1
-
15
93
F3
-
-
-
16
94
G1
-
-
-
17
95
G2
-
-
-
27
5
J4
-
-
-
28
6
L5
-
-
-
39
17
K6
29
J5
-
96
74
C4
76
C4
60
92
70
B5
72
A6
57
Page 30 of 131
MB9AA40NB Series
Pin No
Pin
Function
GPIO
Pin Name
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
Function Description
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
Document Number: 002-05633 Rev *B
LQFP100
QFP100
BGA112
LQFP80
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
73
72
71
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
51
50
49
A9
B9
B11
A8
B8
C8
D9
A7
B7
C7
D7
A6
B6
C6
A5
B5
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
C10
C11
E8
D10
61
62
63
64
65
66
67
68
69
70
71
72
42
43
44
45
46
47
48
49
53
54
55
56
60
59
58
57
BGA96
A10
B9
B11
A9
B8
A8
C8
C7
B7
B6
C6
A6
J11
J10
J8
H10
H9
G10
G9
F10
F9
E11
E10
E9
C10
C11
D9
D10
LQFP/
QFN64
49
50
51
52
53
54
55
56
57
34
35
36
37
38
39
40
44
45
48
47
46
Page 31 of 131
MB9AA40NB Series
Pin No
Pin
Function
GPIO
Pin Name
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P60
P61
P62
P63
P80
P81
PE0
PE2
PE3
Function Description
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
General-purpose I/O port E
Document Number: 002-05633 Rev *B
LQFP100
QFP100
BGA112
LQFP80
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
36
37
39
40
41
42
43
44
45
2
3
4
5
6
7
8
96
95
94
93
98
99
46
48
49
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
5
6
7
8
9
10
14
15
17
18
19
20
21
22
23
80
81
82
83
84
85
86
74
73
72
71
76
77
24
26
27
E1
E2
E3
E4
F1
F2
F3
G1
G2
F4
G3
H1
H2
G4
H3
J2
J4
L5
K5
J5
H5
L6
L3
K3
K6
J6
L7
K7
H6
J7
K8
C1
C2
B3
D1
D2
D3
D5
C4
B4
C5
D6
A3
A2
K9
L9
L10
9
10
11
12
13
14
15
16
17
18
19
21
22
26
27
29
30
31
32
33
34
35
2
3
4
5
6
7
8
76
75
74
73
78
79
36
38
39
BGA96
E2
E3
G1
G2
G3
H1
H2
H3
J1
J2
J4
L5
K5
L3
K3
J5
K6
J6
L7
K7
J7
K8
C1
C2
B3
D1
D2
D3
E1
C4
B4
C5
B5
A3
A2
K9
L9
L10
LQFP/
QFN64
5
6
7
8
9
10
11
12
13
14
15
19
20
22
23
24
25
26
27
2
3
4
60
59
58
62
63
28
30
31
Page 32 of 131
MB9AA40NB Series
Pin No
Pin
Function
Pin Name
SIN0_0
SIN0_1
SOT0_0
(SDA0_0)
Multifunction
Serial
0
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
SIN1_1
SOT1_1
(SDA1_1)
Multifunction
Serial
1
SCK1_1
(SCL1_1)
Function Description
Multi-function serial interface
ch.0 input pin
Multi-function serial interface
ch.0 output pin.
This pin operates as SOT0
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SDA0 when it is
used in an I2C (operation mode
4).
Multi-function serial interface
ch.0 clock I/O pin.
This pin operates as SCK0
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SCL0 when it is
used in an I2C (operation mode
4).
Multi-function serial interface
ch.1 input pin
Multi-function serial interface
ch.1 output pin.
This pin operates as SOT1
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SDA1 when it is
used in an I2C (operation mode
4).
Multi-function serial interface
ch.1 clock I/O pin.
This pin operates as SCK1
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SCL1 when it is
used in an I2C (operation mode
4).
Document Number: 002-05633 Rev *B
LQFP100
QFP100
BGA112
LQFP80
73
56
51
34
C11
H9
59
46
C11
H9
LQFP/
QFN64
48
-
72
50
E8
58
D9
47
57
35
H7
47
G10
-
71
49
D10
57
D10
46
58
36
G10
48
G9
-
53
31
J10
43
J10
35
54
32
J8
44
J8
36
55
33
H10
45
H10
37
BGA96
Page 33 of 131
MB9AA40NB Series
Pin No
Pin
Function
Pin Name
SIN2_2
SOT2_2
(SDA2_2)
Multifunction
Serial
2
SCK2_2
(SCL2_2)
SIN3_1
SIN3_2
SOT3_1
(SDA3_1)
Multifunction
Serial
3
SOT3_2
(SDA3_2)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Function Description
Multi-function serial interface
ch.2 input pin
Multi-function serial interface
ch.2 output pin.
This pin operates as SOT2
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SDA2 when it is
used in an I2C (operation mode
4).
Multi-function serial interface
ch.2 clock I/O pin.
This pin operates as SCK2
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SCL2 when it is
used in an I2C (operation mode
4).
Multi-function serial interface
ch.3 input pin
Multi-function serial interface
ch.3 output pin.
This pin operates as SOT3
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SDA3 when it is
used in an I2C (operation mode
4).
Multi-function serial interface
ch.3 clock I/O pin.
This pin operates as SCK3
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SCL3 when it is
used in an I2C (operation mode
4).
Document Number: 002-05633 Rev *B
LQFP/
QFN64
LQFP100
QFP100
BGA112
LQFP80
BGA96
59
37
G9
49
F10
40
63
41
G8
53
F9
44
64
42
F10
54
E11
45
2
39
80
17
C1
K6
2
29
C1
J5
2
-
3
81
C2
3
C2
3
40
18
J6
30
K6
-
4
82
B3
4
B3
4
41
19
L7
31
J6
-
Page 34 of 131
MB9AA40NB Series
Pin No
Pin
Function
Pin Name
SIN4_0
SIN4_1
SIN4_2
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
Multifunction
Serial
4
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
SIN5_2
SOT5_0
(SDA5_0)
Multifunction
Serial
5
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_2
(SCL5_2)
Function Description
Multi-function serial interface
ch.4 input pin
Multi-function serial interface
ch.4 output pin.
This pin operates as SOT4
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SDA4 when it is
used in an I2C (operation mode
4).
Multi-function serial interface
ch.4 clock I/O pin.
This pin operates as SCK4
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SCL4 when it is
used in an I2C (operation mode
4).
Multi-function serial interface
ch.4 RTS output pin
Multi-function serial interface
ch.4 CTS input pin
Multi-function serial interface
ch.5 input pin
Multi-function serial interface
ch.5 output pin.
This pin operates as SOT5
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SDA5 when it is
used in an I2C (operation mode
4).
Multi-function serial interface
ch.5 clock I/O pin.
This pin operates as SCK5
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SCL5 when it is
used in an I2C (operation mode
4).
Document Number: 002-05633 Rev *B
LQFP100
QFP100
BGA112
LQFP80
87
65
82
65
43
60
D7
F9
C8
67
55
-
C8
E10
-
LQFP/
QFN64
54
-
88
66
A6
68
C7
55
66
44
E11
56
E9
-
83
61
D9
-
-
-
89
67
B6
69
B7
56
67
45
E10
-
-
-
84
62
A7
-
-
-
90
69
86
91
68
85
96
15
68
47
64
69
46
63
74
93
C6
E9
C7
A5
F8
B7
C4
F3
70
71
76
-
B6
C6
C4
-
60
-
95
73
B4
75
B4
59
16
94
G1
-
-
-
94
72
C5
74
C5
58
17
95
G2
-
-
-
BGA96
Page 35 of 131
MB9AA40NB Series
Pin No
Pin
Function
Pin Name
SIN6_0
SIN6_1
SOT6_0
(SDA6_0)
Multifunction
Serial
6
SOT6_1
(SDA6_1)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
SIN7_1
SOT7_1
(SDA7_1)
Multifunction
Serial
7
SCK7_1
(SCL7_1)
Function Description
Multi-function serial interface
ch.6 input pin
Multi-function serial interface
ch.6 output pin.
This pin operates as SOT6
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SDA6 when it is
used in an I2C (operation mode
4).
Multi-function serial interface
ch.6 clock I/O pin.
This pin operates as SCK6
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SCL6 when it is
used in an I2C (operation mode
4).
Multi-function serial interface
ch.7 input pin
Multi-function serial interface
ch.7 output pin.
This pin operates as SOT7
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SDA7 when it is
used in an I2C (operation mode
4).
Multi-function serial interface
ch.7 clock I/O pin.
This pin operates as SCK7
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SCL7 when it is
used in an I2C (operation mode
4).
Document Number: 002-05633 Rev *B
LQFP/
QFN64
LQFP100
QFP100
BGA112
LQFP80
BGA96
5
12
83
90
D1
E4
5
12
D1
G2
8
6
84
D2
6
D2
-
11
89
E3
11
G1
7
7
85
D3
7
D3
-
10
88
E2
10
E3
6
45
23
K8
35
K8
27
44
22
J7
34
J7
26
43
21
H6
33
K7
25
Page 36 of 131
MB9AA40NB Series
Pin No
Pin
Function
Real-time
clock
Pin Name
RTCCO_0
RTCCO_1
RTCCO_2
SUBOUT_0
SUBOUT_1
SUBOUT_2
WKUP0
WKUP1
Low-Power
Consumption
Mode
WKUP2
WKUP3
HDMICEC/
Remote
Control
Reception
0.5 seconds pulse output pin of
Real-time clock
Sub clock output pin
Deep standby mode return
signal input pin 0
Deep standby mode return
signal input pin 1
Deep standby mode return
signal input pin 2
Deep standby mode return
signal input pin 3
LQFP100
QFP100
BGA112
LQFP80
92
55
19
92
55
19
70
33
97
70
33
97
B5
H10
G3
B5
H10
G3
72
45
14
72
45
14
A6
H10
H1
A6
H10
H1
LQFP/
QFN64
57
37
10
57
37
10
92
70
B5
72
A6
57
53
31
J10
43
J10
35
73
51
C11
59
C11
48
96
74
C4
76
C4
60
BGA96
CEC0
HDMI-CEC/RemoteControl
Reception ch.0 input/output pin
43
21
H6
33
K7
25
CEC1
HDMI-CEC/RemoteControl
Reception ch.1 input/output pin
96
74
C4
76
C4
60
VV0
6
84
D2
6
D2
-
VV1
5
83
D1
5
D1
-
4
82
B3
4
B3
-
VV3
3
81
C2
3
C2
-
VV4
2
80
C1
2
C1
2
COM0
21
99
H2
16
H3
12
COM1
20
98
H1
15
H2
11
COM2
19
97
G3
14
H1
10
18
96
F4
13
G3
9
COM4
12
90
E4
12
G2
8
COM5
11
89
E3
11
G1
7
COM6
10
88
E2
10
E3
6
COM7
9
87
E1
9
E2
5
VV2
LCDC
Function Description
LCD drive power supply pin
COM3
LCD common output pin
Document Number: 002-05633 Rev *B
Page 37 of 131
MB9AA40NB Series
Pin No
Pin
Function
LCDC
Pin Name
SEG00
SEG01
SEG02
SEG03
SEG04
SEG05
SEG06
SEG07
SEG08
SEG09
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
Function Description
LCD segment output pin
Document Number: 002-05633 Rev *B
LQFP100
QFP100
BGA112
LQFP80
95
94
93
91
90
86
85
84
83
82
74
73
72
71
69
68
67
66
65
64
63
59
58
57
56
55
54
53
52
42
41
40
39
32
31
24
23
22
8
7
73
72
71
69
68
64
63
62
61
60
52
51
50
49
47
46
45
44
43
42
41
37
36
35
34
33
32
31
30
20
19
18
17
10
9
2
1
100
86
85
B4
C5
D6
A5
C6
C7
B7
A7
D9
C8
C10
C11
E8
D10
E9
F8
E10
E11
F9
F10
G8
G9
G10
H7
H9
H10
J8
J10
J11
K7
L7
J6
K6
L6
H5
J2
H3
G4
D5
D3
75
74
73
71
70
66
60
59
58
57
56
55
54
53
49
48
47
46
45
44
43
42
32
31
30
29
22
21
19
18
17
8
7
BGA96
B4
C5
B5
C6
B6
A8
C10
C11
D9
D10
E9
E10
E11
F9
F10
G9
G10
H9
H10
J8
J10
J11
L7
J6
K6
J5
K5
L5
J4
J2
J1
E1
D3
LQFP/
QFN64
59
58
48
47
46
45
44
40
39
38
37
36
35
34
24
23
22
15
14
13
-
Page 38 of 131
MB9AA40NB Series
Pin No
Pin
Function
Reset
Pin Name
INITX
MD0
Mode
MD1
Power
GND
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Function Description
External Reset Input pin.
A reset is valid when INITX=L.
Mode 0 pin.
During normal operation,
MD0=L must be input. During
serial programming to Flash
memory, MD0=H must be
input.
Mode 1 pin.
During serial programming to
Flash memory, MD1=L must
be input.
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
Document Number: 002-05633 Rev *B
BGA96
LQFP/
QFN64
LQFP100
QFP100
BGA112
LQFP80
38
16
K4
28
K4
21
47
25
L8
37
L8
29
46
24
K9
36
K9
28
1
26
35
51
76
97
25
34
50
75
100
79
4
13
29
54
75
3
12
28
53
78
B1
J1
K1
K11
A10
A4
B2
L1
K2
J3
H4
L4
L11
K10
J9
H8
B10
C9
A11
D8
D4
C3
A1
1
25
41
77
20
24
40
80
B1
K1
K11
A4
F1
F2
F3
B2
L1
K2
J3
L6
L4
L11
K10
J9
B10
C9
D11
A11
A7
C3
A5
A1
1
18
33
61
16
32
64
Page 39 of 131
MB9AA40NB Series
Pin No
Pin
Function
Pin Name
X0
Clock
ADC
power
X0A
X1
X1A
CROUT_0
CROUT_1
AVCC
AVRH
Function Description
Main clock (oscillation) input
pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc
clock output port
A/D converter analog power
supply pin
A/D converter analog
reference voltage input pin
BGA96
LQFP/
QFN64
LQFP100
QFP100
BGA112
LQFP80
48
26
L9
38
L9
30
36
49
37
74
92
14
27
15
52
70
L3
L10
K3
C10
B5
26
39
27
60
72
L3
L10
K3
C10
A6
19
31
20
57
60
38
H11
50
H11
41
61
39
F11
51
F11
42
ADC
GND
AVSS
A/D converter GND pin
62
40
G11
52
G11
43
C pin
C
Power supply stabilization
capacity pin
33
11
L2
23
L2
17
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-05633 Rev *B
Page 40 of 131
MB9AA40NB Series
5. I/O Circuit Type
Type
A
Circuit
Remarks
It is possible to select the main
oscillation / GPIO function
When the main oscillation is selected.
Pull-up
−
resistor
P-ch
Oscillation feedback resistor
: Approximately 1 MΩ
P-ch
Digital output
X1
−
With Standby mode control
When the GPIO is selected.
N-ch
Digital output
R
−
CMOS level output.
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 33 kΩ
Pull-up resistor control
−
IOH= -4 mA, IOL= 4 mA
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Digital output
Pull-up
resistor
R
P-ch
P-ch
X0
N-ch
Digital output
Pull-up resistor control
Document Number: 002-05633 Rev *B
Page 41 of 131
MB9AA40NB Series
Type
B
Circuit
Remarks
−
CMOS level hysteresis input
−
Pull-up resistor
: Approximately 33 kΩ
Pull-up resistor
Digital input
C
Digital input
N-ch
Document Number: 002-05633 Rev *B
−
Open drain output
−
CMOS level hysteresis input
Digital output
Page 42 of 131
MB9AA40NB Series
Type
D
Circuit
Remarks
It is possible to select the sub
oscillation / GPIO function
Pull-up
When the sub oscillation is selected.
resistor
P-ch
−
P-ch
Digital output
X1A
Oscillation feedback resistor
: Approximately 5 MΩ
−
With Standby mode control
When the GPIO is selected.
N-ch
Digital output
R
−
CMOS level output.
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Pull-up resistor control
Digital input
: Approximately 33 kΩ
−
IOH= -4 mA, IOL= 4 mA
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
Document Number: 002-05633 Rev *B
Page 43 of 131
MB9AA40NB Series
Type
E
Circuit
P-ch
P-ch
Remarks
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Digital output
: Approximately 33 kΩ
−
IOH= -4 mA, IOL= 4 mA
−
When this pin is used as an I2C pin, the
digital output P-ch transistor is always off
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
F
P-ch
P-ch
Digital output
−
CMOS level output
−
CMOS level hysteresis input
−
With input control
−
Analog input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 33 kΩ
N-ch
Digital output
−
IOH= -4 mA, IOL= 4 mA
−
When this pin is used as an I2C pin, the
digital output P-ch transistor is always off
R
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
Document Number: 002-05633 Rev *B
Page 44 of 131
MB9AA40NB Series
Type
G
Circuit
Remarks
CMOS level hysteresis input
Mode input
H
P-ch
N-ch
−
CMOS level output
−
CMOS level hysteresis input
−
With standby mode control
−
IOH = - 12.0 mA, IOL = 10.5 mA
−
CMOS level output
−
CMOS level hysteresis input
−
5 V tolerant
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Digital output
Digital output
R
Digital input
Standby mode control
I
P-ch
P-ch
Digital output
: Approximately 33 kΩ
N-ch
Digital output
−
IOH= -4 mA, IOL= 4 mA
−
Available to control PZR registers.
−
When this pin is used as an I2C pin, the
digital output P-ch transistor is always off
R
Pull-up resistor control
Digital input
Standby mode control
Document Number: 002-05633 Rev *B
Page 45 of 131
MB9AA40NB Series
Type
J
Circuit
P-ch
P-ch
Remarks
Digital output
−
CMOS level output
−
CMOS level hysteresis input
−
With input control
−
LCD-VV input/output
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 33 kΩ
N-ch
Digital output
−
IOH= -4 mA, IOL= 4 mA
−
When this pin is used as an I2C pin, the
digital output P-ch transistor is always off
Pull-up resistor control
R
Digital input
Standby mode control
LCD VV
input/output
LCD VV control
K
P-ch
P-ch
Digital output
−
CMOS level output
−
CMOS level hysteresis input
−
With input control
−
LCD output
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 33 kΩ
N-ch
Digital output
−
IOH= -4 mA, IOL= 4 mA
−
When this pin is used as an I2C pin, the
digital output P-ch transistor is always off
R
Pull-up resistor control
Digital input
Standby mode control
LCD output
LCD control
Document Number: 002-05633 Rev *B
Page 46 of 131
MB9AA40NB Series
Type
L
Circuit
P-ch
P-ch
Remarks
Digital output
−
CMOS level output
−
CMOS level hysteresis input
−
With input control
−
Analog input
−
LCD output
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 33 kΩ
N-ch
Digital output
−
IOH= -4 mA, IOL= 4 mA
−
When this pin is used as an I2C pin, the
digital output P-ch transistor is always off
R
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
LCD output
LCD control
Document Number: 002-05633 Rev *B
Page 47 of 131
MB9AA40NB Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-05633 Rev *B
Page 48 of 131
MB9AA40NB Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-05633 Rev *B
Page 49 of 131
MB9AA40NB Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
Document Number: 002-05633 Rev *B
Page 50 of 131
MB9AA40NB Series
6.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-05633 Rev *B
Page 51 of 131
MB9AA40NB Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and
GND pin, between AVCC pin and AVSS pin near this device.
Stabilizing supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
Surface mount type
Size:
Load capacitance:
More than 3.2 mm × 1.5 mm
Approximately 6 pF to 7 pF
Lead type
Load capacitance:
Approximately 6 pF to 7 pF
Document Number: 002-05633 Rev *B
Page 52 of 131
MB9AA40NB Series
Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3)
can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to
X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Can be used as
general-purpose
I/O ports.
X1(PE3),X1A(P47)
Set as
External clock
input
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to
keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.A smoothing capacitor of about 4.7 μF would be recommended for this
series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Document Number: 002-05633 Rev *B
Page 53 of 131
MB9AA40NB Series
Notes on power-on
Turn power-on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC →AVCC → AVRH
Turning off : AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash memory
products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash memory products and MASK products are different because chip
layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up function of 5 V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.
Document Number: 002-05633 Rev *B
Page 54 of 131
MB9AA40NB Series
8. Block Diagram
TRSTX,TCK,
TDI,TMS
TDO
TRACEDx,
TRACECLK
ETM*1
SWJ-DP
TPIU*
SRAM0
8/16 Kbyte
ROM
Table
1
Multi-layer AHB (Max 40 MHz)
Cortex-M3 Core I
@40 MHz(Max)
D
NVIC
Sys
AHB-APB Bridge:
APB0(Max 40 MHz)
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
SRAM1
8/16 Kbyte
On-Chip Flash
64+32 Kbyte/
128+32 Kbyte/
256+32 Kbyte
Flash I/F
Security
DMAC
8ch.
CSV
X0
X1
X0A
X1A
CROUT
Main
Osc
Sub
Osc
PLL
CR
4 MHz
AHB-AHB
Bridge
CLK
Source Clock
CR
100 kHz
MADx
External Bus I/F*2
ADTGx
TIOAx
TIOBx
VVx
COMx,
SEGx
CEC0,CEC1
RTCCO,
SUBOUT
WKUPx
Unit 0
Unit 1
Base Timer
16-bit 8ch./
32-bit 4ch.
Power-On
Reset
LVD Ctrl
LVD
Regulator
C
CRC
Accelerator
Watch Counter
External Interrupt
Controller
16-pin + NMI
INTx
NMIX
MODE-Ctrl
MD0,
MD1
P0x,
P1x,
LCDC
GPIO
PIN-Function-Ctrl
HDMI-CEC/
Remote Reciver Control
Real-Time Clock
MCSXx,
MOEX,
MWEX,
MALE,
MRDY,
MCLKOUT,
MDQMx
IRQ-Monitor
AHB-APB Bridge : APB2 (Max 40 MHz)
ANxx
MADATAx
12-bit A/D Converter
AHB-APB Bridge : APB1 (Max 40 MHz)
AVCC,
AVSS,
AVRH
.
.
.
PEx
Multi-Function Serial I/F
8ch.
(with FIFO ch.4 to ch.7)
HW flow control(ch.4)*2
Deep Standby Ctrl
SCKx
SINx
SOTx
CTS4
RTS4
*1: For the MB9AFA41LB/MB, MB9AFA42LB/MB, and MB9AFA44LB/MB, ETM is not available.
*2: For the MB9AFA41LB, MB9AFA42LB and MB9AFA44LB, the External Bus Interface is not available. And the Multi-function
Serial Interface does not support hardware flow control in these products.
Document Number: 002-05633 Rev *B
Page 55 of 131
MB9AA40NB Series
9. Memory Size
See Memory size in Product Lineup to confirm the memory size.
Document Number: 002-05633 Rev *B
Page 56 of 131
MB9AA40NB Series
10. Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
0x4005_0000
0x4004_0000
0x4003_F000
Reserved
0x4003_C000
0x4003_B000
0x4003_A000
0x7000_0000
0x6000_0000
External Device
Area
Reserved
0x4003_9000
0x4003_8000
0x4003_7000
0x4003_6000
0x4003_5000
0x4400_0000
0x4200_0000
0x4000_0000
32Mbytes
Bit band alias
Peripherals
Reserved
0x2400_0000
0x2200_0000
0x1FFF_0000
0x0020_8000
0x0020_0000
See the next page
"lMemory Map (2)"
for the memory size
details.
0x0010_4000
0x0010_0000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
32Mbytes
Bit band alias
Reserved
0x2008_0000
0x2000_0000
0x4003_4000
0x4002_8000
DMAC
Reserved
EXT-bus I/F
Reserved
RTC
Watch Counter
CRC
MFS
Reserved
LVD/DS mode
HDMI-CEC/
Remote Control Receiver
GPIO
LCDC
Int-Req.Read
EXTI
Reserved
CR Trim
Reserved
0x4002_7000
A/DC
0x4002_6000
Reserved
0x4002_5000
Base Timer
SRAM1
SRAM0
Reserved
Flash(Work area)
Reserved
Security/CR Trim
Reserved
0x4001_6000
0x4001_5000
Flash(Main area)
0x0000_0000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
0x4000_1000
0x4000_0000
Document Number: 002-05633 Rev *B
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
Page 57 of 131
MB9AA40NB Series
Memory Map (2)
MB9AFA44LB/MB/NB
MB9AFA42LB/MB/NB
0x2008_0000
MB9AFA41LB/MB/NB
0x2008_0000
Reserved
0x2008_0000
Reserved
Reserved
0x2000_4000
0x2000_2000
SRAM1
16Kbytes
0x2000_0000
0x2000_0000
SRAM0
16Kbytes
0x1FFF_E000
0x2000_2000
SRAM1
8Kbytes
SRAM0
8Kbytes
0x2000_0000
0x1FFF_E000
SRAM1
8Kbytes
SRAM0
8Kbytes
0x1FFF_C000
SA4-7 (8 KBx4)
Reserved
0x0010_4000
0x0010_2000
0x0010_0000
0x0020_0000
SA4-7 (8 KBx4)
Reserved
0x0010_4000
CR trimming
Security
0x0010_2000
0x0010_0000
0x0020_8000
0x0020_0000
SA4-7 (8 KBx4)
Reserved
Flash(Work area)
32 Kbytes
0x0020_0000
0x0020_8000
Reserved
Flash(Work area)
32 Kbytes
0x0020_8000
Reserved
Flash(Work area)
32 Kbytes
Reserved
0x0010_4000
CR trimming
Security
0x0010_2000
0x0010_0000
CR trimming
Security
Reserved
Reserved
Reserved
0x0000_0000
SA2-3 (8 KBx2)
SA9 (64 KB)
SA8 (48 KB)
0x0000_0000
SA2-3 (8 KBx2)
0x0001_0000
SA8 (48 KB)
0x0000_0000
Flash(Main area)
64 Kbytes
SA8 (48 KB)
0x0002_0000
Flash(Main area)
128 Kbytes
SA9-11 (64 KBx3)
Flash(Main area)
256 Kbytes
0x0004_0000
SA2-3 (8 KBx2)
Refer to the programming manual for the detail of Flash main area.
MB9AB40N/A40N/340N/140N/150R,MB9B520M/320M/120M Series Flash Programming Manual
Document Number: 002-05633 Rev *B
Page 58 of 131
MB9AA40NB Series
Peripheral Address Map
Start address
End address
Bus
Peripherals
0x4000_0000
0x4000_0FFF
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
0x4001_5000
0x4001_5FFF
Dual Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_4FFF
Reserved
0x4002_5000
0x4002_5FFF
Base Timer
0x4002_6000
0x4002_6FFF
Reserved
0x4002_7000
0x4002_7FFF
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Built-in CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt
0x4003_1000
0x4003_1FFF
Interrupt Source Check Register
0x4003_2000
0x4003_2FFF
LCDC
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
HDMI-CEC/Remote control Receiver
0x4003_5000
0x4003_57FF
Low-Voltage Detector
0x4003_5800
0x4003_5FFF
0x4003_6000
0x4003_7FFF
0x4003_8000
0x4003_8FFF
Multi-function serial
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_BFFF
Real-time clock
0x4003_C000
0x4003_EFFF
Reserved
0x4003_F000
0x4003_FFFF
External Memory interface
0x4004_0000
0x4005_FFFF
0x4006_0000
0x4006_0FFF
0x4006_1000
0x41FF_FFFF
Document Number: 002-05633 Rev *B
AHB
APB0
APB1
APB2
Flash memory I/F register
Reserved
Software Watchdog timer
Reserved
A/D Converter
Deep stand-by mode Controller
Reserved
Reserved
AHB
DMAC register
Reserved
Page 59 of 131
MB9AA40NB Series
11. Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the L level.
INITX=1
This is the period when the INITX pin is the H level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the
output follows the peripheral function. If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
Document Number: 002-05633 Rev *B
Page 60 of 131
MB9AA40NB Series
Pin status type
List of Pin Status
A
Function
group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
INITX
input
state
Device
internal
reset
state
Power supply stable
INITX = 0
-
INITX = 1
-
Run
mode or
Sleep
mode
state
Power
supply
stable
INITX = 1
-
Timer mode,
RTC mode, or
Sleep mode state
Deep standby RTC
mode or Deep standby
Stop mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL=1
Return
from
Deep
standby
mode
state
Power
supply
stable
INITX = 1
-
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Main
crystal
oscillator
input pin/
External
main clock
input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
External
main clock
input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
Maintain
previous
state
Maintain
previous
state/Wh
en
oscillatio
n stops*1,
Hi-Z /
Internal
input
fixed at 0
Maintain
previous
state/Wh
en
oscillatio
n stops*1,
Hi-Z /
Internal
input
fixed at 0
Maintain
previous
state/Wh
en
oscillatio
n stops*1,
Hi-Z /
Internal
input
fixed at 0
Maintain
previous
state/Wh
en
oscillatio
n stops*1,
Hi-Z /
Internal
input
fixed at 0
Maintain
previous
state/Wh
en
oscillatio
n stops*1,
Hi-Z /
Internal
input
fixed at 0
B
Main
crystal
oscillator
output pin
Hi-Z /
Internal
input fixed
at 0/
or Input
enabled
Hi-Z /
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
Maintain
previous
state/Wh
en
oscillatio
n stops*1,
Hi-Z /
Internal
input
fixed at 0
C
INITX
input pin
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
D
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Document Number: 002-05633 Rev *B
Page 61 of 131
Pin status type
MB9AA40NB Series
Function
group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
INITX
input
state
Device
internal
reset
state
Run
mode or
Sleep
mode
state
INITX = 0
-
INITX = 1
-
Power
supply
stable
INITX = 1
-
Power supply stable
Timer mode,
RTC mode, or
Sleep mode state
Deep standby RTC
mode or Deep standby
Stop mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL=1
Return
from
Deep
standby
mode
state
Power
supply
stable
INITX = 1
-
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
enabled
GPIO
selected
Hi-Z /
Input
enabled
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
E
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Sub crystal
oscillator
input pin /
External sub
clock input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
F
Document Number: 002-05633 Rev *B
Page 62 of 131
Pin status type
MB9AA40NB Series
Function
group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
INITX
input
state
Device
internal
reset
state
Power supply stable
INITX = 0
-
INITX = 1
-
Run
mode or
Sleep
mode
state
Power
supply
stable
INITX = 1
-
Timer mode,
RTC mode, or
Sleep mode state
Deep standby RTC
mode or Deep standby
Stop mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL=1
Return
from
Deep
standby
mode
state
Power
supply
stable
INITX = 1
-
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
External sub
clock input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Hi-Z/
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state/Wh
en
oscillatio
n stops*2,
Hi-Z /
Internal
input
fixed at 0
Maintain
previous
state/Wh
en
oscillatio
n stops*2,
Hi-Z /
Internal
input
fixed at 0
Maintain
previous
state/Wh
en
oscillatio
n stops*2,
Hi-Z/
Internal
input
fixed at 0
Maintain
previous
state/Wh
en
oscillatio
n stops*2,
Hi-Z/
Internal
input
fixed at 0
Maintain
previous
state/Wh
en
oscillatio
n stops*2,
Hi-Z/
Internal
input
fixed at 0
G
Sub crystal
oscillator
output pin
Hi-Z /
Internal
input fixed
at 0/
or Input
enable
Hi-Z /
Internal
input
fixed at 0
Document Number: 002-05633 Rev *B
Hi-Z /
Internal
input
fixed at 0
Page 63 of 131
Pin status type
MB9AA40NB Series
H
I
Function
group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
INITX
input
state
INITX = 0
-
INITX = 1
-
Hi-Z /
Input
enabled
Maintain
previous
state
Setting
disabled
GPIO
selected
Hi-Z
NMIX
selected
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
Pull-up /
Input
enabled
Pull-up /
Input
enabled
GPIO
selected
JTAG
selected
J
GPIO
selected
K
Resource
selected
GPIO
selected
Run
mode or
Sleep
mode
state
Power
supply
stable
INITX = 1
-
Power supply stable
Hi-Z /
Input
enabled
Resource
other than
above
selected
Device
internal
reset
state
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Document Number: 002-05633 Rev *B
Timer mode,
RTC mode, or
Sleep mode state
Deep standby RTC
mode or Deep standby
Stop mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL=1
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
Power
supply
stable
INITX = 1
-
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Return
from
Deep
standby
mode
state
GPIO
selected
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Page 64 of 131
Pin status type
MB9AA40NB Series
L
Function
group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
External
interrupt
enabled
selected
Resource
other than
above
selected
Setting
disabled
Power supply stable
INITX = 0
-
INITX = 1
-
Setting
disabled
Setting
disabled
N
Power
supply
stable
INITX = 1
-
Timer mode,
RTC mode, or
Sleep mode state
Deep standby RTC
mode or Deep standby
Stop mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL=1
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Power
supply
stable
INITX = 1
-
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Hi-Z
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Hi-Z
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
External
interrupt
enabled
selected
Resource
other than
above
selected
Hi-Z /
Internal
input
fixed at 0
Return
from
Deep
standby
mode
state
Hi-Z /
Input
enabled
GPIO
selected
Analog
input
selected
Run
mode or
Sleep
mode
state
Hi-Z /
Input
enabled
M
Resource
other than
above
selected
Device
internal
reset
state
Hi-Z
GPIO
selected
Analog
input
selected
INITX
input
state
Maintain
previous
state
Setting
disabled
Setting
disabled
GPIO
selected
Document Number: 002-05633 Rev *B
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
Page 65 of 131
Pin status type
MB9AA40NB Series
Function
group
Power
supply
unstable
-
Trace
selected
O
Power-on
reset or
low-voltage
detection
state
Setting
disabled
Resource
other than
above
selected
P
Device
internal
reset
state
Power supply stable
INITX = 0
-
INITX = 1
-
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z /
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
Hi-Z
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
GPIO
selected
Analog
input
selected
INITX
input
state
Run
mode or
Sleep
mode
state
Power
supply
stable
INITX = 1
-
Timer mode,
RTC mode, or
Sleep mode state
Deep standby RTC
mode or Deep standby
Stop mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL=1
Power
supply
stable
INITX = 1
-
Trace
output
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Trace
selected
Resource
other than
above
selected
Return
from
Deep
standby
mode
state
Hi-Z /
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Trace
output
Setting
disabled
Setting
disabled
GPIO
selected
Document Number: 002-05633 Rev *B
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
Page 66 of 131
Pin status type
MB9AA40NB Series
Function
group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
Analog
input
selected
Hi-Z
INITX
input
state
Device
internal
reset
state
Run
mode or
Sleep
mode
state
INITX = 0
-
INITX = 1
-
Power
supply
stable
INITX = 1
-
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Power supply stable
Timer mode,
RTC mode, or
Sleep mode state
Deep standby RTC
mode or Deep standby
Stop mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL=1
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Trace
selected
Q
External
interrupt
enabled
selected
Resource
other than
above
selected
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Return
from
Deep
standby
mode
state
Power
supply
stable
INITX = 1
-
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Trace
output
Setting
disabled
Setting
disabled
GPIO
selected
Document Number: 002-05633 Rev *B
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
Page 67 of 131
Pin status type
MB9AA40NB Series
Function
group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
Analog
input
selected
Hi-Z
INITX
input
state
Device
internal
reset
state
Run
mode or
Sleep
mode
state
INITX = 0
-
INITX = 1
-
Power
supply
stable
INITX = 1
-
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Power supply stable
Timer mode,
RTC mode, or
Sleep mode state
Deep standby RTC
mode or Deep standby
Stop mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL=1
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
WKUP
enabled
Maintain
previous
state
R
External
interrupt
enabled
selected
Resource
other than
above
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
CEC
enabled
S
Resource
other than
above
selected
GPIO
selected
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
WKUP
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
WKUP
input
enabled
Return
from
Deep
standby
mode
state
Power
supply
stable
INITX = 1
-
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Document Number: 002-05633 Rev *B
Page 68 of 131
Pin status type
MB9AA40NB Series
Function
group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
CEC
enabled
Setting
disabled
INITX
input
state
Device
internal
reset
state
Power supply stable
INITX = 0
-
INITX = 1
-
Setting
disabled
Setting
disabled
Run
mode or
Sleep
mode
state
Power
supply
stable
INITX = 1
-
Maintain
previous
state
Timer mode,
RTC mode, or
Sleep mode state
Deep standby RTC
mode or Deep standby
Stop mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL=1
Maintain
previous
state
WKUP
enabled
T
External
interrupt
enabled
selected
Resource
other than
above
selected
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
Hi-Z /
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
Setting
disabled
Setting
disabled
Setting
disabled
Resource
selected
V
GPIO
selected
External
interrupt
enabled
selected
Resource
other than
above
selected
GPIO
selected
Maintain
previous
state
Setting
disabled
Maintain
previous
state
GPIO
selected
U
Setting
disabled
Hi-Z
Hi-Z /
Internal
input
fixed at 0
Document Number: 002-05633 Rev *B
Hi-Z /
Internal
input
fixed at 0
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
Maintain
previous
state
WKUP
input
enabled
Maintain
previous
state
Hi-Z /
WKUP
input
enabled
Return
from
Deep
standby
mode
state
Power
supply
stable
INITX = 1
-
Maintain
previous
state
GPIO
selected
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Page 69 of 131
Pin status type
MB9AA40NB Series
Function
group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
Analog
input
selected
Hi-Z
W
Resource
other than
above
selected
INITX
input
state
Device
internal
reset
state
X
GPIO
selected
Timer mode,
RTC mode, or
Sleep mode state
Deep standby RTC
mode or Deep standby
Stop mode state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL=1
Return
from
Deep
standby
mode
state
INITX = 0
-
INITX = 1
-
Power
supply
stable
INITX = 1
-
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Maintain
previous
state
Hi-Z /
Internal
input
fixed at 0
GPIO
selected
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
Power supply stable
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Hi-Z
Hi-Z /
Internal
input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
Maintain
previous
state
GPIO
selected
Resource
selected
Run
mode or
Sleep
mode
state
Power
supply
stable
INITX = 1
-
External
Maintain
interrupt
Setting
Setting
Setting
previous
enabled
disabled
disabled
disabled
state
GPIO
selected
Hi-Z /
Hi-Z /
Maintain
Maintain
selected
Resource
Internal
Internal
Y
previous
previous
Internal
other than
input
input
Hi-Z /
Hi-Z /
Hi-Z / Internal input
state
state
above
fixed at 0 fixed at 0
Internal
Internal
Hi-Z
input fixed at fixed at 0
selected
input
input
0
fixed at 0 fixed at 0
GPIO
selected
*1: Oscillation is stopped at Sub Timer mode, Low-Speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and
Deep Standby Stop mode.
*2: Oscillation is stopped at Stop mode and Deep Standby Stop mode.
Document Number: 002-05633 Rev *B
Page 70 of 131
MB9AA40NB Series
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Power supply voltage*1, *2
Analog power supply voltage*1, *3
Analog reference voltage*1, *3
LCD input voltage *1, *3
Input voltage*1
Symbol
VCC
AVCC
AVRH
VV0 to
VV4
VI
Rating
Max
VSS + 4.6
VSS + 4.6
VSS + 4.6
V
V
V
VSS - 0.5
VSS + 4.6
V
VSS - 0.5
VSS - 0.5
Analog pin input
voltage*1
Unit
Min
VSS - 0.5
VSS - 0.5
VSS - 0.5
VIA
VSS - 0.5
Output voltage*1
VO
VSS - 0.5
L level maximum output current*4
IOL
-
VCC + 0.5
(≤ 4.6 V)
VSS + 6.5
AVCC + 0.5
(≤ 4.6 V)
VCC + 0.5
(≤ 4.6 V)
10
39
4
L level average output current*5
IOLAV
10.5
L level total maximum output current
∑IOL
100
L level total average output current*6
∑IOLAV
50
- 10
H level maximum output current*4
IOH
39
-4
5
H level average output current*
IOHAV
12
H level total maximum output current
∑IOH
- 100
H level total average output current*6
∑IOHAV
- 50
Power consumption
PD
300
Storage temperature
TSTG
- 55
+ 150
*1: These parameters are based on the condition that VSS = AVSS = 0 V.
Remarks
V
V
5 V tolerant
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
P81, P80 pins
P81, P80 pins
P81, P80 pins
P81, P80 pins
*2: VCC must not drop below VSS - 0.5 V.
*3: Ensure that the voltage does not to exceed VCC + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100
ms period.
*6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms.
WARNING:
−
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
Document Number: 002-05633 Rev *B
Page 71 of 131
MB9AA40NB Series
12.2 Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Parameter
Symbol
Conditions
Power supply voltage
VCC
-
LCD input voltage
Analog power supply voltage
VVV4
AVCC
-
AVRH
-
AVRL
CS
TA
--
Analog reference voltage
Smoothing capacitor
Operating temperature
*1: When LCD Controller is used.
Value
Min
1.65*4
2.2*4
2.2
1.65
2.7
AVCC
AVSS
1
- 40
Max
3.6
3.6
VCC
3.6
AVCC
AVCC
AVSS
10
+ 85
Unit
V
V
V
V
V
V
µF
°C
Remarks
*1
*2
AVCC = VCC
AVCC ≥ 2.7 V
AVCC< 2.7 V
For Regulator*3
*2: When LCD Controller is not used.
*3: See C Pin in Handling Devices for the connection of the smoothing capacitor.
*4: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction
execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is
possible to operate only.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-05633 Rev *B
Page 72 of 131
MB9AA40NB Series
12.3 DC Characteristics
12.3.1 Current rating
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
Pin
name
Conditions
PLL
Run mode
High-speed
CR
Run mode
ICC
Power
supply
current
VCC
ICCS
Sub
Run mode
Low-speed
CR
Run mode
PLL
Sleep mode
High-speed
CR
Sleep mode
Sub
Sleep mode
Low-speed
CR
Sleep mode
Typ*3
Max*4
Unit
Remarks
CPU: 40 MHz,
Peripheral: 40 MHz
15.5
21
mA
*1, *5
CPU: 40 MHz,
Peripheral: the clock stops
NOP operation
8.7
12
mA
*1, *5
CPU/ Peripheral: 4 MHz*2
1.8
2.9
mA
*1
CPU/ Peripheral: 32 kHz
110
680
μA
*1, *6
CPU/ Peripheral: 100 kHz
125
700
μA
*1
Peripheral: 40 MHz
9
12.5
mA
*1, *5
Peripheral: 4 MHz*2
0.8
1.6
mA
*1
Peripheral: 32 kHz
96
670
μA
*1, *6
Peripheral: 100 kHz
110
680
μA
*1
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=3.6 V
*4: TA=+85°C, VCC=3.6 V
*5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
Document Number: 002-05633 Rev *B
Page 73 of 131
MB9AA40NB Series
Parameter
Symbol
ICC
Power
supply
current
Value
Pin
name
VCC
ICCS
Conditions
PLL
Run mode
CPU: 40 MHz,
Peripheral: 40 MHz
CPU: 40 MHz,
Peripheral: the clock stops
NOP operation
High-speed
CR
Run mode
Sub
Run mode
Low-speed
CR
Run mode
PLL
Sleep mode
High-speed
CR
Sleep mode
Sub
Sleep mode
Low-speed
CR
Sleep mode
Typ*3
Max*4
Unit
Remarks
15.5
21
mA
*1, *5
8.7
12
mA
*1, *5
CPU/ Peripheral: 4 MHz*2
1.8
2.9
mA
*1
CPU/ Peripheral: 32 kHz
110
680
μA
*1, *6
CPU/ Peripheral: 100 kHz
125
700
μA
*1
Peripheral: 40 MHz
9
12.5
mA
*1, *5
Peripheral: 4 MHz*2
0.8
1.6
mA
*1
Peripheral: 32 kHz
96
670
μA
*1, *6
Peripheral: 100 kHz
110
680
μA
*1
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=3.6 V
*4: TA=+85°C, VCC=3.6 V
*5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
Document Number: 002-05633 Rev *B
Page 74 of 131
MB9AA40NB Series
Parameter
Symbol
Pin
name
Main Timer
mode
ICCT
Sub Timer
mode
ICCR
RTC mode
ICCH
Power supply
current
Stop mode
VCC
ICCHD
ICCRD
Value
Typ*2
Max*2
Conditions
Deep
Standby
Stop mode
Deep
Standby
RTC mode
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off,
When RAM is off
TA = + 25°C,
When LVD is off,
When RAM is on
TA = + 85°C,
When LVD is off,
When RAM is off
TA = + 85°C,
When LVD is off,
When RAM is on
TA = + 25°C,
When LVD is off,
When RAM is off
TA = + 25°C,
When LVD is off,
When RAM is on
TA = + 85°C,
When LVD is off,
When RAM is off
TA = + 85°C,
When LVD is off,
When RAM is on
Unit
Remarks
2.1
2.5
mA
*1, *3
-
3.4
mA
*1, *3
12
35
μA
*1, *4
-
330
μA
*1, *4
9.8
29
μA
*1, *4
-
280
μA
*1, *4
9
28
μA
*1
-
270
μA
*1
1.25
7
μA
*1, *4, *5
5.3
18
μA
*1, *4, *5
70
μA
*1, *4, *5
100
μA
*1, *4, *5
1.9
9
μA
*1, *5
5.9
20
μA
*1, *5
75
μA
*1, *5
105
μA
*1, *5
-
-
*1: When all ports are fixed.
*2: VCC=3.6 V
*3: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
*5: RAM on/off setting is on-chip SRAM only.
Document Number: 002-05633 Rev *B
Page 75 of 131
MB9AA40NB Series
Low-Voltage Detection Current
(VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Low-voltage
detection circuit
(LVD) power
supply current
Pin
name
Symbol
ICCLVD
Conditions
Value
Typ
Max
Unit
Remarks
At operation
for reset
VCC = 3.6 V
0.13
0.3
μA
At not detect
At operation
for interrupt
VCC = 3.6 V
0.13
0.3
μA
At not detect
VCC
Flash Memory Current
(VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Flash memory
write/erase
current
Pin
name
Symbol
ICCFLASH
VCC
Value
Conditions
At Write/Erase
Typ
9.5
Max
11.2
Unit
mA
Remarks
*
*: The current at which to write or erase Flash memory, ICCFLASH is added to ICC.
A/D Converter Current
(VCC = VCC28 = AVCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = AVSS = 0V, TA = - 40°C to +85°C)
Parameter
Power supply
current
Reference power
supply current
Pin
name
Symbol
ICCAD
ICCAVRH
AVCC
AVRH
Document Number: 002-05633 Rev *B
Conditions
Value
Typ
Max
Unit
At 1unit
operation
0.27
0.42
mA
At stop
0.03
10
μA
At 1unit
operation
AVRH=3.6 V
0.72
1.29
mA
At stop
0.02
2.6
μA
Remarks
Page 76 of 131
MB9AA40NB Series
12.3.2 Pin Characteristics
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
H level input
voltage
(hysteresis
input)
L level input
voltage
(hysteresis
input)
Symbol
Pin name
CMOS
hysteresis
input pin, MD0,
MD1
VIHS
5V tolerant
input pin
CMOS
hysteresis
input pin, MD0,
MD1
Min
VCC ≥ 2.7 V
VCC × 0.8
VCC < 2.7 V
VCC × 0.7
VCC ≥ 2.7 V
VCC × 0.8
VCC < 2.7 V
Typ
Max
Unit
-
VCC + 0.3
V
-
VSS + 5.5
V
Remarks
VCC × 0.7
VCC ≥ 2.7 V
VCC × 0.2
VSS - 0.3
-
V
VCC < 2.7 V
VCC × 0.3
VCC ≥ 2.7 V
VCC × 0.2
VILS
5V tolerant
input pin
4 mA type
H level
output voltage
Conditions
VOH
VSS - 0.3
-
VCC < 2.7 V
V
VCC × 0.3
VCC ≥ 2.7 V,
IOH = - 4 mA
VCC - 0.5
VCC < 2.7 V,
IOH = - 2 mA
VCC - 0.45
-
VCC
V
VCC - 0.4
-
VCC
V
VSS
-
0.4
V
VSS
-
0.4
V
VCC = AVCC =
AVRH = VSS =
AVSS = 0.0 V
-5
-
+5
μA
-
-
+1.8
μA
VCC ≥ 2.7 V
21
33
66
VCC < 2.7 V
-
-
134
-
-
5
15
VCC ≥ 2.7 V,
IOH = - 12 mA
P80/P81
VCC < 2.7 V,
IOH = - 6.5 mA
VCC ≥ 2.7 V,
IOL = 4 mA
4 mA type
L level
output voltage
VOL
P80/P81
Input leak
current
Pull-up
resistor value
Input
capacitance
IIL
RPU
CIN
CEC0,
CEC1
VCC < 2.7 V,
IOL = 2 mA
VCC ≥ 2.7 V,
IOL = 10.5 mA
VCC < 2.7 V,
IOL = 5 mA
Pull-up pin
Other than
VCC,
VSS,
AVCC,
AVSS, AVRH
Document Number: 002-05633 Rev *B
kΩ
pF
Page 77 of 131
MB9AA40NB Series
12.4 LCD Characteristics
(VCC = 2.2V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
VV0 to VV3
Output voltage
(1/4 bias)
VV0 to VV3
Output voltage
(1/3 bias)
VV0 to VV3
Output voltage
(1/2 bias)
Symbol
Pin name
VVV0
VV0
VVV1
VV1
VVV2
VV2
VVV3
VV3
VVV0
VV0
VVV1
VV1
VVV2
VV2
VVV3
VV3
VVV0
VV0
VVV1
VV1
VVV2
VV2
VVV3
VV3
IR100K
VV4
IR10K
VV4
IR100K
VV4
IR10K
VV4
IR100K
VV4
IR10K
VV4
VV4
Static current
IOFF_VV4
VV4
VV0
Output Voltage
in using
external resistor
VVV0E
VV0
VV4
Active current
(1/4 bias)
VV4
Active current
(1/3 bias)
VV4
Active current
(1/2 bias)
Document Number: 002-05633 Rev *B
Conditions
0
When using
internal
dividing
resistor
VVV4 × 1/4
-10%
VVV4 × 1/2
-10%
VVV4 × 3/4
-10%
0
When using
internal
dividing
resistor
VVV4 × 1/3
-10%
VVV4 × 2/3
-10%
VVV4 × 2/3
-10%
0
When using
internal
dividing
resistor
When using
100 kΩ internal
dividing
resistor
When using
10 kΩ internal
dividing
resistor
When using
100 kΩ internal
dividing
resistor
When using
10 kΩ internal
dividing
resistor
When using
100 kΩ internal
dividing
resistor
When using
10 kΩ internal
dividing
resistor
Value
Typ
Min
VVV4 × 1/2
-10%
VVV4 × 1/2
-10%
VVV4 × 1/2
-10%
-
Max
Unit
Remarks
VVV4 × 5%
VVV4 × 1/4
+10%
VVV4 × 1/2
+10%
VVV4 × 3/4
+10%
V
VVV4 × 5%
VVV4 × 1/3
+10%
VVV4 × 2/3
+10%
VVV4 × 2/3
+10%
V
VVV4 × 5%
VVV4 × 1/2
+10%
VVV4 × 1/2
+10%
VVV4 × 1/2
+10%
V
-
10
20
μA
-
100
160
μA
-
12
30
μA
-
120
180
μA
-
18
40
μA
-
180
270
μA
When LCD
stops
-
0.5
1.5
μA
IOL=1 mA
-
-
0.66
V
Page 78 of 131
MB9AA40NB Series
12.5 AC Characteristics
12.5.1 Main Clock Input Characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Input frequency
Input clock cycle
Input clock pulse
width
Input clock rising
time and falling
time
Pin
name
Symbol
Value
Conditions
Min
Max
Unit
Remarks
VCC ≥ 2.7 V
VCC < 2.7 V
4
4
48
20
MHz
When crystal
oscillator is connected
-
4
48
MHz
When using external
clock
-
20.83
250
ns
-
PWH/tCYLH,
PWL/tCYLH
45
55
%
tCF,
tCR
-
-
5
ns
-
-
40
MHz
fCH
tCYLH
fCM
X0,
X1
-
When using external
clock
When using external
clock
When using external
clock
Master clock
Base clock
fCC
40
MHz
(HCLK/FCLK)
Internal operating
fCP0
40
MHz
APB0 bus clock*2
clock*1 frequency
fCP1
40
MHz
APB1 bus clock*2
fCP2
40
MHz
APB2 bus clock*2
Base clock
25
ns
tCYCC
(HCLK/FCLK)
Internal operating
25
ns
APB0 bus clock*2
t
CYCP0
clock*1 cycle time
25
ns
APB1 bus clock*2
tCYCP1
25
ns
APB2 bus clock*2
tCYCP2
*1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
*2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet.
N
divider
Document Number: 002-05633 Rev *B
Page 79 of 131
MB9AA40NB Series
12.5.2 Sub Clock Input Characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Input frequency
Input clock cycle
Input clock pulse
width
Symbol
Pin
name
fCL
tCYLL
X0A,
X1A
-
Value
Conditions
Min
Typ
Max
Unit
Remarks
-
-
32.768
-
kHz
-
32
-
100
kHz
When crystal oscillator is
connected
When using external clock
PWH/tCYLL,
PWL/tCYLL
10
-
31.25
μs
When using external clock
45
-
55
%
When using external clock
X0A
12.5.3 Built-in CR Oscillation Characteristics
Built-in High-speed CR
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Clock frequency
Symbol
fCRH
Conditions
Value
Min
Typ
Max
TA = + 25°C
VCC ≥ 2.7 V
3.96
4
4.04
TA = + 25°C
VCC < 2.7 V
3.9
4
4.1
TA = - 40°C to + 85°C
3.84
4
4.16
Unit
MHz
Remarks
When trimming*1
TA = - 40°C to + 85°C 2.8
5.2
When not trimming
Frequency
tCRWT
30
μs
*2
stabilization time
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming.
*2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value.
This period is able to use High-speed CR clock as source clock.
Built-in Low-speed CR
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Clock frequency
Symbol
fCRL
Document Number: 002-05633 Rev *B
Conditions
-
Value
Min
50
Typ
100
Max
150
Unit
Remarks
kHz
Page 80 of 131
MB9AA40NB Series
12.5.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
PLL oscillation stabilization wait time*1
(LOCK UP time)
PLL input clock frequency
PLL multiple rate
Symbol
Min
Value
Typ
Max
Unit
tLOCK
100
-
-
μs
fPLLI
4
5
-
16
37
MHz
multip
le
MHz
MHz
-
-
PLL macro oscillation clock frequency
fPLLO
75
150
Main PLL clock frequency*2
fCLKPLL
40
*1: Time from when the PLL starts operating until the oscillation stabilizes.
Remarks
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
12.5.5 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input
clock of the Main PLL)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
PLL oscillation stabilization wait time*1
(LOCK UP time)
PLL input clock frequency
PLL multiple rate
Symbol
Value
Min
Typ
Max
Unit
tLOCK
100
-
-
μs
fPLLI
3.8
19
4
4.2
35
MHz
multip
le
MHz
MHz
-
-
PLL macro oscillation clock frequency
fPLLO
72
150
Main PLL clock frequency*2
fCLKPLL
40
*1: Time from when the PLL starts operating until the oscillation stabilizes.
Remarks
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
Note:
−
Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency/temperature has been
trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account
and prevent the master clock from exceeding the maximum frequency.
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
Document Number: 002-05633 Rev *B
K
divider
PLL input
clock
PLL macro
oscillation clock
Main
PLL
M
divider
Main PLL
clock
(CLKPLL)
Page 81 of 131
MB9AA40NB Series
12.5.6 Reset Input Characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Pin
name
Symbol
Reset input time
tINITX
INITX
Value
Conditions
Min
-
Unit
Max
500
-
Remarks
ns
12.5.7 Power-on Reset Timing
(VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Power supply shut down time
Pin name
Value
Conditions
tOFF
Min
Typ
Max
1
-
-
-
Unit
ms
Remarks
*1
Power ramp rate
dV/dt
Vcc:0.2 V to 1.65 V
0.2
1000
mV/μs *2
VCC
Time until releasing Power-on
tPRT
1.34
16.09
ms
reset
*1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1 ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per “12. 5. 6.Reset
Input Characteristics”.
1.65V
VCC
VDH
0.2V
dV/dt
0.2V
tPRT
Internal RST
CPU Operation
RST Active
0.2V
tOFF
release
start
Glossary:
VDH: detection voltage of Low Voltage detection reset. See “12.7 Low-Voltage Detection Characteristics”
Document Number: 002-05633 Rev *B
Page 82 of 131
MB9AA40NB Series
12.5.8 External Bus Timing
External bus clock output characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
Unit
VCC ≥ 2.7 V
40
MHz
VCC < 2.7 V
20
MHz
*: The external bus clock output (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see Chapter 12: External Bus Interface in FM3 Family Peripheral Manual.
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
Output frequency
tCYCLE
MCLKOUT*
MCLKOUT
External bus signal input/output characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
VIH
Value
Unit
0.8 × VCC
V
0.2 × VCC
V
VOH
0.8 × VCC
V
VOL
0.2 × VCC
V
Remarks
Signal input characteristics
VIL
Signal output characteristics
Input signal
VIH
VIL
VIH
VIL
Output signal
VOH
VOL
VOH
VOL
Document Number: 002-05633 Rev *B
Page 83 of 131
MB9AA40NB Series
Separate Bus Access Asynchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
MOEX
Min pulse width
MCSX ↓ → Address
output delay time
MOEX ↑ →
Address hold time
MCSX ↓ →
MOEX ↓ delay time
MOEX ↑ →
MCSX ↑ time
MCSX ↓ →
MDQM ↓ delay time
Data set up →
MOEX ↑ time
MOEX ↑ →
Data hold time
MWEX
Min pulse width
MWEX ↑ → Address
output delay time
MCSX ↓ →
MWEX ↓ delay time
MWEX ↑ →
MCSX ↑ delay time
Symbol
tOEW
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
tDH - OE
Pin name
MWEX,
MCSX[7:0]
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
MCSX,
MDQM[1:0]
MCSX,
MADATA[15:0]
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
MOEX
MCSX[7:0],
MAD[24:0]
MOEX,
MAD[24:0]
MOEX,
MCSX[7:0]
MCSX,
MDQM[1:0]
MOEX,
MADATA[15:0]
MOEX,
MADATA[15:0]
tWEW
MWEX
tWEH - AX
MWEX,
MAD[24:0]
tCSL - WEL
tWEH - CSH
MCSX ↓→
tCSL-WDQML
MDQM ↓ delay time
MWEX ↓→
tCSL - DV
Data output time
Value
Conditions
Min
Unit
MCLK×n-3
-
-9
-12
MCLK×m-9
MCLK×m-12
30
38
+9
+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
0
-
ns
MCLK×n-3
-
ns
0
MCLK×m-9
MCLK×m-12
0
0
MCLK×n-9
MCLK×n-12
0
MCLK×n-9
MCLK×n-12
MCLK-9
MCLK-12
VCC ≥ 2.7 V
MWEX ↑ →
MWEX,
tWEH - DX
0
Data hold time
MADATA[15:0]
VCC < 2.7 V
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
Document Number: 002-05633 Rev *B
Max
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MCLK+12
MCLK×m+9
MCLK×m+12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 84 of 131
MB9AA40NB Series
MCLK
MCSX[7:0]
MAD[24:0]
MOEX
MDQM[1:0]
MWEX
MADATA[15:0]
Document Number: 002-05633 Rev *B
Page 85 of 131
MB9AA40NB Series
Separate Bus Access Synchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Address delay time
Symbol
tAV
tCSL
MCSX delay time
tCSH
tREL
MOEX delay time
tREH
Data set up →
MCLK ↑ time
MCLK ↑ →
Data hold time
tDS
tDH
tWEL
MWEX delay time
tWEH
MDQM[1:0]
delay time
tDQML
tDQMH
Pin name
MCLK,
MAD[24:0]
MCLK,
MCSX[7:0]
MCLK,
MOEX
MCLK,
MADATA[15:0]
MCLK,
MADATA[15:0]
MCLK,
MWEX
MCLK,
MDQM[1:0]
MCLK ↑ →
MCLK,
tODS
Data output time
MADATA[15:0]
MCLK ↑ →
MCLK,
tOD
Data hold time
MADATA[15:0]
Note:
−
When the external load capacitance CL = 30 pF.
Value
Conditions
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC <2.7 V
VCC ≥ 2.7 V
VCC <2.7 V
Min
Max
Unit
1
12
13
ns
1
12
ns
1
12
ns
1
1
9
12
9
12
ns
ns
24
37
-
ns
0
-
ns
1
1
1
1
MCLK + 1
1
9
12
9
12
9
12
9
12
MCLK + 18
MCLK + 24
18
24
ns
ns
ns
ns
ns
ns
MCLK
MCSX[7:0]
MAD[24:0]
MOEX
MDQM[1:0]
MWEX
MADATA[15:0]
Document Number: 002-05633 Rev *B
Page 86 of 131
MB9AA40NB Series
Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Multiplexed
address delay time
tALE-CHMADV
Multiplexed
address hold time
tCHMADH
Pin name
VCC ≥ 2.7 V
MALE,
MADATA[15:0]
Value
Conditions
VCC < 2.7 V
Min
-2
Max
+10
+20
VCC ≥ 2.7 V
MCLK×n+0
MCLK×n+10
VCC < 2.7 V
MCLK×n+0
MCLK×n+20
Unit
ns
ns
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-05633 Rev *B
Page 87 of 131
MB9AA40NB Series
Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
tCHAL
MALE delay time
tCHAH
MCLK ↑ →
Multiplexed
Address delay time
tCHMADV
MCLK ↑ →
Multiplexed
Data output time
tCHMADX
Pin name
MCLK,
ALE
Value
Conditions
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
Min
Max
Unit
9
12
9
12
ns
ns
ns
ns
1
tOD
ns
1
tOD
ns
1
1
Remarks
VCC ≥ 2.7 V
MCLK,
MADATA[15:0]
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
Note:
−
When the external load capacitance CL = 30 pF.
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-05633 Rev *B
Page 88 of 131
MB9AA40NB Series
External Ready Input Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
MCLK ↑
MRDY input
setup time
tRDYI
Pin name
MCLK,
MRDY
Value
Conditions
Min
VCC ≥ 2.7 V
23
VCC < 2.7 V
37
Unit
Max
-
Remarks
ns
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
MCLK
··· ···
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
Document Number: 002-05633 Rev *B
Page 89 of 131
MB9AA40NB Series
12.5.9 Base Timer Input Timing
Timer input timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
TIOAn/TIOBn
(when using as
ECK, TIN)
tTIWH,
tTIWL
-
tTIWH
Value
Min
2tCYCP
Max
-
Unit
Remarks
ns
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
tTRGH,
tTRGL
Pin name
Conditions
TIOAn/TIOBn
(when using
as TGIN)
tTRGH
TGIN
VIHS
-
Value
Min
2tCYCP
Max
-
Unit
Remarks
ns
tTRGL
VIHS
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet.
Document Number: 002-05633 Rev *B
Page 90 of 131
MB9AA40NB Series
12.5.10 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Conditions
-
Baud rate
-
-
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
SCKx
SCKx
,
SOTx
SCKx
,
SINx
SCKx
,
SINx
Serial clock L pulse width
tSLSH
Serial clock H pulse width
tSHSL
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
Notes:
VCC ≥ 2.7 V
VCC < 2.7 V
Min
Max
Min
Max
Unit
-
8
-
8
Mbps
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
36
-
ns
0
-
0
-
ns
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
SCKx
SCKx
,
SOTx
SCKx
,
SINx
SCKx
,
SINx
SCKx
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
-
50
-
33
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Master
mode
Slave mode
−
−
The above characteristics apply to clock synchronous mode.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this
data sheet.
Document Number: 002-05633 Rev *B
Page 91 of 131
MB9AA40NB Series
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
SOT
VOL
tIVSLI
VIH
SIN
tSLIXI
VIH
VIL
VIL
Master mode
tSHSL
SCK
VIH
VIH
VIL
tR
SOT
tSLSH
tF
VIL
VIL
tSHOVE
VOH
VOL
tIVSLE
SIN
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-05633 Rev *B
Page 92 of 131
MB9AA40NB Series
CSIO (SPI = 0, SCINV = 1)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Pin
name
Symbol
Baud rate
-
-
Serial clock cycle time
tSCYC
SCKx
SCK ↑ → SOT delay time
tSHOVI
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
-
VCC ≥ 2.7 V
VCC < 2.7 V
Conditions
Min
Max
Min
Max
Unit
-
8
-
8
Mbps
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
36
-
ns
0
-
0
-
ns
Master mode
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
Serial clock L pulse width
tSLSH
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK ↑ → SOT delay time
tSHOVE
-
50
-
33
ns
SIN → SCK ↓ setup time
tIVSLE
10
-
10
-
ns
SCK ↓ → SIN hold time
tSLIXE
20
-
20
-
ns
SCK falling time
tF
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
Slave mode
−
−
−
The above characteristics apply to clock synchronous mode.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this
data sheet.
Document Number: 002-05633 Rev *B
Page 93 of 131
MB9AA40NB Series
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
SOT
VOL
tIVSLI
VIH
SIN
tSLIXI
VIH
VIL
VIL
Master mode
tSHSL
SCK
VIH
VIH
VIL
tR
SOT
tSLSH
tF
VIL
VIL
tSHOVE
VOH
VOL
tIVSLE
SIN
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-05633 Rev *B
Page 94 of 131
MB9AA40NB Series
CSIO (SPI = 1, SCINV = 0)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Conditions
-
Baud rate
-
-
Serial clock cycle time
tSCYC
SCKx
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓→ SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock L pulse width
tSLSH
Serial clock H pulse width
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓→ SIN hold time
tSLIXE
SCK falling time
SCK rising time
Notes:
VCC ≥ 2.7 V
VCC < 2.7 V
Min
Max
Min
Max
Unit
-
8
-
8
Mbps
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
36
-
ns
0
-
0
-
ns
2tCYCP - 34
-
2tCYCP - 34
-
ns
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
tCYCP + 10
-
tCYCP + 10
-
ns
-
50
-
33
ns
10
-
10
-
ns
20
-
20
-
ns
tF
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
-
5
-
5
ns
tR
SCKx
-
5
-
5
ns
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
Master
mode
Slave mode
−
−
−
The above characteristics apply to clock synchronous mode.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this
data sheet.
Document Number: 002-05633 Rev *B
Page 95 of 131
MB9AA40NB Series
tSCYC
VOH
SCK
VOL
VOH
VOL
SOT
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
VIH
SCK
tR
VOH
VOL
tIVSLE
SIN
VIL
tF
*
SOT
VIL
tSHSL
VIH
VIL
VIH
VIH
tSHOVE
VOH
VOL
tSLIXE
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-05633 Rev *B
Page 96 of 131
MB9AA40NB Series
CSIO (SPI = 1, SCINV = 1)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Min
Max
Min
Max
Unit
Baud rate
-
-
-
8
-
8
Mbps
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK ↓ → SOT delay time
tSLOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN → SCK ↑ setup time
tIVSHI
50
-
36
-
ns
SCK ↑ → SIN hold time
tSHIXI
0
-
0
-
ns
SOT → SCK ↑ delay time
tSOVHI
2tCYCP - 34
-
2tCYCP - 34
-
ns
Serial clock L pulse width
tSLSH
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock H pulse width
tSHSL
tCYCP + 10
-
tCYCP + 10
-
ns
SCK ↓ → SOT delay time
tSLOVE
-
50
-
33
ns
SIN → SCK ↑ setup time
tIVSHE
10
-
10
-
ns
SCK ↑ → SIN hold time
tSHIXE
20
-
20
-
ns
SCK falling time
tF
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
-
VCC ≥ 2.7 V
VCC < 2.7 V
Conditions
Master mode
Slave mode
−
−
−
The above characteristics apply to clock synchronous mode.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this
data sheet.
Document Number: 002-05633 Rev *B
Page 97 of 131
MB9AA40NB Series
tSCYC
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
Master mode
tR
tF
tSHSL
SCK
VIL
tSLSH
VIH
VIH
VIL
VIL
tSLOVE
VOH
VOL
SOT
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Serial clock L pulse width
Serial clock H pulse width
SCK falling time
SCK rising time
tSLSH
tSHSL
tF
tR
Conditions
CL = 30 pF
Value
Min
tCYCP + 10
tCYCP + 10
-
Max
5
5
Unit
Remarks
ns
ns
ns
ns
tF
tR
tSHSL
SCK
V IL
V IH
Document Number: 002-05633 Rev *B
t SLSH
V IH
V IL
V IL
V IH
Page 98 of 131
MB9AA40NB Series
12.5.11 External Input Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Min
Max
Unit
Remarks
ADTG
-
2tCYCP*1
-
ns
A/D converter trigger input
INTxx,
NMIX
*2
2tCYCP + 100*1
-
ns
*3
500
-
ns
External interrupt
NMI
WKUPx
*4
*1: tCYCP indicates the APB bus clock cycle time.
600
-
ns
Deep standby wake up
Input pulse width
tINH,
tINL
About the APB bus number which the Multi-function Timer is connected to, see Block Diagram in this data sheet.
*2: When in Run mode, in Sleep mode.
*3: When in Stop mode, in Timer mode.
*4: When in Deep Standby RTC mode, in Deep Standby Stop mode.
Document Number: 002-05633 Rev *B
Page 99 of 131
MB9AA40NB Series
12.5.12 I2C Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Standard-mode
Parameter
Symbol
Conditions
Min
Fast-mode
Max
Min
Max
Unit
SCL clock frequency
(Repeated) START
condition hold time
SDA ↓ → SCL ↓
FSCL
0
100
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
SCL clock L width
tLOW
4.7
-
1.3
-
μs
SCL clock H width
tHIGH
4.0
-
0.6
-
μs
4.7
-
0.6
-
μs
tHDDAT
0
3.45*2
0
0.9*3
μs
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
2 tCYCP*4
-
2 tCYCP*4
-
ns
(Repeated) START
condition setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
Bus free time between
STOP condition and
START condition
Noise filter
tSUSTA
tSP
CL = 30 pF,
R = (Vp/IOL)*1
-
Remarks
*1: R and C represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of
tSUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see Block Diagram in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-05633 Rev *B
Page 100 of 131
MB9AA40NB Series
12.5.13 ETM Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Data hold
tETMH
TRACECLK
frequency
1/ tTRACE
Pin name
TRACECLK,
TRACED[3:0]
TRACECLK
TRACECLK
clock cycle
Value
Conditions
Min
Max
Unit
VCC ≥ 2.7 V
2
11
VCC < 2.7 V
2
15
VCC ≥ 2.7 V
-
40
MHz
VCC < 2.7 V
-
20
MHz
VCC ≥ 2.7 V
25
-
ns
VCC < 2.7 V
50
-
ns
Remarks
ns
tTRACE
Note:
−
When the external load capacitance CL = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
Document Number: 002-05633 Rev *B
Page 101 of 131
MB9AA40NB Series
12.5.14 JTAG Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
TMS, TDI setup time tJTAGS
TCK,
TMS, TDI
TMS, TDI hold time
tJTAGH
TCK,
TMS, TDI
TDO delay time
tJTAGD
TCK,
TDO
Value
Min
Max
Conditions
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
Unit
15
-
ns
15
-
ns
-
25
-
45
Remarks
ns
Note:
−
When the external load capacitance CL = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-05633 Rev *B
Page 102 of 131
MB9AA40NB Series
12.6 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Parameter
Resolution
Integral Nonlinearity
Differential
Nonlinearity
Zero transition voltage
Full-scale transition
voltage
Pin
name
Symbol
Value
Typ
Min
Max
Unit
-
-
-
±2
12
± 4.5
bit
LSB
-
-
-
± 2.2
± 2.5
LSB
VZT
ANxx
-
±6
± 15
mV
VFST
ANxx
-
AVRH ± 6
AVRH ± 15
mV
2.0*1
-
-
μs
10
us
-
1000
ns
4.0*1
10*1
0.6
1.2
3.0
100
200
500
Conversion time
-
-
Sampling time*2
tS
-
Compare clock
cycle*3
tCCK
-
tSTT
-
-
-
1.0
μs
-
AVCC
-
0.27
0.03
0.42
10
mA
μA
-
0.72
1.29
mA
-
AVRH
-
0.02
2.6
μA
pF
μA
State transition time
to operation
permission
Power supply current
(analog + digital)
Reference power
supply current
(between AVRH to
AVSS)
Analog input capacity
CAIN
-
-
-
Analog input resistor
RAIN
-
-
-
Interchannel disparity
Analog port input leak
current
Analog input voltage
-
-
-
-
9.4
2.2
5.5
10.5
4
-
ANxx
-
-
5
-
ANxx
AVSS
AVRH
2.7
AVRH
AVCC
AVCC
Reference voltage
AVRL
AVSS
AVSS
*1: The conversion time is the value of sampling time (tS) + compare time (tC).
kΩ
Remarks
AVCC ≥ 2.7 V
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
AVCC ≥ 2.7 V
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
AVCC ≥ 2.7 V
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
A/D 1unit operation
When A/D stops
A/D 1unit operation
AVRH=3.6 V
When A/D stops
AVCC ≥ 2.7 V
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
LSB
V
V
AVCC ≥ 2.7 V
AVCC < 2.7 V
V
The condition of the minimum conversion time is the following.
AVCC ≥ 2.7 V, HCLK=40 MHz
sampling time: 0.6 μs, compare time: 1.4 μs
1.8 V < AVCC < 2.7 V, HCLK=40 MHz
sampling time: 1.2 μs, compare time: 2.8 μs
1.65 V < AVCC < 1.8 V, HCLK=40 MHz
sampling time: 3 μs, compare time: 7 μs
Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).
For setting of the sampling time and the compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual
Analog Macro Port.
The register setting of the A/D Converter are reflected in the operation according to the APB bus clock timing.
The sampling clock and compare clock is generated from the Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see Block Diagram in this data sheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: The compare time (tC) is the value of (Equation 2).
Document Number: 002-05633 Rev *B
Page 103 of 131
MB9AA40NB Series
REXT
Analog signal
source
ANxx
Analog input pin
Comparator
RAIN
CAIN
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9
tS:
Sampling time[ns]
RAIN:
Input resistor of A/D[kΩ] = 2.2 kΩ at 2.7 V < AVCC < 3.6 V
Input resistor of A/D[kΩ] = 5.5 kΩ at 1.8 V < AVCC < 2.7 V
Input resistor of A/D[kΩ] = 10.5 kΩ at 1.65 V < AVCC < 1.8 V
CAIN:
Input capacity of A/D[pF] = 9.4 pF at 1.65 V < AVCC < 3.6 V
REXT:
Output impedance of external circuit[kΩ]
(Equation 2) tC = tCCK × 14
tC:
Compare time
tCCK:
Compare clock cycle
Document Number: 002-05633 Rev *B
Page 104 of 131
MB9AA40NB Series
Definition of 12-bit A/D Converter Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Integral Nonlinearity:
Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition
point (0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
Differential Nonlinearity:
Deviation from the ideal value of the input voltage that is required to
change the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
Ideal characteristics
0xN
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
AVSS
Actual conversion characteristics
AVRH
AVSS
AVRH
Analog input
Linearity error of digital output N =
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Differential linearity error of digital output N =
LSB =
N:
VZT:
VFST:
VNT:
- VNT
LSB
(N + 1) T
LSB]
1 [LSB]
- VZT
094
FST
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-05633 Rev *B
Page 105 of 131
MB9AA40NB Series
12.7 Low-Voltage Detection Characteristics
12.7.1 Low-Voltage Detection Reset
(TA = - 40°C to + 85°C)
Parameter
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
LVD stabilization
wait time
Symbol
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
tLVDW
Conditions
SVHR*1 = 00000
SVHR*1 = 00001
SVHR*1 = 00010
SVHR*1 = 00011
SVHR*1 = 00100
SVHR*1 = 00101
SVHR*1 = 00110
SVHR*1 = 00111
SVHR*1 = 01000
SVHR*1 = 01001
SVHR*1 = 01010
SVHR*1 = 01011
SVHR*1 = 01100
SVHR*1 = 01101
SVHR*1 = 01110
SVHR*1 = 01111
SVHR*1 = 10000
SVHR*1 = 10001
SVHR*1 = 10010
SVHR*1 = 10011
-
Value
Min
Typ
Max
1.38
1.50
1.60
1.43
1.55
1.65
1.43
1.55
1.65
Same as SVHR = 00000 value
1.47
1.60
1.73
Same as SVHR = 00000 value
1.52
1.65
1.78
Same as SVHR = 00000 value
1.56
1.70
1.84
Same as SVHR = 00000 value
1.61
1.75
1.89
Same as SVHR = 00000 value
1.66
1.80
1.94
Same as SVHR = 00000 value
1.70
1.85
2.00
Same as SVHR = 00000 value
1.75
1.90
2.05
Same as SVHR = 00000 value
1.79
1.95
2.11
Same as SVHR = 00000 value
1.84
2.00
2.16
Same as SVHR = 00000 value
1.89
2.05
2.21
Same as SVHR = 00000 value
2.30
2.50
2.70
Same as SVHR = 00000 value
2.39
2.60
2.81
Same as SVHR = 00000 value
2.48
2.70
2.92
Same as SVHR = 00000 value
2.58
2.80
3.02
Same as SVHR = 00000 value
2.67
2.90
3.13
Same as SVHR = 00000 value
2.76
3.00
3.24
Same as SVHR = 00000 value
2.85
3.10
3.35
Same as SVHR = 00000 value
2.94
3.20
3.46
Same as SVHR = 00000 value
-
-
5200 × tCYCP*2
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
μs
LVD detection
tLVDDL
200
μs
delay time
*1: The SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is initialized to 00000 by Low-Voltage Detection
Reset.
*2: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05633 Rev *B
Page 106 of 131
MB9AA40NB Series
12.7.2 Interrupt of Low-Voltage Detection
(TA = - 40°C to + 85°C)
Parameter
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
LVD stabilization wait
time
Symbol
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
tLVDW
Conditions
SVHI = 00100
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
SVHI = 01010
SVHI = 01011
SVHI = 01100
SVHI = 01101
SVHI = 01110
SVHI = 01111
SVHI = 10000
SVHI = 10001
SVHI = 10010
SVHI = 10011
-
LVD detection delay
tLVDDL
time
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05633 Rev *B
Value
Typ
Min
Max
Unit
1.56
1.61
1.61
1.66
1.66
1.70
1.70
1.75
1.75
1.79
1.79
1.84
1.84
1.89
1.89
1.93
2.30
2.39
2.39
2.48
2.48
2.58
2.58
2.67
2.67
2.76
2.76
2.85
2.85
2.94
2.94
3.04
1.70
1.75
1.75
1.80
1.80
1.85
1.85
1.90
1.90
1.95
1.95
2.00
2.00
2.05
2.05
2.10
2.50
2.60
2.60
2.70
2.70
2.80
2.80
2.90
2.90
3.00
3.00
3.10
3.10
3.20
3.20
3.30
1.84
1.89
1.89
1.94
1.94
2.00
2.00
2.05
2.05
2.11
2.11
2.16
2.16
2.21
2.21
2.27
2.70
2.81
2.81
2.92
2.92
3.02
3.02
3.13
3.13
3.24
3.24
3.35
3.35
3.46
3.46
3.56
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
-
-
5200 × tCYCP*
μs
-
-
200
μs
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
Page 107 of 131
MB9AA40NB Series
12.8 Flash Memory Write/Erase Characteristics
12.8.1 Write / Erase time
(VCC = 1.65V to 3.6V, TA = - 40°C to + 85°C)
Value
Parameter
Typ*
Large Sector
1.1
2.7
Small Sector
0.3
0.9
Half word (16-bit)
write time
30
Chip erase time
6.8
Sector erase
time
Unit
Remarks
Max*
s
Includes write time prior to internal erase
528
μs
Not including system-level overhead time
18
s
Includes write time prior to internal erase
*: The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write.
12.8.2 Write cycles and data hold time
Erase/write cycles (cycle)
1,000
10,000
*: At average + 85C
Document Number: 002-05633 Rev *B
Data hold time (year)
Remarks
20*
10*
Page 108 of 131
MB9AA40NB Series
12.9 Return Time from Low-Power Consumption Mode
12.9.1 Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Sleep mode
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Max*
tICNT
RTC mode,
Stop mode
Deep Standby RTC mode
Deep Standby Stop mode
Unit
Remarks
μs
tCYCC
Low-speed CR Timer mode
Sub Timer mode
Typ
40
80
μs
350
700
μs
690
880
μs
278
523
μs
318
603
μs
When RAM is off
278
523
μs
When RAM is on
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*)
External
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-05633 Rev *B
Page 109 of 131
MB9AA40NB Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
−
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before
the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in
FM3 Family Peripheral Manual.
Document Number: 002-05633 Rev *B
Page 110 of 131
MB9AA40NB Series
12.9.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Value
Symbol
Typ
Unit
Max*
Remarks
148
263
μs
148
263
μs
258
483
μs
322
516
μs
RTC/Stop mode
278
523
μs
Deep Standby RTC mode
Deep Standby Stop mode
318
603
μs
When RAM is off
278
523
μs
When RAM is on
Sleep mode
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Low-speed CR Timer mode
tRCNT
Sub Timer mode
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Document Number: 002-05633 Rev *B
Start
Page 111 of 131
MB9AA40NB Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
−
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before
the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in
FM3 Family Peripheral Manual.
−
The time during the power-on reset/low-voltage detection reset is excluded. See (6) Power-on
Reset Timing in AC Characteristics in Electrical Characteristics for the detail on the time during
the power-on reset/low-voltage detection reset.
−
When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the
main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time
or the Main PLL clock stabilization wait time.
−
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05633 Rev *B
Page 112 of 131
MB9AA40NB Series
13. Ordering Information
On-chip
Flash
memory
Part number
On-chip
SRAM
MB9AFA41LBPMC1-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA42LBPMC1-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA44LBPMC1-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9AFA41LBPMC-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA42LBPMC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA44LBPMC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9AFA41LBQN-G-AVE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA42LBQN-G-AVE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA44LBQN-G-AVE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9AFA41MBPMC-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA42MBPMC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA44MBPMC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9AFA41MBPMC1-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA42MBPMC1-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA44MBPMC1-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9AFA41MBBGL-GE1
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA42MBBGL-GE1
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA44MBBGL-GE1
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9AFA41NBPMC-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA42NBPMC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA44NBPMC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
Document Number: 002-05633 Rev *B
Package
Packing
Plastic LQFP 64-pin
(0.5mm pitch),
(LQD064)
Plastic LQFP 64-pin
(0.65mm pitch),
(LQG064)
Plastic QFN 64-pin
(0.5mm pitch),
(VNC064)
Plastic LQFP 80-pin
(0.5mm pitch),
(LQH080)
Tray
Plastic LQFP 80-pin
(0.65mm pitch),
(LQJ080)
Plastic PFBGA 96-pin
(0.5mm pitch),
(FDG096)
Plastic LQFP 100-pin
(0.5mm pitch),
(LQI100)
Page 113 of 131
MB9AA40NB Series
Part number
MB9AFA41NBPQC-G-JNE2
On-chip
Flash
memory
Main: 64 Kbyte
Work: 32 Kbyte
On-chip
SRAM
Packing
16 Kbyte
MB9AFA42NBPQC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA44NBPQC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9AFA41NBBGL-GE1
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA42NBBGL-GE1
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFA44NBBGL-GE1
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
Document Number: 002-05633 Rev *B
Package
Plastic QFP 100-pin
(0.65mm pitch),
(PQH100)
Tray
Plastic PFBGA 112-pin
(0.8mm pitch),
(LBC112)
Page 114 of 131
MB9AA40NB Series
14. Package Dimensions
Package Type
Package Code
LQFP 100
LQI100
D
D1
75
4
D
5 7
51
D1
51
50
76
4
5 7
75
50
76
E1 E
5 4
7
E1 E
5 4
7
3
6
26
100
1
26
25
1
25
2 5 7
e
100
BOTTOM VIEW
0.1 0 C A-B D
3
0.2 0 C A-B D
b
TOP VIEW
8
0.0 8
C A-B
D
2
A
9
A
SEAT ING
PLA NE
A'
0.25
L1
0.0 8 C
c
A1
b
10
SECTION A-A'
L
SIDE VIEW
SYMBOL
DETAIL A
DIMENSIONS
MIN.
NOM. MAX.
1.70
A
A1
0.05
b
0.15
0.15
0.27
c
0.09
0.20
D
16.00 BSC
D1
14.00 BSC
e
0.50 BSC
E
16.00 BSC
E1
14.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
NOTES :
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE MOLD PARTING
LINE COINCIDENT WITH WHERE THE LEAD EXITS THE BODY.
3. DATUMS A-B AND D TO BE DETERMINED AT DATUM PLANE H.
4. TO BE DETERMINED AT SEATING PLANE C.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS 0.25mm PRE SIDE.
DIMENSIONS D1 AND E1 INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE H.
6. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED.
7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOWER BODY
SECTIONS. DIMENSIONS D1 AND E1 ARE DETERMINED AT THE LARGEST
FEATURE OF THE BODY EXCLUSIVE OF MOLD FLASH AND GATE BURRS.
BUT INCLUDING ANY MISMATCH BETWEEN THE UPPER AND LOWER
SECTIONS OF THE MOLDER BODY.
8. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR
PROTRUSION (S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED b
MAXIMUM BY MORE THAN 0.08mm. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE LEAD FOOT.
9. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP.
10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO
THE LOWEST POINT OF THE PACKAGE BODY.
002-11500 *A
PACKAGE OUTLINE, 100 LEAD LQFP
14.0X14.0X1.7 MM LQI100 REV*A
Document Number: 002-05633 Rev *B
Page 115 of 131
MB9AA40NB Series
Package Type
Package Code
QFP 100
PQH100
D
D1
4
5 7
80
51
81
51
50
80
50
81
31
100
E1 E
5
7
6
3
4
31
100
1
30
e
3
0.40 C A-B D
30
2 5 7
1
0.20 C A-B D
b
0.13
C A-B
D
BOTTOM VIEW
8
TOP VIEW
2
9
A
A'
SEATING
PLANE
L2
c
10
b
0.10 C
SECTION A-A'
DETAIL A
SIDE VIEW
SYMBOL
DIMENSIONS
MIN.
NOM. MAX.
A1
0.05
0.45
b
0.27
c
0.11
A
3.35
0.32
0.23
D
23.90 BSC
D1
20.00 BSC
e
0.65 BSC
E
17.90 BSC
E1
14.00 BSC
0
L
0.37
0.73
8
0.88
L1
1.95 REF
L2
0.25 BSC
1.03
PACKAGE OUTLINE, 100 LEAD QFP
20.00X14.00X3.35 MM PQH100 REV**
002-15156 **
Document Number: 002-05633 Rev *B
Page 116 of 131
MB9AA40NB Series
Package Type
Package Code
LQFP 80
LQH080
D
D1
60
4
5 7
41
41
40
61
60
40
61
21
80
5
7
E1
E
4
3
6
80
21
1
20
D
e
20
2 5 7
0.10 C A-B D
3
b
0.08
C A-B
1
BOTTOM VIEW
D
0.20 C A-B D
8
TOP VIEW
2
A
A
A'
0.08 C
SIDE VIEW
SEATING
PLANE
9
L1
L
0.25
A1
10
c
b
SECTION A-A'
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
A
A1
1. 70
0.05
0.15
b
0.15
0.27
c
0.09
0.20
D
14.00 BSC.
D1
12.00 BSC.
e
0.50 BSC
E
14.00 BSC.
E1
12.00 BSC.
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
PACKAGE OUTLINE, 80 LEAD LQFP
12.0X12.0X1.7 MM LQH080 Rev **
002-11501 **
Document Number: 002-05633 Rev *B
Page 117 of 131
MB9AA40NB Series
Package Type
Package Code
LQFP 80
LQJ080
D
D1
60
4
5 7
41
41
61
40
E1
60
40
61
21
80
E
5
7
4
3
6
80
21
1
20
20
2 5 7
1
0.10 C A-B D
3
e
0.20 C A-B D
b
ddd
C A-B
D
8
2
A
9
A
A'
0.10 C
SEATING
PLANE
c
L1
0.2 5
A1
10
b
SECTION A-A'
L
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
1.70
A
A1
0.00
b
0.16
c
0.09
0.20
0.32
0.38
0.20
D
16.00 BSC
D1
14.00 BSC
e
0.65 BSC
E
16.00 BSC
14.00 BSC
E1
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
0
8
PACKAGE OUTLINE, 80 LEAD LQFP
14.0X14.0X1.7 MM LQJ080 REV**
002-14043 **
Document Number: 002-05633 Rev *B
Page 118 of 131
MB9AA40NB Series
Package Type
Package Code
LQFP 64
LQD064
4
D
D1
48
5 7
33
33
32
49
48
32
49
17
64
5
7
E1
E
4
3
6
17
64
1
16
e
1
16
2 5 7
3
BOTTOM VIEW
0.10 C A-B D
0.20 C A-B D
b
0.08
C A-B
D
8
TOP VIEW
A
2
9
A
A'
0.08 C
SEATING
PLANE
L1
0.25
L
A1
c
b
SECTION A-A'
10
SIDE VIEW
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
A1
1. 70
0.00
0.20
b
0.15
0.2
c
0.09
0.20
D
12.00 BSC.
D1
10.00 BSC.
e
0.50 BSC
E
12.00 BSC.
E1
10.00 BSC.
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
PACKAGE OUTLINE, 64 LEAD LQFP
10.0X10.0X1.7 MM LQD064 Rev**
002-11499 **
Document Number: 002-05633 Rev *B
Page 119 of 131
MB9AA40NB Series
Package Type
Package Code
LQFP 64
LQG064
D
D1
48
4
5 7
33
33
32
49
48
32
49
17
64
E1 E
5
7
4
3
17
64
1
16
e
1
16
2 5 7
3
BOTTOM VIEW
0.10 C A-B D
0.20 C A-B D
b
0.13
C A-B
D
8
TOP VIEW
2
A
A
A'
0.10 C
SEATI NG
PLA NE
0.2 5
L1
L
9
A1
10
c
b
SEC TION A -A'
SIDE VIEW
SYMBOL
DIMENSION
MIN.
NOM. MAX.
1.70
A
A1
0.00
0.20
b
0.27
c
0.09
0.32
0.37
0.20
D
14.00 BSC
D1
12.00 BSC
e
0.65 BSC
E
14.00 BSC
E1
12.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
0
PACKAGE OUTLINE, 64 LEAD LQFP
12.0X12.0X1.7 MM LQG064 REV**
002-13881 **
Document Number: 002-05633 Rev *B
Page 120 of 131
MB9AA40NB Series
Package Type
Package Code
QFN 64
VNC064
0.10
D
0.10 C
2X
D2
A
48
33
33
32
49
C A B
48
32
49
0.10
C A B
5
(ND-1)
E
e
17
64
1
INDEXMARK
8
E2
16
16
9
B
e
L
0.10 C
TOP VIEW
64
17
BOTTOM VIEW
2X
b
1
4
0.10
0.05
C A B
C
0.10 C
A
0.05 C
SEATINGPLANE
C
A1
SIDE VIEW
DIMENSIONS
NOTES:
SYMBOL
MIN. NOM. MAX.
A
A1
D
0.90
0.00
0.05
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4
9.00 BSC
E
9.00 BSC
b
0.20 0.25 0.30
D2
6.00 BSC
E2
6.00 BSC
6.
7.
e
0.50 BSC
8
R
0.20 REF
L
0.35
0.40 0.45
N
64
ND
16
5
9
DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL
HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL,
THE DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE OR E SIDE.
MAX. PACKAGE WARPAGE IS 0.05mm.
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT
SINK SLUG AS WELL AS THE TERMINALS.
PACKAGE OUTLINE, 64 LEAD QFN
9.0X9.0X0.9 MM VNC064 6.0X6.0 MM EPAD (SAWN) Rev*.*
002-13234 **
Document Number: 002-05633 Rev *B
Page 121 of 131
MB9AA40NB Series
Package Type
Package Code
FBGA 112
LBC112
A
0.20 C
11
2X
10
9
6
8
7
6
5
4
3
2
1
L
PIN A1
CORNER
INDEX MARK
K
J
H
G
F
E
D
7
C
B
A
6
B
0.20 C
TOP VIEW
2X
BOTTOM VIEW
DETAIL A
5
112x φ b
C
0.10 C
DETAIL A
0.08
C A B
SIDE VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
2. SOLDER BALL POSITION DESIGNATIO
N PER JEP95, SECTION 3, SPP-020.
MIN.
NOM.
MAX.
A
-
-
1.45
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
A1
0.25
0.35
0.45
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
D
10.00 BSC
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
E
10.00 BSC
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
D1
8.00 BSC
E1
8.00 BSC
MD
11
ME
11
N
112
b
0.35
0.45
eD
0.80 BSC
eE
0.80 BSC
SD
0.00
SE
0.00
SIZE MD X ME.
5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6. "SD" AND "SE" ARE MEASUREDWITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
0.55
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
7. A1 CORNER TO BE IDENTIFIED BY
CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
PACKAGE OUTLINE, 112 BALL FBGA
10.00X10.00X1.45 MM LBC112 REV**
002-13225 **
Document Number: 002-05633 Rev *B
Page 122 of 131
MB9AA40NB Series
Package Type
Package Code
FBGA 96
FDG096
A
0.20 C
11
2X
10
9
6
8
7
6
5
4
3
2
1
L
PIN A1
CORNER
INDEX MARK
K
J
H
G
F
E
D
7
0.20 C
TOP VIEW
C
B
A
6
B
2X
BOTTOM VIEW
DETAIL A
0.20 C
C
0.08 C
96xφ b
DETAIL A
5
0.05
SIDE VIEW
C A B
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
2. SOLDER BALL POSITION DESIGNATIO
N PER JEP95, SECTION 3, SPP-020.
MIN.
NOM.
MAX.
A
-
-
1.30
3. "e" REPRESENTSTHE SOLDER BALL GRID PITCH.
A1
0.15
0.25
0.35
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
D
6.00 BSC
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
E
6.00 BSC
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
D1
5.00 BSC
E1
5.00 BSC
MD
5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
11
ME
11
N
96
b
SIZE MD X ME.
0.20
0.30
eD
0.50 BSC
eE
0.50 BSC
SD
0.00
SE
0.00
6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
0.40
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
7. A1 CORNER TO BE IDENTIFIED BY
CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
PACKAGE OUTLINE, 96 BALL FBGA
6.0X6.0X1.3 MM FDG096 REV**
002-13224 **
Document Number: 002-05633 Rev *B
Page 123 of 131
MB9AA40NB Series
15. Errata
This chapter describes the errata for MB9AA40N, MB9AA40NA and MB9AA40NB series. Details include errata trigger conditions,
scope of impact, available workaround, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
15.1 Part Numbers Affected
Part Number
Initial Revision
MB9AFA41NPMC-G-JNE2, MB9AFA42NPMC-G-JNE2, MB9AFA44NPMC-G-JNE2,
MB9AFA41NPQC-G-JNE2, MB9AFA42NPQC-G-JNE2, MB9AFA44NPQC-G-JNE2,
MB9AFA41NBGL-GE1, MB9AFA42NBGL-GE1, MB9AFA44NBGL-GE1,
MB9AFA41MPMC-G-JNE2, MB9AFA42MPMC-G-JNE2, MB9AFA44MPMC-G-JNE2,
MB9AFA41MPMC1-G-JNE2, MB9AFA42MPMC1-G-JNE2, MB9AFA44MPMC1-G-JNE2,
MB9AFA41MBGL-GE1, MB9AFA42MBGL-GE1, MB9AFA44MBGL-GE1,
MB9AFA41LPMC1-G-JNE2, MB9AFA42LPMC1-G-JNE2, MB9AFA44LPMC1-G-JNE2,
MB9AFA41LPMC-G-JNE2, MB9AFA42LPMC-G-JNE2, MB9AFA44LPMC-G-JNE2,
MB9AFA41LQN-G-AVE2, MB9AFA42LQN-G-AVE2, MB9AFA44LQN-G-AVE2
Rev. A
MB9AFA41NAPMC-G-JNE2, MB9AFA42NAPMC-G-JNE2, MB9AFA44NAPMC-G-JNE2,
MB9AFA41NAPQC-G-JNE2, MB9AFA42NAPQC-G-JNE2, MB9AFA44NAPQC-G-JNE2,
MB9AFA41NABGL-GE1, MB9AFA42NABGL-GE1, MB9AFA44NABGL-GE1,
MB9AFA41MAPMC-G-JNE2, MB9AFA42MAPMC-G-JNE2, MB9AFA44MAPMC-G-JNE2,
MB9AFA41MAPMC1-G-JNE2, MB9AFA42MAPMC1-G-JNE2, MB9AFA44MAPMC1-G-JNE2,
MB9AFA41MABGL-GE1, MB9AFA42MABGL-GE1, MB9AFA44MABGL-GE1,
MB9AFA41LAPMC1-G-JNE2, MB9AFA42LAPMC1-G-JNE2, MB9AFA44LAPMC1-G-JNE2,
MB9AFA41LAPMC-G-JNE2, MB9AFA42LAPMC-G-JNE2, MB9AFA44LAPMC-G-JNE2,
MB9AFA41LAQN-G-AVE2, MB9AFA42LAQN-G-AVE2, MB9AFA44LAQN-G-AVE2
Rev. B
MB9AFA41NBPMC-G-JNE2, MB9AFA42NBPMC-G-JNE2, MB9AFA44NBPMC-G-JNE2,
MB9AFA41NBPQC-G-JNE2, MB9AFA42NBPQC-G-JNE2, MB9AFA44NBPQC-G-JNE2,
MB9AFA41NBBGL-GE1, MB9AFA42NBBGL-GE1, MB9AFA44NBBGL-GE1,
MB9AFA41MBPMC-G-JNE2, MB9AFA42MBPMC-G-JNE2, MB9AFA44MBPMC-G-JNE2,
MB9AFA41MBPMC1-G-JNE2, MB9AFA42MBPMC1-G-JNE2, MB9AFA44MBPMC1-G-JNE2,
MB9AFA41MBBGL-GE1, MB9AFA42MBBGL-GE1, MB9AFA44MBBGL-GE1,
MB9AFA41LBPMC1-G-JNE2, MB9AFA42LBPMC1-G-JNE2, MB9AFA44LBPMC1-G-JNE2,
MB9AFA41LBPMC-G-JNE2, MB9AFA42LBPMC-G-JNE2, MB9AFA44LBPMC-G-JNE2,
MB9AFA41LBQN-G-AVE2, MB9AFA42LBQN-G-AVE2, MB9AFA44LBQN-G-AVE2
15.2 Qualification Status
Product Status: In Production − Qual.
Document Number: 002-05633 Rev *B
Page 124 of 131
MB9AA40NB Series
15.3 Errata Summary
This table defines the errata applicability to available devices.
Items
Part Number
Silicon Revision
Fix Status
[1] FLASH lower bank read during write
Refer to 15.1
Initial rev.
Fixed in Rev. A
[2] FLASH read during write & erase suspend
Refer to 15.1
Initial rev.
Fixed in Rev. A
[3] Regulator issue
Refer to 15.1
Initial rev., Rev. A
Fixed in Rev. B
[4] HDMI-CEC arbitration lost issue
Refer to 15.1
Initial rev., Rev. A
Fixed in Rev. B
[5] HDMI-CEC polling message issue
Refer to 15.1
Initial rev., Rev. A , Rev. B
Next silicon is not planned
1. FLASH lower bank read during write
PROBLEM DEFINITION
During writing (programming) to FLASH memory of an upper bank, FLASH memory of a lower bank could not be read at a
specific timing in some operation combinations.
PARAMETERS AFFECTED
N/A
TRIGGER CONDITION(S)
This issue may happen when read data or fetch instruction from the FLASH memory lower bank (smaller sector), while a write
(program) operation to the FLASH memory upper bank (larger sector) is in progress.
SCOPE OF IMPACT
Instructions could not be fetched (read) correctly from the lower bank, and then execution of the (corrupted) instructions may
cause a hard fault or run-away. If an instruction in RAM reads a data from the lower bank while writing to the upper bank, an
incorrect value might be read.
WORKAROUND
To rewrite the upper bank of FLASH memory, put the write instruction in RAM instead of the lower bank and execute it from the
RAM. Do not access the lower bank until the write operation is completed (RDY=1). Especially to avoid a vector fetch from
the lower bank of the FLASH memory by an interrupt occurred, the interrupt should be prohibited or the vector address should
be set to RAM by the vector table offset register.
FIX STATUS
This issue was fixed in Rev. A.
2. FLASH Read during Write & Sector Erase Suspend
PROBLEM DEFINITION
When writing is executed during sector erase suspend, FLASH memory could not be read correctly at a specific timing.
PARAMETERS AFFECTED
N/A
TRIGGER CONDITION(S)
This issue may happen when read data or fetch instruction from the FLASH memory bank (higher or lower), while a write
(program) operation is in progress to the opposite bank which has a sector erase suspended. The following flow could not be
executed correctly.
(a) Erase a sector of a bank
(b) Suspend the sector erase operation
(c) Write to a different sector of the bank
(d) Execute an instruction or read data in the opposite bank
SCOPE OF IMPACT
Document Number: 002-05633 Rev *B
Page 125 of 131
MB9AA40NB Series
Instructions could not be fetched (read) correctly, and then execution of the (corrupted) instructions may cause a hard fault or
run-away. If an instruction in RAM reads a data from the bank, an incorrect value might be read.
WORKAROUND
Do not execute the write operation to a different sector in the same bank at sector erase suspend.
FIX STATUS
This issue was fixed in Rev. A.
3. Regulator issue
PROBLEM DEFINITION
The regulator does not get initialized while internal power-up sequence.
PARAMETERS AFFECTED
N/A
TRIGGER CONDITION(S)
This issue rarely happens depending on states of internal circuits which the user cannot control.
SCOPE OF IMPACT
MCU does not start operation if this issue occurs.
WORKAROUND
This error cannot be avoided by any software.
FIX STATUS
This issue was fixed in Rev. B.
4. HDMI-CEC arbitration lost issue
PROBLEM DEFINITION
Large external load on CEC bus may cause arbitration lost.
PARAMETERS AFFECTED
N/A
TRIGGER CONDITION(S)
The arbitration lost detection mechanism samples outputting signals and determines that arbitration lost occurs if sampled
signals do not match the outputting signals. The large external load on the CEC bus increases slew rate of the signals. The
increased slew rate makes the mismatch between outputting signals and sampled signals and the mismatch misleads MCU
that arbitration lost occurs.
SCOPE OF IMPACT
Once the arbitration lost is detected, the CEC aborts the transmission. Any transmission cannot be completed.
WORKAROUND
This error cannot be avoided by any software. Reduce the external load.
FIX STATUS
This issue was fixed in Rev. B.
5. HDMI-CEC polling message issue
PROBLEM DEFINITION
Error#1) While MCU sends a Polling Message, it always returns a NACK to a message coming to the MCU from another node.
Error#2) MCU always waits for 7-bit signal free on CEC line before it drives the line even when the last line initiator was another
node.
PARAMETERS AFFECTED
N/A
TRIGGER CONDITION(S)
This error always happens.
SCOPE OF IMPACT
MCU does not reply properly to another node.
Document Number: 002-05633 Rev *B
Page 126 of 131
MB9AA40NB Series
WORKAROUND
The software workaround is applied to Error #1.
1.
Store 0x0 to SFREE register.
2.
Monitor CEC line with GPIO and wait until 1 lasts for the signal free time.
3.
Store frame data to TXDATA register and store 0x0F to RCADR1 or RCADR2 register.
It sends a message after 3~4 clocks of 32.768 kHz clock when TXDATA is stored 0x0F.
If the device receives a frame from another node within 2~3 clocks after storing TXDATA, the bus error occurs and if the device
receives a frame from another node within 3~4 clocks after storing TXDATA, the arbitration lost occurs. In these cases:
4-A-1. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK
4-A-2. Return back to step 2 above
If the device receives a frame from another node within 1~2 clocks after storing TXDATA, take these steps.
4-B-1. Monitor CEC line with GPIO after 50us from storing TXDATA
4-B-2. Set TXEN to 1 -> 0 -> 1 immediately when GPIO finds state low on the CEC line
4-B-3. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK
4-B-4. Return back to step 2 above
For Error #2, there is no software workaround, but signal free time of fixed 7-bit does not violate HDMI-CEC specification. The
specification says signal free time must be more than and equals to 5-bit.
FIX STATUS
The user uses the workaround to avoid the issue. The next silicon fixing the issue is not planned.
Document Number: 002-05633 Rev *B
Page 127 of 131
MB9AA40NB Series
16. Major Changes
Spansion Publication Number: DS706-00038
Page
Section
Revision 2.0
Feature
2
On-chip Memories
5
Unique ID
Product Lineup
7
Function
52
Handling Devices
Memory Map
57
Memory Map (2)
Pin Status In Each CPU State
62
List of Pin Status
Electrical Characteristics
70
DC Characteristics
Current rating
AC Characteristics
74
Built-in CR Oscillation Characteristics
Built-in high-speed CR
External Bus Timing
78, 79
Separate Bus Access Asynchronous
SRAM Mode
Separate Bus Access Synchronous
80
SRAM Mode
85, 87,
CSIO Timing
89, 91
94
I2C Timing
12-bit A/D Converter
97
Electrical Characteristics for the A/D
Converter
Definition of 12-bit A/D Converter
99
Terms
100
Low-Voltage Detection Characteristics
Low-Voltage Detection Reset
101
Interrupt of Low-Voltage Detection
Revision 2.1
Revision 3.0
Change Results
Revised the descriptions of [Flash memory].
Added the descriptions of "Unique ID".
Added the descriptions.
Revised the Pin status type of "I".
Revised the descriptions of Power supply current.
Added the "Flash memory write/erase current".
Added the footnote.
Revised the table and the footnote.
Revised the table and the figure.
Revised the title to "CSIO Timing".
Revised the note.
Revised the footnote.
• Revised the parameter.
• Revised the symbol.
• Corrected the value.
• Revised the parameter.
• Revised the symbol.
• Corrected "Conditions" and "Value" in the table.
• Added the Item.
• Added the footnote.
Added the Item.
Company name and layout design change
-
-
-
-
2
Features
External Bus Interface
Corrected the Series name.
MB9AB40NA Series → MB9AB40NB Series
Corrected the Product name as follows.
MB9AFB44LB, MB9AFB42LB, MB9AFB41LB
MB9AFB44MB, MB9AFB42MB, MB9AFB41MB
MB9AFB44NB, MB9AFB42NB, MB9AFB41NB
Added the Item.
• Maximum area size : Up to 256 Mbytes
3
Multi-function Serial Interface
Corrected the description of "I2C"
7
Product Lineup
Function
Added the footnote
55
Block Diagram
Corrected the figure
56
68
Memory Map
Memory Map (1)
Electrical Characteristics
Recommended Operating Conditions
Document Number: 002-05633 Rev *B
Corrected the address "External Device Area"
Add the footnote
Page 128 of 131
MB9AA40NB Series
Page
Section
69,70
DC Characteristics
Current rating
92
CSIO Timing
Synchronous serial (SPI=1, SCINV=1)
CSIO Timing
External clock(EXT=1):asynchronous
only
94
I2C Timing
97
12-bit A/D Converter
Electrical Characteristics for
the A/D Converter
103
Ordering Information
Revision 4.0
Memory Map
57
· Memory map(2)
Electrical Characteristics
69 - 71
DC Characteristics
Current rating
Electrical Characteristics
72
DC Characteristics
Pin Characteristics
Electrical Characteristics
AC Characteristics
76
Operating Conditions of Main PLL
Operating Conditions of Main PLL
Electrical Characteristics
77
AC Characteristics
Power-on Reset Timing
Change Results
•Corrected the Condition
•Delete the minimum value
•Corrected the remarks
•Add the footnote
Corrected the figure of "MS bit=1"
Corrected the figure
Corrected the description as follows.
•Typical mode → Standard-mode
•High-speed mode→ Fast-mode
•Corrected the terminal name
AN00 ~ AN23 → ANxx
•Corrected the minimum value of "Sampling time"
•Corrected the max and min value of "State transition time
to operation permission"
•Corrected the footnote
Corrected the "Part number"
Added the summary of Flash memory sector and the note
· Changed the table format
· Added Main Timer mode current
· Moved A/D Converter Current
Added input leak current of CEC pin at power off.
Added the figure of Main PLL connection
· Added Time until releasing Power-on reset
· Changed the figure of timing
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master
mode
· Changed from External shift clock operation to Slave
mode
· Added the typical value of Integral Nonlinearity,
Differential Nonlinearity, Zero transition voltage and
Full-scale transition voltage
· Added Conversion time at AVcc < 2.7V
86 - 93
Electrical Characteristics
AC Characteristics
CSIO/UART Timing
98
Electrical Characteristics
12bit A/D Converter
104 107
Electrical Characteristics
Return Time from Low-Power
Consumption Mode
Added Return Time from Low-Power Consumption Mode
108,
109
Ordering Information
Changed notation of part number
NOTE: Please see “Document History” about later revised information.
Document Number: 002-05633 Rev *B
Page 129 of 131
MB9AA40NB Series
Document History
Document Title: MB9AA40NB Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller
Document Number: 002-05633
Orig. of
Submission
Change
Date
AKIH
06/10/2015
Migrated to Cypress and assigned document number 002-05633.
No change to document contents or format. .
5206929
AKIH
04/08/2016
Updated to Cypress template
Revision
ECN
**
*A
Description of Change
Updated “12.5.7 Power-On Reset Timing”. Changed parameter from “Power Supply
rise time(Tr)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and added some comments
(Page 82)
Modified RTC description in “Features, Real-Time Clock(RTC)” as below
Changed starting count value from 01 to 00. Deleted “second , or day of the week”
in the Interrupt function (Page 2)
Added Notes for JTAG (Page 40), Changed “J-TAG” to” JTAG” in “4 List of Pin
Functions” (Page 28)
Updated Package code and dimensions as follows (Page 7-14, 113-123)
FPT-64P-M38 -> LQD064, FPT-64P-M39
*B
5534251
YSKA
06/01/2017
LCC-64P-M24
-> VNC064,
FPT-80P-M37
FPT-80P-M40 -> LQJ080, BGA-96P-M07
FPT-100P-M23 -> LQI100,
FPT-100P-M36
-> LQG064,
-> LQH080,
-> FDG096,
-> PQH100
BGA-112P-M04 -> LBC112
Added “15. Errata” (Page 124)
Add “Analog reference voltage(AVRL)” in “12.2 Recommended Operating
Conditions” and “12.6 12-bit A/D Converter”(Page 72, 103)
Corrected the following statement
Analog port input current Analog port input leak current
in chapter 12.6. 12-bit A/D Converter (Page 103)
Added the Baud rate spec in “12.5.10 CSIO/UART Timing”(Page 91, 93, 95, 97)
Document Number: 002-05633 Rev *B
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MB9AA40NB Series
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Page 131 of 131