ON NVTFS5C673NL Power mosfet Datasheet

NVTFS5C673NL
Power MOSFET
60 V, 9.8 mW, 50 A, Single N−Channel
Features
•
•
•
•
•
•
Small Footprint (3.3 x 3.3 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
NVTFS5C673NLWF − Wettable Flanks Product
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(on) MAX
ID MAX
9.8 mW @ 10 V
60 V
50 A
15 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
V
Gate−to−Source Voltage
VGS
±20
V
ID
50
A
Continuous Drain Current RqJC
(Notes 1, 2, 3, 4)
Power Dissipation
RqJC (Notes 1, 2, 3)
Continuous Drain Current RqJA
(Notes 1 & 3, 4)
Power Dissipation
RqJA (Notes 1, 3)
Pulsed Drain Current
TC = 25°C
Steady
State
TC = 100°C
TC = 25°C
Steady
State
PD
ID
9
PD
MARKING DIAGRAM
W
3.1
1
1.6
290
A
TJ, Tstg
−55 to
+175
°C
IS
52
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 2.3 A)
EAS
88
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Source Current (Body Diode)
WDFN8
(m8FL)
CASE 511AB
XXXX
A
Y
WW
G
1
S
S
S
G
XXXX
AYWWG
G
D
D
D
D
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
S (1, 2, 3)
A
13
IDM
Operating Junction and Storage Temperature
G (4)
23
TA = 100°C
TA = 25°C, tp = 10 ms
W
46
TA = 100°C
TA = 25°C
D (5 − 8)
35
TC = 100°C
TA = 25°C
N−Channel
Symbol
Value
Unit
Junction−to−Case − Steady State (Note 3)
RqJC
3.2
°C/W
Junction−to−Ambient − Steady State (Note 3)
RqJA
48
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
4. Continuous DC current rating. Maximum current for pulses as long as 1
second is higher but is dependent on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2017
March, 2017 − Rev. 1
1
Publication Order Number:
NVTFS5C673NL/D
NVTFS5C673NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
60
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
28
VGS = 0 V,
VDS = 60 V
mV/°C
TJ = 25°C
10
TJ = 125°C
250
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH)
VGS = VDS, ID = 250 mA
100
mA
nA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
1.2
2.0
−4.5
VGS = 10 V
ID = 25 A
8.1
9.8
VGS = 4.5 V
ID = 25 A
12
15
gFS
VDS =15 V, ID = 25 A
V
mV/°C
37
mW
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
880
VGS = 0 V, f = 1 MHz, VDS = 25 V
450
pF
11
Total Gate Charge
QG(TOT)
VGS = 4.5 V, VDS = 48 V; ID = 25 A
4.5
nC
Total Gate Charge
QG(TOT)
VGS = 10 V, VDS = 48 V; ID = 25 A
9.5
nC
Threshold Gate Charge
QG(TH)
1.0
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
2.0
Plateau Voltage
VGP
2.9
td(ON)
6.0
VGS = 10 V, VDS = 48 V; ID = 25 A
nC
0.8
V
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = 10 V, VDS = 48 V,
ID = 25 A, RG = 2.5 W
tf
25
ns
16
2.0
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Charge
VSD
VGS = 0 V,
IS = 25 A
TJ = 25°C
0.9
TJ = 125°C
0.8
tRR
ta
tb
1.2
V
28
VGS = 0 V, dIs/dt = 100 A/ms,
IS = 25 A
QRR
14
ns
14
18
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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NVTFS5C673NL
TYPICAL CHARACTERISTICS
40
40
VGS = 3.6 V to 10 V
VDS = 3 V
35
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
35
3.2 V
30
3.0 V
25
20
2.8 V
15
10
2.6 V
5
2.4 V
30
25
20
15
TJ = 125°C
10
0
0.5
1.0
2.0
1.5
0
2.5
1.5
2.0
3.0
2.5
3.5
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
Figure 1. On−Region Characteristics
ID = 25 A
TJ = 25°C
35
30
25
20
15
10
5
4
5
6
7
8
9
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
4.0
20
TJ = 25°C
18
16
14
VGS = 4.5 V
12
10
VGS = 10 V
8
6
0
10
20
30
40
50
60
70
80
90 100
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.25
2.00
1.0
VGS, GATE−TO−SOURCE VOLTAGE (V)
40
3
0.5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
100,000
ID = 25 A
VGS = 10 V
TJ = 175°C
10,000
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
TJ = −55°C
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
TJ = 25°C
5
1.75
1.50
1.25
1.00
TJ = 125°C
1000
TJ = 85°C
100
10
0.75
0.50
−50 −25
1
0
25
50
75
100
125
150
175
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
60
NVTFS5C673NL
TYPICAL CHARACTERISTICS
VGS = 0 V
TJ = 25°C
f = 1 MHz
Ciss
1000
VGS, GATE−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
10,000
Coss
100
Crss
10
1
0
10
20
30
40
50
10
QT
9
8
7
6
5
Qgd
4
Qgs
3
TJ = 25°C
VDS = 48 V
ID = 25 A
2
1
0
0
60
2
1
3
4
5
6
7
8
9
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source vs. Total Charge
100
100
VGS = 0 V
IS, SOURCE CURRENT (A)
t, TIME (ns)
tr
10 td(off)
td(on)
tf
1
VDS = 48 V
ID = 25 A
VGS = 10 V
10
0.3
100
TJ = −55°C
0.4
0.5
0.6
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
IPEAK, DRAIN CURRENT (A)
1000
ID, DRAIN CURRENT (A)
TJ = 25°C
0.1
1
100
1 ms
10
500 ms
VGS ≤ 10 V
Single Pulse
TC = 25°C
1
0.01
1
TJ = 125°C
0.1
0.1
10
10 ms
RDS(on) Limit
Thermal Limit
Package Limit
0.1
10
TJ(initial) = 25°C
TJ(initial) = 100°C
1
dc
0.1
1
10
100
1E−5
1E−4
1E−3
1E−2
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TAV, TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
NVTFS5C673NL
TYPICAL CHARACTERISTICS
100
Duty Cycle = 50%
R(t) (°C/W)
10
1
20%
10%
5%
2%
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.1
0.01
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Marking
Package
Shipping†
NVTFS5C673NLTAG
673L
WDFN8
(Pb−Free)
1500 / Tape & Reel
NVTFS5C673NLWFTAG
73LW
WDFN8
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NVTFS5C673NL
PACKAGE DIMENSIONS
WDFN8 3.3x3.3, 0.65P
CASE 511AB
ISSUE D
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
0.20 C
D
A
B
D1
2X
0.20 C
8 7 6 5
4X
q
E1 E
c
1 2 3 4
A1
TOP VIEW
0.10 C
A
0.10 C
SIDE VIEW
0.10
8X b
C A B
0.05
C
4X
DETAIL A
6X
C
e
SEATING
PLANE
DETAIL A
8X
e/2
L
0.42
4
INCHES
NOM
0.030
−−−
0.012
0.008
0.130 BSC
0.116
0.120
0.078
0.083
0.130 BSC
0.116
0.120
0.058
0.063
0.009
0.012
0.026 BSC
0.012
0.016
0.026
0.032
0.012
0.017
0.002
0.005
0.055
0.059
0_
−−−
MIN
0.028
0.000
0.009
0.006
0.65
PITCH
PACKAGE
OUTLINE
K
MAX
0.031
0.002
0.016
0.010
0.124
0.088
0.124
0.068
0.016
0.020
0.037
0.022
0.008
0.063
12 _
4X
0.66
M
E3
8
G
MILLIMETERS
MIN
NOM
MAX
0.80
0.70
0.75
0.00
−−−
0.05
0.23
0.30
0.40
0.15
0.20
0.25
3.30 BSC
2.95
3.05
3.15
1.98
2.11
2.24
3.30 BSC
2.95
3.05
3.15
1.47
1.60
1.73
0.23
0.30
0.40
0.65 BSC
0.30
0.41
0.51
0.65
0.80
0.95
0.30
0.43
0.56
0.06
0.13
0.20
1.40
1.50
1.60
0_
−−−
12 _
SOLDERING FOOTPRINT*
1
E2
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
E3
e
G
K
L
L1
M
q
5
D2
BOTTOM VIEW
3.60
L1
0.75
2.30
0.57
0.47
2.37
3.46
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NVTFS5C673NL/D