TI1 CDC9842 Pc motherboard clock synthesizer/driver Datasheet

CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MAY 1996
D
D
D
D
D
D
D
D
D
D
Provides System Clock Solution for
Pentium/82430X/82430VX and
PentiumPro 82440FX Chipsets
Four Host-Clock Outputs With
Programmable Frequency (50 MHz, 60 MHz
and 66 MHz)
Six PCI Clock Outputs at Half-CPU
Frequency
One 48-MHz Universal Serial Bus (USB)
Clock Output
Three 14.318-MHz Reference Clock Outputs
All Output Clock Frequencies Derived From
a Single 14.31818-MHz Crystal Input
LVTTL-Compatible Inputs and Outputs
Internal Loop Filters for Phase-Locked
Loops Eliminate the Need for External
Components
Operates at 3.3 VCC
Packaged in Plastic Small-Outline Package
DW PACKAGE
(TOP VIEW)
VCC
X1
X2
GND
OE
HCLK0
HCLK1
VCC
HCLK2
HCLK3
GND
SEL1
SEL0
VCC
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
REF0
REF1
VCC
REF2
SBCLK
GND
PCLK0
PCLK1
VCC
PCLK2
PCLK3
GND
PCLK4
PCLK5
description
The CDC9842 is a high-performance clock synthesizer/driver that generates the system clocks necessary to
support Pentium/82430X/82430VX and Pentium Pro 82440FX chipsets. Four host-clock outputs (HCLKn) are
programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control inputs.
Six PCI-clock outputs (PCLKn) are half the frequency of CPU clock outputs and are delayed 1 ns to 4 ns from
the rising edge of the CPU clock. In addition, a universal serial bus (USB) clock output at 48 MHz (SBCLK) and
three 14.318-MHz reference clock outputs (REF0, REF1, REF2) are provided.
All output frequencies are generated from a 14.318-MHZ crystal input. A reference clock can be provided at the
X1 input instead of a crystal input.
Two phase-locked loops (PLLs) are used to generate the host clock frequency and the 48-MHz clock frequency.
On-chip loop filters and internal feedback eliminate the need for external components. The PCI-clock
frequency is derived directly from the host-clock frequency. The PLL circuit can be bypassed in the TEST mode
(i.e., SEL0 = SEL1 = H) to distribute a test clock provided at the X1 input.
The host- and PCI-clock outputs provide low-skew/low-jitter clock signals for reliable clock operation. All outputs
are 3 state and are enabled via OE.
Because the CDC9842 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal
at the X1 input, as well as following any changes to the OE or SELn inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Pentium is a trademark of Intel Corporation.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MAY 1996
FUNCTION TABLE
2
OE
SEL0
SEL1
X1
HCLKn
PCLKn
REFn
SBCLK
L
X
X
14.318 MHz
Hi-Z
Hi-Z
Hi-Z
Hi-Z
H
L
L
14.318 MHz
50 MHz
25 MHz
14.318 MHz
48 MHz
H
L
H
14.318 MHz
60 MHz
30 MHz
14.318 MHz
48 MHz
H
H
L
14.318 MHz
TCLK†
66 MHz
33 MHz
14.318 MHz
48 MHz
H
H
H
TCLK /2
† TCLK is a test-clock input at the X1 input during test mode.
TCLK /4
TCLK
TCLK /4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MAY 1996
functional block diagram
OE
X2
5
3
28
REF0
OSC
X1
2
27
25
÷2
6
48-MHz
PLL
7
9
CPU CLK
PLL
10
÷2
15
16
SEL1
REF2
÷2
24
SEL0
REF1
SBCLK
HCLK0
HCLK1
HCLK2
HCLK3
PCLK5
PCLK4
13
12
Select
Logic
18
19
21
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PCLK3
PCLK2
PCLK1
PCLK0
3
CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MAY 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance state or power-off state,
VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
recommended operating conditions (see Note 3)
MIN
MAX
3.135
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
–8
mA
Low-level output current
8
mA
70
°C
High-level input voltage
2
V
0.8
Input voltage
0
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
0
V
V
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 3.135 V,
VCC = 3.135 V,
II = –18 mA
IOH = – 8 mA
VOL
II
VCC = 3.135 V,
VCC = 3.6 V,
IOL = 8 mA
VI = VCC or GND
IOZ
VCC = 3.6 V,
VO = VCC or GND
ICC
Ci
VCC = 3.6 V,,
VI = VCC or GND
IO = 0,,
MIN
–1.2
2.5
V
V
0.4
V
±1
µA
µA
50
mA
Outputs disabled
1
mA
VI = VCC or GND
VO = VCC or GND
POST OFFICE BOX 655303
UNIT
Outputs enabled§
Co
‡ All typical values are at VCC = 3.3 V.
§ Device in normal operating mode with no load on outputs
4
TA = 25°C
TYP‡
MAX
• DALLAS, TEXAS 75265
6
pF
6
pF
CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MAY 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
Stabilization time†
MAX
After SEL1, SEL0
5
After OE↑
5
After power up
5
UNIT
ms
† Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications for propagation delay and
skew parameters given in the switching characteristics table are not applicable.
switching characteristics (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
(
)
TO
(OUTPUT)
(
)
tskew‡
Offset‡
HCLKn
Duty cycle
200
ps
PCLKn
400
ps
4
ns
HCKLn
±250
ps
PCLKn
±350
ps
Any output
HCKLn
tc‡
PCLKn
1
45%
55%
SEL0 = L, SEL1 = L
20
ns
SEL0 = L, SEL1 = H
16.7
ns
SEL0 = H, SEL1 = L
15
ns
SEL0 = L, SEL1 = L
40
ns
SEL0 = L, SEL1 = H
33.3
ns
SEL0 = H, SEL1 = L
30
ns
HCLKn
tr‡§
UNIT
HCLKn
PCLKn
Jitter‡
VCC = 3.135 V
to 3.6 V,
TA = 0°C to 70°C
MIN
MAX
PCKLn
2
ns
2
ns
HCKLn
tf‡§
PCLKn
‡ Specifications are applicable only after the PLL stabilization time has elapsed.
§ Rise and fall times are characterized using the load circuits shown in Figure 1.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MAY 1996
PARAMETER MEASUREMENT INFORMATION
CLOCK DRIVER CIRCUITS
tc
Duty Cycle
From Output
Under Test
CL = 20 pF
(see Note A)
500 Ω
2.4 V
1.5 V
0.4 V
LOAD CIRCUIT
tr
tf
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
C. The outputs are measured one at a time with one transition per measurement.
v 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,tf ≤ 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
VOH
1.5 V
CPU Clock
(HCLK)
GND
VOH
1.5 V
CPU Clock
(HCLK)
GND
skew
HCLK-to-HCLK Skew
VOH
1.5 V
PCI Clock
(PCLK)
GND
VOH
1.5 V
PCI Clock
(PCLK)
GND
skew
PCLK-to-PCLK Skew
VOH
1.5 V
CPU Clock
(HCLK)
GND
VOH
1.5 V
PCI Clock
(PCLK)
GND
Offset
Offset
HCLK-to-PCLK Offset
Figure 2. Waveforms for Calculation of tskew and Offset
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Low Power Wireless www.ti.com/lpw
Mailing Address:
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2007, Texas Instruments Incorporated
Similar pages