Renesas ISL9305IRTHWCNLZEV1Z 3mhz dual 1.5a step-down converters and dual low-input ldos with i2c compatible interface Datasheet

DATASHEET
ISL9305H
FN7724
Rev 2.00
March 7, 2014
3MHz Dual 1.5A Step-Down Converters and Dual Low-Input LDOs with I2C
Compatible Interface
The ISL9305H is an integrated mini Power Management IC
(mini-PMIC) for powering low-voltage microprocessors, or
applications using a single Li-Ion or Li-Polymer cell battery to
power multiple voltage rails. The ISL9305H integrates two
high-efficiency 3MHz synchronous step-down converters (DCD1
and DCD2) and two low-input, low-dropout linear regulators
(LDO1 and LDO2).
Features
The 3MHz PWM switching frequency allows the use of very
small external inductors and capacitors. Both step-down
converters can enter skip mode under light load conditions to
further improve the efficiency and maximize the battery life.
For noise sensitive applications, they can also be programmed
through I2C interface to operate in forced PWM mode
regardless of the load current condition. The I2C interface
supports on-the-fly slew rate control of the output voltage from
0.825V to 3.6V at 25mV/step size for dynamic power saving.
Each step-down converter can supply up to 1.5A load current.
The default output voltage can be set from 0.8V to VIN using
external feedback resistors on the adjustable version, or the
ISL9305H can be ordered in factory pre-set voltage options
from 0.9V to 3.6V in 50mV step.
• 400kb/s I2C-Bus Series Interface Transfers the Control Data
Between the Host Controller and the ISL9305H
• Dual 1.5A, Synchronous Step-down Converters and Dual
300mA, General-purpose LDOs
• Input Voltage Range
- DCD1/DCD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to 5.5V
- LDO1/LDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 5.5V
• Adjustable Output Voltage
- VODCD1/VODCD2 . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to VIN
• Fixed Output I2C Programmability
- At 25mV/Step . . . . . . . . . . . . . . . . . . . . . . . . 0.825V to 3.6V
• LDO1/LDO2 Output Voltage I2C Programmability
- At 50mV/Step . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9V to 3.6V
• 50μA IQ (Typ) with DCD1/DCD2 in Skip Mode; 20μA IQ (Typ)
for Each Enabled LDO
The ISL9305H also provides two 300mA low dropout (LDO)
regulators. The input voltage range is 1.5V to 5.5V allowing them
to be powered from one of the on-chip step-down converters or
directly from the battery. The default LDO output comes with
factory pre-set fixed output voltage options between 0.9V to 3.3V.
The ISL9305H is available in a 4mmx4mm 16 Ld TQFN package.
• On-the-fly I2C Programming of DC/DC and LDO Output
Voltages
• DCD1/DCD2 I2C Programmable Skip Mode Under Light
Load or Forced Fixed Switching Frequency PWM Mode
• Small, Thin 4mmx4mm TQFN Package
Applications
• Cellular Phones, Smart Phones
Related Literature
• PDAs, Portable Media Players, Portable Instruments
• FN7605, ISL9305 Data Sheet
• Single Li-Ion/Li-Polymer Battery-Powered Equipment
• AN1564 “ISL9305 and ISL9305H Evaluation Boards”
• DSP Core Power
PG
2.5V TO 5.5V
C10
10µF
1.5V TO 5.5V
C2
1µF
1.5V TO 5.5V
C3
1µF
SW1
VINDCD1
VINDCD2
FB1
SDAT
SCLK
SW2
VINLDO1
ISL9305H
FB2
VOLDO1
VOLDO2
GNDDCD1 GNDDCD2 GNDLDO
L1 = 1.5µH
R1
1.5A
R2
*
L2 = 1.5µH
R3
C4
10µF
1.5A
*
R4
C5
10µF
300mA
VINLDO2
300mA
C6
1µF
C7
1µF
*Only for adjustable output version. For fixed output version, directly
connect the FB pin to the output of the buck converter.
FIGURE 1. TYPICAL APPLICATION DIAGRAM
FN7724 Rev 2.00
March 7, 2014
Page 1 of 17
ISL9305H
TABLE 1. TYPICAL APPLICATION PARTS LIST
PARTS
L1, L2
DESCRIPTION
MANUFACTURER
PART NUMBER
SPECIFICATIONS
SIZE
Inductor
Sumida
CDRH2D14NP-1R5
1.5µH/1.80A/50mΩ
3.0mmx3.0mmx1.55mm
C1
Input capacitor
Murata
GRM21BR60J106KE19L
10µF/6.3V
0805
C2, C3
Intput capacitor
Murata
GRM185R60J105KE26D
1µF/6.3V
0603
C4, C5
Output capacitor
Murata
GRM21BR71A106KE51L
10µF/6.3V
0805
C6, C7
Output capacitor
Murata
GRM185R60J105KE26D
1µF/6.3V
0603
R1, R2,
R3, R4
Resistor
Various
1%, SMD, 0.1W
0603
Pin Configuration
SW1
GNDCDC1
GNDDCD1
GNDDCD2
SW2
ISL9305H
(16 LD 4x4 TQFN)
TOP VIEW
16
15
14
13
VINDCD1 1
12 VINDCD2
FB1 2
11 FB2
E-PAD
SCLK 3
10 DCDPG
9 GNDLDO
5
6
7
8
VINLDO1
VOLDO1
VOLDO2
VINLDO2
SDAT 4
Pin Descriptions
PIN NUMBER
(TQFN)
NAME
DESCRIPTION
1
VINDCD1
Input voltage for buck converter DCD1 and it also serves as the power supply pin for the whole internal digital/analog
circuits.
2
FB1
Feedback pin for DCD1, connect external voltage divider resistors between DCDC1 output, this pin and ground. For
fixed output versions, connect this pin directly to the DCD1 output.
3
SCLK
I2C interface clock pin.
4
SDAT
I2C interface data pin.
5
VINLDO1
Input voltage for LDO1.
6
VOLDO1
Output voltage of LDO1.
7
VOLDO2
Output voltage of LDO2.
8
VINLDO2
Input voltage for LDO2.
9
GNDLDO
Power ground for LDO1 and LDO2.
10
DCDPG
FN7724 Rev 2.00
March 7, 2014
The DCDPG pin is an open-drain output to indicate the state of the DCD1/DCD2 output voltages. When both DCD1
and DCD2 are enabled, the output is released to be pulled high by an external pull-up resistor if both converter
voltages are within the power good range. The pin will be pulled low if either DCD is outside their range. When only
one DCD is enabled, the state of the enabled DCD’s output will define the state of the DCDPG pin. The DCDPG state
can be programmed for a delay of up to 200ms before being released to rise high. The programming range is
1ms~200ms through the I2C interface.
Page 2 of 17
ISL9305H
Pin Descriptions (Continued)
PIN NUMBER
(TQFN)
NAME
DESCRIPTION
11
FB2
Feedback pin for DCD2, connect external voltage divider resistors between DCD2 output, this pin and ground. For
fixed output versions, connect this pin directly to the DCD2 output.
12
VINDCD2
13
SW2
14
GNDDCD2
Power ground for DCD2.
15
GNDDCD1
Power ground for DCD1.
16
SW1
Switching node for DCD1, connect to one terminal of the inductor.
E-PAD
E-PAD
Exposed Pad. Connect to system ground.
Input voltage for buck converter DCD2.
Switching node for DCD2, connect to one terminal of the inductor.
Block Diagram
SHORT
CIRCUIT
PROTECTION
DCDPG
ANALOG/LOGIC
CIRCUIT INPUT
VINDCD1
10µF
DCD1
PGOOD WITH
1~200ms
DELAY TIME
BUCK
CONVERTER
SW1
GNDDCD1
SW2
DCD2
BUCK
CONVERTER
I2C
INTERFACE
10µF
GNDDCD2
VOLDO1
1µF
VINLDO2
1µF
LDO2
300mA
FN7724 Rev 2.00
March 7, 2014
FB2
10µF
1µF
LDO1
300mA
SCLK
1.5µH
VINLDO1
THERMAL
SHUTDOWN
SDAT
10µF
FB1
VINDCD2
OVERCURRENT
PROTECTION
UVLO
VREF
OSC
1.5µH
VOLDO2
GNDLDO
1µF
Page 3 of 17
ISL9305H
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
FBSEL
DCD1
(V)
FBSEL
DCD2
(V)
SLV
LDO1
(V)
SLV
LDO2
(V)
TEMP. RANGE
(°C)
PACKAGE
Tape & Reel
(Pb-free)
PKG.
DWG. #
ISL9305IRTHAANLZ-T
9305I HAANLZ
Adj
Adj
3.3
2.9
-40 to +85
16 Ld TQFN
L16.4x4G
ISL9305IRTHWBNLZ-T
9305I HWBNLZ
1.2
1.5
3.3
2.9
-40 to +85
16 Ld TQFN
L16.4x4G
ISL9305IRTHWCLBZ-T
9305I HWCLBZ
1.2
1.8
2.9
1.5
-40 to +85
16 Ld TQFN
L16.4x4G
ISL9305IRTHWCNYZ-T
9305I HWCNYZ
1.2
1.8
3.3
0.9
-40 to +85
16 Ld TQFN
L16.4x4G
ISL9305IRTHWCNLZ-T
9305I HWCNLZ
1.2
1.8
3.3
2.9
-40 to +85
16 Ld TQFN
L16.4x4G
ISL9305IRTHWLNCZ-T
9305I HWLNCZ
1.2
2.9
3.3
1.8
-40 to +85
16 Ld TQFN
L16.4x4G
ISL9305IRTHBCNLZ-T
9305I HBCNLZ
1.5
1.8
3.3
2.9
-40 to +85
16 Ld TQFN
L16.4x4G
ISL9305IRTHBFNCZ-T
9305I HBFNCZ
1.5
2.5
3.3
1.8
-40 to +85
16 Ld TQFN
L16.4x4G
ISL9305IRTHAANLZEV1Z
Evaluation Board for ISL9305IRTHAANLZ
ISL9305IRTHBCNLZEV1Z
Evaluation Board for ISL9305IRTHBCNLZ
ISL9305IRTHBFNCZEV1Z
Evaluation Board for ISL9305IRTHBFNCZ
ISL9305IRTHWBNLZEV1Z
Evaluation Board for ISL9305IRTHWBNLZ
ISL9305IRTHWCLBZEV1Z
Evaluation Board for ISL9305IRTHWCLBZ
ISL9305IRTHWCNLZEV1Z
Evaluation Board for ISL9305IRTHWCNLZ
ISL9305IRTHWCNYZEV1Z
Evaluation Board for ISL9305IRTHWCNYZ
ISL9305IRTHWLNCZEV1Z
Evaluation Board for ISL9305IRTHWLNCZ
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL9305H. For more information on MSL please see techbrief TB363.
FN7724 Rev 2.00
March 7, 2014
Page 4 of 17
ISL9305H
Absolute Maximum Ratings (Refer to ground)
Thermal Information
SW1, SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V
FB1, FB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3.6V
GNDDCD1, GNDDCD2, GNDLDO. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
ESD Ratings
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . .3.5kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 225V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . .2.2kV
Latch Up (Tested per JESD78B, Class II, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
16 Ld TQFN Package (Notes 4, 5) . . . . . . .
40.2
5
Maximum Junction Temperature Range . . . . . . . . . . . . . .-40°C to +150°C
Recommended Junction Temperature Range . . . . . . . . .-40°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VINDCD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to 5.5V
VINDCD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to VINDCD1
VINLDO1 and VINLDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to VINDCD1
DCD1 and DCD2 Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.5A
LDO1 and LDO2 Output Current . . . . . . . . . . . . . . . . . . . . . . 0mA to 300mA
Operating Ambient Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. JC, “case temperature” location is at the center of the exposed metal pad on the package underside.
Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions
and the typical specifications are measured at the following conditions: TA = +25°C, VINDCD1 = 3.6V, VINDCD2 = 3.3V. For LDO1 and LDO2,
VINLDOx = VOLDOx + 0.5V to 5.5V with VINLDOx always no higher than VINDCD1, L1 = L2 = 1.5µH, C1 = 10µF, C4 = C5 = 10µF, C2 = C3 = C6 = C7 = 1µF,
IOUT = 0A for DCD1, DCD2, LDO1 and LDO2 (see “Typical Application Diagram” on page 1 for more details). Boldface limits apply over the operating
temperature range, -40°C to +85°C.
PARAMETER
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
2.5
-
5.5
V
Rising
-
2.2
2.3
V
Falling
1.9
2.1
-
V
SYMBOL
TEST CONDITIONS
VINDCD1, VINDCD2 Voltage Range
VINDCD1, VINDCD2 Undervoltage
Lockout Threshold
VUVLO
Quiescent Supply Current on VINDCD1
IVIN1
Only DCD1 enabled, no load and no switching on DCD1
-
40
60
µA
IVIN2
Only DCD1 and LDO1 enabled, with no load and no
switching on DCD1
-
60
95
µA
IVIN3
Both DCD1 and DCD2 enabled, no load and no switching
on both DCD1 and DCD2
-
50
75
µA
IVIN4
Only LDO1 and LDO2 enabled
-
75
100
µA
IVIN5
DCD1, DCD2, LDO1 and LDO2 are enabled, with no load
and no switching on both DCD1 and DCD2
-
100
130
µA
IVIN6
Only one DCD in forced PWM mode, no load
-
4
7.5
mA
VINDCD1 = 5.5V, DCD1, DCD2, LDO1 and LDO2 are
disabled through I2C interface, VINDCD1 = 4.2V
-
0.15
5
µA
Thermal Shutdown
-
155
-
°C
Thermal Shutdown Hysteresis
-
30
-
°C
0.785
0.8
0.815
V
FB = 0.75V
-
0.001
-
µA
VIN = VO + 0.5V to 5.5V (minimal 2.5V), 1mA load
-3
-
+3
%
Shutdown Supply Current
ISD
DCD1 AND DCD2
FB1, FB2 Regulation Voltage
VFB
FB1, FB2 Bias Current
IFB
Output Voltage Accuracy
FN7724 Rev 2.00
March 7, 2014
Page 5 of 17
ISL9305H
Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions
and the typical specifications are measured at the following conditions: TA = +25°C, VINDCD1 = 3.6V, VINDCD2 = 3.3V. For LDO1 and LDO2,
VINLDOx = VOLDOx + 0.5V to 5.5V with VINLDOx always no higher than VINDCD1, L1 = L2 = 1.5µH, C1 = 10µF, C4 = C5 = 10µF, C2 = C3 = C6 = C7 = 1µF,
IOUT = 0A for DCD1, DCD2, LDO1 and LDO2 (see “Typical Application Diagram” on page 1 for more details). Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
PARAMETER
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
-
0.1
-
%/V
1500
-
-
mA
VIN = 3.6V, IO = 200mA
-
0.14
0.20
Ω
VIN = 2.3V, IO = 200mA
-
0.24
0.40
Ω
VIN = 3.6V, IO = 200mA
-
0.11
0.20
Ω
0.18
0.34
Ω
2.1
2.5
2.75
A
-
100
-

-
0.005
1
µA
2.6
3.0
3.4
MHz
-
70
-
ns
-
115
-
Ω
-
-
0.25
V
SYMBOL
Line Regulation
TEST CONDITIONS
VIN = VO + 0.5V to 5.5V (minimal 2.5V)
Maximum Output Current
P-Channel MOSFET ON-resistance
N-Channel MOSFET ON-resistance
VIN = 2.3V, IO = 200mA
P-Channel MOSFET Peak Current Limit
IPK
SW Maximum Duty Cycle
VIN = 5.5V
SW Leakage Current
PWM Switching Frequency
fS
VFB = 0.75V
SW Minimum ON-time
Bleeding Resistor
PG
Output Low Voltage
Sinking 1mA, FB1 = FB2 = 0.7V
Rising Delay Time
Based on 1ms programmed nominal delay time
0.6
1.1
1.8
ms
Falling Delay Time
Based on 1ms programmed nominal delay time
-
30
-
µs
PG Pin Leakage Current
PG = VINDCD1 = VINDCD2 = 3.6V
-
0.005
0.1
µA
PG Low Rising Threshold
Percentage of nominal regulation voltage
-
91
-
%
PG Low Falling Threshold
Percentage of nominal regulation voltage
-
87
-
%
PG High Rising Threshold
Percentage of nominal regulation voltage
-
112
-
%
PG High Falling Threshold
Percentage of nominal regulation voltage
-
109
-
%
1.5
-
5.5
V
Rising
-
1.41
1.46
V
Falling
1.33
1.37
-
V
350
425
540
mA
IO = 300mA, VO  2.1V
-
120
250
mV
IO = 300mA, 2.1V < VO  2.8V
-
100
200
mV
IO = 300mA, VO > 2.8V
-
80
170
mV
Power Supply Rejection Ratio
IO = 300mA @ 1kHz, VIN = 3.6V, VO = 2.6V, TA = +25°C
-
55
-
dB
Output Voltage Noise
VIN = 4.2V, IO = 10mA, TA = +25°C, BW = 10Hz to 100kHz
-
45
-
µVRMS
LDO1 AND LDO2
VINLDO1, VINLDO2 Supply Voltage
VINLDO1, VINLDO2 Undervoltage
Lockout Threshold
No higher than VINDCD1
VUVLO
Internal Peak Current Limit
Dropout Voltage
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN7724 Rev 2.00
March 7, 2014
Page 6 of 17
ISL9305H
Theory of Operation
vEAMP
DCD1 and DCD2 Introduction
vCSA
Both the DCD1 and DCD2 converters on ISL9305H use the
peak-current-mode pulse-width modulation (PWM) control scheme
for fast transient response and pulse-by-pulse current limiting.
Both converters are able to supply up to 1.5A load current. The
default output voltage ranges from 0.8V to 3.6V depending on the
factory pre-set configuration and can be programmed via the I2C
interface in the range of 0.825V to 3.6V at 25mV/step with a
programmable slew rate. An open-drain DCDPG (DCD Power-Good)
signal is also provided to monitor the DCD1 and DCD2 output
voltages. Optionally, both DCD1 and DCD2 can be programmed to
be actively discharged via an on-chip bleeding resistor (typical
115Ω) when the converter is disabled.
Skip Mode (PFM Mode) for DCD1/DCD2
Under light load condition, the DCD1 and DCD2 can be programmed
to automatically enter a pulse-skipping mode to minimize the
switching loss by reducing the switching frequency. Figure 3
illustrates the skip mode operation. A zero-cross sensing circuit
monitors the current flowing through SW node for zero crossing.
When it is detected to cross zero for 16 consecutive cycles, the
regulator enters the skip mode. During the 16 consecutive cycles,
the inductor current could be negative. The counter is reset to zero
when the sensed current flowing through the SW node does not
cross zero during any cycle within the 16 consecutive cycles. Once
the converter enters the skip mode, the pulse modulation is
controlled by an internal comparator while each pulse cycle remains
synchronized to the PWM clock. The P-Channel MOSFET is turned on
at the rising edge of the clock and turned off when its current
reaches ~20% of the peak current limit. As the average inductor
current in each cycle is higher than the average current of the load,
the output voltage rises cycle-over-cycle. When the output voltage is
sensed to reach 1.5% above its nominal voltage, the P-Channel
MOSFET is turned off immediately and the inductor current is fully
discharged to zero and stays at zero. The output voltage reduces
gradually due to the load current discharging the output capacitor.
When the output voltage drops to the nominal voltage, the
P-Channel MOSFET will be turned on again, repeating the previous
operations.
d
iL
vOUT
FIGURE 2. PWM OPERATION WAVEFORMS
The regulator resumes normal PWM mode operation when the
output voltage is sensed to drop below 1.5% of its nominal
voltage value.
Soft-Start
The soft-start reduces the in-rush current during the start-up stage.
The soft-start block limits the current rising speed so that the
output voltage rises in a controlled fashion.
Overcurrent Protection
The overcurrent protection for DCD1 and DCD2 is provided on the
ISL9305H when an overload condition occurs. When the current at
P-Channel MOSFET is sensed to reach the current limit, the
internal protection circuit is triggered to turn off the P-Channel
MOSFET immediately.
DCD Short-Circuit Protection
The ISL9305H provides Short-Circuit Protection for both DCD1 and
DCD2. The feedback voltage is monitored for output short-circuit
protection. When the output voltage is sensed to be lower than a
certain threshold, the internal circuit will change the PWM oscillator
frequency to a lower frequency in order to protect the IC from
damage. The P-Channel MOSFET peak current limit remains active
during this state.
16 CYCLES
CLOCK
20% PEAK CURRENT LIMIT
IL
0
1.015*VOUT_NOMINAL
VOUT
VOUT_NOMINAL
FIGURE 3. SKIP MODE OPERATION WAVEFORMS
FN7724 Rev 2.00
March 7, 2014
Page 7 of 17
ISL9305H
Undervoltage Lockout (UVLO)
An undervoltage lockout (UVLO) circuit is provided on ISL9305H. The
UVLO circuit block can prevent abnormal operation in the event that
the supply voltage is too low to guarantee proper operation. The
UVLO on VINDCD1 is set for a typical 2.2V with 100mV hysteresis.
VINLDO1 and VINLDO2 are set for a typical 1.4V with 50mV
hysteresis. When the input voltage is sensed to be lower than the
UVLO threshold, the related channel is disabled.
Active Output Voltage Discharge for
DCD1/DCD2
The ISL9305H offers a feature to actively discharge the output
voltage of DCD1 and DCD2 via an internal bleeding resistor
(typical 115Ω) when the channel is disabled. This feature is
enabled by default, but individual outputs can be disabled
through programming the control bit in the DCD_PARAMETER
register.
DCDPG (DCD Power-Good)
Thermal Shutdown
ISL9305H offers an open-drain Power-Good signal with
programmable delay time for monitoring the converters DCD1
and DCD2 output voltage status.
The ISL9305H provides a built-in thermal protection function
with thermal shutdown threshold temperature set at +155°C
with +25°C hysteresis (typical). When the die temperature is
sensed to reach +130°C, the regulator is completely shut down
and as the temperature is sensed to drop to +105°C (typical), the
device resumes normal operation starting from the soft-start.
When both DCD1 and DCD2 are enabled and their output voltages
are within the power-good window, an internal power-good signal is
issued to turn off the open-drain MOSFET so the DCDPG pin voltage
can be externally pulled high after a programmed delay time. If
either DCD1 or DCD2 output voltages or both of them are not within
the power-good window, the DCDPG outputs an open-drain logic low
signal after the programmed delay time.
When only one DCD converter (either DCD1 or DCD2) is enabled,
then the DCDPG only indicates the status of this active DCD
converter. For example, if only DCD1 converter is enabled and
DCD2 converter is disabled, when DCD1 output is within the
power-good window, an internal power-good signal will be issued
to turn off the open-drain MOSFET so the DCDPG pin voltage is
externally pulled high after the programmed delay time. If the
output voltage of DCD1 is outside the power-good window, the
DCDPG outputs an open-drain logic low signal after the
programmed delay time. It is similar when only DCD2 is enabled
and DCD1 is disabled. When both converters are disabled,
DCDPG always outputs the open-drain logic low signal.
Low Dropout Operation
Both DCD1 and DCD2 converters feature the low dropout operation
to maximize the battery life. When the input voltage drops to a level
that the converter can no longer operate under switching regulation
to maintain the output voltage, the P-Channel MOSFET is completely
turned on (100% duty cycle). The dropout voltage under such a
condition is the product of the load current and the ON-resistance of
the P-Channel MOSFET. Minimum required input voltage VIN under
such condition is the sum of output voltage plus the voltage drop
across the inductor and the P-Channel MOSFET switch.
I2C Compatible Interface
The ISL9305H offers an I2C compatible interface, using two pins:
SCLK for the serial clock and SDAT for serial data respectively.
According to the I2C specifications, a pull-up resistor is needed for
the clock and data signals to connect to a positive supply. When the
ISL9305 and the host use different supply voltages, the pull-up
resistors should be connected to the higher voltage rail.
Signal timing specifications should satisfy the standard I2C bus
specification. The maximum bit rate is 400kb/s and more details
regarding the I2C specifications can be found from Philips.
I2C Slave Address
The ISL9305H serves as a slave device and the 7-bit default chip
address is 1101000, as shown in Figure 4. According to the I2C
specifications, here the value of Bit 0 determines the direction of
the message (“0” means “write” and “1” means “read”).
MSB
LSB
1
1
0
1
0
0
0
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FIGURE 4. I2C SLAVE ADDRESS
I2C Protocol
Figures 5, 6, and 7 show three typical I2C-bus transaction protocols.
FN7724 Rev 2.00
March 7, 2014
Page 8 of 17
ISL9305H
S
SLAVE ADDRESS
0 A
REGISTER ADDRESS
A
DATA BYTE 1
A
SYSTEM HOST
R/W
AUTO INCREMENT
REGISTER ADDRESS
OPTIONAL
DATA BYTE 2
A
DATA BYTE N
AUTO INCREMENT
REGISTER ADDRESS
A
ISL9305H
A – ACKNOWLEDGE
N – NOT ACKNOWLEDGE
S – START
P – STOP
P
AUTO INCREMENT
REGISTER ADDRESS
FIGURE 5. I2C WRITE
S
SLAVE ADDRESS
0 A
REGISTER ADDRESS
A
S
SLAVE ADDRESS
1 A
SYSTEM HOST
R/W
ISL9305H
R/W
OPTIONAL
DATA BYTE 1
A
DATA BYTE 2
AUTO INCREMENT
REGISTER ADDRESS
A
DATA BYTE N
AUTO INCREMENT
REGISTER ADDRESS
N
P
A – ACKNOWLEDGE
N – NOT ACKNOWLEDGE
S – START
P – STOP
AUTO INCREMENT
REGISTER ADDRESS
FIGURE 6. I2C READ SPECIFYING REGISTER ADDRESS
OPTIONAL
S
SLAVE ADDRESS
1 A
R/W
DATA BYTE 1
A
DATA BYTE 2
AUTO INCREMENT
REGISTER ADDRESS
A
AUTO INCREMENT
REGISTER ADDRESS
DATA BYTE N
N
P
AUTO INCREMENT
REGISTER ADDRESS
SYSTEM HOST A – ACKNOWLEDGE
N – NOT ACKNOWLEDGE
S – START
ISL9305H
P – STOP
FIGURE 7. I2C READ NOT SPECIFYING REGISTER ADDRESS
FN7724 Rev 2.00
March 7, 2014
Page 9 of 17
ISL9305H
I2C Control Registers
TABLE 2. BUCK CONVERTERS OUTPUT VOLTAGE CONTROL REGISTER
All the registers are reset at initial start-up.
BIT
DCD OUTPUT VOLTAGE CONTROL REGISTER
B7
Reserve
DCD1OUT, address 0x00h; DCD2OUT, address 0x01h
B6
DCDxOUT-6
B5
DCDxOUT-5
R/W
0
B4
DCDxOUT-4
R/W
1
B3
DCDxOUT-3
R/W
0
B2
DCDxOUT-2
R/W
0
B1
DCDxOUT-1
R/W
0
B0
DCDxOUT-0
R/W
0
The output voltages of the two DC/DC converters at power-up are
internally fixed by the IC fuse as dictated by the part number,
After power-up, different voltages can be selected (except for the
adjustable version) by first writing a desired value to this register.
Then write a “1” to Bit 6 of the SYS_PARAMETER (Table 7) to
change the voltage control method to I2C control.
NAME
ACCESS
DEFAULT
-
0
R/W
0
DESCRIPTION
Refer to Table 3
TABLE 3. DCD1 AND DCD2 OUTPUT VOLTAGE SETTING
DCDOUT
<7:0>
DCD OUTPUT
VOLTAGE
(V)
DCDOUT
<7:0>
DCD OUTPUT
VOLTAGE
(V)
DCDOUT
<7:0>
DCD OUTPUT
VOLTAGE
(V)
DCDOUT
<7:0>
DCD OUTPUT
VOLTAGE
(V)
00
0.825
20
1.625
40
2.425
60
3.225
01
0.850
21
1.650
41
2.450
61
3.250
02
0.875
22
1.675
42
2.475
62
3.275
03
0.900
23
1.700
43
2.500
63
3.300
04
0.925
24
1.725
44
2.525
64
3.325
05
0.950
25
1.750
45
2.550
65
3.350
06
0.975
26
1.775
46
2.575
66
3.375
07
1.000
27
1.800
47
2.600
67
3.400
08
1.025
28
1.825
48
2.625
68
3.425
09
1.050
29
1.850
49
2.650
69
3.450
0A
1.075
2A
1.875
4A
2.675
6A
3.475
0B
1.100
2B
1.900
4B
2.700
6B
3.500
0C
1.125
2C
1.925
4C
2.725
6C
3.525
0D
1.150
2D
1.950
4D
2.750
6D
3.550
0E
1.175
2E
1.975
4E
2.775
6E
3.575
0F
1.200
2F
2.000
4F
2.800
6F
3.600
10
1.225
30
2.025
50
2.825
11
1.250
31
2.050
51
2.850
12
1.275
32
2.075
52
2.875
13
1.300
33
2.100
53
2.900
14
1.325
34
2.125
54
2.925
15
1.350
35
2.150
55
2.950
16
1.375
36
2.175
56
2.975
17
1.400
37
2.200
57
3.000
18
1.425
38
2.225
58
3.025
19
1.450
39
2.250
59
3.050
1A
1.475
3A
2.275
5A
3.075
1B
1.500
3B
2.300
5B
3.100
1C
1.525
3C
2.325
5C
3.125
1D
1.550
3D
2.350
5D
3.150
1E
1.575
3E
2.375
5E
3.175
1F
1.600
3F
2.400
5F
3.200
FN7724 Rev 2.00
March 7, 2014
Page 10 of 17
ISL9305H
LDO1 AND LDO2 OUTPUT VOLTAGE CONTROL
REGISTERS
TABLE 4. LDOX OUTPUT VOLTAGE CONTROL REGISTERS
BIT
LDO1OUT, address 0x02h and LDO2OUT, address 0x03h.
The output voltages of the two LDO’s at power-up are internally
fixed by the IC fuse as dictated by the part number, After
power-up, different voltages can be selected by first writing a
desired value to this register. Then write a “1” to Bit 6 of the
SYS_PARAMETER (Table 7) to change the voltage control method
to I2C control.
NAME
ACCESS
DEFAULT
B7
Reserve
-
0
B6
Reserve
-
0
B5
LDOxOUT-5
R/W
0
B4
LDOxOUT-4
R/W
0
B3
LDOxOUT-3
R/W
1
B2
LDOxOUT-2
R/W
1
B1
LDOxOUT-1
R/W
0
B0
LDOxOUT-0
R/W
0
DESCRIPTION
Refer to Table 5 for
output voltage
settings
TABLE 5. LDOX OUTPUT VOLTAGE SETTINGS
LDOOUT
<7:0>
LDO OUTPUT
VOLTAGE (V)
LDOOUT
<7:0>
LDO OUTPUT
VOLTAGE (V)
LDOOUT
<7:0>
LDO OUTPUT
VOLTAGE (V)
LDOOUT
<7:0>
LDO OUTPUT
VOLTAGE (V)
00
0.9
10
1.70
20
2.50
30
3.30
01
0.95
11
1.75
21
2.55
31
3.35
02
1.00
12
1.80
22
2.60
32
3.40
03
1.05
13
1.85
23
2.65
33
3.45
04
1.1
14
1.90
24
2.70
34
3.50
05
1.15
15
1.95
25
2.75
35
3.55
06
1.20
16
2.00
26
2.80
36
3.60
07
1.25
17
2.05
27
2.85
08
1.30
18
2.10
28
2.90
09
1.35
19
2.15
29
2.95
0A
1.40
1A
2.20
2A
3.00
0B
1.45
1B
2.25
2B
3.05
0C
1.50
1C
2.30
2C
3.10
0D
1.55
1D
2.35
2D
3.15
0E
1.60
1E
2.40
2E
3.20
0F
1.65
1F
2.45
2F
3.25
FN7724 Rev 2.00
March 7, 2014
Page 11 of 17
ISL9305H
DCD1 AND DCD2 CONTROL REGISTER
DCD_PARAMETER, address 0x04h
TABLE 6. DCD_PARAMETER REGISTER
BIT
NAME
B7
-
ACCESS RESET
B6 DCD_PHASE
-
0
R/W
0
Reserved
DCD1 and DCD2 PWM switch
selection. 0-in phase; 1 to 180°
out-of-phase.
R/W
0
Ultrasonic feature under PFM mode
for DCD2. 0-disabled; 1-enabled.
B4 DCD1_ULTRA
R/W
0
Ultrasonic feature under PFM mode
for DCD1. 0-disabled; 1-enabled.
B3
R/W
1
Selection of DCD2 for active output
voltage discharge when disabled.
0-disabled; 1-enabled.
B2
DCD1_BLD
R/W
1
DCD_SRCTL, address 0x06h
TABLE 8. DCD OUTPUT VOLTAGE SLEW RATE CONTROL REGISTER
DESCRIPTION
B5 DCD2_ULTRA
DCD2_BLD
DCD OUTPUT VOLTAGE SLEW RATE CONTROL
REGISTER
Selection of DCD1 for active output
voltage discharge when disabled.
0-disabled; 1-enabled.
B1 DCD2_MODE
R/W
1
Selection on DCD2 of auto
PFM/PWM mode (= 1) or forced
PWM mode (= 0).
B0 DCD1_MODE
R/W
1
Selection on DCD1 of auto
PFM/PWM mode (= 1) or forced
PWM mode (= 0).
BIT
NAME
ACCESS RESET
DESCRIPTION
B7 DCD2SR_2
R/W
0
B6 DCD2SR_1
R/W
0
B5 DCD2SR_0
R/W
1
-
0
Reserved
B3 DCD1SR_2
R/W
0
B2 DCD1SR_1
R/W
0
B1 DCD1SR_0
R/W
1
DCD1 Slew Rate Setting, DCD1SR[2:0]:
000 to 0.225mV/µs
001 to 0.45mV/µs
010 to 0.90mV/µs
011 to 1.8mV/µs
100 to 3.6mV/µs
101 to 7.2mV/µs
110 to 14.4mV/µs
111 to 28.8mV/µs
-
0
B4
B0
Reserve
Reserve
DCD2 Slew Rate Setting, DCD2SR[2:0]:
000 to 0.225mV/µs
001 to 0.45mV/µs
010 to 0.90mV/µs
011 to 1.8mV/µs
100 to 3.6mV/µs
101 to 7.2mV/µs
110 to 14.4mV/µs
111 to 28.8mV/µs
Reserved
SYSTEM CONTROL REGISTER
SYS_PARAMETER, address 0x05h
TABLE 7. SYS_PARAMETER REGISTER
BIT
NAME
ACCESS RESET
DESCRIPTION
B7
-
-
0
Reserved
B6
I2C_CTRL
R/W
0
Output voltage control method, 0-fuse
control; 1-I2C control
B5 DCDPOR_1
R/W
1
B4 DCDPOR_0
R/W
0
DCDPG Delay Time Setting,
DCDPG[1:0]:
00 to 1ms
01 to 50ms
10 to 150ms
11 to 200m
B3
LDO2_EN
R/W
1
LDO2 enable selection. 0-disable,
1-enable.
B2
LDO1_EN
R/W
1
LDO1 enable selection. 0-disable,
1-enable
B1 DCD2_EN
R/W
1
DCD2 enable selection. 0-disable,
1-enable.
B0 DCD1_EN
R/W
1
DCD1 enable selection. 0-disable,
1-enable
FN7724 Rev 2.00
March 7, 2014
Page 12 of 17
ISL9305H
Typical Operating Conditions
FIGURE 8. DCD OUTPUT RIPPLE (VIN = 4.2V, PFM, TIME SCALE = 1µs)
CH1: VODCD1 (20mV/DIV), CH2: IL1 (500mA/DIV),
CH3: VODCD2 (20mV/DIV), CH4: IL2 (500mA/DIV)
FIGURE 9. DCD OUTPUT RIPPLE (VIN = 4.2V, FULL LOADING @
VODCD1 AND VODCD2, TIME SCALE = 200ns)
CH1: SW1 (5V/DIV), CH2: VODCD1 (20mA/DIV),
CH3: SW2 (5V/DIV), CH4: VODCD2 (20mA/DIV)
FIGURE 10. INDUCTOR CURRENT RIPPLE (VIN = 3.6V, PFM,
TIME SCALE = 200ns) CH1: SW1 (2V/DIV),
CH2: IL1 (200mA/DIV), CH3: SW2 (2V/DIV),
CH4: IL2 (200mA/DIV)
FIGURE 11. INDUCTOR CURRENT RIPPLE (VIN = 3.6V, FULL LOADING,
PWM, TIME SCALE = 200ns) CH1: SW1 (2V/DIV),
CH2: IL1 (500mA/DIV), CH3: SW2 (2V/DIV),
CH4: IL2 (500mA/DIV)
FIGURE 12. DCD1 TRANSIENT RESPONSE (VIN = 3.6V, STEP LOAD:
150mA TO 1500mA) CH1: VODCD1 (100mV/DIV, AC),
CH2: VODCD2 (50mV/DIV, AC, CH4: IL4 (500mA/DIV)
FIGURE 13. DCD2 TRANSIENT RESPONSE (VIN = 3.6V, STEP LOAD:
150mA TO 1500mA) CH1: VODCD1 (100mV/DIV, AC),
CH2: VODCD2 (50mV/DIV, AC, CH4: IL4 (500mA/DIV)
FN7724 Rev 2.00
March 7, 2014
Page 13 of 17
ISL9305H
Typical Operating Conditions (Continued)
FIGURE 15. 4-CHANNEL DEFAULT START-UP @ FULL LOAD
CH1: VODCD1 (2V/DIV), CH2: VODCD2 (1V/DIV),
CH3: VOLDO1 (1V/DIV), CH4: VOLDO2 (2V/DIV)
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
FIGURE 14. 4-CHANNEL DEFAULT START-UP @ NO LOAD
CH1: VODCD1 (2V/DIV), CH2: VODCD2 (1V/DIV),
CH3: VOLDO1 (1V/DIV), CH4: VOLDO2 (2V/DIV)
70
VIN = 5.5V VIN = 3.6V
60
VIN = 2.8V
50
VIN = 5.5V VIN = 3.6V
60
50
1
10
100
1000
30
10000
1
10
OUTPUT CURRENT (mA)
FIGURE 16. EFFICIENCY vs LOAD (VOUT = 1.8V, PFM/PWM)
1.83
1.23
1.82
1.22
1.81
1.80
VIN = 5.5V
1.79
VIN = 3.6V
VIN = 2.8V
1.78
10000
1.21
1.20
VIN = 5.5V
VIN = 3.6V
VIN = 2.8V
1.19
1.18
1.77
1.76
100
1000
OUTPUT CURRENT (mA)
FIGURE 17. EFFICIENCY vs LOAD (VOUT = 1.2V, FORCED PWM)
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VIN = 2.8V
40
40
30
70
1
10
100
1000
OUTPUT CURRENT (mA)
FIGURE 18. DCD OUTPUT VOLTAGE vs OUTPUT CURRENT
(VOUT = 1.8V, PFM/PWM)
FN7724 Rev 2.00
March 7, 2014
10000
1.17
1
10
100
1000
OUTPUT CURRENT (mA)
10000
FIGURE 19. DCD OUTPUT VOLTAGE vs OUTPUT CURRENT
(VOUT = 1.2V, PFM/PWM)
Page 14 of 17
ISL9305H
70
58
QUIESCENT CURRENT (µA)
POWER SUPPLY REJECTION RATIO (dB)
Typical Operating Conditions (Continued)
60
50
40
30
PSRR
20 V = 3.6V
IN
10 VOUT = 2.6V
LOAD = 300mA
0
0.1
1
56
52
50
100
1000
+25°C
48
46
44
42
10
+85°C
54
40
2.5
-40°C
VO = 1.2V
DCD1 = DCD2 = NO SWITCHING, NO LOAD
LDO1 = LDO2 = DISABLED
3.0
3.5
FREQUENCY (kHz)
FIGURE 20. RIPPLE REJECTION RATIO vs FREQUENCY
4.0
4.5
5.0
5.5
6.0
INPUT VOLTAGE (V)
FIGURE 21. QUIESCENT CURRENT vs INPUT VOLTAGE
© Copyright Intersil Americas LLC 2010-2014. All Rights Reserved.
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
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otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7724 Rev 2.00
March 7, 2014
Page 15 of 17
ISL9305H
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
3/7/14
FN7724.2 Pg4 - Added Evaluation board descriptions.
Pg10 - Deleted Caution: Disable DCD prior to changing from fixed output voltage to adjustable output voltage or from adjustable
output voltage to fixed output voltage using I2C. Added description of the DCD’s output voltage control. Changed Table 2 column
name from “RESET” to “DEFAULT.
Pg11 - Added description of the LDO’s output voltage control. Changed Table 4column name from “RESET” to “DEFAULT.
7/24/12
Pg 1 - Changed “the ISL9305H can be ordered in factory pre-set power-up default voltages in increments of 100mV from 0.9V
to 3.6V.” to “the ISL9305H can be ordered in factory pre-set output voltage options from 0.9V to 3.6V in 50mV step.”
Pg 1 - Changed Related Literature AN1564 title from “ISL9305IRTZEVAL1Z and ISL9305HIRTZEVAL1Z
Evaluation Boards” to “ISL9305 and ISL9305H Evaluation Boards”
Pg 1 Features - Changed “at 50mV/Step.....0.9V to 3.3V” to “25mV/Step.......0.9V to 3.6V” under LDO1/LDO2 output voltage I2C
programmability.
Pg 3 - Changed the output capacitor value at VOLDO1 and VOLDO2 from "10uF" to "1uF" in the block diagram
Pg 4 - List of Eval Board FGs in Ordering Information table changed from ISL9305IRTBCNLZEV1Z, ISL9305IRTBFNCZEV1Z,
ISL9305IRTAANLZEV1Z to ISL9305IRTHAANLZEV1Z, ISL9305IRTHBCNLZEV1Z, ISL9305IRTHBFNCZEV1Z,
ISL9305IRTHWBNLZEV1Z, ISL9305IRTHWCLBZEV1Z, ISL9305IRTHWCNLZEV1Z, ISL9305IRTHWCNYZEV1Z,
ISL9305IRTHWLNCZEV1Z
Pg 5 - Abs Max Ratings, ESD Ratings changed from:
Machine Model (Tested per JESD22-A115-A) . . . . . . . 2.2kV
Charged Device Model (Tested per JESD22-C101D) . . . . 225V
to:
Machine Model (Tested per JESD22-A115-A) . . . . . . . 225V
Charged Device Model (Tested per JESD22-C101D) . . . . 2.2kV
Pg 12 - Removed PCN “Note 7” under Table 8. Changed “111 to reserve for system use” to “111 to 28.8mV/µs.
- Changed “DCD2” to “DCD1” in line B0 of Table 7.
5/23/11 FN7724.1 -Table 8 on page 12 changed 111 description from “to immediate” to “reserved for system use (Note 7).”
Added Note to Table 8, which reads "The IC can be damaged when output is programmed from high to low and the slew rate
register is set to 111."
Added Eval boards:
ISL9305IRTBCNLZEV1Z
ISL9305IRTBFNCZEV1Z
ISL9305IRTAANLZEV1Z
-Corrected Theta JA Thermal Information on page 5 for TQFN from 42 to 40.2
-“Electrical Specifications” on page 5:
Added "Boldface limits apply over the operating temperature range, -40°C to +85°C." to common conditions. Bolded applicable
specs.
Changed “Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.”
note in Electrical Spec Table on page 6 to “Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested.” per Product Line decision.
11/8/10 FN7724.0 Initial Release.
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FN7724 Rev 2.00
March 7, 2014
Page 16 of 17
ISL9305H
Package Outline Drawing
L16.4x4G
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 4/10
4X 1.95
4.00
12X 0.65
A
B
13
6
PIN 1
INDEX AREA
6
PIN #1
INDEX AREA
16
1
4.00
12
2 . 10 ± 0 . 10
9
(4X)
4
0.15
8
TOP VIEW
5
0.10 M C A B
16X 0 . 50 ± 0 . 1
4 0.30 ± 0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0.75
C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
( 3 . 6 TYP )
(
2 . 10 )
( 12X 0 . 65 )
C
0 . 2 REF
5
( 16X 0 . 30 )
0 . 00 MIN.
0 . 05 MAX.
( 16 X 0 . 70 )
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
JEDEC reference drawing: MO220K.
either a mold or mark feature.
FN7724 Rev 2.00
March 7, 2014
Page 17 of 17