ON NCP1339EDR2G High-voltage, quasiresonant controller featuring valley lock-out and power saving mode Datasheet

NCP1339
High-Voltage, QuasiResonant Controller
featuring Valley Lock-Out
and Power Saving Mode
The NCP1339 is a highly integrated quasi−resonant flyback
controller capable of controlling rugged and high−performance
off−line power supplies as required by adapter applications. With an
integrated active X−cap discharge feature and power savings mode,
the NCP1339 can enable no−load power consumption below 10 mW
for 45 W notebook adapters.
The quasi−resonant current−mode flyback stage features a
proprietary valley−lockout circuitry, ensuring stable valley switching.
This system works down to the 6th valley and toggles to a frequency
foldback mode to eliminate switching losses. When the loop tends to
force below 25−kHz frequencies, the NCP1339 skips cycles to contain
the power delivery.
To help build rugged converters, the controller features several key
protective features: an internal brown−out, a non−dissipative Over Power
Protection for a constant maximum output current regardless of the
input voltage, a latched over−voltage protection through a dedicated pin.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High−voltage Current Source for Lossless Start−up Sequence
X2 Capacitors Discharge Capability
Power Savings Mode (PSM) for Extremely Low No−Load Power:
Wide VCC Range from 10 V to 28 V
Latching−off 28−V VCC Over−Voltage Protection
Abnormal Overcurrent Fault Protection for Winding Short Circuit or
Inductor Saturation Detection
Integrated High−Voltage Startup Circuit with Brown−Out Detection
Fault Input for Severe Fault Conditions, NTC Compatible for OTP
Circuit Latching Off In Severe Fault Detection (OVP or OTP)
Internal Temperature Shutdown
Valley Switching Operation with Valley−Lockout for Noise−Free
Operation
Frequency Fold−back for Highest Performance in Standby Mode
25−kHz Clamp and Skip Mode
Timer−Based Overload Protection (Latched or Auto−Recovery
Options)
Adjustable Overpower Protection
4−ms Soft−Start Timer
ZCD Blanking Time to Ignore Leakage Ringing at Turn−Off:
3 ms for C, D and E versions and 0.7 ms for F, G, H, I and J versions
Ready for High−Density QR design (F, G, H, I and J versions)
These Devices are Pb−Free and are RoHS Compliant
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 5
1
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1
SOIC−14 NB
(LESS PIN 13)
D SUFFIX
CASE 751AN
MARKING DIAGRAM
14
NCP1339xG
AWLYWW
1
NCP1339 = Specific Device Code
x
= C, D, E, F, G, H, I or J
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
X2
REM
OPP
ZCD
Fault
FB
CS
HV
NC
NC
VCC
DRV
GND
(For C, D, E, F, G, and H versions)
X2
REM
OPP
ZCD
Fault
FB
CS
HV
NC
IFF
VCC
DRV
GND
(For I and J versions)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 31 of this data sheet.
Publication Order Number:
NCP1339/D
NCP1339
PART NUMBER MATRIX
Abnormal
Overcurrent
Fault
ZCD Blanking Time
Jittering
Function
Adjustable Frozen
Peak Current
(IFF pin)
Device
Version
Overload
Protection
NCP1339CDR2G
NCP1339C
Auto−recovery
Auto−recovery
3 ms
Disabled
Disabled
NCP1339DDR2G
NCP1339D
Latching−off
Latching−off
3 ms
Disabled
Disabled
NCP1339EDR2G
NCP1339E
Latching−off
Latching−off
3 ms
Enabled
Disabled
NCP1339FDR2G
NCP1339F
Latching−off
Latching−off
0.7 ms
Enabled
Disabled
NCP1339GDR2G
NCP1339G
Auto−recovery
Auto−recovery
0.7 ms
Enabled
Disabled
NCP1339HDR2G
NCP1339H
Auto−recovery
Auto−recovery
0.7 ms
Disabled
Disabled
NCP1339IDR2G
NCP1339I
Latching−off
Latching−off
0.7 ms
Enabled
Enabled
NCP1339JDR2G
NCP1339J
Auto−recovery
Auto−recovery
0.7 ms
Enabled
Enabled
Vout
Vaux
GND
PSM_OFF
NCP1339
X2
1
14
REM
2
13
3
12
4
11
5
10
6
9
7
8
N
EMI
Filter
L1
FB
Vcc
GND
CS
Rsense
Figure 1. NCP1339 Typical Application Circuit (without IFF pin)
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2
NCP1339
Vout
Vaux
GND
PSM_OFF
NCP1339
X2
1
14
REM
2
13
3
12
4
11
5
10
6
9
7
8
N
EMI
Filter
IFF
Vcc
FB
L1
GND
CS
Rsense
Figure 2. NCP1339 Typical Application Circuit (with IFF pin)
PIN FUNCTION DESCRIPTION
Pin
Number
Pin
Name
1
X2
2
REM
The part operates when the REM pin is forced lower than a certain level and enters the Power Savings
Mode (PSM) otherwise.
3
OPP
A resistive divider from the auxiliary winding to this pin sets the OPP compensation level.
4
ZCD
Input to the demagnetization detection comparator for the QR Flyback controller.
5
Fault
The controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds. A precise pull up current source allows direct interface with an NTC thermistor. Fault detection triggers a latch.
6
FB
Feedback input for the QR Flyback controller. Allows direct connection to an optocoupler.
7
CS
Input to the cycle−by−cycle current limit comparator for the QR Flyback section.
8
GND
Ground reference.
9
DRV
This is the drive pin of the circuit. The DRV high−current capability (−0.5 /+0.8 A) makes it suitable to effectively drive high gate charge power MOSFETs.
10
VCC
This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 15 V and turns off
when VCC goes below 9 V (typical values). After start−up, the operating range is 10 V up to 28 V. An OVP
comparator monitors this pin and offers a means to latch the converter in fault conditions.
11
NC or IFF
The external resistor connected to this pin adjusts the frozen peak current during frequency foldback mode
and the power gap between different valley lockouts.
12
NC
13
14
Function
When the voltage on this pin disappears, the controller ensures the X2−capacitors discharge.
Removed for creepage distance.
HV
This pin provides a charging current during start−up and auto−recovery faults but also a means to efficiently
discharge the input X2 capacitors.
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NCP1339
ZCD
+
DEMAG
QR
Logic
QR clock
−
VFB
Vzcd(th)
Clock_25 kHz
VCC charge
X2 Capacitor discharge
BONOK detection
Line monitoring
PSM control
HV
HV(stop)
Blanking Time
Tzcd(blank)
VFB
Fault or PSM
REM
Timeout
DRV
(internal)
Latch
X2
FB
BO_buf
Skip
VCC
QR Clock
Vskip
Clamp
Skip Comparator
HV(stop)
S
VCC Management
and internal Reference
VCC
UVLO
VCC(OVP)
Q
Frequency Clamp
R
Circuit reset
When VCC<VCC(reset)
VDD
DRV
Q
Clock_25 kHz
25−kHz
DRV
Latch
Overcurrent
PWM Reset
Delay
GND
Frozen Curent
Comparator
5V
Latch
S
OPP
VOPP
Vfreeze
Q
Vfault(OVP)
or VIFF/4
Q
Ifault(OTP)
PWM
Reset
Fault
R
/Kfb
PWM
comparator
Rfault(clamp)
Vfault(OTP)
BONOK
Vfault(clamp)
Ip_flag
LEB
tcs(LEB1)
Peak current
Comparator with OPP
Overload Timer
Auto−Restart
Fault Control
Count Down
Count Up
5V
+
Vilim1
Overcurrent
ICS
VOPP
5V
Thermal
Shutdown
Peak current
Comparator W/O OPP
IFF(bias)
CSStop
IFF
FB
LEB
tcs(LEB2)
Counter count
VIFF
Reset
Short Circuit
Comparator
DRV
(internal)
I and J versions only
Figure 3. NCP1339 Functional Block Diagram
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Vilim2
CS
NCP1339
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
High Voltage Startup Circuit Input Voltage
VHV
−0.3 to 500
V
High Voltage Startup Circuit Input Current
IHV
20
mA
Supply Input Voltage
VCC(MAX)
−0.3 to 30
V
Supply Input Current
ICC(MAX)
30
mA
Supply Input Voltage Slew Rate
dVCC/dt
1
V/ms
Fault and IFF Input Voltage
Vi1
−0.3 to (VCC + 1)
V
Fault and IFF Input Current
Ii1
10
mA
REM and X2 Input Voltage
Vi2
−0.3 to 10
V
REM and X2 Input Current
Ii2
10
mA
Zero Current Detection and OPP Input Voltage
VZCD
−0.3 to (VCC + 1)
V
Zero Current Detection and OPP Input Current
IZCD
−2/+5
mA
Current Sense Input Voltage
VCS
−0.3 to 5
V
Current Sense Input Current
ICS
10
mA
Feedback Input Voltage
VFB
−0.3 to 9
V
Feedback Input Current
IFB
10
mA
VDRV
−0.3 to VDRV(high)
V
IDRV(SRC)
IDRV(SNK)
500
800
mA
TJ
−40 to 125
°C
Maxim Junction Temperature
TJ(MAX)
150
°C
Storage Temperature Range
TSTG
–60 to 150
°C
Thermal Resistance, Junction to Ambient 2 Oz Cu Printed Circuit Copper Clad
With a 100 mm2 copper heat spreader area
RθJA
132
°C/W
Driver Maximum Voltage (Note 1)
Driver Maximum Current
Operating Junction Temperature
ESD Capability (All pins except HV) (Note 4)
Human Body Model per JEDEC Standard JESD22−A114F.
Machine Model per JEDEC Standard JESD22−A115C.
Charge Device Model per JEDEC Standard JESD22−C101E.
V
2000
200
500
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum driver voltage is limited by the driver clamp voltage, VDRV(high), when VCC exceeds the driver clamp voltage. Otherwise, the
maximum driver voltage is VCC.
2. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78.
3. Low Conductivity Board. As mounted on 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper trances and heat
spreading area. As specified for a JEDEC51−1 conductivity test PCB. Test conditions were under natural convection of zero air flow.
4. Pin 14 is rated up to 1 kV.
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NCP1339
ELECTRICAL CHARACTERISTICS (VCC = 12 V, VHV = 120 V, VFault = open, VFB = 3 V, VCS = 0 V, VZCD = 0 V, CVCC = 100 nF ,
CDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
VCC(on)
VCC(off)
15.0
9.0
−
1.00
16.0
10.0
−
1.20
Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Operating Hysteresis
Transition from Istart1 to Istart2
Blanking Duration After VCC(off)
Startup Delay
dV/dt = 0.1 V/ms
VCC increasing
VCC decreasing
VCC(on) − VCC(off)
VCC increasing, IHV = 650 mA
VCC(inhibit)
14.0
8.0
5.6
0.55
VCC above VCC(reset)
tUVLO(blank)
2
–
15
ms
Delay from VCC(on) to QR Enable
tdelay(start)
–
–
725
ms
VHVmin
−
30
60
V
Minimum voltage for current source
operation
Current flowing out of Vcc
V
Vcc = 0 V
IC1
−0.8
−0.5
−0.3
mA
Vcc = Vcc(on) – 0.5 V
IC2
−15
−10
−6
mA
VHV = 500 V, Vcc = 15 V, VREM = 0 V
Ileak1
−
−
25.5
mA
HV pin leakage current when PSM is active
VHV = 141 V
Ileak2
−
−
11
mA
HV pin leakage current when PSM is active
VHV = 325 V
Ileak3
−
−
18
mA
VCC(bias)
4.7
5.5
6.3
V
ICC2
ICC3
0.05
0.2
1.0
0.10
0.68
1.6
0.54
1.0
3.0
VCC(OVP)
27
28
29.5
V
tdelay(VCC_OVP)
22.5
30.0
37.5
ms
Current flowing out of Vcc pin
Off−state leakage current
Vcc level during a fault
Supply Current
Before Startup, Fault or Latch
Flyback in Skip
switching at 70 kHz
mA
VCC = VCC(on) – 0.5 V
VFB = 0.35 V
CDRV open
VCC Overvoltage Protection Threshold
VCC Overvoltage Protection Delay
INPUT FILTER DISCHARGE
Vth_X2
1.0
1.5
2.0
V
Hysteresis on the X2 pin
Vth_X2_hyst
−
150
−
mV
X2 input clamp voltage
V_X2_clamp
−
4
−
V
X2_timer
50
−
170
ms
X2 timer disable switch threshold voltage
X2 timer duration
X2 input leakage current
VX2 = 2.5 V
I_X2_leak
−
−
0.3
mA
Maximum discharge switch current
VCC = 10V
I_X2_dis
7
10
14
mA
Remote pin voltage below which PSM is
deactivated
VREM increasing
V_REM_on
1
1.5
2
V
Remote pin voltage above which PSM is
activated
VREM decreasing
V_REM_off
7.2
8
8.8
V
V_REM = 10 V
I_REM_leak
−
20
1000
nA
REM_timer
50
−
170
ms
R_SW_REM
1000
−
3000
W
REMOTE INPUT – POWER SAVINGS MODE
Remote input leakage current
Remote timer duration
Resistance of the Remote Pin Internal
pull−down Switch
BROWN OUT DETECTION
Brown−Out Start Level
HV pin voltage increasing
VBO(start)
90
101
110
V
System Shutdown Threshold
HV pin voltage decreasing
VBO(stop)
84
93
104
V
Brown−out Detection Blanking Time
VHV decreasing, delay from
VBO(stop) to drive disable
tBO(stop)
30
−
100
ms
VDRV from 10 to 90%
tDRV(rise)
–
40
80
ns
GATE DRIVE
Rise Time (10−90%)
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NCP1339
ELECTRICAL CHARACTERISTICS (VCC = 12 V, VHV = 120 V, VFault = open, VFB = 3 V, VCS = 0 V, VZCD = 0 V, CVCC = 100 nF ,
CDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
90 to 10% of VDRV
tDRV(fall)
–
20
–
Unit
GATE DRIVE
Fall Time (90−10%)
Current Capability
Source
Sink
ns
mA
VDRV = 2 V
VDRV = 10 V
IDRV(SRC)
IDRV(SNK)
–
–
500
800
–
–
High State Voltage
VCC = VCC(off) + 0.2 V, RDRV = 10 kW
VCC = 26 V, RDRV = 10 kW
VDRV(high1)
VDRV(high2)
8
10
–
12
–
14
V
Low Stage Voltage
VFault = 4 V
VDRV(low)
–
–
0.25
V
VFB(open)
4.48
4.7
5.0
V
KFB
3.8
4.0
4.2
–
VFB = 0.4 V
RFB
17
20
23
kW
VFB decreasing, VIFF = 0.8 V
VFB decreasing, VIFF = 0.8 V
VFB decreasing, VIFF = 0.8 V
VFB decreasing, VIFF = 0.8 V
VFB decreasing, VIFF = 0.8 V
VFB decreasing, VIFF = 0.8 V
VFB increasing, VIFF = 0.8 V
VFB increasing, VIFF = 0.8 V
VFB increasing, VIFF = 0.8 V
VFB increasing, VIFF = 0.8 V
VFB increasing, VIFF = 0.8 V
VFB increasing, VIFF = 0.8 V
VH2D
VH3D
VH4D
VH5D
VH6D
VHVCOD
VHVCOI
VH6I
VH5I
VH4I
VH3I
VH2I
1.316
1.128
1.034
0.940
0.846
0.760
0.900
1.410
1.504
1.598
1.692
1.880
1.400
1.200
1.100
1.000
0.900
0.800
1.000
1.500
1.600
1.700
1.800
2.000
1.484
1.272
1.166
1.060
0.954
0.830
1.060
1.590
1.696
1.802
1.908
2.120
ton(MAX)
27
32
40
ms
VZCD decreasing
VZCD(th)
35
55
90
mV
FEEDBACK
Feedback Input Open Voltage
VFB to Internal Current
Setpoint Division Ratio
FB Pull Up Resistor
Valley Thresholds
Transition from 1st to 2nd valley
Transition from 2nd to 3rd valley
Transition from 3rd to 4th valley
Transition from 4th to 5th valley
Transition from 5th to 6th valley
Transition from 6th to FF
Transition from FF to 6th valley
Transition from 6th to 5th valley
Transition from 5th to 4th valley
Transition from 4th to 3rd valley
Transition from 3rd to 2nd valley
Transition from 2nd to 1st valley
V
Maximum On Time
DEMAGNETIZATION INPUT
ZCD threshold voltage
ZCD hysteresis
VZCD increasing
VZCD(HYS)
15
35
55
mV
VZCD step from 4.0 V to −0.3 V
tDEM
–
150
250
ns
IQZCD = 5.0 mA
IQZCD = −2.0 mA
VZCD(MAX)
VZCD(MIN)
12.4
−0.9
12.7
−0.7
13
0
(C, D and E versions)
(F, G, H, I and J versions)
tZCD(blank)
2
0.5
3
0.7
4
0.9
ms
Timeout while in soft−start
Timeout after soft−start complete
t(out1)
t(out2)
80
5.1
100
6
120
6.9
ms
VCS increasing
VCS increasing, VOPP = 1 V
VILIM1a
VILIM1b
0.760
0.760
0.800
0.800
0.840
0.840
V
Cycle by Cycle Leading Edge Blanking
Duration
Minimum on time minus tCS(delay1)
tCS(LEB1)
220
275
330
ns
Cycle by Cycle Current Sense Propagation
Delay
VCS dv/dt = 1 V/ms, measured from
VILIM1 to DRV falling edge
tCS(delay1)
–
125
175
ns
VIFF = 0.8 V
Vfreeze
−
200
−
mV
VIFF = 0.8 V (I and J versions)
IFF(bias)
−110
−100
−85
mA
Demagnetization Propagation Delay
Input Voltage Excursion
Upper Clamp
Negative Clamp
Blanking Delay After Turn−Off
Timeout After Last Demagnetization Detection
V
CURRENT SENSE
Current Sense Voltage Threshold (VILIM1)
Internal peak current setpoint freeze
IFF pin current source
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NCP1339
ELECTRICAL CHARACTERISTICS (VCC = 12 V, VHV = 120 V, VFault = open, VFB = 3 V, VCS = 0 V, VZCD = 0 V, CVCC = 100 nF ,
CDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
CURRENT SENSE
Abnormal Overcurrent Fault Threshold
VCS increasing, VFB = 4 V
VILIM2
1.125
1.200
1.275
V
Abnormal Overcurrent Fault Blanking
Duration
Step VCS 0 V to VILIM2 + 0.5 V to
DRV falling edge, dV/dt = 10 V/ms
tCS(LEB2)
90
120
150
ns
Abnormal Overcurrent Fault Propagation
Delay
Step VCS 0 V to VILIM2 + 0.5 V to
DRV falling edge, dV/dt = 10 V/ms
tCS(delay2)
–
125
175
ns
Set point decrease for VOPP = − 250 mV
VCS Increasing, VFB = 4 V
VOPP(MAX)
27
31.25
33
%
VCS dv/dt = 1 V/ms, measured from
VOPP(MAX) to DRV falling edge
tOPP(delay)
–
125
175
ns
tOPP(blank)
100
120
200
ns
VCS = 1.5 V
ICS
−1.5
1.0
−0.5
mA
Frequency of the Jittering CS Pin Source
Current
CS pin being grounded)
Fjit
1.0
1.3
1.6
kHz
Amplitude of the CS Source Current
CS pin being grounded
Ijit
85
100
110
mA
HV Pin Voltage for jittering activation
HV pin voltage rising
(Vin,jit)H
210
250
290
V
HV Pin Voltage below which the jittering
Timer activated
HV pin voltage falling
(Vin,jit)L
185
220
255
V
Blanking Time before Jittering disabling
VHV < 184 V
Tjit(blank)
25
40
55
ms
Soft−Start Period
(Done digitally with 63 steps)
Measured from
1st DRV pulse to VCS = VILIM1
tSSTART
2.8
4.0
5.0
ms
Flyback Overload Fault Timer
VCS = VILIM1
tOVLD
120
160
200
ms
Overvoltage Protection (OVP) Threshold
VFault increasing
VFault(OVP)
2.79
3.00
3.23
V
Delay Before Fault Confirmation
Used for OVP Detection
Used for OTP Detection
VFault increasing
VFault decreasing
tdelay(Fault_OVP)
tdelay(Fault_OTP)
20
20
27.5
27.5
35
35
VFault decreasing
VFault(OTP_in)
0.395
0.40
0.435
IFault(OTP)
45.5
45.5
48.5
–
Overpower Protection Delay
Overpower Signal Blanking Delay
Pull−up Current Source
JITTERING (For E, F, G, I and J versions only)
FAULT PROTECTION
Overtemperature Protection (OTP) Threshold (Note 5)
OTP Pull−up Current Source (Note 5)
ms
V
mA
VFault = VFault(OTP_in) + 0.2 V
TJ = 110 °C
IFault(OTP_110)
42.5
–
VFault = open
VFault(clamp)
1.15
1.7
2.25
V
Fault Input Clamp Series Resistor
RFault(clamp)
1.32
1.55
1.78
kW
Auto−recovery Timer
TA−rec_timer
1.1
2
FClamp
23.5
25
27.5
Fault Input Clamp Voltage
s
STAND−BY MANAGEMENT
Frequency clamp Threshold
kHz
Skip Threshold
VFB decreasing
VSKIP
0.35
0.40
0.45
V
Skip Hysteresis
VFB increasing
VSKIP(HYS)
35
60
85
mV
Thermal Shutdown
(Note 6)
TSHDN
140
150
170
°C
Thermal Shutdown Hysteresis
(Note 6)
TSHDN(HYS)
20
40
60
°C
Thermal Shutdown Delay
(Note 6)
tdelay(TSHDN)
−
30.0
−
ms
THERMAL PROTECTION
5. NTC with R110 = 8.8 kW (TTC03−474).
6. The value is not subjected to production test − verified by design/characterization.
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NCP1339
TYPICAL CHARACTERISTICS
8.90
15.50
15.45
VCC(off) (V)
VCC(on) (V)
8.85
15.40
15.35
8.80
15.30
8.75
15.25
15.20
−40
−20
0
20
40
60
80
100
8.70
−40
120
−20
0
20
40
60
80
120
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 4. VCC(on) vs. Junction Temperature
Figure 5. VCC(off) vs. Junction Temperature
−0.35
1.2
−0.40
1.1
IC1 (mA)
VCC(inhibit) (V)
−0.45
1.0
0.9
0.8
−0.50
−0.55
−0.60
−0.65
0.7
−0.70
0.6
−40
−20
0
20
40
60
80
100
−0.75
−40
120
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. VCC(inhibit) vs. Junction Temperature
Figure 7. IC1 vs. Junction Temperature
120
−6
6.4
−7
6.2
VCC(bias) (V)
IC2 (mA)
−8
−9
−10
6.0
5.8
5.6
−11
5.4
−12
5.2
−13
−40
−20
0
20
40
60
80
100
5.0
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. IC2 vs. Junction Temperature
Figure 9. VCC(bias) vs. Junction Temperature
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9
NCP1339
TYPICAL CHARACTERISTICS
0.50
0.74
0.45
0.72
0.70
Icc2 (mA)
Icc1 (mA)
0.40
0.35
0.30
0.68
0.66
0.64
0.25
0.62
0.20
−40
−20
0
20
40
60
80
100
0.60
−40
120
−20
0
20
40
60
80
120
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. ICC1 vs. Junction Temperature
Figure 11. ICC2 vs. Junction Temperature
1.70
1.65
1.65
1.60
Vth_x2 (V)
Icc3 (mA)
1.63
1.61
1.59
1.55
1.50
1.45
1.40
1.57
1.35
1.55
−40
−20
0
20
40
60
80
100
1.30
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. ICC3 vs. Junction Temperature
Figure 13. Vth_x2 vs. Junction Temperature
12.5
119
12.0
115
I_X2_dis (mA)
X2_timer (ms)
117
113
111
11.5
11.0
10.5
109
10.0
107
105
−40
−20
0
20
40
60
80
100
9.5
−40 −20
120
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. X2_timer vs. Junction Temperature
Figure 15. TLEB vs. Junction Temperature
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10
120
NCP1339
2.0
8.5
1.9
8.4
1.8
8.3
1.7
8.2
V_REM_off (V)
V_REM_on (V)
TYPICAL CHARACTERISTICS
1.6
1.5
1.4
1.3
8.1
8.0
7.9
7.8
1.2
7.7
1.1
7.6
7.5
−40
1.0
−40
−20
0
20
40
60
80
100
120
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. V_REM_on vs. Junction
Temperature
Figure 17. V_REM_off vs. Junction
Temperature
120
130
109
107
120
Vbo(start) (V)
REM_timer (ms)
125
115
110
105
103
101
99
105
97
100
−40
−20
0
20
40
60
80
100
95
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. REM_timer vs. Junction
Temperature
Figure 19. VBO(start) vs. Junction Temperature
96
83
95
tbo(stop) (ms)
Vbo(stop) (V)
78
94
93
92
73
68
63
91
58
90
−40
−20
0
20
40
60
80
100
53
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 20. VBO(stop) vs. Junction Temperature
Figure 21. tBO(stop) vs. Junction Temperature
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11
NCP1339
80
40
75
35
tdrv(fall) (ns)
tdrv(rise) (ns)
TYPICAL CHARACTERISTICS
70
65
30
25
20
60
55
−40
−20
0
20
40
60
80
100
15
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. tDRV(rise) vs. Junction Temperature
Figure 23. tDRV(fall) vs. Junction Temperature
21.0
4.06
20.6
4.04
20.4
Rfb (kW)
Kfb
20.8
4.05
4.03
4.02
20.2
20.0
19.8
19.6
4.01
19.4
4.00
3.99
−40
−20
0
20
40
60
80
100
19.2
19.0
−40
120
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 24. KFB vs. Junction Temperature
Figure 25. RFB vs. Junction Temperature
34.0
60
33.5
59
33.0
120
58
Vzcd(th) (mV)
ton(max) (ms)
−20
32.5
32.0
31.5
57
56
55
31.0
54
30.5
30.0
−40
−20
0
20
40
60
80
100
53
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 26. ton(MAX) vs. Junction Temperature
Figure 27. VZCD(th) vs. Junction Temperature
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12
NCP1339
2.80
102
2.75
101
100
2.70
t(out1) (ms)
tzcd(blank) (ms)
TYPICAL CHARACTERISTICS
2.65
2.60
98
97
2.55
96
2.50
−40
−20
0
20
40
60
80
100
95
−40
120
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 28. tZCD(blank) vs. Junction Temperature
Figure 29. t(out1) vs. Junction Temperature
6.5
120
0.810
6.4
0.808
6.3
Vilim1a (V)
t(out2) (ms)
99
6.2
0.806
0.804
6.1
0.802
6.0
5.9
−40
−20
0
20
40
60
80
100
0.800
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 30. t(out2) vs. Junction Temperature
Figure 31. Vilim1a vs. Junction Temperature
64
290
62
tcs(delay1) (ns)
tcs(leb1) (ns)
280
275
270
60
58
56
54
265
52
260
−40
−20
0
20
40
60
80
100
50
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 32. tCS(LEB1) vs. Junction Temperature
Figure 33. tCS(delay1) vs. Junction Temperature
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13
NCP1339
TYPICAL CHARACTERISTICS
1.230
119
117
Vilim2 (V)
tcs(leb2) (ns)
1.225
1.220
115
113
111
109
1.215
107
1.210
−40 −20
0
20
40
60
80
100
105
−40
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 34. Vilim2 vs. Junction Temperature
Figure 35. tCS(LEB2) vs. Junction Temperature
198
47
46
197
45
Vfreeze (mV)
tcs(delay2) (ns)
−20
44
43
42
196
195
194
193
41
40
−40
−20
0
20
40
60
80
100
192
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 36. tCS(delay2) vs. Junction Temperature
Figure 37. Vfreeze vs. Junction Temperature
32.0
2.7
31.5
2.6
Vopp(max) (%)
t(Autorec) (s)
31.0
2.5
2.4
2.3
30.5
30.0
29.5
29.0
2.2
2.1
−40
28.5
−20
0
20
40
60
80
100
28.0
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 38. TA−rec_timer vs. Junction
Temperature
Figure 39. VOPP(MAX) vs. Junction Temperature
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14
NCP1339
TYPICAL CHARACTERISTICS
3.30
169
3.25
Vfault(ovp) (V)
t(ovld) (ms)
167
165
163
161
3.15
3.10
3.05
159
157
−40
3.20
−20
0
20
40
60
80
100
3.00
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 40. tOVLD vs. Junction Temperature
Figure 41. Vfault(OVP) vs. Junction Temperature
0.420
46.0
45.5
Ifault(OTP) (mA)
Vfault(otp_in) (V)
0.415
0.410
45.0
44.5
0.405
44.0
0.400
−40
−20
0
20
40
60
80
100
43.5
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 42. VFault(OTP_in) vs. Junction
Temperature
Figure 43. IFault(OTP) vs. Junction Temperature
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15
NCP1339
DETAILED OPERATING DESCRIPTION
Introduction
The NCP1339 implements a standard quasi−resonant
current−mode architecture. This component represents the
ideal candidate where low part−count and cost effectiveness
are the key parameters, particularly in low−cost ac−dc
adapters, open−frame power supplies etc. The NCP1339
brings all the necessary components normally needed in
modern power supply designs, bringing several
enhancements such as non−dissipative OPP, brown−out
protection or sophisticated frequency reduction
management for an optimized efficiency over the power
range. Accounting for the new needs of extremely low
standby power requirements, the part includes an automatic
X2−capacitor discharge circuitry which can save the
power−consuming resistors otherwise needed across the
front−end filtering capacitors. The controller is also able to
enter Power Savings Mode (PSM) that is, a deep sleep mode
via its dedicated remote (“REM”) pin.
• High−Voltage start−up: low standby power results
cannot be obtained with the classical resistive start−up
network. In this part, a high−voltage current−source
provides the necessary current at start−up and turns off
afterwards.
• Internal Brown−Out protection: the bulk voltage is
internally sensed via the high−voltage pin monitoring
(pin 14). When Vpin14 is too low, the part stops pulsing.
No re−start attempt is made until Vpin14 recovers its
normal range. At that moment, the brown−out
comparator sends a general reset to the controller
(de−latch occurs) and authorizes to re−start.
• X2−capacitors discharge capability: per IEC−950
standard, the time constant of the front−end filter
capacitors and their associated discharge resistors must
be less than 1 s. This is to avoid electrical stress when
users unplug the converter and inadvertently touch the
power cord terminals. The circuitry for discharging the
X2 capacitors can save the need for discharge resistors,
helping to further save power.
• PSM control: a dedicated pin allows the IC to enter a
deep sleep mode when the REM input pin is brought
above a certain level. This option offers an efficient
means to operate the adapter in a power savings mode
and draw the least input power from the mains in this
mode. When the REM is actively pulled down via a
dedicated optocoupler, the adapter immediately
re−starts. The component that controls PSM is then
active in normal operation (active−ON) and OFF in
PSM (wasting no energy).
• Quasi−resonant, current−mode operation: QR operation
is an efficient mode where the MOSFET turns on when
its drain−source is at the minimum (valley). However,
at light load, the switching frequency tends to get high.
The NCP1339 valley lock−out and frequency foldback
•
•
•
•
•
•
•
technique eliminate this drawback so that the efficiency
remains at the highest over the power range.
Valley Lockout: a continuous flow of pulses is not
compatible with no−load/light−load standby power
requirements. To excel in this domain, the controller
observes the feedback pin voltage (FB) and when it
reaches a level of 1.4 V, the circuit enters a valley
lockout mode where the circuit skips a valley. If FB
further decreases, more valleys are skipped until 6th
valley is reached.
Frequency Fold−back: if FB continues declining and
reaches 0.8 V, the current setpoint is frozen to Vfreeze
and the circuit regulates by modulating the switching
frequency until it reaches 25 kHz (For C, D, E, F, G and
H versions). For I and J versions, the current setpoint is
frozen to (VIFF/4) when FB falling and reaches the IFF
voltage (VIFF) set on the IFF pin.
Skip cycle: to avoid acoustic noise, the circuit prevents
the switching frequency from decaying below 25 kHz.
Instead, the circuit contains the power delivery by
entering skip cycle mode when the system would
otherwise need to further lower the switching frequency
below 25 kHz.
Internal OPP (Over Power Protection): by routing a
portion of the negative voltage present during the
on−time on the auxiliary winding to the OPP pin
(pin 3), the user has a simple and non−dissipative
means to alter the maximum current setpoint as the bulk
voltage increases. If the pin is grounded, no OPP
compensation occurs.
Internal soft−start: a 4−ms soft−start precludes the main
power switch from being stressed upon start−up. It is
activated whenever a startup sequence occurs including
autorecovery hiccup.
Fault input: the NCP1339 includes a dedicated fault
input (pin 5). It can be used to sense an overvoltage
condition and latch off the controller by pulling up the
pin above the upper fault threshold, VFault(OVP),
typically 3.0 V. The controller is also disabled if the
Fault pin voltage, VFault, is pulled below the lower fault
threshold, VFault(OTP_in), typically 0.4 V. The lower
threshold is normally used for detecting an
overtemperature fault (by the means of an NTC).
Short−circuit/Overload protection: short−circuit and
especially overload protections are difficult to
implement when a strong leakage inductance between
auxiliary and power windings affects the transformer
(the aux winding level does not properly collapse in
presence of an output short). Here, every time the
internal 0.8−V maximum peak current limit is activated
(or less when OPP is used), an error flag is asserted and
a 160−ms timer begins counting. When the timer has
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16
NCP1339
•
HV Current Source Pin
elapsed, the fault is validated. An internal timer keeps
the pulses off for 2 s typically which, associated to the
160−ms pulsing re−try period, ensures a duty−cycle in
fault mode of 10%, independent from the line level. As
soon as the fault disappears, the SMPS resumes
operation. Please note that some versions (C, G, H and
J) offer an auto−recovery mode as we just described,
versions D, E, F and I do not and latch off in case of a
short circuit.
EMI jittering (Disabled for C and D versions): in
high−line conditions, a low−frequency triangular
current is sourced by the CS pin. The resistor placed
between the CS pin and the current sense resistor
adjusts the jittering amount that is applied to the power
supply. This helps spreading out energy in conducted
noise analysis. Jittering is disabled in frequency
foldback mode and in low line conditions.
D1
The NCP1339 HV circuitry provides three features:
• Start−up current source to charge the VCC capacitor at
start−up.
• Brown−out protection: when the HV pin voltage is
below 93 V for the 50−ms blanking time, the NCP1339
stops operating and recovers when the HV pin voltage
exceeds 101 V (typical values)
• X2 capacitor discharge: when circuit X2 pin detects
that the power supply is no more powered, the start−up
current source turns on to discharge the X2 capacitors.
Because of this last feature, it is firmly recommended to wire
it according to Figure 44 sketch. The HV pin is not
connected to the bulk voltage but directly to the line terminals
through diodes (D1 and D2 of Figure 44). It is further
recommended to implement one or two 2.2−kW resistors to
reduce the noise that can be picked−up by the HV pin.
R2
2.2k
D2
R1
2.2k
1
14
2
13
3
12
4
11
5
10
6
9
7
8
Vcc
D3
C1
Vbulk
N
EMI
Filter
L1
Figure 44. Two Diodes Route the Full−wave Rectified Mains to the HV Pin
Start−up Sequence:
stress if the VCC pin happens to be accidentally grounded.
When VCC exceeds VCC(inhibit), a 10−mA current (IC2) is
provided that charges the VCC capacitor.
The VCC charging time is then the total of the two
following durations:
• Charge from 0 V to VCC(inhibit):
The start−up time of a power supply largely depends on
the time necessary to charge the VCC capacitor to the
controller VCC start−up threshold (VCC(on) which is 15 V
typically). The NCP1339 high−voltage current−source
provides the necessary current for a prompt start−up and
turns off afterwards. The delivered current (IC1) is reduced
to less than 500 mA when the VCC voltage is below
VCC(inhibit) (1 V typically). This feature reduces the die
t start1 +
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17
V CC(inhibit)C Vcc
IC1
(eq. 1)
NCP1339
• Charge from VCC(inhibit) to VCC(on):
t start2 +
ǒVCC(on) * VCC(inhibit)ǓCVcc
IC2
(eq. 2)
Assuming a 100−mF VCC capacitor is selected and replacing
IC1, IC2, VCC(inhibit) and VCC(on) by their typical values, it
comes:
t start1 +
1 V 100 mF
+ 200 ms
500 mA
t start2 +
(15 * 1) 100 mF
+ 140 ms
10 mA
(eq. 3)
t start + t start1 ) t start2 + 340 ms
VCC(on)
VCC(inhibit)
tstart2
tstart1
Figure 45. Vcc at Start−up is made of Two Segments given the
Short−circuit Protection Implemented on the HV Source
If the VCC capacitor is first dimensioned to supply the
controller for the traditional 5 to 50 ms until the auxiliary
winding takes over, no−load standby requirements usually
cause it to be larger. The HV start−up current source is then
a key feature since it allows keeping short start−up times
with large VCC capacitors (the total start−up sequence
duration is often required to be less than 1 s).
standby power, the external network adds a consumption
burden and deteriorates the standby power performance of
the power supply. Owing to its proprietary high−voltage
technology, ON Semiconductor now offers onboard line
sensing without using an external sensing network. The
brown−out thresholds are fixed (101 V line rising, 93 V
falling, typically). Respectively correponding to about 72 V
rms and 66 V rms, these levels are designed to fit most of
standard ac−dc converter applications. The simplified
internal schematic appears in Figure 46 while typical
operating waveforms are drawn in Figure 47.
Brown−out Circuitry
For the vast majority of controllers, input line sensing is
performed via a resistive network monitoring the bulk
voltage or the incoming ac signal. When in the quest of low
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18
NCP1339
D1
R1
2.2k
R2
2.2k
D2
HV
Rbo_H
BO_OK
Rbo_L
GND
Vbulk
N
EMI
Filter
L1
Figure 46. Simplified View of the Brown−out Circuitry
Please note that the HV start−up current is not reduced for
the time when VCC is below VCC(inhibit) (as it happens when
the power supply is first plugged in) not to delay the power
supply recovery.
If a brown−out event occurs during the Vcc capacitor
charge phase, the start−up phase is interrupted but the Vcc
pin is not grounded to make a fresh restart. The start−up
resumes as soon as the line recovers (terminating the
brown−out situation).
When the HV pin voltage drops below the VBO(stop)
threshold (93 V typically) for more than the 50−ms blanking
time (TBO(stop)), the brown−out protection trips: the
controller stops generating DRV pulses and maintains Vcc to
the 5.5−V VCC(bias) level. This state is maintained by the
high−voltage current−source until the input voltage happens
to exceed the brown−out upper threshold (VBO(start) that is
101 V typically). At that moment, the controller briefly
grounds the Vcc capacitor to make a fresh start−up sequence
with soft−start.
Figure 47. Internal Circuit Implements a 50−ms Timeout to Accommodate with Full−wave Rectification
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19
NCP1339
X2 Discharge Circuitry
The NCP1339 X2 discharge circuitry in Figure 48 uses a
dedicated pin (X2) together with an external charge
pump−based sensing network to detect the presence or the
absence of the mains. Owing to this simple external source,
the X2 circuitry is independent from the rest of the controller
that can be fully disabled in the off mode. A 100−ms timeout
D1
block makes sure the X2 discharge switch is only activated
upon a real mains loss (when the user unplugs the converter)
and not when a parasitic ac line dropout occurs. The internal
Vcc discharge switch is activated once the X2 timer elapses.
At that moment, the HV startup current source is enabled
and pumps out the energy stored by the X2 capacitors.
R2
2.2k
R1
2.2k
D2
HV
R5
C1
HV
Startup
Vcc
D3
X2
D4
C2
X2 Capacitor
Discharge Circuitry
C3
R6
GND
Vbulk
N
EMI
Filter
L1
Figure 48. Simplified Block Diagram of X2 Capacitor Discharge Circuitry
An over temperature protection block monitors the
junction temperature during the discharge process and
avoids thermal runaway, in particular during open/short pins
safety tests. Please note that the X2 discharge capability is
also active during off−mode but also before the controller
actually starts to pulse (e.g. if the user unplugs the converter
during the start−up sequence).
introduce a time constant that prevents the converter from
entering the off mode immediately, in case spurious noise
would appear on the opto LED bias current. When the
voltage across C2 eventually reaches 8 V, the controller
enters the off mode. In the absence of pulses, the auxiliary
no longer maintains Vcc that slowly vanishes to 0. At this
moment, the X2 monitoring circuit is the only living block
and the IC power consumption is reduced to an extremely
low level. The voltage on the REM pin starts to fall. When
it reaches the re−start level (1.5 V), the controller resumes
operation and initiates a fresh start−up sequence. If no
secondary−side signal appears to bias the optocoupler LED,
a new self−relaxing cycle takes place when the REM pin
voltage reaches 8 V. If a secondary−side signal biases
optocoupler before the REM pin voltage has reached 8 V, the
power supply operates normally.
Power Savings Mode
The NCP1339 features a dedicated input (remote pin) that
allows the user to activate an ultra−low consumption mode.
Figure 49 describes the internal arrangement of the remote
circuitry. In normal operation, the optocoupler is biased
from the secondary side and pulls the remote pin to ground.
When the secondary−side circuitry decides to release the
optocoupler, the remote pin level starts to grow. It is lifted
up by R1 connected to the auxiliary Vcc. C3 , R1 and R2
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20
NCP1339
D1
Vcc
REM to Vcc
management
C1
D2
V_REM_off
C3
R1
REM
C2
R2
GND
Figure 49. Simplified Block Diagram of the Remote Control Input
Neglecting the resistor voltage drop, the OVP threshold is
then:
In summary, the REM pin works as follows:
• When pulled below a certain level (V_REM_on, 1.5 V
typical), the power supply operates normally. As
capacitors are connected to this pin, it is important to
discharge them properly during the start−up sequence.
A 100−ms timer performs this function by pulling the
pin to ground. It is operating in any re−start conditions
(brown−out recovery, short−circuit, latch reset and so
on) except in the self−relaxing PSM mode ( during
which the voltage on the pin swings up and down.
• When brought above a certain level (V_REM_off, 8 V
typical), the power supply stops working. In the
absence of an external bias, the remote pin starts to
drop at a pace imposed by the various time constants
around it. During this mode, despite the absence of Vcc,
the X2 discharge circuitry remains active and monitors
the ac input line.
V AUX(OVP) + V Z ) V Fault(OVP),
(eq. 4)
where VZ is the Zener diode voltage.
The controller can also be latched off if the Fault pin
voltage, VFault, is pulled below the lower fault threshold,
VFault(OTP_in), typically 0.4 V. This capability is normally
used for detecting an overtemperature fault by means of an
NTC thermistor. A pull up current source IFault(OTP),
(typically 45.5 mA) generates a voltage drop across the
thermistor. The resistance of the NTC thermistor decreases
at higher temperatures resulting in a lower voltage across the
thermistor. The controller detects a fault once the thermistor
voltage drops below VFault(OTP_in).
The circuit detects an overtemperature situation when:
R NTC @ I Fault(OTP) + V Fault(OTP).
(eq. 5)
Hence, the OTP protection trips when
Fault Input
The NCP1339 includes a dedicated fault input accessible
via the Fault pin. Figure 50 shows the architecture of the
Fault input. The controller can be latched by pulling up the
pin above the upper fault threshold, VFault(OVP), typically
3.0 V. An active clamp prevents the Fault pin voltage from
reaching the VFault(OVP) if the pin is open. To reach the upper
threshold, the external pull−up current has to be higher than
the pull−down capability of the clamp (set by RFault(clamp) at
VFault(clamp)), i.e., approximately 1 mA.
This function is typically used to detect a VCC or auxiliary
winding overvoltage by means of a Zener diode generally in
series with a small resistor (see Figure 50).
R NTC +
V Fault(OTP)
I Fault(OTP)
(eq. 6)
that is 8.8 kohms typically.
The controller bias current is reduced during power up by
disabling most of the circuit blocks including IFault(OTP).
This current source is enabled once VCC reaches VCC(on). A
bypass capacitor is usually connected between the Fault and
GND pins. It will take some time for VFault to reach its steady
state value once IFault(OTP) is enabled. Therefore, the lower
fault comparator (i.e. overtemperature detection) is ignored
during soft−start.
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21
NCP1339
Vaux
5V
S
Latch
Vfault(OVP)
Ifault(OTP)
Q
Q
Fault
R
NTC
Rfault(clamp)
Vfault(OTP)
Vfault(clamp)
BONOK
Figure 50. Fault Detection Schematic
Timeout
As a matter of fact, the controller operates normally while
the Fault pin voltage is maintained within the upper and
lower fault thresholds. Upper and lower fault detector have
blanking delays to prevent noise from triggering them. Both
blanking timers (tdelay(Fault_OVP) and tdelay(Fault_OTP)) are
typically 27.5 ms.
When the part is latched−off, the drive is immediately
turned off. Also, VCC drops and stabilize to the 5.5−V
VCC(bias) level. The power supply needs to be un−plugged to
reset the part as a result of a BONOK (BO fault condition)
and/or the X2 circuitry activation.
PSM mode cannot be triggered in latched−off mode.
The ZCD block actually detects falling edges of the
auxiliary winding voltage applied to the ZCD pin. At
start−up or other transient phases, the ZCD comparator may
be unable to detect such an event. Also, in the case of
extremely damped oscillations, the system may not succeed
in detecting all the valleys required by VLO operation (see
next section). In this condition, the NCP1339 ensures
continued operation by incorporating a maximum timeout
period that resets when a demagnetization phase is detected.
The timeout signal substitutes ZCD signal for the valley
counter. Figure 51 shows the timeout period generator
circuit schematic. The steady state timeout period, t(out2), is
set at 6 ms.
During startup, the output voltage is still low leading to
long demagnetization phases difficult to detect since the
auxiliary winding voltage is small as well. In this condition,
the 6−ms steady−state timeout is generally shorter than the
inductor demagnetization period and if used to restart a
switching cycle, it can cause continuous current mode
(CCM) operation for few cycles until the voltage on the ZCD
pin is high enough for proper valleys detection. A longer
timeout period, t(out1), (typically 100 ms) is therefore set
during soft−start to prevent CCM operation.
In VLO operation, the timeout periods of time are counted
instead of valleys when the drain−source voltage
oscillations are too damped to be detected. For instance, if
the circuit must turn on at the fifth valley and if the ZCD
ringing only enables to detect:
• Valleys 1 to 4: the circuit generates a DRV pulse 6 ms
(steady−state timeout delay) after valley 4 detection.
• Valleys 1 to 3: the timeout delay must run twice so that
the circuit generates a DRV pulse 12 ms after valley 3
detection.
Zero Current Detection
The NCP1339 integrates a quasi−resonant (QR) flyback
controller. The power switch turn−off of a QR converter is
determined by the peak current set by the feedback loop. The
switch turn−on is determined by the transformer
demagnetization. The demagnetization is detected by
monitoring the transformer auxiliary winding voltage.
Turning on the power switch once the transformer is
demagnetized or reset reduces switching losses. Once the
transformer is demagnetized, the drain voltage starts ringing
at a frequency determined by the transformer magnetizing
inductance and the drain lump capacitance eventually
settling at the input voltage. A QR controller takes
advantage of the drain voltage ringing and turns on the
power switch at the drain voltage minimum or “valley” to
reduce switching losses and electromagnetic interference
(EMI).
As sketched by Figure 51, a valley is detected once the
ZCD pin voltage falls below the QR flyback
demagnetization threshold, VZCD(th), typically 55 mV. The
controller will switch once the valley is detected or
increment the valley counter depending on FB voltage.
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22
NCP1339
ZCD
Rzcd
+
−
Czcd
QR
Logic
Vzcd(th)
Blanking Time
Tzcd(blank)
Timeout
DRV
(internal)
Figure 51. Valley Lockout Detection Circuitry Internal Schematic
Valley Lockout (VLO) and Frequency Foldback (FF)
extends QR operation over a wider output power range
while maintaining good efficiency and limiting the
maximum operating frequency.
The operating valley (1st, 2nd, 3rd, 4th, 5th or 6th) is
determined by the FB voltage. As VFB decreases or
increases, the valley comparators toggle one after another to
select the proper valley. The decimal counter increases each
time a valley is detected. The activation of an “n” valley
comparator blanks the “n−1” or “n+1” valley comparator
output depending if VFB decreases or increases,
respectively. Figure 52 shows a typical frequency
characteristic obtainable at low line in a 60−W application.
The operating frequency of a traditional QR flyback
controller is inversely proportional to the system load. In
other words, a load reduction increases the operating
frequency. A maximum frequency clamp can be useful to
limit the operating frequency range. However such an
approach causes instabilities since when this clamp is active,
the controller tends to jump (or hesitate) between two
valleys generating audible noise.
Instead, the NCP1339 incorporates a patent pending
valley lockout circuitry to eliminate valley jumping. Once a
valley is selected, the controller stays locked in this valley
until the output power changes significantly. This technique
1x10
(Hz) Fsw
8x10
6x10
6th 5th 4th
5
2x10
2nd
1st
VCO
4 mode
4
6th
4x10
3rd
5th
4th
3rd
2nd
1st
4
4
0
VCO
mode
0
20
Pout (W)
40
60
Figure 52. Valley Lockout Frequency vs Output Power Relationship
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23
NCP1339
When an “n” valley is asserted by the valley selection
circuitry, the controller is locked in this valley until the FB
voltage decreases to the lower threshold (“n+1” valley
activates) or increases to the “n valley threshold” + 600 mV
(“n−1” valley activates). The regulation loop adjusts the
peak current to deliver the necessary output power. Each
valley selection comparator features a 600−mV hysteresis
that helps stabilize operation despite the FB voltage swing
produced by regulation loop.
Valley FB Thresholds (typical values):
FB Falling
FB Rising
1st to 2nd valley
1.4 V
FF mode to 6th valley
1.0 V
2nd to 3rd valley
1.2 V
6th to 5th valley
1.5 V
3rd to 4th valley
1.1 V
5th to 4th valley
1.6 V
1.0 V
4th
0.9 V
3rd
0.8 V
2nd
4th
5th
6th
to
5th
to
6th
valley
valley
valley to FF mode
Frequency Foldback
to
3rd
valley
1.7 V
to
2nd
valley
1.8 V
to
1st
valley
2.0 V
The dead−time is dimensioned to generate a 2−ms
dead−time when VFB = 0.8 V and could linearly go to
virtually infinity as VFB falls down to 0.4 V if the switching
was not forced to keep above 25−kHz to eliminate risk of
audible noise.
Figure 53 summarizes the operation mode with respect to
the FB voltage for versions without IFF pin (fixed internally
to 0.8 V).
As the output load decreases (FB voltage decreases), the
valleys are incremented from 1 to 6. For versions without
IFF pin, if when the sixth valley is reached, the FB voltage
further decreases below 0.8 V, the controller enters the
frequency foldback mode (FF). The current setpoint being
internally forced to remain above 0.2 V (setpoint
corresponding to VFB = 0.8 V), the controller regulates the
power delivery by modulating the switching frequency.
When a load increase causes FB to exceed the 1−V FF upper
threshold (200−mV hysteresis), the circuit recovers VLO
operation.
For versions with the IFF pin available, both frequency
foldback threshold and frozen peak current are adjustable.
Thanks to an external pull down resistor combined with the
internal pull up current source (IFF(bias)), the voltage develops
across this resistor will determine when the controller enters
in FF mode. In FF operation, the peak current is frozen to
(VIFF /4). When as a result of a load increase, FB exceeds
back the (VIFF + 200 mV) level (200 mV hysteresis), the
circuit recovers VLO operation.
In frequency foldback mode, the system reduces the
switching frequency by adding some dead−time after the 6th
valley is detected. This dead−time increases when the FB
voltage decays. There is no discontinuity when the system
transitions from VLO to FF and the frequency smoothly
reduces as FB goes below 0.8 V (or VIFF).
25−kHz Frequency Clamp and Skip Mode
As aforementioned, the circuit prevents the switching
frequency from dropping below 25 kHz. When the
switching cycle is longer than 40 ms, the circuit forces a new
switching cycle. However, the 25−kHz frequency clamp
cannot generate a DRV pulse until the demagnetization is
completed. In other words, it cannot cause operation in
continuous conduction mode.
Since the NCP1339 forces a minimum peak current (as
aforementioned, the circuit prevents the peak current from
dropping below (0.2 V / RSENSE or (VIFF/4) / RSENSE)
where RSENSE is the current sense resistor) and a minimum
frequency (25 kHz typically), the power delivery cannot be
continuously controlled down to zero. Instead, the circuit
stops pulsing when the FB voltage drops below 400 mV and
recovers operation when VFB exceeds 450 mV (50−mV
hysteresis). This skip−mode method provides an efficient
power control in light load.
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24
NCP1339
Operating Mode
VFB decreases
FF
VFB increases
Valley 6
Valley 5
Valley 4
Fault !
Valley 3
Valley 2
Valley 1
0.8 0.9 1.0 1.1 1.2 1.4 1.5 1.6 1.7 1.8 2.0
3.2
VFB (V)
Figure 53. Valley Lockout Thresholds Without IFF Pin
Operating Mode
1.4V − VIFF
6
B = VIFF 600 mV
A=
200 mV
FF
Valley 6
Valley 5
Valley 4
Valley 3
Valley 2
Valley 1
VIFF
VIFF+3A
VIFF+A
VIFF+2A
VIFF+4A
VIFF+6A
(1.4 V)
B+A B+2A
B+3A B+4A B+6A
(2.0 V)
Figure 54. Valley Lockout Thresholds With IFF Pin
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25
FB (V)
NCP1339
Over Power Compensation (OPP)
Instead, the auxiliary winding voltage (VAUX) is used.
During power−switch on−time, VAUX provides a negative
voltage that is a Vbulk portion (input voltage scaled down by
the primary to auxiliary winding turns ratio) as shown in
Figure 55. The negative voltage applied to the pin is referred
as VOPP. The maximum internal current setpoint (VCS(OPP))
is the sum of VOPP and peak current sense threshold, VILIM1.
The current setpoint is calculated using Equation 7.
The power delivered by a QR flyback stage is an
increasing function of the bulk voltage, Vbulk. It is however
desirable to clamp the power delivery to limit the stress on
the power components that can otherwise be excessive
during transient or fault conditions.
An integrated overpower circuit provides a relatively
constant output power across bulk voltage, Vbulk.
Practically, the maximum peak current is made a decreasing
function of the bulk voltage. The direct measure of the Vbulk
high−voltage rail would cause losses in the sensing network
and hence alter the standby efficiency.
V CS(OPP) + V ILIM1 ) V OPP
That is that:
ǒ
Ǔ
N AUX
@ V BULK
NP
(eq. 8)
VAUX (V)
V CS(OPP) + V ILIM1 *
(eq. 7)
⎛
⎢
⎝
⎛N
− ⎢ AUX VBULK
⎝ NP
Figure 55. Auxiliary Winding Voltage Waveform
For example, (VOPP = −0.25 V) results in a current
setpoint of 0.55 V. In general, VOPP is selected in the range
of −200 mV at the highest line level. Refer to application
notes for more details.
even if the OPP pin is adversely biased above 0 V, the current
setpoint remains clamped to 0.8 V typically.
For optimum performance over temperature, we
recommend keeping the low−side OPP resistor below 3 kW.
ǒVCS(OPP) + 0.8−0.25 + 0.55 + 68.75% @ 0.8 + 68.75% @ VILIM1Ǔ
Current Setpoint
As explained in this operating description, the current
setpoint is affected by several functions. Figure 56
summarizes these interactions. As shown by this figure, the
current setpoint is FB/4. However, this value is limited by
the following functions:
• This level is clamped during the soft−start phase. The
setpoint is actually limited by a clamp level ramping
from 0 to 0.8 V within 4 ms.
• It is also limited by the OPP function: during the
on−time, a negative voltage is applied to the OPP pin.
This voltage is summed with a 0.8−V voltage reference
to form the actual maximum setpoint (see OPP section).
The OPP pin is not designed to operate below –250 mV
which corresponds to a 31.25% decrease of the maximum
current limit. If a lower voltage happens to be applied, the
internal ESD diode that clamps OPP pin negative voltages
may turn on and lead to carriers injection within the die. To
avoid possible resulting disturbance, care must be taken to
limit the current sourced by the diode below 2 mA. If the
circuitry of Figure 56 is used, a conservative condition is:
V AUX,max
R OPP1
w −2 mA å R OPP1 w *
V AUX,max
2m
(eq. 9)
Finally, please note that another comparator internally
fixes the maximum peak current set point to VILIM1. Hence,
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26
NCP1339
•
Ropp1
prevents the over−current limit from being increased
due to the OPP function if a positive voltage is
accidentally applied during the on−time. Hence, even in
this faulty condition, the MOSFET current setpoint
remains limited to VILIM1 (0.8 V typically).
OPP
0.2 V (Without IFF pin)
VIFF/4 (With IFF pin)
FB
Rfb
+
Vdd
0.8V
Frozen
current
−
•
It must be noted that the OPP pin voltage is high during
the off−time. The summer is designed to face this
situation without degradation of the circuitry.
A minimum setpoint is forced that equals to Vfreeze
(0.2 V, typically).
In addition, a second OCP comparator ensures that in
any case the current setpoint is limited to 0.8 V. This
PWM latch
RESET
+
Soft
Start
Ramp
3R
−
R
+
OPP COMP
−
+
PWM COMP
275−ns
LEB
+
CS
−
Rcs
Rs
DRV
OCP COMP
+
Overload detection block
−
0.8 V
Short Circuit COMP
120−ns
LEB
DRV
+
Abnormal Over−current fault (CSStop)
−
1.2 V
Figure 56. Current Setpoint
Current Sense and Associated Protections
The Maximum Peak Current Comparator compares the
current sense signal to a reference voltage to limit the
maximum peak current of the system. The maximum peak
current reference voltage, VILIM1, is typically 0.8 V. The
maximum peak current setpoint is reduced by the overpower
compensation (OPP) circuitry. In case, a wrong OPP signal
is applied to the circuit, a second comparator to VILIM1 is
placed to get sure that the current setpoint is at least limited
to VILIM1. An overload condition causes the output of one of
the Maximum Peak Current Comparators to transition high
and enable the overload timer. Figure 57 shows the
implementation of the current sensing circuitry.
The feedback voltage (VFB) is internally divided by KFB
(KFB=4, typically) to form the current setpoint. The power
switch on time is modulated by comparing a ramp
proportional to the switch current to VFB/KFB using the
PWM Comparator. The switch current is sensed across a
current sense resistor, RSENSE and the resulting voltage is
applied to the CS pin. The current sense signal is blanked by
a leading edge blanking (LEB) circuit. The blanking period
eliminates the leading edge spike and high frequency noise
during the switch turn−on event. The LEB period, tCS(LEB1),
is typically 275 ns. The drive pulse terminates once the
current sense signal exceeds VFB/KFB.
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27
NCP1339
FB
/Kfb
PWM
comparator
LEB
tcs(LEB1)
5V
Peak current
Comparator with OPP
Overload Timer
ICS
CS
Count Down
Count Up
+
Disable DRV
VOPP
Vilim1
Peak current
Comparator W/O OPP
LEB
CSStop
Counter count
tcs(LEB2)
Reset
OPP
Short Circuit
Comparator
Vilim2
VOPP
DRV
Figure 57. Overload Circuitry
Overload Protection
time, the PWM Comparator takes precedence and the
overload timer counts down. When the overloard timer
elapses, the circuit detects an overload condition and
♦ The controller latches off (versions D, E, F and I) or
♦ Enters a safe low duty−ratio operation named
auto−recovery mode (versions C, G, H and J).
The overload timer integrates the duration of the overload
fault. That is, the timer count increases while the fault is
present and reduces its count once it is removed. The timer
counts up or down in 10 ms increments. The overload timer
duration, tOVLD, is typically 160 ms. If both the PWM and
Maximum Peak Current Comparators toggle at the same
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28
NCP1339
Latching or Auto−Recovery Mode
5.5 V VCC(bias) level for 2 s only (typically). After this 2 s
delay time, the circuit attempts to restart. More practically,
after an overload condition is detected, operation is
interrupted and hence, the VCC that is provided by an
auxiliary winding, decays. When it reaches VCC(off), the
circuit waits for 2 s before allowing the circuit operation
recovery. During this delay, VCC is forced to the 5.5 V
VCC(bias) level so that the blocks monitoring the line remain
active. When this phase is complete, a VCC charge sequence
starts.
Figures 58 and 59 show operating waveforms for
auto−recovery and latched overload conditions.
The NCP1339D, E, F and I latch off when it detects an
overload situation. In this condition, the circuit stops
generating drive pulses and let VCC drop down. When VCC
has reached its 5.5 V VCC(bias) level, the circuit maintains
VCC to this level. It cannot recover operation until VCC
drops below its reset level. Practically, the power supply
must be unplugged to be reset.
The NCP1339C, G, H and J versions are autorecovery.
When an overload fault is detected, like latched versions, it
stops generating drive pulses and let VCC drop down to its
5.5 V VCC(bias) level. However, the VCC is maintained to its
2s
Figure 58. Auto−recovery Overload Operation
Figure 59. Latched Overload Operation
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29
NCP1339
A 2nd Over−Current Comparator for Abnormal
Overcurrent Fault Detection
Also, the Fault comparator to 0.4 V (or OTP comparator
since typically used for overtemperature) is blanked for the
soft−start duration. The pin can then be filtered by an
external capacitor.
A severe fault like a winding short−circuit can cause the
switch current to increase very rapidly during the on−time.
The current sense signal significantly exceeds VILIM1. But,
because the current sense signal is blanked by the LEB
circuit during the switch turn on, the power switch current
can become huge causing system damage.
The NCP1339 protects against this fault by adding an
additional comparator for Abnormal Overcurrent Fault
detection. The current sense signal is blanked with a shorter
LEB duration, tCS(LEB2), typically 125 ns, before applying
it to the Abnormal Overcurrent Fault Comparator. The
voltage threshold of the comparator, VILIM2, typically 1.2 V,
is set 50% higher than VILIM1, to avoid interference with
normal operation. Four consecutive Abnormal Overcurrent
faults cause the controller to enter latch mode (NCP1339D,
E, F and I versions) or auto−recovery (NCP1339C, G, H and
J). The count to 4 provides noise immunity during surge
testing. The counter is reset each time a DRV pulse occurs
without activating the Fault Overcurrent Comparator.
Jittering Capability
In order to help meet the EMI requirements, the NCP1339
(E, F, G, I and J versions) features the jittering capability to
average the spectrum rays over the frequency range. The
function consists of sourcing a 0 to 100 mA, 1.3 kHz
triangular current out of the CS pin (IJIT ). This current
together with the external resistor placed on the CS pin
generates an offset that will change the actual power switch
peak current and hence the operation frequency.
The jittering current source and hence the jittering
function is enabled only in high line condition since at low
line, the input voltage ripple is generally sufficient to help
meet EMI specs. This function is also disabled in Frequency
Foldback operation mode.
The jittering function modulates the peak current level. As
a result, the FB signal that struggles for compensating this
effect and limiting the output voltage ripple, exhibits a
swing. The resistor placed between the CS pin and the
current sense resistor must not be too high. Otherwise, the
jittering offset on the CS pin can lead to a FB swing
exceeding the VLO mode 600 mV hysteresis inbuilt to avoid
unwanted transitions between valleys. In practice, this
resistor is generally below 1 kohm.
Protecting from a Failure of the Current Sensing
A 1−mA (typically) pull−up current source, ICS, pulls up
the CS pin to disable the controller if the pin is left open.
In addition the maximum on−time (32 ms typically) avoids
that the MOSFET stays permanently on if the switch current
cannot reach the current setpoint when for instance, the input
voltage is low.
Driver
Soft−Start
The NCP1339 maximum supply voltage, VCC(max), is
28 V. Typical high−voltage MOSFETs have a maximum
gate voltage rating of 20 V. The DRV pin incorporates an
active voltage clamp to limit the gate voltage on the external
MOSFETs. The DRV voltage clamp, VDRV(high) is typically
12 V with a maximum limit of 14 V.
Soft−start is achieved by ramping up an internal reference,
VSSTART, and comparing it to current sense signal. VSSTART
ramps up from 0 V once the controller powers up. The
setpoint rise is then limited by the VSSTART ramp so that a
gradual increase of the power switch current during
start−up. The soft−start duration (that is, the time necessary
for the ramp to reach the VILIM1 steady state current limit),
tSSTART, is typically 4 ms.
During soft−start the ZCD timeout duration is extended.
This is because, during startup, demagnetization phases are
long and difficult to detect since the auxiliary winding
voltage is small. In this condition, the 6−ms steady−state
timeout is generally shorter than the inductor
demagnetization period and if used to restart a switching
cycle, it can cause continuous current mode (CCM)
operation for few cycles until the voltage on the ZCD pin is
high enough for proper valleys detection. A longer timeout
period, t(out1), (typically 100 ms) is therefore set during
soft−start to prevent CCM operation.
Thermal Shutdown
An internal thermal shutdown circuit monitors the
junction temperature of the IC. The controller is disabled if
the junction temperature exceeds the thermal shutdown
threshold, TSHDN, typically 150°C. A continuous VCC
hiccup is initiated after a thermal shutdown fault is detected.
The controller restarts at the next VCC(on) once the IC
temperature drops below TSHDN by the thermal shutdown
hysteresis, TSHDN(HYS), typically 40°C.
The thermal shutdown is also cleared if VCC drops below
VCC(reset), a brown−out fault is detected or if the controller
enters power savings mode. A new power up sequences
commences at the next VCC(on) once all the faults are
removed.
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30
NCP1339
ORDERING INFORMATION
Part Number
Overload
Protection
Abnormal
Overcurrent Fault
ZCD Blanking
Time
Jittering
Function
NCP1339CDR2G
Auto-Recovery
Auto−recovery
3 ms
Disabled
NCP1339DDR2G
Latching−off
Latching−off
3 ms
Disabled
NCP1339EDR2G
Latching−off
Latching−off
3 ms
Enabled
NCP1339FDR2G
Latching−off
Latching−off
0.7 ms
Enabled
NCP1339GDR2G
Auto-Recovery
Auto−recovery
0.7 ms
Enabled
NCP1339HDR2G
Auto-Recovery
Auto−recovery
0.7 ms
Disabled
NCP1339IDR2G
Latching−off
Latching−off
0.7 ms
Enabled
NCP1339JDR2G
Auto-Recovery
Auto−recovery
0.7 ms
Enabled
Shipping†
2500 / Tape &
Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
31
NCP1339
PACKAGE DIMENSIONS
D
SOIC−14 NB, LESS PIN 13
CASE 751AN
ISSUE A
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
b
0.25
M
C A
S
B
S
DETAIL A
h
A
e
DIM
A
A1
A3
b
D
E
e
H
h
L
M
X 45 _
M
A1
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
SOLDERING FOOTPRINT*
6.50
13X
1.18
1
1.27
PITCH
13X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP1339/D