MB9B520M Series
32-bit Arm® Cortex®-M3
FM3 Microcontroller
The MB9B520M Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power
consumption mode and competitive cost.
These series are based on the Arm® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions
such as various timers, ADCs, DACs and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE9 product categories in “FM3 Family Peripheral Manual”.
Features
32-bit Arm® Cortex®-M3 Core
[USB device]
Processor version: r2p1
USB2.0 Full-Speed supported
Up to 72 MHz Frequency Operation
Max 6 EndPoint supported
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
[Flash memory]
EndPoint
0 is control transfer
1, 2 can select Bulk-transfer, Interrupt-transfer or
Isochronous-transfer
EndPoint 3 to 5 can select Bulk-transfer or
Interrupt-transfer
EndPoint 1 to 5 are comprised of Double Buffers.
The size of each endpoint is according to the follows.
• Endpoint 0, 2 to 5: 64 bytes
• Endpoint 1: 256 bytes
EndPoint
[USB host]
Dual operation Flash memory
Dual
Operation Flash memory has the upper bank and the
lower bank.
So, this series could implement erase, write and read
operations for each bank simultaneously.
Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank
+ 16 Kbytes lower bank)
Work area: 32 Kbytes (lower bank)
Read cycle: 0 wait-cycle
USB2.0 Full/Low-speed supported
Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
USB Device connected/dis-connected automatic detection
Automatic processing of the IN/OUT token handshake
packet
Max 256-byte packet-length supported
Security function for code protection
Wake-up function supported
[SRAM]
This Series on-chip SRAM is composed of two independent
SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus
and D-code bus of Cortex-M3 core. SRAM1 is connected to
System bus.
CAN Interface
SRAM0: Up to 16 Kbytes
Built-in 32 message buffer
Compatible with CAN Specification 2.0A/B
Maximum transfer rate: 1 Mbps
SRAM1: Up to 16 Kbytes
Multi-function Serial Interface (Max eight channels)
USB Interface
The USB interface is composed of Device and Host.
PLL for USB is built-in, USB clock can be generated by
multiplication of Main clock.
Cypress Semiconductor Corporation
Document Number: 002-05649 Rev. *D
•
4 channels with 16 steps×9-bit FIFO (ch.0/1/3/4), 4 channels
without FIFO (ch.2/5/6/7)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
I2 C
198 Champion Court
•
San Jose , CA 95134-1709
•
408-943-2600
Revised February 9, 2018
MB9B520M Series
[UART]
A/D Converter (Max 26 channels)
Full duplex double buffer
[12-bit A/D Converter]
Selection with or without parity supported
Successive Approximation type
Built-in dedicated baud rate generator
Built-in 2 units
External clock available as a serial clock
Conversion time: 0.8 μs @ 5 V
Hardware Flow control: Automatically control the
Priority conversion available (priority at 2 levels)
transmission/reception by CTS/RTS (only ch.4)
Various error detection functions available (parity errors,
framing errors, and overrun errors)
[CSIO]
Full duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[LIN]
LIN protocol Rev.2.1 supported
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion:
4 steps)
D/A Converter (Max two channels)
R-2R type
10-bit resolution
Base Timer (Max eight channels)
Full duplex double buffer
Operation mode is selectable from the followings for each
channel.
Master/Slave mode supported
16-bit PWM timer
LIN break field generation (can be changed to 13 to 16-bit
16-bit PPG timer
length)
LIN break delimiter generation (can be changed to 1 to 4-bit
length)
Various error detection functions available (parity errors,
framing errors, and overrun errors)
[I2C]
Standard mode (Max 100 kbps) / Fast mode (Max 400 kbps)
supported
DMA Controller (Eight channels)
16-/32-bit reload timer
16-/32-bit PWC timer
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for peripherals. Moreover, the port relocate
function is built in. It can set which I/O port the peripheral
function can be allocated to.
Capable of pull-up control per pin
The DMA Controller has an independent bus from the CPU, so
CPU and DMA Controller can process simultaneously.
Capable of reading pin level directly
8 independently configured and operated channels
Up to 65 high-speed general-purpose I/O Ports@80pin
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
Built-in the port relocate function
Package
Some ports are 5V tolerant.
See “List of Pin Functions” and “I/O Circuit Type” to confirm
the corresponding pins.
transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Free-running
Periodic (=Reload)
One-shot
Document Number: 002-05649 Rev. *D
Page 2 of 108
MB9B520M Series
Quadrature Position/Revolution Counter (QPRC)
(Max two channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use as the up/down counter.
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Multi-function Timer
The Multi-function timer is composed of the following blocks.
External Interrupt Controller Unit
Up to 23 external interrupt input pins @ 80 pin Package
Include one non-maskable interrupt (NMI) input pin
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
The "Hardware" watchdog timer is clocked by the built-in
Low-speed CR oscillator. Therefore, the "Hardware" watchdog
is active in any low-power consumption modes except RTC,
Stop, Deep Standby RTC, Deep Standby Stop modes.
16-bit free-run timer × 3 ch./unit
CRC (Cyclic Redundancy Check) Accelerator
Input capture × 4 ch./unit
Output compare × 6 ch./unit
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
A/D activation compare × 2 ch./unit
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
Waveform generator × 3 ch./unit
CCITT CRC16 Generator Polynomial: 0x1021
16-bit PPG timer × 3 ch./unit
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
The following function can be used to achieve the motor
control.
Clock and Reset
PWM signal output function
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
DC chopper waveform output function
[Clocks]
Dead time function
Main Clock:
4 MHz to 48 MHz
Input capture function
Sub Clock:
32.768 kHz
A/D convertor activate function
Built-in High-speed CR Clock: 4 MHz
DTIF (Motor emergency stop) interrupt function
Built-in Low-speed CR Clock: 100 kHz
Main PLL Clock
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
[Resets]
Reset requests from INITX pin
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Leap year automatic count is available.
Clock Super Visor (CSV)
Watch Counter
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
The Watch counter is used for wake up from Sleep and Timer
mode.
If external clock failure (clock stop) is detected, reset is
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
If external frequency anomaly is detected, interrupt or reset is
asserted.
asserted.
Document Number: 002-05649 Rev. *D
Page 3 of 108
MB9B520M Series
Low-Voltage Detector (LVD)
Debug
This Series includes 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage that has been
set, Low-Voltage Detector generates an interrupt or reset.
Serial Wire JTAG Debug Port (SWJ-DP)
LVD1: error reporting via interrupt
Unique value of the device (41 bits) is set.
LVD2: auto-reset operation
Power Supply
Low-Power Consumption Mode
Six low-power consumption modes supported.
Sleep
Unique ID
Wide range voltage:
VCC
= 2.7 V to 5.5 V
USBVCC = 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
Timer
RTC
Stop
Deep Standby RTC (selectable between keeping the value of
RAM and not)
Deep Standby Stop (selectable between keeping the value of
RAM and not)
Document Number: 002-05649 Rev. *D
Page 4 of 108
MB9B520M Series
Contents
1. Product Lineup .................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. List of Pin Functions....................................................................................................................................................... 15
5. I/O Circuit Type................................................................................................................................................................ 33
6. Handling Precautions ..................................................................................................................................................... 39
6.1
Precautions for Product Design ................................................................................................................................... 39
6.2
Precautions for Package Mounting .............................................................................................................................. 40
6.3
Precautions for Use Environment ................................................................................................................................ 41
7. Handling Devices ............................................................................................................................................................ 42
8. Block Diagram ................................................................................................................................................................. 44
9. Memory Size .................................................................................................................................................................... 45
10. Memory Map .................................................................................................................................................................... 45
11. Pin Status in Each CPU State ........................................................................................................................................ 48
12. Electrical Characteristics ............................................................................................................................................... 54
12.1 Absolute Maximum Ratings ......................................................................................................................................... 54
12.2 Recommended Operating Conditions.......................................................................................................................... 56
12.3 DC Characteristics....................................................................................................................................................... 57
12.3.1 Current Rating .............................................................................................................................................................. 57
12.3.2 Pin Characteristics ....................................................................................................................................................... 60
12.4 AC Characteristics ....................................................................................................................................................... 61
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 61
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 62
12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 63
12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL) ................................... 64
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of Main PLL) .............. 64
12.4.6 Reset Input Characteristics .......................................................................................................................................... 65
12.4.7 Power-on Reset Timing................................................................................................................................................ 65
12.4.8 Base Timer Input Timing .............................................................................................................................................. 66
12.4.9 CSIO/UART Timing ...................................................................................................................................................... 67
12.4.10 External Input Timing ................................................................................................................................................ 75
12.4.11 Quadrature Position/Revolution Counter timing ........................................................................................................ 76
12.4.12 I2C Timing ................................................................................................................................................................. 78
12.4.13 JTAG Timing ............................................................................................................................................................. 79
12.5 12-bit A/D Converter .................................................................................................................................................... 80
12.5.1 Definition of 12-bit A/D Converter Terms ..................................................................................................................... 82
12.6 10-bit D/A Converter .................................................................................................................................................... 83
12.7 USB Characteristics .................................................................................................................................................... 84
12.8 Low-Voltage Detection Characteristics ........................................................................................................................ 88
12.8.1 Low-Voltage Detection Reset ....................................................................................................................................... 88
12.8.2 Interrupt of Low-Voltage Detection ............................................................................................................................... 89
12.9 Flash Memory Write/Erase Characteristics ................................................................................................................. 90
12.9.1 Write / Erase time......................................................................................................................................................... 90
12.9.2 Write cycles and data hold time ................................................................................................................................... 90
12.10 Return Time from Low-Power Consumption Mode ...................................................................................................... 91
12.10.1 Return Factor: Interrupt/WKUP ................................................................................................................................. 91
Document Number: 002-05649 Rev. *D
Page 5 of 108
MB9B520M Series
12.10.2 Return Factor: Reset ................................................................................................................................................ 93
13. Ordering Information ...................................................................................................................................................... 95
14. Package Dimensions ...................................................................................................................................................... 96
15. Major Changes .............................................................................................................................................................. 104
Document History ............................................................................................................................................................... 107
Sales, Solutions, and Legal Information ........................................................................................................................... 108
Document Number: 002-05649 Rev. *D
Page 6 of 108
MB9B520M Series
1. Product Lineup
Memory Size
Product name
On-chip
Flash memory
On-chip SRAM
MB9BF521K/L/M
Main area
Work area
SRAM0
SRAM1
Total
64 Kbytes
32 Kbytes
8 Kbytes
8 Kbytes
16 Kbytes
MB9BF522K/L/M
128 Kbytes
32 Kbytes
8 Kbytes
8 Kbytes
16 Kbytes
MB9BF524K/L/M
256 Kbytes
32 Kbytes
16 Kbytes
16 Kbytes
32 Kbytes
Function
MB9BF521K
MB9BF522K
MB9BF524K
Product name
Pin count
MB9BF521M
MB9BF522M
MB9BF524M
48
64
80/96
Cortex-M3
72 MHz
2.7 V to 5.5 V
1 ch. (Max)
1 ch. (Max)
8 ch.
4 ch. (Max)
8 ch. (Max)
ch.0/1/3: FIFO
ch.0/1/3/4 FIFO
ch.5: No FIFO
ch.2/5/6/7: No FIFO
(In ch.1/5, only UART and LIN
(In ch.1, only UART and LIN are available.)
are available.)
CPU
Freq.
Power supply voltage range
USB2.0 (Device/Host)
CAN
DMAC
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
A/D activation
compare
Input capture
MFFree-run timer
Timer
Output compare
Waveform generator
PPG
QPRC
MB9BF521L
MB9BF522L
MB9BF524L
8 ch. (Max)
2 ch.
4 ch.*
3 ch.
6 ch.
3 ch.
3 ch.
1 unit
1 ch.
Dual Timer
1 unit
Real-Time Clock
Watch Counter
CRC Accelerator
Watchdog timer
1 unit
1 unit
Yes
1 ch. (SW) + 1 ch. (HW)
14 pins (Max) +
NMI × 1
35 pins (Max)
14 ch. (2 units)
2 ch. (Max)
Yes
2 ch.
4 MHz
100 kHz
SWJ-DP
Yes
External Interrupts
I/O ports
12-bit A/D converter
10-bit D/A converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
High-speed
Built-in CR
Low-speed
Debug Function
Unique ID
2 ch. (Max)
19 pins (Max) +
NMI × 1
50 pins (Max)
23 ch. (2 units)
23 pins (Max) +
NMI × 1
65 pins (Max)
26 ch. (2 units)
*: The external input channel which can be used is shown as follows.
• ch.0 to ch.3 : MB9BF521M/F522M/F524M
• ch.0, ch.2, ch.3 : MB9BF521K/F522K/F524K, MB9BF521L/F522L/F524L
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See “12.Electrical Characteristics 12.4.AC Characteristics 12.4.3 Built-in CR Oscillation Characteristics” for accuracy of
built-in CR.
Document Number: 002-05649 Rev. *D
Page 7 of 108
MB9B520M Series
2. Packages
Product name
Package
MB9BF521K
MB9BF522K
MB9BF524K
MB9BF521L
MB9BF522L
MB9BF524L
MB9BF521M
MB9BF522M
MB9BF524M
LQFP:
LQA048 (0.5 mm pitch)
-
-
QFN:
VNA048 (0.5 mm pitch)
-
-
LQFP:
LQD064 (0.5 mm pitch)
-
-
LQFP:
LQG064 (0.65 mm pitch)
-
-
QFN:
VNC064 (0.5 mm pitch)
-
-
LQFP:
LQH080 (0.5 mm pitch)
-
-
LQFP:
LQJ080 (0.65 mm pitch)
-
-
BGA:
FDG096 (0.5 mm pitch)
-
-
: Supported
Note:
−
See “Package Dimensions” for detailed information on each package.
Document Number: 002-05649 Rev. *D
Page 8 of 108
MB9B520M Series
3. Pin Assignment
LQH080/LQJ080
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
63
62
61
P04/TDO/SWO
P03/TMS/SWDIO
65
64
P0B/AN16/SOT4_0/TIOB6_1/INT18_0
P0A/AN15/SIN4_0/INT00_2
P07/ADTG_0/INT23_1
68
67
66
P0D/RTS4_0/TIOA3_2/INT20_0
P0C/AN17/SCK4_0/TIOA6_1/INT19_0
70
69
P63/INT03_0
P0F/AN18/NMIX/SUBOUT_0/CROUT_1/RTCCO_0/WKUP0
P0E/CTS4_0/TIOB3_2/INT21_0
73
72
71
P61/AN20/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
P62/AN19/SCK5_0/ADTG_3
76
75
74
P80/UDM0/INT16_1
USBVCC
P60/AN21/SIN5_0/TIOA2_2/INT15_1/WKUP3/IGTRG_1
78
77
VSS
P81/UDP0/INT17_1
80
79
(TOP VIEW)
VCC
1
60
P20/INT05_0/CROUT_0/AIN1_1
P50/AN22/INT00_0/AIN0_2/SIN3_1
2
59
P21/AN14/SIN0_0/INT06_1/BIN1_1/WKUP2
P51/AN23/INT01_0/BIN0_2/SOT3_1
3
58
P22/AN13/SOT0_0/TIOB7_1/ZIN1_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
4
57
P23/AN12/SCK0_0/TIOA7_1
P53/SIN6_0/TIOA1_2/INT07_2
5
56
P1B/AN11/SOT4_1/INT20_2/IC01_1
P54/SOT6_0/TIOB1_2/INT18_1
6
55
P1A/AN10/SIN4_1/INT05_1/IC00_1
P55/SCK6_0/ADTG_1/INT19_1
7
54
P19/AN09/SCK2_2
P56/INT08_2
8
53
P18/AN08/SOT2_2
P30/AN25/AIN0_0/TIOB0_1/INT03_2
9
52
AVRL
P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2
10
51
AVRH
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
11
50
AVCC
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
12
49
P17/AN07/SIN2_2/INT04_1
P39/DTTI0X_0/INT06_0/ADTG_2
13
48
P16/AN06/SCK0_1/INT15_0
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
14
47
P15/AN05/SOT0_1/INT14_0/IC03_2
P3B/RTO01_0/TIOA1_1
15
46
P14/AN04/SIN0_1/INT03_1/IC02_2
P3C/RTO02_0/TIOA2_1/INT18_2
16
45
AVSS
LQFP - 80
38
39
40
PE2/X0
PE3/X1
VSS
36
37
MD0
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2
PE0/MD1
33
34
35
P4C/TIOB3_0/SCK7_1/INT12_0/AIN1_2
P4B/TIOB2_0/INT22_1/ZIN0_1/IGTRG_0
P4D/TIOB4_0/SOT7_1/INT13_0/BIN1_2
31
32
P4A/TIOB1_0/SCK3_2/INT21_1/BIN0_1/DA1_0
28
29
30
INITX
P48/SIN3_2/INT14_1
P49/TIOB0_0/SOT3_2/INT20_1/AIN0_1/DA0_0
25
26
27
P46/X0A
VCC
P47/X1A
41
23
20
24
P10/AN00
VSS
C
42
VSS
19
VCC
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/WKUP1
P3F/RTO05_0/TIOA5_1
21
P12/AN02/SOT1_1/TX1_2/IC00_2
43
22
44
18
P44/TIOA4_0/INT10_0
17
P45/TIOA5_0/INT11_0
P3D/RTO03_0/TIOA3_1
P3E/RTO04_0/TIOA4_1/INT19_2
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05649 Rev. *D
Page 9 of 108
MB9B520M Series
LQD064/LQG064
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
52
51
50
49
P0A/AN15/SIN4_0/INT00_2
P04/TDO/SWO
54
53
P0C/AN17/SCK4_0/TIOA6_1/INT19_0
P0B/AN16/SOT4_0/TIOB6_1/INT18_0
56
55
P62/AN19/SCK5_0/ADTG_3
P0F/AN18/NMIX/SUBOUT_0/CROUT_1/RTCCO_0/WKUP0
58
57
P60/AN21/SIN5_0/TIOA2_2/INT15_1/WKUP3/IGTRG_1
P61/AN20/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
60
59
P80/UDM0/INT16_1
USBVCC
62
61
VSS
P81/UDP0/INT17_1
64
63
(TOP VIEW)
VCC
1
48
P21/AN14/SIN0_0/INT06_1/WKUP2
P50/AN22/INT00_0/AIN0_2/SIN3_1
2
47
P22/AN13/SOT0_0/TIOB7_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
3
46
P23/AN12/SCK0_0/TIOA7_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
4
45
P19/AN09/SCK2_2
P30/AN25/AIN0_0/TIOB0_1/INT03_2
5
44
P18/AN08/SOT2_2
P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2
6
43
AVRL
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
7
42
AVRH
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
8
41
AVCC
P39/DTTI0X_0/INT06_0/ADTG_2
9
40
P17/AN07/SIN2_2/INT04_1
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
10
39
P15/AN05/SOT0_1/INT14_0/IC03_2
P3B/RTO01_0/TIOA1_1
11
38
P14/AN04/SIN0_1/INT03_1/IC02_2
P3C/RTO02_0/TIOA2_1/INT18_2
12
37
AVSS
P3D/RTO03_0/TIOA3_1
13
36
P12/AN02/SOT1_1/TX1_2/IC00_2
P3E/RTO04_0/TIOA4_1/INT19_2
14
35
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/WKUP1
P3F/RTO05_0/TIOA5_1
15
34
P10/AN00
VSS
16
33
VCC
29
30
31
32
PE3/X1
VSS
PE0/MD1
MD0
27
28
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2
PE2/X0
25
26
P4C/TIOB3_0/SCK7_1/INT12_0/AIN1_2
P4B/TIOB2_0/INT22_1/ZIN0_1/IGTRG_0
P4D/TIOB4_0/SOT7_1/INT13_0/BIN1_2
23
24
P4A/TIOB1_0/SCK3_2/INT21_1/BIN0_1/DA1_0
21
22
INITX
19
20
P46/X0A
P47/X1A
P49/TIOB0_0/SOT3_2/INT20_1/AIN0_1/DA0_0
17
18
C
VCC
LQFP - 64
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05649 Rev. *D
Page 10 of 108
MB9B520M Series
VNC064
VSS
P81/UDP0/INT17_1
P80/UDM0/INT16_1
USBVCC
P60/AN21/SIN5_0/TIOA2_2/INT15_1/WKUP3/IGTRG_1
P61/AN20/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
P62/AN19/SCK5_0/ADTG_3
P0F/AN18/NMIX/SUBOUT_0/CROUT_1/RTCCO_0/WKUP0
P0C/AN17/SCK4_0/TIOA6_1/INT19_0
P0B/AN16/SOT4_0/TIOB6_1/INT18_0
P0A/AN15/SIN4_0/INT00_2
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(TOP VIEW)
VCC
1
48
P21/AN14/SIN0_0/INT06_1/WKUP2
P50/AN22/INT00_0/AIN0_2/SIN3_1
2
47
P22/AN13/SOT0_0/TIOB7_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
3
46
P23/AN12/SCK0_0/TIOA7_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
4
45
P19/AN09/SCK2_2
P30/AN25/AIN0_0/TIOB0_1/INT03_2
5
44
P18/AN08/SOT2_2
P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2
6
43
AVRL
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
7
42
AVRH
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
8
41
AVCC
P39/DTTI0X_0/INT06_0/ADTG_2
9
40
P17/AN07/SIN2_2/INT04_1
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
10
39
P15/AN05/SOT0_1/INT14_0/IC03_2
P3B/RTO01_0/TIOA1_1
11
38
P14/AN04/SIN0_1/INT03_1/IC02_2
P3C/RTO02_0/TIOA2_1/INT18_2
12
37
AVSS
P3D/RTO03_0/TIOA3_1
13
36
P12/AN02/SOT1_1/TX1_2/IC00_2
P3E/RTO04_0/TIOA4_1/INT19_2
14
35
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/WKUP1
P3F/RTO05_0/TIOA5_1
15
34
P10/AN00
VSS
16
33
VCC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0/SOT3_2/INT20_1/AIN0_1/DA0_0
P4A/TIOB1_0/SCK3_2/INT21_1/BIN0_1/DA1_0
P4B/TIOB2_0/INT22_1/ZIN0_1/IGTRG_0
P4C/TIOB3_0/SCK7_1/INT12_0/AIN1_2
P4D/TIOB4_0/SOT7_1/INT13_0/BIN1_2
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
QFN - 64
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05649 Rev. *D
Page 11 of 108
MB9B520M Series
LQA048
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
40
39
38
37
P0F/AN18/NMIX/SUBOUT_0/CROUT_1/RTCCO_0/WKUP0
P04/TDO/SWO
42
41
P60/AN21/SIN5_0/TIOA2_2/INT15_1/WKUP3/IGTRG_1
P61/AN20/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
44
43
P80/UDM0/INT16_1
USBVCC
46
45
VSS
P81/UDP0/INT17_1
48
47
(TOP VIEW)
VCC
1
36
P21/AN14/SIN0_0/INT06_1/WKUP2
P50/AN22/INT00_0/AIN0_2/SIN3_1
2
35
P22/AN13/SOT0_0/TIOB7_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
3
34
P23/AN12/SCK0_0/TIOA7_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
4
33
AVRL
P39/DTTI0X_0/INT06_0/ADTG_2
5
32
AVRH
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
6
31
AVCC
P3B/RTO01_0/TIOA1_1
7
30
P15/AN05/SOT0_1/INT14_0/IC03_2
P3C/RTO02_0/TIOA2_1/INT18_2
8
29
P14/AN04/SIN0_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1
9
28
AVSS
P3E/RTO04_0/TIOA4_1/INT19_2
10
27
P12/AN02/SOT1_1/TX1_2/IC00_2
P3F/RTO05_0/TIOA5_1
11
26
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/WKUP1
VSS
12
25
P10/AN00
21
22
23
24
PE3/X1
VSS
PE0/MD1
MD0
19
20
P4A/TIOB1_0/INT21_1/DA1_0
PE2/X0
17
18
INITX
15
16
P46/X0A
P47/X1A
P49/TIOB0_0/INT20_1/DA0_0
13
14
C
VCC
LQFP - 48
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05649 Rev. *D
Page 12 of 108
MB9B520M Series
VNA048
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
40
39
38
37
P0F/AN18/NMIX/SUBOUT_0/CROUT_1/RTCCO_0/WKUP0
P04/TDO/SWO
42
41
P60/AN21/SIN5_0/TIOA2_2/INT15_1/WKUP3/IGTRG_1
P61/AN20/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
44
43
P80/UDM0/INT16_1
USBVCC
46
45
VSS
P81/UDP0/INT17_1
48
47
(TOP VIEW)
VCC
1
36
P21/AN14/SIN0_0/INT06_1/WKUP2
P50/AN22/INT00_0/AIN0_2/SIN3_1
2
35
P22/AN13/SOT0_0/TIOB7_1
P51/AN23/INT01_0/BIN0_2/SOT3_1
3
34
P23/AN12/SCK0_0/TIOA7_1
P52/AN24/INT02_0/ZIN0_2/SCK3_1
4
33
AVRL
P39/DTTI0X_0/INT06_0/ADTG_2
5
32
AVRH
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2
6
31
AVCC
P3B/RTO01_0/TIOA1_1
7
30
P15/AN05/SOT0_1/INT14_0/IC03_2
P3C/RTO02_0/TIOA2_1/INT18_2
8
29
P14/AN04/SIN0_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1
9
28
AVSS
P3E/RTO04_0/TIOA4_1/INT19_2
10
27
P12/AN02/SOT1_1/TX1_2/IC00_2
P3F/RTO05_0/TIOA5_1
11
26
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/WKUP1
VSS
12
25
P10/AN00
21
22
23
24
PE3/X1
VSS
PE0/MD1
MD0
19
20
P4A/TIOB1_0/INT21_1/DA1_0
PE2/X0
17
18
INITX
15
16
P46/X0A
P47/X1A
P49/TIOB0_0/INT20_1/DA0_0
13
14
C
VCC
QFN - 48
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05649 Rev. *D
Page 13 of 108
MB9B520M Series
FDG096
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
VSS
UDP0
UDM0
USBVCC
VSS
AN18
VSS
P07
TMS/
SWDIO
TRSTX
VSS
B
VCC
VSS
AN24
AN20
P63
P0D
AN17
TDO/
SWO
TCK/
SWCLK
VSS
TDI
C
AN22
AN23
VSS
AN21
AN19
P0E
AN16
AN15
VSS
P20
AN14
D
P53
P54
P55
Index
AN13
AN12
VSS
E
P56
AN25
AN26
AN11
AN10
AN09
F
VSS
VSS
VSS
AN08
AN07
AVRH
G
P32
P33
P39
AN06
AN05
AVRL
H
P3A
P3B
P3C
AN04
AVSS
AVCC
J
P3D
P3E
VSS
P3F
P48
P4A
P4D
AN02
VSS
AN01
AN00
K
VCC
VSS
X1A
INITX
P45
P49
P4C
P4E
MD1
VSS
VCC
L
VSS
C
X0A
VSS
P44
VSS
P4B
MD0
X0
X1
VSS
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05649 Rev. *D
Page 14 of 108
MB9B520M Series
4. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
LQFP-80
1
LQFP-64
QFN-64
BGA-96
B1
1
1
I/O circuit
type
Pin Name
LQFP-48
QFN-48
VCC
Pin state
type
-
P50
INT00_0
2
C1
2
2
AIN0_2
F
N
F
N
F
N
E
L
E
L
E
L
E
L
F
N
SIN3_1
AN22
P51
INT01_0
3
C2
3
3
BIN0_2
SOT3_1
(SDA3_1)
AN23
P52
INT02_0
4
B3
4
4
ZIN0_2
SCK3_1
(SCL3_1)
AN24
P53
5
D1
-
-
SIN6_0
TIOA1_2
INT07_2
P54
6
D2
-
-
SOT6_0
(SDA6_0)
TIOB1_2
INT18_1
P55
7
D3
-
-
SCK6_0
(SCL6_0)
ADTG_1
INT19_1
8
E1
-
-
P56
INT08_2
P30
AIN0_0
9
E2
5
-
TIOB0_1
INT03_2
AN25
Document Number: 002-05649 Rev. *D
Page 15 of 108
MB9B520M Series
Pin No
LQFP-80
LQFP-64
QFN-64
BGA-96
I/O circuit
type
Pin Name
LQFP-48
QFN-48
Pin state
type
P31
BIN0_0
TIOB1_1
10
E3
6
-
SCK6_1
(SCL6_1)
F
N
E
L
E
L
E
L
G
L
G
K
G
L
G
K
INT04_2
AN26
P32
ZIN0_0
11
G1
7
-
TIOB2_1
SOT6_1
(SDA6_1)
INT05_2
P33
INT04_0
12
G2
8
-
TIOB3_1
SIN6_1
ADTG_6
P39
13
G3
9
5
DTTI0X_0
INT06_0
ADTG_2
P3A
RTO00_0
(PPG00_0)
14
H1
10
6
TIOA0_1
INT07_0
SUBOUT_2
RTCCO_2
P3B
15
H2
11
7
RTO01_0
(PPG00_0)
TIOA1_1
P3C
16
H3
12
8
RTO02_0
(PPG02_0)
TIOA2_1
INT18_2
P3D
17
J1
13
9
RTO03_0
(PPG02_0)
TIOA3_1
Document Number: 002-05649 Rev. *D
Page 16 of 108
MB9B520M Series
Pin No
LQFP-80
LQFP-64
QFN-64
BGA-96
I/O circuit
type
Pin Name
LQFP-48
QFN-48
Pin state
type
P3E
18
J2
14
10
RTO04_0
(PPG04_0)
G
L
G
K
TIOA4_1
INT19_2
P3F
19
J4
15
11
20
L1
16
12
21
L5
-
-
22
K5
-
-
23
L2
17
24
L4
-
25
K1
18
RTO05_0
(PPG04_0)
TIOA5_1
-
13
VSS
P44
TIOA4_0
INT10_0
P45
TIOA5_0
INT11_0
C
-
VSS
-
14
VCC
-
26
L3
19
15
27
K3
20
16
28
K4
21
17
P46
X0A
P47
X1A
INITX
G
L
G
L
-
D
F
D
G
B
C
E
L
L
L
L
L
P48
29
J5
-
-
INT14_1
SIN3_2
P49
18
30
K6
22
TIOB0_0
INT20_1
DA0_0
-
SOT3_2
(SDA3_2)
AIN0_1
P4A
19
31
J6
23
TIOB1_0
INT21_1
DA1_0
-
SCK3_2
(SCL3_2)
BIN0_1
Document Number: 002-05649 Rev. *D
Page 17 of 108
MB9B520M Series
Pin No
LQFP-80
LQFP-64
QFN-64
BGA-96
I/O circuit
type
Pin Name
LQFP-48
QFN-48
Pin state
type
P4B
TIOB2_0
32
L7
24
-
INT22_1
E
L
I*
L
I*
L
I*
L
C
E
K
D
A
A
A
B
IGTRG_0
ZIN0_1
P4C
TIOB3_0
33
K7
25
-
SCK7_1
(SCL7_1)
INT12_0
AIN1_2
P4D
TIOB4_0
34
J7
26
-
SOT7_1
(SDA7_1)
INT13_0
BIN1_2
P4E
TIOB5_0
35
K8
27
-
INT06_2
SIN7_1
ZIN1_2
36
K9
28
20
37
L8
29
21
MD1
PE0
MD0
X0
38
L9
30
22
39
L10
31
23
40
L11
32
24
VSS
-
41
K11
33
-
VCC
-
42
J11
34
25
PE2
X1
PE3
P10
AN00
F
M
F
N
F
M
P11
AN01
SIN1_1
43
J10
35
26
INT02_1
RX1_2
FRCK0_2
WKUP1
P12
AN02
44
J8
36
27
SOT1_1
(SDA1_1)
TX1_2
IC00_2
Document Number: 002-05649 Rev. *D
Page 18 of 108
MB9B520M Series
Pin No
LQFP-80
45
LQFP-64
QFN-64
BGA-96
H10
37
28
I/O circuit
type
Pin Name
LQFP-48
QFN-48
AVSS
Pin state
type
-
P14
AN04
46
H9
38
29
INT03_1
F
N
F
N
F
N
F
N
IC02_2
SIN0_1
P15
AN05
47
G10
39
30
IC03_2
SOT0_1
(SDA0_1)
INT14_0
P16
AN06
48
G9
-
-
SCK0_1
(SCL0_1)
INT15_0
P17
AN07
49
F10
40
-
50
H11
41
31
AVCC
-
51
F11
42
32
AVRH
-
52
G11
43
33
AVRL
-
SIN2_2
INT04_1
P18
53
F9
44
-
AN08
SOT2_2
(SDA2_2)
F
M
F
M
F
N
P19
54
E11
45
-
AN09
SCK2_2
(SCL2_2)
P1A
AN10
55
E10
-
-
SIN4_1
INT05_1
IC00_1
Document Number: 002-05649 Rev. *D
Page 19 of 108
MB9B520M Series
Pin No
LQFP-80
LQFP-64
QFN-64
BGA-96
I/O circuit
type
Pin Name
LQFP-48
QFN-48
Pin state
type
P1B
AN11
56
E9
-
-
SOT4_1
(SDA4_1)
F
N
F
M
F
M
F
N
E
N
E
J
E
J
E
J
E
J
E
J
E
L
IC01_1
INT20_2
P23
57
D10
46
34
SCK0_0
(SCL0_0)
TIOA7_1
AN12
P22
58
D9
47
35
SOT0_0
(SDA0_0)
TIOB7_1
AN13
-
-
ZIN1_1
P21
SIN0_0
59
C11
48
36
INT06_1
WKUP2
BIN1_1
AN14
P20
60
C10
-
-
INT05_0
CROUT_0
AIN1_1
61
A10
49
37
62
B9
50
38
P00
TRSTX
P01
TCK
SWCLK
63
B11
51
39
64
A9
52
40
P02
TDI
P03
TMS
SWDIO
P04
65
B8
53
41
TDO
SWO
P07
66
A8
-
-
ADTG_0
INT23_1
Document Number: 002-05649 Rev. *D
Page 20 of 108
MB9B520M Series
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-80
I/O circuit
type
Pin Name
LQFP-48
QFN-48
Pin state
type
P0A
67
C8
54
-
SIN4_0
INT00_2
J*
N
J*
N
J*
N
E
L
E
L
F
I
E
L
F
M
F
M
AN15
P0B
68
C7
55
-
SOT4_0
(SDA4_0)
TIOB6_1
AN16
INT18_0
P0C
69
B7
56
-
SCK4_0
(SCL4_0)
TIOA6_1
INT19_0
AN17
P0D
70
B6
-
-
RTS4_0
TIOA3_2
INT20_0
P0E
71
C6
-
-
CTS4_0
TIOB3_2
INT21_0
P0F
NMIX
SUBOUT_0
72
A6
57
42
CROUT_1
RTCCO_0
WKUP0
AN18
73
B5
-
-
P63
INT03_0
P62
74
C5
58
-
SCK5_0
(SCL5_0)
ADTG_3
AN19
P61
SOT5_0
(SDA5_0)
75
B4
59
43
TIOB2_2
UHCONX
DTTI0X_2
AN20
Document Number: 002-05649 Rev. *D
Page 21 of 108
MB9B520M Series
Pin No
LQFP-80
LQFP-64
QFN-64
BGA-96
I/O circuit
type
Pin Name
LQFP-48
QFN-48
Pin state
type
P60
SIN5_0
TIOA2_2
76
C4
60
44
INT15_1
J*
N
WKUP3
IGTRG_1
AN21
77
A4
61
45
USBVCC
-
P80
78
A3
62
46
UDM0
H
H
H
H
INT16_1
P81
79
A2
63
47
UDP0
INT17_1
80
A1
64
48
VSS
-
-
A5, A7, A11, B2,
B10, C3, C9, D11,
F1, F2, F3, J3, J9,
K2, K10, L6
-
-
VSS
-
*: 5 V tolerant I/O
Document Number: 002-05649 Rev. *D
Page 22 of 108
MB9B520M Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin function
ADC
Pin name
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_6
AN00
AN01
AN02
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
Function description
A/D converter external trigger input pin
A/D converter analog input pin.
ANxx describes ADC ch.xx.
Document Number: 002-05649 Rev. *D
LQFP-80
66
7
13
74
12
42
43
44
46
47
48
49
53
54
55
56
57
58
59
67
68
69
72
74
75
76
2
3
4
9
10
Pin No
LQFP-64
BGA-96
QFN-64
A8
D3
G3
C5
G2
J11
J10
J8
H9
G10
G9
F10
F9
E11
E10
E9
D10
D9
C11
C8
C7
B7
A6
C5
B4
C4
C1
C2
B3
E2
E3
9
58
8
34
35
36
38
39
40
44
45
46
47
48
54
55
56
57
58
59
60
2
3
4
5
6
LQFP-48
QFN-48
5
25
26
27
29
30
34
35
36
42
43
44
2
3
4
-
Page 23 of 108
MB9B520M Series
Pin function
Base Timer
0
Base Timer
1
Base Timer
2
Base Timer
3
Base Timer
4
Base Timer
5
Base Timer
6
Base Timer
7
Debugger
Pin name
TIOA0_1
TIOB0_0
TIOB0_1
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOB4_0
TIOA5_0
TIOA5_1
TIOB5_0
TIOA6_1
TIOB6_1
TIOA7_1
TIOB7_1
SWCLK
SWDIO
SWO
TCK
TDI
TDO
TMS
TRSTX
Function description
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Serial wire debug interface clock input pin
Serial wire debug interface data input / output
pin
Serial wire viewer output pin
JTAG test clock input pin
JTAG test data input pin
JTAG debug data output pin
JTAG test mode state input/output pin
JTAG test reset input pin
Document Number: 002-05649 Rev. *D
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-48
QFN-48
14
30
9
15
5
31
10
6
16
76
32
11
75
17
70
33
12
71
21
18
34
22
19
35
69
68
57
58
62
H1
K6
E2
H2
D1
J6
E3
D2
H3
C4
L7
G1
B4
J1
B6
K7
G2
C6
L5
J2
J7
K5
J4
K8
B7
C7
D10
D9
B9
10
22
5
11
23
6
12
60
24
7
59
13
25
8
14
26
15
27
56
55
46
47
50
6
18
7
19
8
44
43
9
10
11
34
35
38
64
A9
52
40
65
62
63
65
64
61
B8
B9
B11
B8
A9
A10
53
50
51
53
52
49
41
38
39
41
40
37
LQFP-80
Page 24 of 108
MB9B520M Series
Pin function
External
Interrupt
Pin name
INT00_0
INT00_2
INT01_0
INT02_0
INT02_1
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_0
INT06_1
INT06_2
INT07_0
INT07_2
INT08_2
INT10_0
INT11_0
INT12_0
INT13_0
INT14_0
INT14_1
INT15_0
INT15_1
INT16_1
INT17_1
INT18_0
INT18_1
INT18_2
INT19_0
INT19_1
INT19_2
Function description
External interrupt request 00 input pin
External interrupt request 01 input pin
External interrupt request 02 input pin
External interrupt request 03 input pin
External interrupt request 04 input pin
External interrupt request 05 input pin
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
External interrupt request 10 input pin
External interrupt request 11 input pin
External interrupt request 12 input pin
External interrupt request 13 input pin
External interrupt request 14 input pin
External interrupt request 15 input pin
External interrupt request 16 input pin
External interrupt request 17 input pin
External interrupt request 18 input pin
External interrupt request 19 input pin
Document Number: 002-05649 Rev. *D
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-48
QFN-48
2
C1
2
2
67
C8
54
-
3
4
43
73
46
9
12
49
10
60
55
11
13
59
35
14
5
8
21
22
33
34
47
29
48
76
78
79
68
6
16
59
7
18
C2
B3
J10
B5
H9
E2
G2
F10
E3
P20
E10
G1
G3
C11
K8
H1
D1
E1
L5
K5
K7
J7
G10
J5
G9
C4
A3
A2
C7
D2
H3
C11
D3
J2
3
4
35
38
5
8
40
6
7
9
48
27
10
25
26
39
60
62
63
55
12
56
14
3
4
26
29
5
36
6
30
44
46
47
8
10
LQFP-80
Page 25 of 108
MB9B520M Series
Pin function
External
Interrupt
GPIO
Pin name
INT20_0
INT20_1
INT20_2
INT21_0
INT21_1
INT22_1
INT23_1
NMIX
P00
P01
P02
P03
P04
P07
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P14
P15
P16
P17
P18
P19
P1A
P1B
P20
P21
P22
P23
Function description
External interrupt request 20 input pin
External interrupt request 21 input pin
External interrupt request 22 input pin
External interrupt request 23 input pin
Non-Maskable Interrupt input pin
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
Document Number: 002-05649 Rev. *D
LQFP-80
70
30
56
71
31
32
66
72
61
62
63
64
65
66
67
68
69
70
71
72
42
43
44
46
47
48
49
53
54
55
56
60
59
58
57
Pin No
LQFP-64
BGA-96
QFN-64
B6
K6
E9
C6
J6
L7
A8
A6
A10
B9
B11
A9
B8
A8
C8
C7
B7
B6
C6
A6
J11
J10
J8
H9
G10
G9
F10
F9
E11
E10
E9
C10
C11
D9
D10
22
23
24
57
49
50
51
52
53
54
55
56
57
34
35
36
38
39
40
44
45
48
47
46
LQFP-48
QFN-48
18
19
42
37
38
39
40
41
42
25
26
27
29
30
36
35
34
Page 26 of 108
MB9B520M Series
Pin function
GPIO
Pin name
P30
P31
P32
P33
P39
P3A
P3B
P3C
P3D
P3E
P3F
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P60
P61
P62
P63
P80
P81
PE0
PE2
PE3
Function description
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
General-purpose I/O port E
Document Number: 002-05649 Rev. *D
LQFP-80
9
10
11
12
13
14
15
16
17
18
19
21
22
26
27
29
30
31
32
33
34
35
2
3
4
5
6
7
8
76
75
74
73
78
79
36
38
39
Pin No
LQFP-64
BGA-96
QFN-64
E2
E3
G1
G2
G3
H1
H2
H3
J1
J2
J4
L5
K5
L3
K3
J5
K6
J6
L7
K7
J7
K8
C1
C2
B3
D1
D2
D3
E1
C4
B4
C5
B5
A3
A2
K9
L9
L10
5
6
7
8
9
10
11
12
13
14
15
19
20
22
23
24
25
26
27
2
3
4
60
59
58
62
63
28
30
31
LQFP-48
QFN-48
5
6
7
8
9
10
11
15
16
18
19
2
3
4
44
43
46
47
20
22
23
Page 27 of 108
MB9B520M Series
Pin function
Pin name
Multifunction Serial
0
SIN0_0
SIN0_1
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
Multifunction
Serial
1
SIN1_1
Multifunction Serial
2
SIN2_2
SOT1_1
(SDA1_1)
SOT2_2
(SDA2_2)
SCK2_2
(SCL2_2)
Multifunction Serial
3
SIN3_1
SIN3_2
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-48
QFN-48
59
C11
48
36
46
H9
38
29
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA0 when it is used in an I2C (operation mode 4).
58
D9
47
35
47
G10
39
30
Multi-function serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a
CSIO (operation mode 2) and as SCL0 when it is
used in an I2C (operation mode 4).
57
D10
46
34
48
G9
-
-
Multi-function serial interface ch.1 input pin
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a
UART/LIN (operation modes 0,1,3) .
Multi-function serial interface ch.2 input pin
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA2 when it is used in an I2C (operation mode 4).
Multi-function serial interface ch.2 clock I/O pin.
This pin operates as SCK2 when it is used in a
CSIO (operation mode 2) and as SCL2 when it is
used in an I2C (operation mode 4).
43
J10
35
26
44
J8
36
27
49
F10
40
-
53
F9
44
-
54
E11
45
-
2
C1
2
2
29
J5
-
-
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA3 when it is used in an I2C (operation mode 4).
3
C2
3
3
30
K6
-
-
Multi-function serial interface ch.3 clock I/O pin.
This pin operates as SCK3 when it is used in a
CSIO (operation mode 2) and as SCL3 when it is
used in an I2C (operation mode 4).
4
B3
4
4
31
J6
-
-
Function description
Multi-function serial interface ch.0 input pin
Multi-function serial interface ch.3 input pin
Document Number: 002-05649 Rev. *D
LQFP-80
Page 28 of 108
MB9B520M Series
Pin function
Pin name
Multifunction Serial
4
SIN4_0
SIN4_1
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SCK4_0
(SCL4_0)
Multifunction Serial
5
RTS4_0
CTS4_0
SIN5_0
SOT5_0
(SDA5_0)
SCK5_0
(SCL5_0)
Multifunction Serial
6
SIN6_0
SIN6_1
SOT6_0
(SDA6_0)
SOT6_1
(SDA6_1)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-48
QFN-48
67
C8
54
-
55
E10
-
-
68
C7
55
-
56
E9
-
-
69
B7
56
-
70
71
76
B6
C6
C4
60
44
75
B4
59
43
74
C5
58
-
5
D1
-
-
12
G2
8
-
Multi-function serial interface ch.6 output pin.
This pin operates as SOT6 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA6 when it is used in an I2C (operation mode 4).
6
D2
-
-
11
G1
7
-
Multi-function serial interface ch.6 clock I/O pin.
This pin operates as SCK6 when it is used in a
CSIO (operation mode 2) and as SCL6 when it is
used in an I2C (operation mode 4).
7
D3
-
-
10
E3
6
-
Function description
Multi-function serial interface ch.4 input pin
Multi-function serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA4 when it is used in an I2C (operation mode 4).
Multi-function serial interface ch.4 clock I/O pin.
This pin operates as SCK4 when it is used in a
CSIO (operation mode 2) and as SCL4 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.4 RTS output pin
Multi-function serial interface ch.4 CTS input pin
Multi-function serial interface ch.5 input pin
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA5 when it is used in an I2C (operation mode 4).
Multi-function serial interface ch.5 clock I/O pin.
This pin operates as SCK5 when it is used in a
CSIO (operation mode 2) and as SCL5 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.6 input pin
Document Number: 002-05649 Rev. *D
LQFP-80
Page 29 of 108
MB9B520M Series
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-48
QFN-48
35
K8
27
-
34
J7
26
-
33
K7
25
-
13
G3
9
5
75
B4
59
43
43
55
J10
E10
35
-
26
-
44
J8
36
27
56
E9
-
-
IC02_2
46
H9
38
29
IC03_2
47
G10
39
30
Pin function
Pin name
Multifunction Serial
7
SIN7_1
SOT7_1
(SDA7_1)
SCK7_1
(SCL7_1)
Multifunction Timer
0
DTTI0X_0
DTTI0X_2
FRCK0_2
IC00_1
Function description
Multi-function serial interface ch.7 input pin
Multi-function serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA7 when it is used in an I2C (operation mode 4).
Multi-function serial interface ch.7 clock I/O pin.
This pin operates as SCK7 when it is used in a CSIO
(operation mode 2) and as SCL7 when it is used in
an I2C (operation mode 4).
Input signal of waveform generator to control outputs
RTO00 to RTO05 of Multi-function timer 0.
16-bit free-run timer ch.0 external clock input pin
IC00_2
IC01_1
16-bit input capture input pin of Multi-function timer 0.
ICxx describes channel number.
LQFP-80
RTO00_0
(PPG00_0)
Waveform generator output pin of Multi-function
timer 0.
This pin operates as PPG00 when it is used in PPG0
output mode.
14
H1
10
6
RTO01_0
(PPG00_0)
Waveform generator output pin of Multi-function
timer 0.
This pin operates as PPG00 when it is used in PPG0
output mode.
15
H2
11
7
RTO02_0
(PPG02_0)
Waveform generator output pin of Multi-function
timer 0.
This pin operates as PPG02 when it is used in PPG0
output mode.
16
H3
12
8
RTO03_0
(PPG02_0)
Waveform generator output pin of Multi-function
timer 0.
This pin operates as PPG02 when it is used in PPG0
output mode.
17
J1
13
9
RTO04_0
(PPG04_0)
Waveform generator output pin of Multi-function
timer 0.
This pin operates as PPG04 when it is used in PPG0
output mode.
18
J2
14
10
RTO05_0
(PPG04_0)
Waveform generator output pin of Multi-function
timer 0.
This pin operates as PPG04 when it is used in PPG0
output mode.
19
J4
15
11
IGTRG_0
IGTRG_1
PPG IGBT mode external trigger input pin
32
76
L7
C4
24
60
44
Document Number: 002-05649 Rev. *D
Page 30 of 108
MB9B520M Series
Pin function
Pin name
Quadrature Position/
Revolution Counter 0
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_1
AIN1_2
BIN1_1
BIN1_2
ZIN1_1
ZIN1_2
UDM0
UDP0
UHCONX
TX1_2
RX1_2
RTCCO_0
RTCCO_2
SUBOUT_0
SUBOUT_2
WKUP0
WKUP1
WKUP2
WKUP3
DA0
DA1
Quadrature Position/
Revolution Counter 1
USB
CAN
Real-time clock
Low-Power
Consumption
Mode
DAC
Reset
INITX
Document Number: 002-05649 Rev. *D
Function description
QPRC ch.0 AIN input pin
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
USB device/host D – pin
USB device/host D + pin
USB external pull-up control pin
CAN interface TX output pin
CAN interface RX input pin
0.5 seconds pulse output pin of Real-time
clock
Sub clock output pin
Deep standby mode return signal input pin 0
Deep standby mode return signal input pin 1
Deep standby mode return signal input pin 2
Deep standby mode return signal input pin 3
D/A converter ch.0 analog output pin
D/A converter ch.1 analog output pin
External Reset Input pin.
A reset is valid when INITX="L".
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-48
QFN-48
9
30
2
10
31
3
11
32
4
60
33
59
34
58
35
78
79
75
44
43
72
14
72
14
72
43
59
76
30
31
E2
K6
C1
E3
J6
C2
G1
L7
B3
C10
K7
C11
J7
D9
K8
A3
A2
B4
J8
J10
A6
H1
A6
H1
A6
J10
C11
C4
K6
J6
5
22
2
6
23
3
7
24
4
25
26
27
62
63
59
36
35
57
10
57
10
57
35
48
60
22
23
2
3
4
46
47
43
27
26
42
6
42
6
42
26
36
44
18
19
28
K4
21
17
LQFP-80
Page 31 of 108
MB9B520M Series
Pin function
Pin name
Mode
MD0
MD1
Power
GND
Clock
Analog
Power
VCC
VCC
VCC
USBVCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
X0
X0A
X1
X1A
CROUT_0
CROUT_1
AVCC
AVRH
Analog
GND
C pin
AVSS
AVRL
C
Function description
Mode 0 pin.
During normal operation, MD0="L" must be input.
During serial programming to Flash memory,
MD0="H" must be input.
Mode 1 pin.
During serial programming to Flash memory,
MD1="L" must be input.
Power supply Pin
Power supply Pin
Power supply Pin
3.3V Power supply port for USB I/O
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc clock output port
A/D converter and D/A converter
analog power supply pin
A/D converter analog reference voltage input pin
A/D converter and D/A converter
GND pin
A/D converter analog reference voltage input pin
Power supply stabilization capacity pin
Pin No
LQFP-64
BGA-96
QFN-64
LQFP-48
QFN-48
37
L8
29
21
36
K9
28
20
1
25
41
77
20
24
40
80
38
26
39
27
60
72
B1
K1
K11
A4
F1
F2
F3
B2
L1
K2
J3
L6
L4
L11
K10
J9
B10
C9
D11
A11
A7
C3
A5
A1
L9
L3
L10
K3
C10
A6
1
18
33
61
16
32
64
30
19
31
20
57
1
14
45
12
24
48
22
15
23
16
42
50
H11
41
31
51
F11
42
32
45
H10
37
28
52
23
G11
L2
43
17
33
13
LQFP-80
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-05649 Rev. *D
Page 32 of 108
MB9B520M Series
5. I/O Circuit Type
Type
A
Circuit
Remarks
It is possible to select the main
oscillation / GPIO function
Pull-up
When the main oscillation is selected.
resistor
P-ch
P-ch
Digital output
X1A
• Oscillation feedback resistor
: Approximately 1 MΩ
• With Standby mode control
When the GPIO is selected.
N-ch
Digital output
R
Pull-up resistor control
•
•
•
•
•
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
• CMOS level hysteresis input
• Pull-up resistor
: Approximately 50 kΩ
B
Pull-up resistor
Digital input
Document Number: 002-05649 Rev. *D
Page 33 of 108
MB9B520M Series
Type
C
Circuit
Remarks
Digital input
• Open drain output
• CMOS level hysteresis input
Digital output
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
When the sub oscillation is selected.
resistor
P-ch
P-ch
Digital output
X1A
• Oscillation feedback resistor
: Approximately 5 MΩ
• With Standby mode control
When the GPIO is selected.
N-ch
Digital output
R
Pull-up resistor control
•
•
•
•
•
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
Document Number: 002-05649 Rev. *D
Page 34 of 108
MB9B520M Series
Type
E
Circuit
Remarks
•
•
•
•
•
P-ch
P-ch
N-ch
Digital output
Digital output
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
• +B input is available
R
Pull-up resistor control
Digital input
Standby mode control
F
P-ch
P-ch
N-ch
R
Digital output
Digital output
•
•
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
• +B input is available
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
Document Number: 002-05649 Rev. *D
Page 35 of 108
MB9B520M Series
Type
G
Circuit
Remarks
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH= -12 mA, IOL= 12 mA
• +B input is available
P-ch
P-ch
Digital output
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
H
It is possible to select the USB I/O /
GPIO function.
GPIO Digital output
GPIO Digital input/output direction
When the USB I/O is selected.
GPIO Digital input
• Full-speed, Low-speed control
GPIO Digital input circuit control
When the GPIO is selected.
UDP output
UDP0/P81
USB Full-speed/Low-speed control
UDP input
Differential
UDM0/P80
• CMOS level output
• CMOS level hysteresis input
• With standby mode control
Differential input
USB/GPIO select
UDM input
UDM output
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
Document Number: 002-05649 Rev. *D
Page 36 of 108
MB9B520M Series
Type
I
Circuit
P-ch
P-ch
N-ch
Remarks
Digital output
Digital output
R
•
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
5 V tolerant
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• Available to control PZR registers.
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
Pull-up resistor control
Digital input
Standby mode control
J
P-ch
P-ch
N-ch
R
Digital output
Digital output
•
•
•
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With input control
Analog input
5 V tolerant
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• Available to control PZR registers.
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
CMOS level hysteresis input
K
Mode input
Document Number: 002-05649 Rev. *D
Page 37 of 108
MB9B520M Series
Type
L
Circuit
P-ch
R
P-ch
Digital output
N-ch
Digital output
Remarks
•
•
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With input control
Analog output
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
Pull-up resistor control
Digital input
Standby mode Control
Analog output
Document Number: 002-05649 Rev. *D
Page 38 of 108
MB9B520M Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-05649 Rev. *D
Page 39 of 108
MB9B520M Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-05649 Rev. *D
Page 40 of 108
MB9B520M Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level
of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-05649 Rev. *D
Page 41 of 108
MB9B520M Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and
GND pin, between AVCC pin and AVSS pin, between AVRH pin and AVRL pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions
is recommended for sub crystal oscillator to stabilize the oscillation.
• Surface mount type
Size:
More than 3.2 mm × 1.5 mm
Load capacitance: Approximately 6 pF to 7 pF
• Lead type
Load capacitance: Approximately 6 pF to 7 pF
Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3)
can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to
X0A. X1A (P47) can be used as a general-purpose I/O port.
• Example of Using an External Clock
Device
X0(X0A)
Can be used as
general-purpose
I/O ports.
Document Number: 002-05649 Rev. *D
X1(PE3),
X1A (P47)
Set as
External clock
input
Page 42 of 108
MB9B520M Series
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to
keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC → USBVCC
VCC → AVCC → AVRH
Turning off : AVRH → AVCC → VCC
USBVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash memory
products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash memory products and MASK products are different because chip
layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up function of 5 V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.
Document Number: 002-05649 Rev. *D
Page 43 of 108
MB9B520M Series
8. Block Diagram
MB9BF521K/L/M, F522K/L/M, F524K/L/M
TRSTX,TCK,
TDI,TMS
TDO
SRAM0
8/16 Kbytes
SWJ-DP
ROM Table
Multi-layer AHB (Max 72MHz)
Cortex-M3 Core I
@72MHz(Max)
D
NVIC
Sys
AHB-APB Bridge:
APB0(Max 40MHz)
Dual-Timer
WatchDog Timer
(Software)
INITX
Clock Reset
Generator
WatchDog Timer
(Hardware)
SRAM1
8/16 Kbytes
On-Chip Flash
64+32 Kbytes/
128+32 Kbytes/
256+32 Kbytes
Flash I/F
Security
USB2.0 PHY
(Host/
Device)
USBVCC
UDP0/UDM0
UHCONX
DMAC
8ch.
CSV
CLK
Main
Osc
Sub
Osc
PLL
CR
4MHz
Source Clock
AHB-AHB
Bridge
X0
X1
X0A
X1A
CR
100kHz
CROUT
ADTGx
DAx
TIOAx
TIOBx
AINx
BINx
ZINx
Unit 0
CAN Prescaler
Unit 1
USB Clock Ctrl
10-bit D/A Converter
2units
LVD Ctrl
LVD
IRQ-Monitor
Regulator
Base Timer
16-bit 8ch./
32-bit 4ch.
QPRC
2ch.
A/D Activation
Compare 2ch.
IC0x
FRCKx
16-bit Input Capture
4ch.
16-bit Free-run Timer
3ch.
16-bit Output
Compare 6ch.
DTTI0X
RTO0x
IGTRG_x
Waveform Generator
3ch.
16-bit PPG
3ch.
Multi-function Timer
AHB-APB Bridge : APB2 (Max 40MHz)
ANxx
TX1_2,
RX1_2
12-bit A/D Converter
AHB-APB Bridge : APB1 (Max 40MHz)
AVCC,
AVSS,
AVRH,
AVRL
CAN
PLL
Power-On
Reset
C
CRC
Accelerator
RTCCO_x,
SUBOUT_x
Real-Time Colck
Watch Counter
External Interrupt
Controller
16-pin + NMI
INTx
NMIX
MD0,
MD1
MODE-Ctrl
Deep Standby Ctrl
WKUPx
P0x,
P1x,
GPIO
PIN-Function-Ctrl
・
・
・
PFx
SCKx
Multi-Function Serial I/F
8ch.
(with FIFO ch.0/1/3/4)
HW flow control(ch.4)
SINx
SOTx
CTS4
RTS4
Document Number: 002-05649 Rev. *D
Page 44 of 108
MB9B520M Series
9. Memory Size
See “Memory size” in “Product Lineup” to confirm the memory size.
10. Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_4000
0x4006_3000
0x4006_1000
0x4006_0000
Reserved
0x4005_0000
0x4004_0000
0x4003_C000
0x7000_0000
0x6000_0000
0x4003_B000
External DeviceArea
0x4003_A000
0x4003_9000
0x4003_8000
Reserved
0x4400_0000
0x4200_0000
0x4000_0000
0x2400_0000
0x2200_0000
0x2008_0000
0x2000_0000
0x1FF8_0000
0x0020_8000
0x0020_0000
0x0010_4000
See " • Memory Map (2)"
for the memory size
details.
0x0010_0000
0x4003_7000
0x4003_6000
32Mbytes
Bit band alias
Peripherals
Reserved
32Mbytes
Bit band alias
Reserved
SRAM1
SRAM0
Reserved
Flash(Work area)
Reserved
Security/CR Trim
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
0x4002_9000
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
0x0000_0000
DMAC
Reserved
USB ch.0
Reserved
RTC
Watch Counter
CRC
MFS
CAN Prescaler
USB Clock Ctrl
LVD/DS mode
Reserved
GPIO
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
Reserved
D/AC
A/DC
QPRC
Base Timer
PPG
Reserved
0x4001_6000
0x4001_5000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
0x4000_1000
0x4000_0000
Document Number: 002-05649 Rev. *D
Reserved
0x4002_1000
0x4002_0000
Flash(Main area)
CAN ch.1
MFT unit0
Reserved
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
Page 45 of 108
MB9B520M Series
Memory Map (2)
MB9BF524K/L/M
MB9BF522K/L/M
0x2008_0000
MB9BF521K/L/M
0x2008_0000
Reserved
0x2008_0000
Reserved
Reserved
0x2000_4000
0x2000_2000
SRAM1
16Kbytes
0x2000_0000
0x2000_0000
SRAM0
16Kbytes
0x1FFF_E000
0x2000_2000
SRAM1
8Kbytes
SRAM0
8Kbytes
0x2000_0000
0x1FFF_E000
SRAM1
8Kbytes
SRAM0
8Kbytes
0x1FFF_C000
Reserved
Reserved
0x0020_0000
Reserved
0x0010_0000
0x0020_8000
0x0020_0000
Reserved
0x0010_4000
0x0010_2000
SA7(8KB)
SA6(8KB)
SA5(8KB)
SA4(8KB)
Reserved
0x0010_4000
CR trimming
Security
0x0010_2000
0x0010_0000
SA7(8KB)
SA6(8KB)
SA5(8KB)
SA4(8KB)
Flash(Work area)
32Kbytes
0x0020_8000
Flash(Work area)
32Kbytes
0x0020_0000
SA7(8KB)
SA6(8KB)
SA5(8KB)
SA4(8KB)
Flash(Work area)
32Kbytes
0x0020_8000
Reserved
0x0010_4000
CR trimming
Security
0x0010_2000
0x0010_0000
CR trimming
Security
Reserved
0x0004_0000
Reserved
SA11(64KB)
0x0002_0000
SA8(48KB)
0x0000_0000
SA3(8KB)
SA2(8KB)
SA8(48KB)
0x0000_0000
SA3(8KB)
SA2(8KB)
0x0001_0000
SA8(48KB)
0x0000_0000
SA3(8KB)
SA2(8KB)
Flash(Main area)
64Kbytes
SA9(64KB)
Flash(Main area)
128Kbytes
SA9(64KB)
Flash(Main area)
256Kbytes
SA10(64KB)
Reserved
Refer to the programming manual for the detail of Flash main area.
MB9AB40N/A40N/340N/140N/150R,MB9B520M/320M/120M Series Flash Programming Manual
Document Number: 002-05649 Rev. *D
Page 46 of 108
MB9B520M Series
Peripheral Address Map
Start address
End address
Bus
Peripherals
0x4000_0000
0x4000_0FFF
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function timer unit0
0x4002_1000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
Base Timer
0x4002_6000
0x4002_6FFF
0x4002_7000
0x4002_7FFF
0x4002_8000
0x4002_8FFF
D/A Converter
0x4002_9000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Built-in CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt
0x4003_1000
0x4003_1FFF
Interrupt Source Check Resister
0x4003_2000
0x4003_2FFF
Reserved
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_57FF
Low-Voltage Detector
0x4003_5800
0x4003_5FFF
0x4003_6000
0x4003_6FFF
0x4003_7000
0x4003_7FFF
CAN prescaler
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_BFFF
Real-time clock
0x4003_C000
0x4003_FFFF
Reserved
0x4004_0000
0x4004_FFFF
USB ch.0
0x4005_0000
0x4005_FFFF
Reserved
0x4006_0000
0x4006_0FFF
0x4006_1000
0x4006_2FFF
0x4006_3000
0x4006_3FFF
CAN ch.1
0x4006_4000
0x41FF_FFFF
Reserved
Document Number: 002-05649 Rev. *D
AHB
APB0
APB1
APB2
AHB
Flash Memory I/F register
Reserved
Software Watchdog timer
Reserved
Quadrature Position/Revolution Counter (QPRC)
A/D Converter
Deep standby mode Controller
USB clock generator
DMAC register
Reserved
Page 47 of 108
MB9B520M Series
11. Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the "L" level.
INITX=1
This is the period when the INITX pin is the "H" level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0".
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
Document Number: 002-05649 Rev. *D
Page 48 of 108
MB9B520M Series
Pin status type
List of Pin Status
A
Power-on
reset or
low-voltage
detection
state
INITX
input
state
Device
internal
reset
state
Run
mode or
SLEEP
mode
state
Timer mode,
RTC mode, or
STOP mode state
Deep standby
RTC mode or Deep
standby STOP mode
state
Return
from
Deep
standby
mode
state
Power
supply
stable
Power supply stable
Power supply stable
Power
supply
stable
INITX = 1
INITX = 1
INITX = 1
INITX = 1
Function
group
Power
supply
unstable
Power supply
stable
-
INITX = 0
-
-
INITX =
1
-
-
SPL = 0
SPL = 1
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
Main crystal
oscillator input
pin/
External main
clock input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state/Wh
en
oscillation
stops*1,
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state/Wh
en
oscillation
stops*1,
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
External main
clock input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Setting
disabled
B
SPL = 0
GPIO
selected
Internal
input
fixed at
"0"
SPL = 1
-
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Maintain
previous
state/Wh
en
oscillation
stops*1,
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state/Wh
en
oscillation
stops*1,
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Maintain
previous
state
Main crystal
oscillator output
pin
Hi-Z /
Internal input
fixed at "0"/
or Input
enable
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state/Whe
n
oscillation
stops*1,
Hi-Z /
Internal
input
fixed at
"0"
C
INITX
input pin
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
D
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Document Number: 002-05649 Rev. *D
Maintain
previous
state/Whe
n
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at "0"
Page 49 of 108
Pin status type
MB9B520M Series
Power-on
reset or
low-voltage
detection
state
INITX
input
state
Device
internal
reset
state
Timer mode,
RTC mode, or
STOP mode state
Deep standby
RTC mode or Deep
standby STOP mode
state
Return
from
Deep
standby
mode
state
Power
supply
stable
Power supply stable
Power supply stable
Power
supply
stable
INITX = 1
INITX = 1
INITX = 1
INITX = 1
Function
group
Power
supply
unstable
Power supply
stable
-
INITX = 0
-
-
INITX =
1
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
-
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
enabled
GPIO
selected
Hi-Z /
Input
enabled
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
E
F
Run
mode or
SLEEP
mode
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Sub crystal
oscillator input
pin /
External sub
clock input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
External sub
clock input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state/Wh
en
oscillation
stops*2,
Hi-Z /
Internal
input
fixed at
"0"
G
Sub crystal
oscillator output
pin
Hi-Z /
Internal input
fixed at "0"/
or Input
enable
Document Number: 002-05649 Rev. *D
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state/Wh
en
oscillation
stops*2,
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Maintain
previous
state/Wh
en
oscillation
stops*2,
Hi-Z/
Internal
input
fixed at
"0"
Hi-Z/
Internal
input
fixed at
"0"
Maintain
previous
state/Wh
en
oscillation
stops*2,
Hi-Z/
Internal
input
fixed at
"0"
Maintain
previous
state
Maintain
previous
state/Whe
n
oscillation
stops*2,
Hi-Z/
Internal
input fixed
at "0"
Page 50 of 108
Pin status type
MB9B520M Series
Power-on
reset or
low-voltage
detection
state
INITX
input
state
Device
internal
reset
state
Run
mode or
SLEEP
mode
state
Timer mode,
RTC mode, or
STOP mode state
Deep standby
RTC mode or Deep
standby STOP mode
state
Return
from
Deep
standby
mode
state
Power
supply
stable
Power supply stable
Power supply stable
Power
supply
stable
INITX = 1
INITX = 1
INITX = 1
INITX = 1
Function
group
Power
supply
unstable
External interrupt
enabled selected
GPIO
selected
Power supply
stable
-
INITX = 0
-
-
INITX =
1
-
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
-
Maintain
previous
state
Hi-Z /
Input
enabled
Maintain
previous
state
H
Setting
disabled
Setting
disabled
Setting
disabled
Analog input
selected
Hi-Z
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
NMIX selected
Setting
disabled
Setting
disabled
Setting
disabled
USB I/O pin
SPL = 0
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
Pull-up /
Input
enabled
Pull-up /
Input
enabled
GPIO
selected
JTAG
selected
J
GPIO
selected
Setting
disabled
Document Number: 002-05649 Rev. *D
Setting
disabled
Setting
disabled
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
SPL = 0
Maintain
previous
state
-
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Hi-Z at
transmission/
Input
enabled/
Internal
input
fixed at
"0" at
reception
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
disabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
disabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
disabled
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
Maintain
previous
state
Maintain
previous
state
SPL = 1
Hi-Z at
transmission/
Input
enabled/
Internal
input
fixed at
"0" at
reception
I
Resource other
than above
selected
SPL = 1
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Page 51 of 108
Pin status type
MB9B520M Series
Power-on
reset or
low-voltage
detection
state
INITX
input
state
Device
internal
reset
state
Run
mode or
SLEEP
mode
state
Timer mode,
RTC mode, or
STOP mode state
Deep standby
RTC mode or Deep
standby STOP mode
state
Return
from
Deep
standby
mode
state
Power
supply
stable
Power supply stable
Power supply stable
Power
supply
stable
INITX = 1
INITX = 1
INITX = 1
INITX = 1
Function
group
Power
supply
unstable
-
INITX = 0
-
-
Resource
selected
K
Power supply
stable
INITX =
1
-
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Maintain
previous
state
Analog output
selected
External interrupt
enabled selected
L
Resource other
than above
selected
Maintain
previous
state
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
*3
*4
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
M
Resource other
than above
selected
SPL = 1
Hi-Z
GPIO
selected
Analog input
selected
SPL = 0
Document Number: 002-05649 Rev. *D
SPL = 0
GPIO
selected
Internal
input
fixed at
"0"
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
GPIO
selected
Internal
input
fixed at
"0"
SPL = 1
-
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Page 52 of 108
Pin status type
MB9B520M Series
Power-on
reset or
low-voltage
detection
state
INITX
input
state
Device
internal
reset
state
Run
mode or
SLEEP
mode
state
Timer mode,
RTC mode, or
STOP mode state
Deep standby
RTC mode or Deep
standby STOP mode
state
Return
from
Deep
standby
mode
state
Power
supply
stable
Power supply stable
Power supply stable
Power
supply
stable
INITX = 1
INITX = 1
INITX = 1
INITX = 1
Function
group
Power
supply
unstable
Analog input
selected
Power supply
stable
-
INITX = 0
-
-
Hi-Z
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
INITX =
1
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
SPL = 0
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
N
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Maintain
previous
state
External interrupt
enabled selected
Resource other
than above
selected
SPL = 1
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
SPL = 0
SPL = 1
-
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
*1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and
Deep Standby Stop mode.
*2: Oscillation is stopped at Stop mode and Deep Standby Stop mode.
*3: Maintain previous state at Timer mode. GPIO selected Internal input fixed at "0" at RTC mode, Stop mode.
*4: Maintain previous state at Timer mode. Hi-Z/Internal input fixed at "0" at RTC mode, Stop mode.
Document Number: 002-05649 Rev. *D
Page 53 of 108
MB9B520M Series
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1, *2
Power supply voltage (for USB)*1, * 3
Analog power supply voltage*1, *4
Analog reference voltage*1, *4
VCC
USBVCC
AVCC
AVRH
Rating
Min
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
Input voltage*
1
VI
VSS - 0.5
VSS - 0.5
Analog pin input voltage*
1
VIA
VSS - 0.5
Output voltage*1
VO
VSS - 0.5
Clamp maximum current
Clamp total maximum current
ICLAMP
Σ[ICLAMP]
L level maximum output current*
5
IOL
-2
-
L level average output current*6
IOLAV
-
L level total maximum output current
L level total average output current*7
∑IOL
∑IOLAV
-
H level maximum output current*5
IOH
-
H level average output current*6
IOHAV
H level total maximum output current
∑IOH
∑IOHAV
PD
TSTG
H level total average output current*7
Power consumption
Storage temperature
- 55
Max
VSS + 6.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
VCC + 0.5
(≤ 6.5V)
USBVCC + 0.5
(≤ 6.5 V)
VSS + 6.5
AVCC + 0.5
(≤ 6.5 V)
VCC + 0.5
(≤ 6.5 V)
+2
+20
10
20
39
4
12
16.5
100
50
- 10
- 20
- 39
-4
- 12
- 18
- 100
- 50
300
+ 150
Unit
Remarks
V
V
V
V
V
Except for USB pin
V
USB pin
V
5 V tolerant
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
*8
*8
4 mA type
12 mA type
The pin doubled as USB I/O
4 mA type
12 mA type
The pin doubled as USB I/O
4 mA type
12 mA type
The pin doubled as USB I/O
4 mA type
12 mA type
The pin doubled as USB I/O
*1: These parameters are based on the condition that VSS = AVSS = 0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: USBVCC must not drop below VSS - 0.5 V.
*4: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on.
*5: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*6: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100
ms period.
*7: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms.
Document Number: 002-05649 Rev. *D
Page 54 of 108
MB9B520M Series
*8:
•
•
•
•
•
See “List of Pin Functions” and “I/O Circuit Type” about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does
not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.
• Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the
pins, so that incomplete operation may result.
• The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
P-ch
Limiting
+B input (0V to 16V)
resistor
N-ch
R
Digital output
Digital input
AVCC
Analog input
WARNING:
−
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-05649 Rev. *D
Page 55 of 108
MB9B520M Series
12.2 Recommended Operating Conditions
(VSS = AVSS = AVRL = 0.0V)
Parameter
Power supply voltage
Symbol
VCC
Conditions
-
Max
2.7*4
5.5
Unit
2.7
-
2.7
AVCC
V
-
AVSS
AVSS
V
-
1
10
μF
- 40
+ 105
°C
3.0
USBVCC
Analog power supply voltage
AVCC
-
AVRH
AVRL
Smoothing capacitor
CS
Operating temperature
TA
-
2.7
-
Remarks
V
3.6
(≤ VCC)
5.5
(≤ VCC)
5.5
Power supply voltage (3V power supply) for
USB
Analog reference voltage
Value
Min
*1
V
*2
V
AVCC = VCC
For Regulator*3
*1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0).
*2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80).
*3: See “C Pin” in “Handling Devices" for the connection of the smoothing capacitor.
*4: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction
execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is
possible to operate only.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or
combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to
contact their representatives beforehand.
Document Number: 002-05649 Rev. *D
Page 56 of 108
MB9B520M Series
12.3 DC Characteristics
12.3.1 Current Rating
(VCC = AVCC = USBVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Conditions
ICC
VCC
Sleep
mode
current
ICCS
Value
Max
Unit
Remarks
32.5
41
mA
*1, *5
CPU:72 MHz,
Peripheral clock stops
NOP operation
18
23
mA
*1, *5
High-speed
CR
Run mode
CPU/ Peripheral: 4 MHz*2
2.5
3.4
mA
*1
Sub
Run mode
CPU/ Peripheral: 32 kHz
110
980
µA
*1, *6
Low-speed
CR
Run mode
CPU/ Peripheral: 100 kHz
130
1030
µA
*1
Peripheral: 36 MHz
22
28
mA
*1, *5
Peripheral: 4 MHz*2
1.6
2.6
mA
*1
Peripheral: 32 kHz
96
955
µA
*1, *6
Peripheral: 100 kHz
115
975
µA
*1
PLL
Run mode
Run
mode
current
CPU: 72 MHz,
Peripheral: 36 MHz
Typ
PLL
Sleep mode
High-speed
CR
Sleep mode
Sub
Sleep mode
Low-speed
CR
Sleep mode
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=5.5 V
*4: TA=+105°C, VCC=5.5 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-05649 Rev. *D
Page 57 of 108
MB9B520M Series
(VCC = AVCC = USBVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Main
Timer mode
ICCT
Timer
mode
current
Sub
Timer mode
ICCT
RTC
mode
current
ICCR
Stop
mode
current
ICCH
Conditions
RTC mode
Stop mode
VCC
ICCRD
Deep Standby
RTC mode
Deep Standby
mode
current
ICCHD
Deep Standby
Stop mode
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off,
When RAM is off
TA = + 25°C,
When LVD is off,
When RAM is on
TA = + 105°C,
When LVD is off,
When RAM is off
TA = + 105°C,
When LVD is off,
When RAM is on
TA = + 25°C,
When LVD is off,
When RAM is off
TA = + 25°C,
When LVD is off,
When RAM is on
TA = + 105°C,
When LVD is off,
When RAM is off
TA = + 105°C,
When LVD is off,
When RAM is on
Value
Typ*2
Max*2
Unit
Remarks
4.1
4.8
mA
*1, *4
-
5.4
mA
*1, *4
17
66
μA
*1, *5
-
835
μA
*1, *5
15
61
μA
*1, *5
-
680
μA
*1, *5
14
53
μA
*1
-
600
μA
*1
2.2
11
μA
*1, *3, *5
6.2
23
μA
*1, *3, *5
155
μA
*1, *3, *5
215
μA
*1, *3, *5
1.6
9.6
μA
*1, *3
5.6
22
μA
*1, *3
150
μA
*1, *3
210
μA
*1, *3
-
-
*1: When all ports are fixed.
*2: VCC=5.5 V
*3: RAM on/off setting is on-chip SRAM only.
*4: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-05649 Rev. *D
Page 58 of 108
MB9B520M Series
Low-Voltage Detection Current
Parameter
Low-voltage detection
circuit (LVD) power
supply current
Symbol
ICCLVD
Pin
name
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Unit
Remarks
Typ
Max
Conditions
At operation
for reset
Vcc = 5.5 V
0.13
0.3
μA
At not detect
At operation
for interrupt
Vcc = 5.5 V
0.13
0.3
μA
At not detect
VCC
Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Flash memory
write/erase
current
Symbol
ICCFLASH
Pin
name
VCC
Value
Conditions
At Write/Erase
Typ
Max
9.5
11.2
Unit
mA
Remarks
*
*: The current at which to write or erase Flash memory, "I CCFLASH" is added to "ICC".
A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Power supply current
Reference power
supply current
Symbol
ICCAD
ICCAVRH
Pin
name
Value
Conditions
Unit
Typ
Max
At 1unit operation
0.69
0.90
mA
At stop
0.25
25.84
μA
At 1unit operation
AVRH=5.5 V
1.1
1.97
mA
At stop
0.2
3.4
μA
Remarks
AVCC
AVRH
D/A Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Power supply
current*1
Symbol
Pin
name
IDDA*2
AVCC
IDSA
Conditions
At 1unit
operation
AVCC=3.3 V
At 1unit
operation
AVCC=5.0 V
At stop
Min
Value
Typ
Max
250
315
380
μA
380
475
580
μA
-
-
16
μA
Unit
Remarks
*1: No-load
*2: Generates the max current by the CODE about 0x200
Document Number: 002-05649 Rev. *D
Page 59 of 108
MB9B520M Series
12.3.2 Pin Characteristics
(VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
H level input
voltage
(hysteresis
input)
VIHS
L level input
voltage
(hysteresis
input)
VILS
Pin name
CMOS
hysteresis
input pin,
MD0, MD1
5 V tolerant
input pin
CMOS
hysteresis
input pin,
MD0, MD1
5 V tolerant
input pin
4 mA type
H level
output voltage
VOH
12 mA type
The pin
doubled as
USB I/O
4 mA type
L level
output voltage
VOL
12 mA type
The pin
doubled as
USB I/O
Input leak current
IIL
-
Pull-up resistance
value
RPU
Pull-up pin
Input capacitance
CIN
Other than
VCC,
USBVCC,
VSS,
AVCC,
AVSS,
AVRH,
AVRL
Document Number: 002-05649 Rev. *D
Conditions
Min
Value
Typ
Max
Unit
-
VCC × 0.8
-
VCC + 0.3
V
-
VCC × 0.8
-
VSS + 5.5
V
-
VSS - 0.3
-
VCC × 0.2
V
-
VSS - 0.3
-
VCC × 0.2
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
USBVCC - 0.4
-
USBVCC
V
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
-5
-
+5
μA
VCC ≥ 4.5 V
33
50
90
VCC < 4.5 V
-
-
180
-
-
5
15
VCC ≥ 4.5 V,
IOH = - 4 mA
VCC < 4.5 V,
IOH = - 2 mA
VCC ≥ 4.5 V,
IOH = - 12 mA
VCC < 4.5 V,
IOH = - 8 mA
USBVCC ≥ 4.5 V,
IOH = - 18.0 mA
USBVCC < 4.5 V,
IOH = - 12.0 mA
VCC ≥ 4.5 V,
IOL = 4 mA
VCC < 4.5 V,
IOL = 2 mA
VCC ≥ 4.5 V,
IOL = 12 mA
VCC < 4.5 V,
IOL = 8 mA
USBVCC ≥ 4.5 V,
IOL = 16.5 mA
USBVCC < 4.5 V,
IOL = 10.5 mA
-
Remarks
kΩ
pF
Page 60 of 108
MB9B520M Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input frequency
Value
Unit
Remarks
Max
4
4
4
4
20.83
50
48
20
48
20
250
250
45
55
%
-
-
5
ns
-
-
-
72
MHz
Master clock
fCC
fCP0
fCP1
fCP2
-
-
-
-
-
72
40
40
40
MHz
MHz
MHz
MHz
Base clock (HCLK/FCLK)
-
tCYCC
tCYCP0
tCYCP1
tCYCP2
-
-
-
-
-
-
-
ns
ns
ns
ns
Base clock (HCLK/FCLK)
-
13.8
25
25
25
fCH
tCYLH
Input clock pulse width
-
Input clock rising time and
falling time
tCF,
tCR
fCM
Internal operating
clock cycle time*1
Conditions
Min
Input clock cycle
Internal operating
clock frequency*1
Pin
name
Symbol
X0,
X1
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
PWH/tCYLH,
PWL/tCYLH
MHz
When crystal oscillator is
connected
MHz
When using external
Clock
ns
When using external
Clock
When using external
Clock
When using external
Clock
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
*1: For more information about each internal operating clock, see “Chapter: Clock” in “FM3 Family Peripheral Manual”.
*2: For about each APB bus which each peripheral is connected to, see “Block Diagram” in this datasheet.
X0
Document Number: 002-05649 Rev. *D
Page 61 of 108
MB9B520M Series
12.4.2 Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Input frequency
1/ tCYLL
Input clock cycle
tCYLL
Input clock pulse width
-
Pin
name
X0A,
X1A
Value
Conditions
Min
Typ
Max
Unit
Remarks
-
-
32.768
-
kHz
-
32
-
100
kHz
When crystal oscillator is
connected
When using external clock
-
10
-
31.25
μs
When using external clock
PWH/tCYLL,
PWL/tCYLL
45
-
55
%
When using external clock
*: See “Sub crystal oscillator” in “Handling Devices” for the crystal oscillator used.
X0A
Document Number: 002-05649 Rev. *D
Page 62 of 108
MB9B520M Series
12.4.3 Built-in CR Oscillation Characteristics
Built-in High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
fCRH
Value
Conditions
Min
Typ
Max
TA = + 25°C
3.92
4
4.08
TA = 0°C to + 85°C
3.9
4
4.1
TA = -40°C to + 105°C
3.88
4
4.12
TA = + 25°C
VCC ≤ 3.6 V
TA = - 20°C ~ + 85°C
VCC ≤ 3.6 V
TA = - 20°C ~ + 105°C
VCC ≤ 3.6 V
3.94
4
4.06
3.92
4
4.08
3.9
4
4.1
2.8
4
5.2
-
-
30
TA = - 40°C to + 105°C
Frequency stabilization
time
tCRWT
-
Unit
Remarks
When trimming*1
MHz
When not trimming
μs
*2
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming.
*2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value.
This period is able to use high-speed CR clock as source clock.
Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
fCRL
Document Number: 002-05649 Rev. *D
Conditions
-
Value
Min
Typ
Max
50
100
150
Unit
Remarks
kHz
Page 63 of 108
MB9B520M Series
12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
PLL oscillation stabilization wait time*1
(LOCK UP time)
PLL input clock frequency
PLL multiplication rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
USB clock frequency*3
Symbol
Value
Unit
Remarks
Min
Typ
Max
tLOCK
100
-
-
μs
fPLLI
4
5
75
-
-
16
37
150
72
48
MHz
multiplier
MHz
MHz
MHz
-
fPLLO
fCLKPLL
fCLKSPLL
After the M frequency division
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see “Chapter 2-1: Clock” in “FM3 Family Peripheral Manual”.
*3: For more information about USB clock, see “Chapter 2-2: USB Clock Generation” in “FM3 Family Peripheral Manual
Communication Macro Part”.
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of Main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
PLL oscillation stabilization wait time*1
(LOCK UP time)
Symbol
tLOCK
Value
Typ
Max
100
-
-
μs
4.2
35
150
72
MHz
multiplier
MHz
MHz
3.8
4
19
fPLLO
72
Main PLL clock frequency*2
fCLKPLL
*1: Time from when the PLL starts operating until the oscillation stabilizes.
PLL input clock frequency
PLL multiplication rate
PLL macro oscillation clock frequency
Unit
Min
fPLLI
-
Remarks
*2: For more information about Main PLL clock (CLKPLL), see “Chapter 2-1: Clock” in “FM3 Family Peripheral Manual”.
Note:
−
Make sure to input to the Main PLL source clock, the high-speed CR clock (CLKHC) that the frequency/temperature has been
trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the
master clock from exceeding the maximum frequency.
Main PLL connection
K
divider
PLL input
clock
PLL macro
oscillation clock
Main
PLL
M
divider
Main PLL
clock
(CLKPLL)
N
divider
Document Number: 002-05649 Rev. *D
Page 64 of 108
MB9B520M Series
USB PLL connection
Main clock (CLKMO)
K
divider
PLL input
clock
PLL macro
oscillation clock
M
divider
USB PLL
USB
clock
N
divider
12.4.6 Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Reset input time
Symbol
Pin name
tINITX
INITX
Conditions
-
Value
Min
Max
500
-
Unit
Remarks
ns
12.4.7 Power-on Reset Timing
(VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Power supply shut down time
tOFF
Power ramp rate
dV/dt
Pin
name
VCC
Conditions
Value
Unit
Remarks
Min
Typ
Max
-
1
-
-
ms
*1
VCC: 0.2 V to 2.70 V
0.3
-
1000
mV/µs
*2
Time until releasing Power-on reset
tPRT
1.34
18.6
ms
*1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1 ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12.4.6.
2.7V
VCC
VDH
0.2V
dV/dt
0.2V
tPRT
Internal RST
RST Active
CPU Operation
0.2V
tOFF
release
start
Glossary
• VDH: detection voltage (when SVHR=00000) of Low-Voltage detection reset. See "12.8. Low-Voltage Detection
Characteristics".
Document Number: 002-05649 Rev. *D
Page 65 of 108
MB9B520M Series
12.4.8 Base Timer Input Timing
Timer input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
TIOAn/TIOBn
(when using as ECK,
TIN)
tTIWH,
tTIWL
-
tTIWH
Value
Min
Max
2tCYCP
-
Unit
Remarks
ns
tTIWL
ECK
VIHS
TIN
VIHS
VILS
VILS
Trigger input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
tTRGH,
tTRGL
Pin name
TIOAn/TIOBn
(when using as
TGIN)
Conditions
-
tTRGH
TGIN
VIHS
Value
Min
Max
2tCYCP
-
Unit
Remarks
ns
tTRGL
VIHS
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see “Block Diagram” in this data sheet.
Document Number: 002-05649 Rev. *D
Page 66 of 108
MB9B520M Series
12.4.9 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Baud rate
Serial clock cycle time
-
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
tSCYC
Pin
name
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
VCC < 4.5 V
Min
Max
8
4tCYCP
-
Conditions
-
VCC ≥ 4.5 V
Min
Max
8
4tCYCP
-
Unit
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Master mode
Slave mode
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
−
−
−
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “Block Diagram” in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05649 Rev. *D
Page 67 of 108
MB9B520M Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
SOT
VOL
tIVSHI
SIN
tSHIXI
VIH
VIH
VIL
VIL
Master mode
tSLSH
SCK
tSHSL
VIH
VIH
tF
VIL
VIL
VIH
tR
tSLOVE
SOT
VOH
VOL
tIVSHE
SIN
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
Document Number: 002-05649 Rev. *D
Page 68 of 108
MB9B520M Series
CSIO (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Baud rate
Serial clock cycle time
-
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK falling time
SCK rising time
tF
tR
tSCYC
Pin
name
SCKx
VCC < 4.5 V
Min
Max
8
4tCYCP
-
Conditions
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
VCC ≥ 4.5 V
Min
Max
8
4tCYCP
-
Unit
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Master mode
Slave mode
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
−
−
−
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “Block Diagram” in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05649 Rev. *D
Page 69 of 108
MB9B520M Series
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
SOT
VOL
tIVSLI
SIN
tSLIXI
VIH
VIH
VIL
VIL
Master mode
tSHSL
SCK
tSLSH
VIH
VIH
VIL
tR
tF
VIL
VIL
tSHOVE
SOT
VOH
VOL
tIVSLE
SIN
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-05649 Rev. *D
Page 70 of 108
MB9B520M Series
CSIO (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Baud rate
Serial clock cycle time
-
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓→ SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓→ SIN hold time
tSLIXE
SCK falling time
SCK rising time
tF
tR
tSCYC
Pin
name
SCKx
VCC < 4.5 V
Min
Max
8
4tCYCP
-
Conditions
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
VCC ≥ 4.5 V
Min
Max
8
4tCYCP
-
Unit
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Master mode
Slave mode
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
−
−
tCYCP indicates the APB bus clock cycle time.
−
−
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
About the APB bus number which Multi-function serial is connected to, see “Block Diagram” in this data sheet.
These characteristics only guarantee the same relocate port number.
When the external load capacitance CL = 30 pF.
Document Number: 002-05649 Rev. *D
Page 71 of 108
MB9B520M Series
tSCYC
VOH
SCK
VOL
VOH
VOL
SOT
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
VIH
SCK
tR
VOH
VOL
tIVSLE
SIN
VIL
tF
*
SOT
VIL
tSHSL
VIH
VIH
tSHOVE
VOH
VOL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-05649 Rev. *D
Page 72 of 108
MB9B520M Series
CSIO (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Baud rate
Serial clock cycle time
-
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
tSCYC
Pin
name
SCKx
VCC < 4.5 V
Min
Max
8
4tCYCP
-
Conditions
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
VCC ≥ 4.5 V
Min
Max
8
4tCYCP
-
Unit
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Master mode
Slave mode
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
−
−
−
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “Block Diagram” in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05649 Rev. *D
Page 73 of 108
MB9B520M Series
tSCYC
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
Master mode
tR
tF
tSHSL
SCK
tSLSH
VIH
VIH
VIL
VIL
VIL
tSLOVE
VOH
VOL
SOT
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Serial clock L pulse width
Serial clock H pulse width
SCK falling time
SCK rising time
Symbol
tSLSH
tSHSL
tF
tR
Conditions
CL = 30 pF
Min
Max
Unit
tCYCP + 10
tCYCP + 10
5
5
ns
ns
ns
ns
-
tR
tF
tSHSL
SCK
Document Number: 002-05649 Rev. *D
VIL
Remarks
VIH
tSLSH
VIH
VIL
VIL
Page 74 of 108
MB9B520M Series
12.4.10 External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
Unit
ADTG
Input pulse width
tINH,
tINL
FRCKx
ICxx
DTTIxX
INTxx,
NMIX
WKUPx
Remarks
A/D converter trigger input
-
*2
*3
*4
2tCYCP*1
-
ns
2tCYCP*1
2tCYCP + 100*1
-
ns
ns
ns
ns
500
500
Free-run timer input clock
Input capture
Waveform generator
External interrupt
NMI
Deep standby wake up
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see
“Block Diagram” in this data sheet.
*2: When in Run mode, in Sleep mode.
*3: When in Stop mode, in RTL mode, in Timer mode.
*4: When in Deep Standby RTC mode, in Deep Standby Stop mode.
Document Number: 002-05649 Rev. *D
Page 75 of 108
MB9B520M Series
12.4.11 Quadrature Position/Revolution Counter timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
AIN pin H width
AIN pin L width
BIN pin H width
BIN pin L width
BIN rising time from
AIN pin H level
AIN falling time from
BIN pin H level
BIN falling time from
AIN pin L level
AIN rising time from
BIN pin L level
AIN rising time from
BIN pin H level
BIN falling time from
AIN pin H level
AIN falling time from
BIN pin L level
BIN rising time from
AIN pin L level
ZIN pin H width
ZIN pin L width
AIN/BIN rising and falling time from
determined ZIN level
Determined ZIN level from AIN/BIN
rising and falling time
Value
Conditions
tAHL
tALL
tBHL
tBLL
-
tAUBU
PC_Mode2 or PC_Mode3
tBUAD
PC_Mode2 or PC_Mode3
tADBD
PC_Mode2 or PC_Mode3
tBDAU
PC_Mode2 or PC_Mode3
tBUAU
PC_Mode2 or PC_Mode3
tAUBD
PC_Mode2 or PC_Mode3
tBDAD
PC_Mode2 or PC_Mode3
tADBU
PC_Mode2 or PC_Mode3
tZHL
tZLL
QCR:CGSC=0
QCR:CGSC=0
tZABE
QCR:CGSC=1
tABEZ
QCR:CGSC=1
Min
Max
2tCYCP*
-
Unit
ns
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see “Block Diagram” in this data
sheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
Document Number: 002-05649 Rev. *D
tBLL
Page 76 of 108
MB9B520M Series
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-05649 Rev. *D
Page 77 of 108
MB9B520M Series
12.4.12 I2C Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
SCL clock frequency
fSCL
Standardmode
Min
Max
0
100
(Repeated) START condition hold
time
SDA ↓ → SCL ↓
tHDSTA
4.0
-
0.6
-
μs
tLOW
tHIGH
4.7
4.0
-
1.3
0.6
-
μs
μs
4.7
-
0.6
-
μs
0
3.45*2
0
0.9*3
μs
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
2tCYCP*4
-
2tCYCP*4
-
ns
Parameter
SCL clock L width
SCL clock H width
(Repeated) START condition setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
Bus free time between
STOP condition and
START condition
Noise filter
Symbol
Conditions
tSUSTA
tHDDAT
tSP
CL = 30 pF,
R = (VP/IOL)*1
-
Fastmode
Min
Max
0
400
Unit
Remarks
kHz
*1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast mode I2C bus device can be used on a Standard mode I2C bus system as long as the device satisfies the requirement of
"tSUDAT ≥ 250 ns".
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see “Block Diagram” in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-05649 Rev. *D
Page 78 of 108
MB9B520M Series
12.4.13 JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin name
TMS, TDI setup time
tJTAGS
TCK,
TMS, TDI
TMS, TDI hold time
tJTAGH
TCK,
TMS, TDI
TDO delay time
tJTAGD
TCK,
TDO
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
Value
Unit
Min
Max
15
-
ns
15
-
ns
-
25
-
45
Remarks
ns
Note:
−
When the external load capacitance CL = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-05649 Rev. *D
Page 79 of 108
MB9B520M Series
12.5 12-bit A/D Converter
Electrical characteristics for the A/D converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Pin
name
Symbol
Min
0.8*1
1.0*1
0.24
0.3
40
Value
Typ
± 1.5
± 1.7
± 10
AVRH ± 5
-
50
-
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition voltage
-
VZT
VFST
ANxx
ANxx
Conversion time
-
-
Sampling time*2
tS
-
Compare clock cycle*3
tCCK
-
State transition time to operation
permission
tSTT
-
-
Analog input capacity
CAIN
-
Analog input resistor
RAIN
-
Max
12
± 4.5
± 2.5
± 15
AVRH ± 15
-
-
bit
LSB
LSB
mV
mV
μs
10
μs
1000
ns
-
1.0
μs
-
-
9.7
pF
-
-
1.7
2.4
4
5
AVRH
AVCC
AVSS
kΩ
Analog input voltage
ANxx
AVRL
AVRH
2.7
Reference voltage
AVRL
AVSS
*1: The conversion time is the value of sampling time (t S) + compare time (tC).
Interchannel disparity
Analog port input leak current
Unit
ANxx
Remarks
AVRH = 2.7 V to 5.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
LSB
μA
V
V
V
The condition of the minimum conversion time is the following.
AVCC ≥ 4.5 V, HCLK=50 MHz
AVCC < 4.5 V, HCLK=40 MHz
sampling time: 240 ns, compare time: 560 ns
sampling time: 300 ns, compare time: 700 ns
Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).
For setting of the sampling time and compare clock cycle, see "Chapter 1-1: A/D Converter" in “FM3 Family Peripheral Manual
Analog Macro Part”.
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing.
For the number of the APB bus to which the A/D Converter is connected, see "Block Diagram".
The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: A necessary sampling time changes by external impedance.
Ensure that it sets the sampling time to satisfy (Equation 1).
*3: The compare time (tC) is the value of (Equation 2).
Document Number: 002-05649 Rev. *D
Page 80 of 108
MB9B520M Series
Analog signal
source
REXT
ANxx
Analog input pin
Comparator
RAIN
CAIN
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9
tS:
Sampling time
RAIN:
Input resistor of A/D = 1.5 kΩ at 4.5 V < AVCC < 5.5 V ch.0 to ch.7
Input resistor of A/D = 1.6 kΩ at 4.5 V < AVCC < 5.5 V ch.8 to ch.15
Input resistor of A/D = 1.7 kΩ at 4.5 V < AVCC < 5.5 V ch.16 to ch.26
Input resistor of A/D = 2.2 kΩ at 2.7 V < AVCC < 4.5 V ch.0 to ch.7
Input resistor of A/D = 2.3 kΩ at 2.7 V < AVCC < 4.5 V ch.8 to ch.15
Input resistor of A/D = 2.4 kΩ at 2.7 V < AVCC < 4.5 V ch.16 to ch.26
CAIN:
Input capacity of A/D = 9.7 pF at 2.7 V < AVCC < 5.5 V
REXT:
Output impedance of external circuit
(Equation 2) tC = tCCK × 14
tC:
Compare time
tCCK:
Compare clock cycle
Document Number: 002-05649 Rev. *D
Page 81 of 108
MB9B520M Series
12.5.1 Definition of 12-bit A/D Converter Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Integral Nonlinearity:
Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001)
and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual
conversion characteristics.
Differential Nonlinearity:
Deviation from the ideal value of the input voltage that is required to change the output code
by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actually-measured
value)
0x003
0x002
(Actuallymeasured
value)
Digital output
Digital output
0xFFD
Ideal characteristics
0xN
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
AVRL
Actual conversion characteristics
AVRH
AVRL
AVRH
Analog input
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VZT
4094
N:
A/D converter digital output value.
VZT:
Voltage at which the digital output changes from 0x000 to 0x001.
VFST:
Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT:
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-05649 Rev. *D
Page 82 of 108
MB9B520M Series
12.6 10-bit D/A Converter
Electrical Characteristics for the D/A Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Resolution
Conversion time
Symbol
Pin name
tC20
tC100
Integral Nonlinearity*1
INL
Differential Nonlinearity*1,*2
DNL
Output Voltage offset
VOFF
Analog output impedance
RO
Output undefined period
tR
DAx
Min
0.47
2.37
- 4.0
- 0.9
- 20.0
3.10
2.0
-
Value
Typ
0.58
2.90
3.80
-
Max
10
0.69
3.43
+ 4.0
+ 0.9
10.0
+ 5.4
4.50
70
Unit
bit
μs
μs
LSB
LSB
mV
mV
kΩ
MΩ
ns
Remarks
Load 20 pF
Load 100 pF
Code is 0x000
Code is 0x3FF
D/A operation
D/A stop
*1: No-load
*2: Generates the max current by the CODE about 0x200
Document Number: 002-05649 Rev. *D
Page 83 of 108
MB9B520M Series
12.7 USB Characteristics
(VCC = 2.7V to 5.5V, USBVCC = 3.0V to 3.6V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Conditions
Value
Min
Max
Unit
Remarks
VIH
-
2.0
USBVCC + 0.3
V
*1
VIL
-
VSS - 0.3
0.8
V
*1
VDI
-
0.2
-
V
*2
Different common mode range
VCM
-
0.8
2.5
V
*2
Output H level voltage
VOH
2.8
3.6
V
*3
Output L level voltage
VOL
0.0
0.3
V
*3
1.3
4
4
90
28
75
75
80
2.0
20
20
111.11
44
300
300
125
V
ns
ns
%
Ω
ns
ns
%
*4
*5
*5
*5
*6
*7
*7
*7
Input H level voltage
Input
Input L level voltage
characterisDifferential input sensitivity
tics
Output
Crossover voltage
characteris- Rising time
tics
Falling time
Rising/falling time matching
Output impedance
Rising time
Falling time
Rising/falling time matching
VCRS
tFR
tFF
tFRFM
ZDRV
tLR
tLF
tLRFM
UDP0,
UDM0
External
pull-down
resistor = 15 kΩ
External pull-up
resistor = 1.5
kΩ
Full-Speed
Full-Speed
Full-Speed
Full-Speed
Low-Speed
Low-Speed
Low-Speed
*1: The switching threshold voltage of the Single-End-Receiver of USB I/O buffer is set as within VIL
(Max) = 0.8V, VIH (Min) = 2.0 V (TTL input standard).
There are some hysteresis to lower noise sensitivity.
Minimum differential input
sensitivity [V]
*2: Use the differential-Receiver to receive the USB differential data signal.
The Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the
local ground reference level.
The voltage range above is said to be the common mode input voltage range.
Common mode input voltage [V]
Document Number: 002-05649 Rev. *D
Page 84 of 108
MB9B520M Series
*3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to
ground and 15 kΩ load) at High-State (VOH).
*4: The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to 2.0 V.
VCRS specified range
*5: They indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.
Rising time
Document Number: 002-05649 Rev. *D
Falling time
Page 85 of 108
MB9B520M Series
*6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic impedance
(Differential Mode).
USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series resistor
(Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) Series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistor.
Rs series resistor 25Ω to 30Ω
Series resistor of 27Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence".
*7: They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
Rising time
Falling time
See "Low-Speed Load (Compliance Load)" for conditions of the external load.
Document Number: 002-05649 Rev. *D
Page 86 of 108
MB9B520M Series
Low-Speed Load (Upstream Port Load) - Reference 1
CL = 50pF to 150pF
CL = 50pF to 150pF
Low-Speed Load (Downstream Port Load) - Reference 2
CL = 200pF to
600pF
CL = 200pF to
600pF
Low-Speed Load (Compliance Load)
CL = 200pF to 450pF
CL = 200pF to 450pF
Document Number: 002-05649 Rev. *D
Page 87 of 108
MB9B520M Series
12.8 Low-Voltage Detection Characteristics
12.8.1 Low-Voltage Detection Reset
(TA = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Value
Min
Typ
Max
2.25
2.45
2.65
2.30
2.50
2.70
2.39
2.60
2.81
Same as SVHR = 00000 value
2.48
2.70
2.92
Same as SVHR = 00000 value
2.58
2.80
3.02
Same as SVHR = 00000 value
2.76
3.00
3.24
Same as SVHR = 00000 value
2.94
3.20
3.46
Same as SVHR = 00000 value
3.31
3.60
3.89
Same as SVHR = 00000 value
3.40
3.70
4.00
Same as SVHR = 00000 value
3.68
4.00
4.32
Same as SVHR = 00000 value
3.77
4.10
4.43
Same as SVHR = 00000 value
3.86
4.20
4.54
Same as SVHR = 00000 value
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
SVHR*1=
LVD stabilization wait time
tLVDW
-
-
-
8160 × tCYCP*2
μs
LVD detection delay time
tLVDDL
-
-
-
200
μs
00000
SVHR*1=
00001
SVHR*1=
00010
SVHR*1=
00011
SVHR*1=
00100
SVHR*1=
00101
SVHR*1=
00110
SVHR*1=
00111
SVHR*1=
01000
SVHR*1=
01001
SVHR*1=
01010
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
*1: The SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is initialized to "00000" by Low-Voltage Detection
Reset.
*2: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05649 Rev. *D
Page 88 of 108
MB9B520M Series
12.8.2 Interrupt of Low-Voltage Detection
(TA = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Min
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
Value
Typ
2.80
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
Max
3.02
3.13
3.24
3.35
3.46
3.56
3.89
4.00
4.00
4.10
4.32
4.43
4.43
4.54
4.54
4.64
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDH
VDL
VDH
VDL
VDH
VDL
VDH
LVD stabilization wait time
tLVDW
-
-
-
8160 ×
tCYCP*
μs
LVD detection delay time
tLVDDL
-
-
-
200
μs
SVHI = 00011
SVHI = 00100
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
SVHI = 01010
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05649 Rev. *D
Page 89 of 108
MB9B520M Series
12.9 Flash Memory Write/Erase Characteristics
12.9.1 Write / Erase time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Parameter
Value
Typ
Max
Large Sector
1.1
2.7
Small Sector
0.3
0.9
Half word (16-bit)
write time
16
Chip erase time
6.8
Unit
Remarks
s
Includes write time prior to internal erase
310
μs
Not including system-level overhead time
18
s
Includes write time prior to internal erase
Sector erase time
*: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write.
12.9.2 Write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
1,000
20*
10,000
10*
Remarks
*: At average + 85°C
Document Number: 002-05649 Rev. *D
Page 90 of 108
MB9B520M Series
12.10 Return Time from Low-Power Consumption Mode
12.10.1 Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Typ
Max*
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Low-speed CR Timer mode
tICNT
Sub Timer mode
RTC mode,
Stop mode
Deep Standby RTC mode
Deep Standby Stop mode
Remarks
μs
tCYCC
Sleep mode
Unit
40
80
μs
340
680
μs
680
860
μs
268
503
μs
308
583
μs
When RAM is off
268
503
μs
When RAM is on
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*)
External
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-05649 Rev. *D
Page 91 of 108
MB9B520M Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
−
−
See “Chapter 6: Low Power Consumption Mode” and “Operations of Standby Modes” in FM3 Family Peripheral Manual.
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See “Chapter 6: Low Power Consumption Mode” in “FM3 Family Peripheral Manual”.
Document Number: 002-05649 Rev. *D
Page 92 of 108
MB9B520M Series
12.10.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Parameter
Symbol
Sleep mode
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Low-speed CR Timer mode
Value
Max*
263
148
263
μs
248
463
μs
312
496
μs
268
503
μs
308
268
583
503
μs
μs
tRCNT
Sub Timer mode
RTC mode,
Stop mode
Deep Standby RTC mode
Deep Standby Stop mode
Unit
Typ
148
Remarks
μs
When RAM is off
When RAM is on
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Document Number: 002-05649 Rev. *D
Start
Page 93 of 108
MB9B520M Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
−
−
See “Chapter 6: Low Power Consumption Mode” and “Operations of Standby Modes” in FM3 Family Peripheral Manual.
−
The time during the power-on reset/low-voltage detection reset is excluded. See “12.4.7. Power-on Reset Timing in 12.4. AC
Characteristics in 12.Electrical Characteristics” for the detail on the time during the power-on reset/low -voltage detection reset.
−
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time.
−
The internal resource reset means the watchdog reset and the CSV reset.
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See “Chapter 6: Low Power Consumption Mode” in “FM3 Family Peripheral Manual”.
Document Number: 002-05649 Rev. *D
Page 94 of 108
MB9B520M Series
13. Ordering Information
Part number
On-chip Flash
memory
On-chip
SRAM
MB9BF521KQN-G-AVE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522KQN-G-AVE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524KQN-G-AVE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF521KPMC-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522KPMC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524KPMC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF521LQN-G-AVE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522LQN-G-AVE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524LQN-G-AVE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF521LPMC1-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522LPMC1-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524LPMC1-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF521LPMC-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522LPMC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524LPMC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF521MPMC-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522MPMC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524MPMC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF521MPMC1-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522MPMC1-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524MPMC1-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF521MBGL-GE1
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF522MBGL-GE1
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF524MBGL-GE1
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
Document Number: 002-05649 Rev. *D
Package
Packing
Plastic・QFN
(0.5 mm pitch), 48-pin
(VNA048)
Plastic・LQFP
(0.5 mm pitch), 48-pin
(LQA048)
Plastic・QFN
(0.5 mm pitch), 64-pin
(VNC064)
Plastic・LQFP
(0.5 mm pitch), 64-pin
(LQD064)
Tray
Plastic・LQFP
(0.65 mm pitch), 64-pin
(LQG064)
Plastic・LQFP
(0.5 mm pitch), 80-pin
(LQH080)
Plastic・LQFP
(0.65 mm pitch), 80-pin
(LQJ080)
Plastic・PFBGA
(0.5 mm pitch), 96-pin
(FDG096)
Page 95 of 108
MB9B520M Series
14. Package Dimensions
Package Type
LQFP 80
Package Code
LQH080
D
D1
60
4
5 7
41
41
40
61
60
40
61
21
80
5
7
E1
E
4
3
6
80
21
1
20
D
e
20
2 5 7
0.10 C A-B D
3
b
0.08
C A-B
1
BOTTOM VIEW
D
0.20 C A-B D
8
TOP VIEW
2
A
A
A'
0.08 C
SIDE VIEW
SYMBOL
SEATING
PLANE
9
L1
L
0.25
A1
10
c
b
SECTION A-A'
DIMENSIONS
MIN. NOM. MAX.
A
A1
1. 70
0.05
0.15
b
0.15
0.27
c
0.09
0.20
D
14.00 BSC.
D1
12.00 BSC.
e
0.50 BSC
E
14.00 BSC.
E1
12.00 BSC.
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
PACKAGE OUTLINE, 80 LEAD LQFP
12.0X12.0X1.7 MM LQH080 Rev **
Document Number: 002-05649 Rev. *D
002-11501 **
Page 96 of 108
MB9B520M Series
Package Type
LQFP 80
Package Code
LQJ080
D
D1
60
4
5 7
41
41
61
40
E1
60
40
61
21
80
E
5
7
4
3
6
80
21
1
20
20
2 5 7
1
0.10 C A-B D
3
e
0.20 C A-B D
b
ddd
C A-B
D
8
2
A
9
A
A'
0.10 C
SEATING
PLANE
c
L1
0.2 5
A1
10
b
SECTION A-A'
L
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
1.70
A
A1
0.00
b
0.16
c
0.09
0.20
0.32
0.38
0.20
D
16.00 BSC
D1
14.00 BSC
e
0.65 BSC
E
16.00 BSC
E1
14.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
0
8
002-14043 **
PACKAGE OUTLINE, 80 LEAD LQFP
14.0X14.0X1.7 MM LQJ080 REV**
Document Number: 002-05649 Rev. *D
Page 97 of 108
MB9B520M Series
Package Type
LQFP 64
Package Code
LQD064
4
D
D1
48
5 7
33
33
32
49
48
32
49
17
64
5
7
E1
E
4
3
6
17
64
1
16
e
1
16
2 5 7
3
BOTTOM VIEW
0.10 C A-B D
0.20 C A-B D
b
0.08
C A-B
D
8
TOP VIEW
A
2
9
A
A'
0.08 C
SEATING
PLANE
L1
0.25
L
A1
c
b
SECTION A-A'
10
SIDE VIEW
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
A1
1. 70
0.00
0.20
b
0.15
0.2
c
0.09
0.20
D
12.00 BSC.
D1
10.00 BSC.
e
0.50 BSC
E
12.00 BSC.
E1
10.00 BSC.
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
PACKAGE OUTLINE, 64 LEAD LQFP
10.0X10.0X1.7 MM LQD064 Rev**
Document Number: 002-05649 Rev. *D
002-11499 **
Page 98 of 108
MB9B520M Series
Package Type
LQFP 64
Package Code
LQG064
D
D1
48
4
5 7
33
33
32
49
48
32
49
17
64
E1 E
5
7
4
3
17
64
1
16
e
1
16
2 5 7
3
BOTTOM VIEW
0.10 C A-B D
0.20 C A-B D
b
0.13
C A-B
D
8
TOP VIEW
2
A
A
A'
0.10 C
SEATI NG
PLA NE
0.2 5
L1
L
9
A1
10
c
b
SEC TION A -A'
SIDE VIEW
SYMBOL
DIMENSION
MIN.
NOM. MAX.
1.70
A
A1
0.00
0.20
b
0.27
c
0.09
0.32
0.37
0.20
D
14.00 BSC
D1
12.00 BSC
e
0.65 BSC
E
14.00 BSC
E1
12.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
0
002-13881 **
PACKAGE OUTLINE, 64 LEAD LQFP
12.0X12.0X1.7 MM LQG064 REV**
Document Number: 002-05649 Rev. *D
Page 99 of 108
MB9B520M Series
Package Type
QFN 64
Package Code
VNC064
0.10
D
A
48
0.10 C
2X
33
33
32
49
C A B
D2
48
32
49
0.10
C A B
5
(ND-1)
E
e
17
64
1
INDEXMARK
8
E2
16
9
B
e
L
0.10 C
TOP VIEW
64
17
16
BOTTOM VIEW
2X
b
1
4
0.10
0.05
C A B
C
0.10 C
A
0.05 C
SEATINGPLANE
C
A1
SIDE VIEW
DIMENSIONS
NOTES:
SYMBOL
MIN. NOM. MAX.
A
A1
0.90
0.00
0.05
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4
D
9.00 BSC
E
9.00 BSC
b
0.20 0.25 0.30
D2
6.00 BSC
E2
6.00 BSC
6.
7.
e
0.50 BSC
8
R
0.20 REF
L
0.35
0.40 0.45
N
64
ND
16
5
9
DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL
HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL,
THE DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE OR E SIDE.
MAX. PACKAGE WARPAGE IS 0.05mm.
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT
SINK SLUG AS WELL AS THE TERMINALS.
002-13234 **
PACKAGE OUTLINE, 64 LEAD QFN
9.0X9.0X0.9 MM VNC064 6.0X6.0 MM EPAD (SAWN) Rev*.*
Document Number: 002-05649 Rev. *D
Page 100 of 108
MB9B520M Series
Package Type
LQFP 48
Package Code
LQA048
4
D
D1
5 7
36
25
37
24
E1
24
37
13
48
E
5
7
3
36
25
4
6
48
13
1
12
e
1
12
2 5 7
0.10 C A-B D
3
0.20 C A-B D
b
0.80
C A-B
D
8
2
A
9
A
A'
0.80 C
SYMBOL
L1
0.25
L
A1
c
b
10
SECTION A-A'
DIMENSIONS
MIN.
NOM. MAX.
0.00
0.20
1.70
A
A1
SEATING
PLANE
b
0.15
0.27
c
0.09
0.20
D
9.00 BSC
D1
7.00 BSC
e
0.50 BSC
E
9.00 BSC
E1
7.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
0
8
002-13731 **
PACKAGE OUTLINE, 48 LEAD LQFP
7.0X7.0X1.7 MM LQA048 REV**
Document Number: 002-05649 Rev. *D
Page 101 of 108
MB9B520M Series
Package Type
QFN 48
Package Code
VNA048
0.10
D
C A B
D2
A
25
36
0.10 C
24
2X
(ND-1)
E
0.10
37
e
C A B
E2
5
13
9
INDEX MARK
8
48
12
R
1
L
B
TOP VIEW
e
b
4
0.10 C
0.10
0.05
C A B
C
BOTTOM VIEW
2X
0.10 C
A
0.05 C SEATING PLANE
A1
9
C
SIDE VIEW
DIMENSIONS
SYMBOL
MIN.
NOM.
A
A1
0.90
0.00
0.05
D
7.00 BSC
E
7.00 BSC
b
0.20
0.25
D2
5.50 BSC
E2
5.50 BSC
e
0.50 BSC
R
0.20 REF
L
MAX.
0.35
0.40
NOTE
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCINC CONFORMS TO ASME Y14.5-1994.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINAL HAS
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL. THE
DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
5. ND REFER TO THE NUMBER OF TERMINALS ON D OR E SIDE.
0.30
6. MAX. PACKAGE WARPAGE IS 0.05mm.
7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS.
8. PIN #1 ID ON TOP WILL BE LOCATED WITHIN INDICATED ZONE.
9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSEDHEAT
SINK SLUG AS WELL AS THE TERMINALS.
0.45
10. JEDEC SPEC
IFICATIONNO . REF : N/A
002-15528 **
PACKAGE OUTLINE, 48 LEAD QFN
7.0X7.0X0.9 MMVNA048 5.5X5.5 MMEPAD(SAWN) REV**
Document Number: 002-05649 Rev. *D
Page 102 of 108
MB9B520M Series
Package Type
FBGA 96
Package Code
FDG096
A
0.20 C
11
2X
10
9
6
8
7
6
5
4
3
2
1
L
PIN A1
CORNER
INDEX MARK
K
J
H
G
F
E
D
7
0.20 C
TOP VIEW
C
B
A
6
B
2X
BOTTOM VIEW
DETAIL A
0.20 C
0.08 C
C
96xφb
DETAIL A
5
0.05
SIDE VIEW
C A B
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
MIN.
NOM.
MAX.
2. SOLDER BALL POSITION DESIGNATIO
N PER JEP95, SECTION 3, SPP-020.
A
-
-
1.30
3. "e" REPRESENTSTHE SOLDER BALL GRID PITCH.
A1
0.15
0.25
0.35
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
D
6.00 BSC
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
E
6.00 BSC
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
D1
5.00 BSC
E1
5.00 BSC
MD
11
ME
11
N
96
b
0.20
0.30
eD
0.50 BSC
eE
0.50 BSC
SD
0.00
SE
0.00
SIZE MD X ME.
5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
0.40
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
7. A1 CORNER TO BE IDENTIFIED BY
CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
002-13224 **
PACKAGE OUTLINE, 96 BALL FBGA
6.0X6.0X1.3 MM FDG096 REV**
Document Number: 002-05649 Rev. *D
Page 103 of 108
MB9B520M Series
15. Major Changes
Spansion Publication Number: DS706-00048
Page
Section
Change Results
Revision 1.0
Features
2
Can Interface
A/D Converter (Max 26channels)
3
Uniqueid
6
Product Lineup
7
Function
List Of Pin Functions
16 to 18
List Of Pin Numbers
List Of Pin Functions
33
I/O Circuit Type
39
Block Diagram
46
55
57
58, 59
62
63
Electrical Characteristics
1. Absolute Maximum Ratings
2. Recommended Operating Conditions
3. Dc Characteristics
(1) Current Rating
4. Ac Characteristics
(3) Built-In Cr Oscillation Characteristics
(4-2) Operating Conditions Of Main PLL (In The
Case Of Using Built-In High-Speed CR For Input
Clock Of Main PLL)
5. 12-Bit A/D Converter
Electrical Characteristics For The A/D Converter
79
82
87
6. 10-Bit D/A Converter
8. Low-Voltage Detection Characteristics
9. Mainflash Memory Write/Erase Characteristics
88
Revision 1.1
Revision 2.0
Features
On-Chip Memories [Flash Memory]
2
USB Interface [USB Function]
3
2
Multi-Function Serial Interface [I C]
General-Purpose I/O Port
4
Multi-Function Timer
Document Number: 002-05649 Rev. *D
Preliminary → Data Sheet
Corrected the following description.
CAN Interface (Max 2channels) → CAN Interface
Revised the conversion time: 1.0μs → 0.8μs
Added the "Unique ID".
Added the "Unique ID".
Corrected the I/O circuit type.
Corrected the Pin state type.
Corrected the Pin function.
Added the "Type: L".
Corrected the figure.
- TIOA: input → input/output
- TIOB: output → input
Revised the value of "TBD".
Revised the Condition of "Operating temperature".
Revised the value of "TBD".
Added "Flash memory write/erase current".
Revised the Condition.
Revised the footnote.
Revised the value of "TBD".
Deleted "(Preliminary value)".
Revised the conversion time.
Min: 1.0μs → 0.8μs
Revised the value of "Compare clock cycle (AVCC ≥ 4.5V )".
Min: 50ns → 40ns
Revised the footnote.
Deleted "(Preliminary value)".
Revised the value of "TBD".
Revised the value of "TBD".
Revised the value of "Sector erase time".
- Large Sector Typ: 1.065s → 1.1s
- Small Sector Typ: 0.606s → 0.3s
Revised the value of "Chip erase time".
Typ: 9.11s → 6.8s
Deleted "(targeted value)".
Company name and layout design change
Revised the features of Dual operation Flash memory
Added the size of each endpoint.
Corrected the mode.
High speed mode → Fast mode
Revised the features of 5V tolerant I/O.
Corrected the number of A/D activating compare channels.
3ch. → 2ch.
Page 104 of 108
MB9B520M Series
Page
Section
Change Results
Product Lineup
Function
Corrected the number of A/D activating compare channels.
3ch. → 2ch.
Revised Built-in CR .
High-speed: 4MHz(± 2%) → 4MHz
Low-speed: 100kHz(Typ) → 100kHz
Revised the footnote.
21
List Of Pin Functions
List Of Pin Numbers
Corrected the pin number of ZIN1_1.
24
29
31
List Of Pin Functions
37
I/O Circuit Type
44
Handling Devices
Sub Crystal Oscillator
Added the descriptions.
47
Block Diagram
Corrected the figure.
-A/D Activation Compare: 3ch → 2ch
49
Memory Map
Memory Map (2)
Added the explanatory note.
7
8
54
55
Pin Status In Each Cpu State
List Of Pin Status
58
Electrical Characteristics
2. Recommended Operating Conditions
59
3. Dc Characteristics
(1) Current Rating
63
64
66
4. Ac Characteristics
(2) Sub Clock Input Characteristics
(3) Built-In CR Oscillation Characteristics
Built-In High-Speed CR
(6) Power-On Reset Timing
68
(8) Csio Timing
70,72,74
79
81
(11) I2c Timing
5. 12-Bit A/D Converter
Electrical Characteristics For The A/D Converter
82
83
Difinition Of 12-Bit A/D Converter Terms
84
6. 10-Bit D/A Converter
Electrical Characteristics For The D/A Converter
Document Number: 002-05649 Rev. *D
Corrected the pin number of ADTG_2.
Corrected pin numbers of SIN0_1 and SOT0_1.
Corrected the pin number of DTTI0X_2.
Corrested the I/O circuit figure.
TYPE H : GPIO Digital input → GPIO Digital output
Added the pin function of selected Analog output about type L.
Corrected the footnote.
Sub CR timer→ Low-speed CR tim
Added the note and footnote.
Corrected the value of Analog reference voltage “AVRH”.
Min.: AVss → 2.7
Added notes and footnotes.
Added the remarks of Icc.
Added the frequency of main clock crystal oscillator in remarks.
Added the footnote.
Added "Frequency stabilization time"
Added notes and footnotes.
Added "Timing until releaseing Power-on reset"
Added the timing chart
Corrected the title.
UART Timing → CSIO Timing
Corrected the notefoot.
UART → Multi-function serial
Corrected the notefoot.
UART → Multi-function serial
Revised the Condition.
Revised the footnote.
Changed the name of parameter.
•Non Linearity error → Integral Nonlinearity
•Differential linearity error → Differential Nonlinearity
Changed the Symbol. Of Zero transition voltage.
VoT → VZT
Changed the pin name.
AN00 to AN26 → ANxx
Corrected the value of V0T, VFST, Ts, Tstt, and reference voltage.
Revides footnotes.
Change the figure.
AN00 to AN26 → ANxx
•Linearity error → Integral Nonlinearity
•Differential linearity error → Differential Nonlinearity
V0T → VZT
•Revised the remark of IDDA.
D/A operation → D/A 1unit operation
Changed the name of parameter.
•Linearity error → Integral Nonlinearity
•Differential linearity error → Differential Nonlinearity
Page 105 of 108
MB9B520M Series
Page
Section
89
8. Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
90
(2) Interrupt Of Low-Voltage Detection
91
9. Flash Memory Write/Erase Characteristics
92
10. Return Time Low-Power Consumption Mode
Revision 3.0
Features
2
Usb Interface
36, 37
I/O Circuit Type
Memory Map
49
· Memory Map(2)
PIN STATUS IN EACH CPU STAE
54
· List Of Pin Status
Electrical Characteristics
56, 57
1. Absolute Maximum Ratings
59-61
66
69-76
77
Electrical Characteristics
3. DC Characteristics
(1) Current Rating
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions Of Main And USB PLL
(4-2) Operating Conditions Of Main PLL
Electrical Characteristics
4. Ac Characteristics
(7) Csio/Uart Timing
Electrical Characteristics
4. Ac Characteristics
(9) External Input Timing
82
Electrical Characteristics
5. 12bit A/D Converter
97, 98
Ordering Information
Change Results
Corrected the condition and the value.
Added the note and the footnote.
Added “LVD detection delay time”.
Corrected the condition and the value.
Added “LVD detection delay time”.
Changed the title of Chapter.
Main Flash Memory Write/Erase Characteristics →
Flash Memory Write/Erase Characteristics
Added the Chapter “Return Time from Low-Power Consumption Mode”.
Added The Description Of Pll For Usb
Added About +B Input
Added The Summary Of Flash Memory Sector And The Note
Changed The Pin Status Of I-Type
· Added The Clamp Maximum Current
· Added About +B Input
· Changed The Table Format
· Added Main TIMER Mode Current
· Moved A/D Converter Current
· Moved D/A Converter Current
· Added The Figure Of Main PLL Connection And USB PLL Connection
· Modified From Uart Timing To Csio/Uart Timing
· Changed From Internal Shift Clock Operation To Master Mode
· Changed From External Shift Clock Operation To Slave Mode
Added Input Pulse Width Of Wkupx Pin
· Added The Typical Value Of Integral Nonlinearity, Differential Nonlinearity,
Zero Transition Voltage And Full-Scale Transition Voltage
· Added Conversion Time At Avcc < 4.5V
Change To Full Part Number
Note: Please see “Document History” about later revised information.
Document Number: 002-05649 Rev. *D
Page 106 of 108
MB9B520M Series
Document History
Document Title: MB9B520M Series 32-bit Arm® Cortex®-M3, FM3 Microcontroller
Document Number: 002-05649
Orig. of
Submission
Change
Date
–
TOYO
09/13/2012
5164786
TOYO
03/07/2016
Revision
ECN
**
*A
Description of Change
Migrated to Cypress and assigned document number 002-05649.
No change to document contents or format.
Updated to Cypress format.
・ Modified RTC description in “Features, Real-Time Clock(RTC)”. Changed
starting count value from 01 to 00. Deleted “second , or day of the week” in the
Interrupt function. (Page 3)
・ Updated Package code and dimensions as follows (Page 8-14, 95-103)
*B
5653470
HTER
03/09/2017
-
FPT-48P-M49 -> LQA048
-
LCC-48P-M73 -> VNA048
-
FPT-64P-M38 -> LQD064
-
FPT-64P-M39 -> LQG064
-
LCC-64P-M24 -> VNC064
-
FPT-80P-M37 -> LQH080
-
FPT-80P-M40 -> LQJ080
-
BGA-96P-M07 -> FDG096
・ Added Notes for JTAG. (Page 32)
・ Updated “12.4.7 Power-On Reset Timing”. Changed parameter from “Power
Supply rise time(Tr) [ms]” to “Power ramp rate(dV/dt) [mV/us]” and add some
comments. (Page 65)
・ Added the Baud rate spec in “12.4.9 CSIO/UART Timing”.(Page 67-73)
・ Corrected the erroneous descriptions as follows.
-
“USB Function” -> “USB Device” (Page 1, 7, 31, 44)
-
“J-TAG” -> “JTAG” (Page 24)
-
“Analog port input current” -> “Analog port input leak current” (Page 80)
*C
5764936
AESATMP9
06/15/2017
Updated logo and copyright.
*D
6064687
HUAL
02/09/2018
Updated the Sales information and legal
Document Number: 002-05649 Rev. *D
Page 107 of 108
MB9B520M Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
Clocks & Buffers
Interface
Internet of Things
Memory
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
PSoC
cypress.com/psoc
Power Management ICs
cypress.com/pmic
Wireless Connectivity
Community | Projects | Videos | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/memory
cypress.com/mcu
USB Controllers
Cypress Developer Community
cypress.com/iot
Microcontrollers
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/touch
cypress.com/usb
cypress.com/wireless
Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
© Cypress Semiconductor Corporation, 2012-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or
other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software,
then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source
code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form
externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are
infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction,
modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security
breach, such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is
any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable,
in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-05649 Rev. *D
February 9, 2018
Page 108 of 108