IRF IRS21091 Half-bridge driver Datasheet

Data Sheet No. PD60311
IRS21091(S)PbF
HALF-BRIDGE DRIVER
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Floating channel designed for bootstrap operation
Fully operational to +600 V
Tolerant to negative transient voltage, dV/dt
immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for both channels
3.3 V, 5 V, and 15 V input logic compatible
Cross-conduction prevention logic
Matched propagation delay for both channels
High-side output in phase with IN input
Logic and power ground +/- 5 V offset
Internal 500 ns deadtime, and programmable
up to 5 µs with one external RDT resistor
Lower di/dt gate driver for better noise immunity
The dual function DT/SD input turns off both
channels
RoHS compliant
Product Summary
VOFFSET
600 V max.
IO+/VOUT
ton/off (typ.)
Deadtime
120 mA / 250 mA
10 V - 20 V
750 ns & 200 ns
540 ns
Packages
Description
The IRS21091 is a high voltage, high speed power
MOSFET and IGBT driver with dependent high- and
low-side referenced output channels. Proprietary
HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. The logic input is
8 Lead PDIP
8 Lead SOIC
compatible with standard CMOS or LSTTL output,
IRS21091
IRS21091S
down to 3.3 V logic. The output drivers feature a
high pulse current buffer stage designed for minimum
driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in
the high-side configuration which operates up to 600 V.
Typical Connection
up to 600 V
VCC
VCC
IN
DT/SD
IN
VB
HO
DT/SD
VS
COM
LO
TO
LOAD
(Refer to Lead Assignments for
correct configuration). These diagrams show electrical connections only. Please refer to our
Application Notes and DesignTips
for proper circuit board layout.
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1
IRS21091(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
VB
High-side floating absolute voltage
-0.3
625
VS
High-side floating supply offset voltage
VB - 25
VB + 0.3
VHO
High-side floating output voltage
VS - 0.3
VB + 0.3
VCC
Low-side and logic fixed supply voltage
-0.3
25
VLO
Low-side output voltage
-0.3
VCC + 0.3
Programmable deadtime and shutdown pin voltage
VSS - 0.3
VCC + 0.3
Logic input voltage (IN & DT/SD)
VSS - 0.3
VCC + 0.3
—
50
DT/SD
VIN
dVS/dt
PD
Allowable offset supply voltage transient
Package power dissipation @ TA ≤ +25 °C
(8 Lead PDIP)
—
1.0
(8 Lead SOIC)
—
0.625
(8 Lead PDIP)
—
125
(8 Lead SOIC)
—
200
Junction temperature
—
150
TS
Storage temperature
-50
150
TL
Lead temperature (soldering, 10 seconds)
—
300
RthJA
TJ
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Thermal resistance, junction to ambient
Units
V
V/ns
W
°C/W
°C
2
IRS21091(S)PbF
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig.1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supply biased at a 15 V differential.
Symbol
Definition
Min.
Max.
VS + 10
VS + 20
(Note 1)
600
High-side floating output voltage
VS
VB
VCC
Low-side and logic fixed supply voltage
10
20
VLO
Low-side output voltage
0
VCC
VIN
Logic input voltage (IN & DT/SD)
V SS
VCC
Programmable deadtime and shutdown pin voltage
V SS
VCC
Ambient temperature
-40
125
VB
High-side floating supply absolute voltage
VS
High-side floating supply offset voltage
VHO
DT/SD
TA
Units
V
°C
Note 1: Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, CL = 1000 pF, TA = 25 °C, unless otherwise specified.
Symbol
Min.
Typ.
ton
Turn-on propagation delay
—
750
toff
Turn-off propagation delay
—
Shutdown propagation delay
—
tsd
MT
Definition
Max. Units Test Conditions
950
VS = 0 V
200
280
VS = 0 V or 600 V
550
715
Delay matching, HS & LS turn-on/off
—
0
70
tr
Turn-on rise time
—
100
220
tf
Turn-off fall time
—
35
80
400
DT
MDT
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Deadtime: LO turn-off to HO turn-on(DTLO-HO) &
HO turn-off to LO turn-on (DTHO-LO)
Deadtime matching = DTLO - HO - DTHO-LO
540
680
4
5
6
—
0
60
—
0
600
ns
VS = 0 V
RDT= 0 Ω
µs
ns
RDT = 200 kΩ
RDT= 0 Ω
RDT = 200 kΩ
3
IRS21091(S)PbF
Static Electrical Characteristics
VBIAS (VCC , VBS) = 15 V, and TA = 25 °C unless otherwise specified. The VIL, VIH, and IIN parameters are referenced to
COM and are applicable to the respective input leads: IN and DT/SD. The VO, IO, and Ron parameters are referenced to
COM and are applicable to the respective output leads: HO and LO.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
VIH
Logic “1” input voltage for HO & logic “0” for LO
VIL
Logic “0” input voltage for HO & logic “1” for LO
VSD,TH
DT/SD input threshold
2.5
—
—
—
—
0.8
11.5
13
14.5
VOH
High level output voltage, VBIAS - VO
—
0.05
0.2
VOL
Low level output voltage, VO
—
0.02
0.1
ILK
Offset supply leakage current
—
—
50
IQBS
Quiescent VBS supply current
20
75
130
IQCC
Quiescent VCC supply current
0.4
1.0
1.6
IIN+
Logic “1” input bias current
—
5
20
IIN-
Logic “0” input bias current
—
—
5
8.0
8.9
9.8
7.4
8.2
9.0
Hysteresis
0.3
0.7
—
IO+
Output high short circuit pulsed current
120
290
—
IO-
Output low short circuit pulsed current
250
600
—
VCCUV+
VBSUV+
VCCUVVBSUVVCCUVH
VBSUVH
VCC and VBS supply undervoltage positive going
threshold
VCC and VBS supply undervoltage negative going
threshold
VCC = 10 V to 20 V
V
IO = 2 mA
µA
VB = VS = 600 V
IN = 0 V or 5 V
IN = 0 V or 5 V
mA
µA
RDT = 0 Ω
IN = 5 V, DT/SD = 0 V
IN = 0 V, DT/SD = 5 V
V
mA
VO = 0 V, PW ≤ 10 µs
VO = 15 V,PW ≤ 10 µs
Lead Assignments
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1
VCC
VB
8
2
IN
HO
7
3
DT/SD
VS
6
4
COM
LO
5
VCC
VB
8
IN
HO
7
3
DT/SD
VS
6
4
COM
LO
5
1
2
8 Lead PDIP
8 Lead SOIC
IRS21091PbF
IRS21091SPbF
4
IRS21091(S)PbF
Functional Block Diagrams
VB
UV
DETECT
HO
R
VSS/COM
LEVEL
SHIFT
IN
DT/SD
HV
LEVEL
SHIFTER
R
PULSE
FILTER
Q
S
VS
PULSE
GENERATOR
VCC
DEADTIME
UV
DETECT
VSS/COM
LEVEL
SHIFT
DELAY
LO
COM
Lead Definitions
Symbol Description
IN
Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO
DT/SD
Programmable deadtime lead,disables input/output logic when tied to VCC
VB
High-side floating supply
HO
High-side gate drive output
VS
High-side floating supply return
VCC
Low-side and logic fixed supply
LO
Low-side gate drive output
COM
Low-side return
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5
IRS21091(S)PbF
IN(LO)
IN
50%
50%
IN(HO)
DT/SD
ton
toff
tr
HO
90%
LO
HO
LO
tf
90%
10%
10%
Figure 2. Switching Time Waveform Definitions
Figure 1. Input/Output Timing Diagram
50%
50%
IN
50%
90%
DT/SD
HO
tsd
HO
LO
DT LO-HO
LO
90%
10%
DTHO-LO
90%
10%
MDT=
DTLO-HO
- DTHO-LO
Figure 4. Deadtime Waveform Definitions
Figure 3. Shutdown Waveform Definitions
IN (LO)
50%
50%
IN (HO)
LO
HO
10%
MT
MT
90%
LO
HO
Figure 5. Delay Matching Waveform Definitions
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6
IRS21091(S)PbF
Note: For the following figures the VBIAS (VCC, VBS) = 15 V and TA = 25 OC unless otherwise specified.
1300
Turn-on Propagation Delay (ns)
Turn-on Propagation Delay (ns)
1300
1100
900
M ax
.
700
Typ.
500
-50
-25
0
25
50
75
100
1100
M ax.
900
Typ.
700
500
125
10
12
Temperature ( C)
Figure 6A. Turn-on Propagation Delay
Figure 6A. Turn-On Propagation Delay
vs. Temperature
18
20
500
Turn-of f Propagation Delay (ns)
Turn-of f Propagation Delay (ns)
16
Figure 6B. Turn-On Propagation Delay
vs. Supply Voltage
500
400
300
200
14
V BIAS Supply Voltage (V)
o
M ax.
Typ.
100
400
M ax.
300
Typ.
200
100
0
0
-50
-25
0
25
50
75
100
125
Temperature ( C)
o
Figure 7A. Turn-off Propagation Delay
Figure 7A. Turn-Off Propagation Delay
vs. Temperature
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10
12
14
16
18
20
V BIAS Supply Voltage (V)
Figure 7B. Turn-off Propagation Delay
Figure 7B. Turn-Off Propagation Delay
vs. Supply Voltage
7
IRS21091(S)PbF
500
SD Propagation Delay (ns)
SD Propagation Delay (ns)
500
400
300
M ax.
200
Typ.
100
400
M ax.
300
Typ.
200
100
0
0
-50
-25
0
25
50
75
100
10
125
12
Figure 8A. SD Propagation Delay
vs. Temperature
16
18
20
Figure 8B. SD Propagation Delay
vs. Supply Voltage
50 0
Turn-On
(ns)
T urn-O n Rise
R is e TTime
im e (ns
)
5 00
T urn-O n RRise
is e TTime
im e (ns(ns)
)
Turn-On
14
V BIAS Supply Voltage (V)
Temperature ( C)
o
4 00
3 00
2 00
Max.
1 00
Typ.
0
40 0
30 0
Max.
20 0
Typ.
10 0
0
-5 0
-2 5
0
25
50
75
1 00
Temperature(oC)
Figure 9A. Turn-On Rise Time
vs. Temperature
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1 25
10
12
14
16
18
20
V BIAS Supply Voltage (V)
Figure 9B. Turn-On Rise Time
vs. Supply Volta ge
8
IRS21091(S)PbF
200
Turn-Off
FallFall
Time
(ns)ns
Turn-Off
Time
Turn-Off Fall Time (ns)
200
150
100
Max.
50
Typ.
0
-50
-25
0
25
50
75
100
125
150
100
M ax.
50
Typ.
0
10
12
14
16
18
20
V BIAS Supply Voltage (V)
Temperature ( oC)
Figure 10B. Turn-Off Fall Time
vs. Supply Voltage
1000
1000
800
800
Deadtime (ns)
Deadtime (ns)
Figure 10A. Turn-Off Fall Time
vs. Temperature
M ax.
600
Typ.
400
M in.
600
M ax.
Typ.
M in.
400
200
200
-50
-25
0
25
50
75
100
125
Temperature ( C)
o
Figure 11A. Deadtime vs. Temperature
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10
12
14
16
18
20
V BIAS Supply Voltage (V)
Figure 11B. Deadtime vs. Supply Voltage
9
IRS21091(S)PbF
5
7
Input Voltage (V)
Deadtime
( s)
Deadtime
(µs)
6
M ax.
5
Typ.
4
M in.
3
2
4
3
Min.
2
1
1
-50
0
0
50
100
150
200
-25
0
R
RDT
DT(kΩ)
(KΩ)
Min.
2
1
14
16
18
V BIAS Supply Voltage (V)
Figure 12B. Logic “1” Input Voltage
vs. Supply Voltage
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20
Logic "0" Input Bias Current (µA)
Input Voltage (V)
4
12
75
100
125
Figure 12A. Logic “1” Input Voltage
vs. Temperatu re
5
10
50
Temperature (°C)
Figure 11C. Deadtime vs. R DT
3
25
6
5
Max
4
3
2
1
0
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 13A. Logic "0" Input Bias Current
vs. Temperature
10
18
6
5
SD Input threshold (+) (V)
Logic "0" Input Bias Current (µA)
IRS21091(S)PbF
Max
4
3
2
1
12
14
16
18
Max.
14
12
10
8
-50
0
10
16
20
-25
0
Figure 13B. Logic "0" Input Bias Current
High Level Output Voltage (V)
SD Input threshold (+) (V)
18
Max.
14
12
10
8
12
14
16
18
V CC Supply Voltage (V)
Figure 14B. SD Input Positive Going
Threshold (+) vs. Supply Voltage
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75
100
125
Figure 14A. SD Input Positive Going
Threshold (+) vs. Temperature
vs. Voltage
10
50
Temperature (oC)
Supply Voltage (V)
16
25
20
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
Max.
0.1
0.1
Typ.
0.0
0.0
-50
10
-50
-25
-25
00
25
25
50
50
75
75
100
100
125
125
Temperature ( oC)
o
Temperature ( C)
Figure 15A. High Level Output Voltage
vs. Temperature
11
IRS21091(S)PbF
Low Level Output Voltage (V)
High Level Output Voltage (V)
0.5
0.4
0.3
Max.
0.2
0.1
0.0
Typ.
10
12
14
16
18
20
0.5
0.4
0.3
0.2
0.1
Max.
Typ.
0.0
-50
-25
0.3
0.2
Max.
0.1
Typ.
0
18
VBIAS Supply Voltage (V)
Figure 16B. Low Level Output Voltage
vs. Supply Voltage
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20
Offset
OffsetSupply
SupplyLeakage
LeakageCurrent
Current(µA)
( A)
Low Level Output Voltage (V)
0.4
16
75
100
125
Figure 16A. Low Level Output Voltage
vs. Temperature
0.5
14
50
Temperature ( C)
Figure 15B. High Level Output Voltage
vs. Supply Voltage
12
25
o
VBIAS Supply Voltage (V)
10
0
500
400
300
200
100
M ax.
0
-50
-25
0
25
50
75
100
125
Temperature ( oC)
Figure 17A. Offset Supply Leakage Current
vs. Temperature
12
400
500
V BS Supply Current (μA)
Offset Supply Leakage Current (µA)
IRS21091(S)PbF
400
300
200
100
300
200
Max.
100
Max.
0
-50
0
0
100
200
300
400
500
Typ.
600
Min.
-25
0
50
75
100
125
Temperature (oC)
VB Boost Voltage (V)
Figure 18A. VBS Supply Current vs.
Temperature
Figure 17B. Offset Supply Leakage Current
vs. Boost Voltage
400
3.0
VVCcCcSS
uu
pp
plpyly CCuurrrreennt (m
( mAA) )
V BS Supply Current (μA)
25
300
200
Max.
100
Typ.
Min.
2.5
2.0
M ax.
1.5
Typ.
1.0
M in.
0.5
0
10
12
14
16
18
Supply Voltage (V)
Figure 18B. VBS Supply Current vs. Supply
Voltage
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20
0.0
-50
-25
0
25
50
75
100
125
Temperature (oC)
Figure 19A. VCC Supply Current
vs. Temperature
13
IRS21091(S)PbF
60
2.5
Logic
Logic “1”
"1"Input
Input Current
Current(mA)
( A)
V CC Supply Current (mA)
3.0
2.0
1.5
M ax.
1.0
Typ.
0.5
M in.
50
40
30
20
Typ.
0.0
10
12
14
16
V CC Supply Voltage (V)
Figure 20B. V
18
0
20
-50
-25
0
25
50
75
100
125
Temperature ( oC)
Supply Current
Figure 19B. VCC Supply Current
vs. VCC Supply Voltage
Figure 20A. Logic “1” Input Current
vs. Temperature
10
Logic 0” Input Current (µA)
60
Logic “1”
"1" Input
Input Current
Current (mA)
( A)
Logic
M ax.
10
50
40
30
M ax.
20
10
Typ.
0
10
12
14
16
18
V CC Supply Voltage (V)
Figure 21B. Logic "1" Input Current
Figure 20B. Logic “1” Input Current
vs. Supply Voltage
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20
8
Max.
6
4
2
0
-50
-25
0
25
50
75
100
125
Temperature (oC)
Figure 21A. Logic “0” Input Current
vs. Temperature
14
IRS21091(S)PbF
12
V CC UVLO Threshold (+) (V)
Logic 0” Input Current (µA)
10
8
M ax.
6
4
2
11
10
M ax.
9
Typ.
0
10
12
14
16
18
M in.
8
7
20
-50
-25
V CC Supply Voltage (V)
25
50
75
100
125
Temperature ( C)
o
Figure 22. VCC Undervoltage Threshold (+)
vs. Temperature
Figure 21B. Logic “0” Input Currentt
vs. Supply Voltage
12
V BS UVLO Threshold (+) (V)
11
V CC UVLO Threshold (-) (V)
0
10
M ax.
9
Typ.
8
M in.
7
6
-50
-25
0
25
50
75
100
125
Temperature ( oC)
Figure 23. VCC Undervoltage Threshold (-)
vs. Temperature
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11
10
9
8
M ax.
Typ.
M in.
7
-50
-25
0
25
50
75
100
125
Temperature ( C)
o
Figure 24. VBS Undervoltage Threshold (+)
vs. Temperature
15
IRS21091(S)PbF
500
Output Source Current (mA)
V BS UVLO Threshold (-) (V)
11
10
9
M ax.
Typ.
8
M in.
7
400
Typ.
300
200
Min.
100
0
6
-50
-25
0
25
50
75
100
-50
125
-25
Temperature ( C)
o
75
100
125
Figure 26A. Output Source Current vs.
Tem perature
1000
Output
O
utput Sink
SinkCurrent
Curren(m A) )
Output Source Current (mA)
50
Temperature ( C)
500
400
300
200
0
25
o
Figure 25. VBS Undervoltage Threshold (-)
vs. Temperature
100
0
Typ.
Min.
10
12
14
16
18
20
800
Typ.
600
400
200
Min.
0
-50
-25
0
25
50
75
100
V BIAS Supply Voltage (V)
Temperature (oC)
Figure 26B. Output Source Current
vs. Supply Voltage
Figure 27A. Output Sink Current
vs. Temperature
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125
16
IRS21091(S)PbF
0
V S Offset Supply Voltage (V)
OOutput
u tp u t S
inkCurrent
Curren(mA)
Sink
1000
800
600
400
Typ.
200
Min.
0
10
12
14
16
18
VBIAS Supply Voltage (V)
Figure 27B. Output Sink Currentt
vs. Supply Voltage
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20
-2
Typ.
-4
-6
-8
-10
10
12
14
16
18
20
V BS Floating Supply Voltage (V)
Figure 28. Maximum VS Negative Offset
vs. Supply Voltage
17
IRS21091(S)PbF
Case Outlines
01-6014
01-3003 01 (MS-001AB)
8 Lead PDIP
D
DIM
B
5
A
FOOTPRINT
8
6
7
6
5
H
E
1
2
3
0.25 [.010]
4
A
6.46 [.255]
MIN
.0532
.0688
1.35
1.75
A1 .0040
e
3X 1.27 [.050]
e1
.0098
0.10
0.25
.013
.020
0.33
0.51
c
.0075
.0098
0.19
0.25
D
.189
.1968
4.80
5.00
E
.1497
.1574
3.80
4.00
e
.050 BASIC
0.25 [.010]
A1
0.635 BASIC
H
.2284
.2440
5.80
6.20
K
.0099
.0196
0.25
0.50
L
.016
.050
0.40
1.27
y
0°
8°
0°
8°
y
0.10 [.004]
8X L
8X c
7
C A B
NOTES:
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INC HES].
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
8 Lead SOIC
www.irf.com
.025 BASIC
1.27 BASIC
K x 45°
A
C
8X b
8X 1.78 [.070]
MAX
b
e1
6X
MILLIMETERS
MAX
A
8X 0.72 [.028]
INCHES
MIN
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
7 DIMENSION IS THE LENG TH OF LEAD FOR SOLDERING TO
A SUBSTRATE.
01-6027
01-0021 11 (MS-012AA)
18
IRS21091(S)PbF
Tape & Reel
8-lead SOIC
LOAD ED TA PE FEED DIRECTION
A
B
H
D
F
C
N OTE : CO NTROLLING
D IMENSION IN M M
E
G
C A R R I E R T A P E D IM E N S I O N F O R 8 S O I C N
M etr ic
Im p e r i a l
Cod e
M in
M ax
M in
M ax
A
7 .9 0
8 .1 0
0 . 31 1
0 .3 1 8
B
3 .9 0
4 .1 0
0 . 15 3
0 .1 6 1
C
1 1 .7 0
1 2.30
0 .4 6
0 .4 8 4
D
5 .4 5
5 .5 5
0 . 21 4
0 .2 1 8
E
6 .3 0
6 .5 0
0 . 24 8
0 .2 5 5
F
5 .1 0
5 .3 0
0 . 20 0
0 .2 0 8
G
1 .5 0
n/ a
0 . 05 9
n/ a
H
1 .5 0
1 .6 0
0 . 05 9
0 .0 6 2
F
D
C
B
A
E
G
H
R E E L D IM E N S I O N S F O R 8 S O IC N
M etr ic
Im p e r i a l
Cod e
M in
M ax
M in
M ax
A
3 2 9. 6 0
3 3 0 .2 5
1 2 .9 7 6
1 3 .0 0 1
B
2 0 .9 5
2 1.45
0 . 82 4
0 .8 4 4
C
1 2 .8 0
1 3.20
0 . 50 3
0 .5 1 9
D
1 .9 5
2 .4 5
0 . 76 7
0 .0 9 6
E
9 8 .0 0
1 0 2 .0 0
3 . 85 8
4 .0 1 5
F
n /a
1 8.40
n /a
0 .7 2 4
G
1 4 .5 0
1 7.10
0 . 57 0
0 .6 7 3
H
1 2 .4 0
1 4.40
0 . 48 8
0 .5 6 6
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IRS21091(S)PbF
LEADFREE PART MARKING INFORMATION
IRxxxxxx
S
Part number
YWW?
Date code
Pin 1
Identifier
?
P
MARKING CODE
Lead Free Released
Non-Lead Free
Released
IR logo
?XXXX
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
Per SCOP 200-002
ORDER INFORMATION
8-Lead PDIP IRS21091PbF
8-Lead SOIC IRS21091SPbF
8-Lead SOIC Tape & Reel IRS21091STRPbF
The SOIC-8 is MSL2 qualified.
This product has been designed and qualified for the industrial level.
Qualification standards can be found at www.irf.com
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
Data and specifications subject to change without notice. 6/22/2007
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20