P'"
JIG
7
F
7 {()
ANALOG
8-, 10-,12-BitVideoSpeed
W DEVICES CurrentandVoltageOut,D/ A Converters
FEA TURES
Current Settling Times to 15ns
:t1.5V Compliance
Voltage Settling Times to 100ns (MDH)
Monotonicity Guaranteed Over Temperature
15mA
High Output Currents
-30°C to +85°C Operating Range
Industry Standard Pin Outs
20V, p.p Out (MDH)
TTl or ECl logic
,.
-
OBS
APPLICATIONS
CRT Vector Displays
Digitial Waveform Generation
Automatic Test Equipment
TV Picture Reconstruction
OLE
GENERAL DESCRIPTION
This broad family of digital-to-analog converters represents the
"state of the art" in modular, high speed, voltage and current
output devices. The family consists of a total of 11 devices in
4 series (MDS, MDSE, MDSL and MDH) that allow the user to
make engineering trade-offs between resolution, speed, output
and logic type. The first 3 are high compliance current output
unitS which make possible linear output swings greater than
:t1.5V. The voltage output MDH series contain a fast settling
hybrid operational amplifier which provides:t 10V output at
:t5OmA. To simplify selection these major specifications are
summarized in Table 1.
FULL SCALE
MODEL
BITS
MDS-0815
MDS-I020
MDS-1240
8
to
12
MDS-O815E
MDS-I020E
8
10
MDSL-0825
MDSL-I035
MDSL-1250
8
10
12
MDH-0870
MDH-l00l
MDH-1202
8
10
12
FULL SCALE
SETTLING TIME
OUTPUT
INPUT
LOGIC
(Fastest Settling High Current Out)
15mA
15ns to 0.4% FS
15mA
20n5 to 0.1% FS
15mA
40n5 to 0.025% FS
(MDS with ECL Logic)
15mA
15ns to 0.4% FS
15mA
20n5 to 0.1% FS
(Low Current MDS)
SmA
25n5toO.l%
SmA
25n5toO.l%
SmA
SOns to 0.025%
(Voltage Out MDSL)
10V /50mA
150n5 to 0.4%
,tOV/50mA
200n5 to 0,1 %
tOV /50mA
500n5 to 0.025%
Table
TTL
TTL
TTL
ECL
ECL
TTL
TTL
TTL
TTL
TTL
TTL
achieve ultra-high speed operation. In fact, it is the fastest 12bit D/A available, settling to 0.025% in 40ns. Hybrid construction eliminates the thermal lag problem inherent in 12-bit
D/A's constructed with discrete componentS. This in turn
means that the accuracy is maintained over the total frequency
range of operation, yielding superior results for frequency domain applications.
TE
The MDS-1240 is particularly well suited for CRT display applications because of its unsurpassed speed and drive capabilities. The high output current (ISmA) allows the use of low
impedance loads so that settling times remain short - even
with higher output voltage levels. The ability to drive load capacitance is at least 3 times that of other 12-bit D/A's thus
providing capability to drive a terminated transmission line
directly. The MDS-815 and MDS-I020 provide similar performance at 8 and 10 bits, while the MDS-E units provide it
with ECL logic. MDSL-082S, MDSL-I035 and MDSL-12S0
also utilize this reliable hybrid construction. The use of laser
trimmed resistor networks within the D/A's not only eliminates thermal time lag errors but provide the linearity tempco of 2ppmtC; guaranteeing monotonic operation over the
extended temperature range of -30°C to +8SoC. The power
dissipation of the MDSL series is one-half that of competitive D/A's, but a full SmA output current is maintained. This
allows driving transmission lines or other low impedance loads
directly.
(continued on page 1955)
1.
SPEED WITH PRECISION
Analog Devices' model MDS-1240 is the first D/A converter
available with highly reliable, internal hybrid construction to
Page 1 of 8
D/A CONVERTERS 1915
',:-",~,,"",
,'C
,:C°';'"
-:",
~",;:",,":_'.,-:
:-"
"".':_-"_:'.~,':,,-:.:.c'-,
',',:'
<,:'"",..:,~.~,,':".,':<""",-,;",.,::,,:,::;,.:,.',,',:,,':;:":'.-:.'
,;,:'
",:"',',",
SPECIFICATIONS
(typical @+25°C unlessotherwisespecified)
MODEL
UNITS
CURRENT OUTPUT
MDS
0815
1020
RESOLUTION
Bits
8
10
12
8
10
LSB (Weight)
ACCURACY
Initial (Adjust to 0)
Linearity (Integral)
Monotonicity
IlA
58.6
14.6
3.66
58.6
14.6
:!:%FS
LSB max
0.2
:!:li2
0.05
.
0.012
.
0.2
0.05
.
.
.
Guaranteed Over
' Operating Temp Range
ISnA max
Zero Offset (Adjust to 0)
TEMPERATURECOEFFICIENTS
Linearity
ppm/C
Gain
..
5
OBS
DATA INPUTS
Logic Comparability
Logic Voltage Levels
V
V
BitOnLogic"I"
Bit Off Logic "0"
LogicCurrent (Each Bit)
BitOnLogic"I"
Bit Off Logic"0"
JlA
mA
MSB
OUTPUT
Current Range
Unipolar
mA
Bipolar
mA
..
TTL
"
+2 to +5.0
0 to +0.4
'
.
.
'
.
.
.
.
';;;50
-8
N/A
-5max
-10max
All Units Binary(BIN) for Unipolar,
Offset Binary (OBN) for Bipolar
n
112
INTERNAL
REFERENCE
VOLTAGE
OUT
V
4.32k
N/A
..
.
.
SETTLING TIME2
Current
ns to %.
IS to 0.4
20 to 0.10
V
:!:11to :tl6
'
mA max
mA max
%/V
105
IS
0.04
Impedance
(See Figure
n
3)
Compliance (MDH VOUT)
Load Resistance for VOUT (See Figure 5)
Oro+lV
:!:IV
Unipolar
Bipolar
Voltage
Voltage
(RL
(RL
= 300n
= 2325n
ns to %
III0pF)
ns to %
Current at Nominal-V
POWER SUPPLY REJECTION RATIO
+15V
-15V (Bipolar)
-15V (Unipolar)
TEMPERATURE RANGE
Operating
165
ECL
ECL
-0.9
-0.9
-1.7
-1.7
.
120
..
...
..
..
.
TE
0 to -15
.
-1.5, +2
-1.5, +2
'
.
'
20 to 0.10
..
.
.
.
'
.
100
'
..
.
2
Oto-15
200:!: 1%
'
+1.5,-2
750
-6.2 :!:5%
20 to 0.1
40 to 0.025
:!:14.5 to :!:16.5
55
20
'
"la/V
%/V
%/V
..
..
.
..
..
120
.
-0.0001
-0.002
-0.2
°c
-20 to +75
°c
-55 to +85
$
..
.
.
..
.
.
'
Oto+15
:!:7.5
'
'
-30 to +85
-55 to +125
Diallyl Phthalate per MIL-M-14 Type SDG-F
(1-4)
.Specifications
NOTES,
n
II 10pF)
POWER REQUIREMENTS
Range
Current at Nominal +V
Storage
CASE
PRICE
V
.'
OLE
mA
Coding
2
20
.
.
30
ppm/C
15
ppm/C
0.5
:!:%/yrmax
Offset (ipolar)
STABILITY WITH TIME
1240
CURRENT OUTPUT
MDS-E (ECL)
0815
1020
lIS
137
149
'
.
.
129
149
'
same as MDS~81S.
1 Ippmt' C for current output, Op amp is SOllY /° C. (See tables in Figures
for overall TC in various configurations.)
'For Full Scale Step.
15. 16 and 17,
'0 to +5V Out
'0 to +10V Out
See Figures 15 and 16 for test circuits.
'tSV Out
f
Specifications subject to change without notice,
Page 2 of 8
1925 D/A CONVERTERS
CURRENT OUTPUT
MDSL
1035
1250
0870
8
10
12
8
19.6
4.88
1.22
0825
...
0.2
2
20
...
0.05
2
20
VOLTAGE OUT
MDH
1001
10
1202
12
Depends on VOUT
..
..
.
0.012
2
20
..
..
0.2
0.05
0.012
lOmV
10mV
10mV
2
20
.
.
.
..
.
..
.
.
.
.
..
.
..
.
.
.
.
..
.
..
.
-1.6
-1.6
0 to +5
:t2.5
600:tl%
0 to +5
:t2.5
600:t1%
0 to +5
:t2.5
600:t 1%
300
2.325k
.
.
..
.
...
2
20
See Note 1
OBS
.
.
..
.
...
2
20
.
.
..
.
..
.
OLE
-1.6
-1.6
.
:t50 max
:t50 max
0.1 max
:t10
:t50 max
:t50 max
0.1 max
:t10
:t50 max
:t50 max
0.1 max
:t10
300
2.325k
300
2.325k
N/A
N/A
N/A
N/A
N/A
N/A
-6.2 :t5%
-6.2 :t5%
-6.2 :t5%
, -6.2 :t5%
-6.2 :t5%
-6.2 :t5%
25 to 0.1
25 to 0.1
50 to 0.25
115(00.2
25 to 0.10
50 to 0.25
45 to 0.4
70 to 0.1
75 to 0.4
100 to 0.1
70 to 0.1
80 to 0.05
100 to 0.1
110 to 0.05
90 to 0.025
100toto0.1
70
0.1
125 to 0.025
150 to 0.44
70 toto0.43
100
0.45
100 to 0.13
200 to 0.14
l30taO.15
200 to 0.0253
400 to 0.0254
250 to 0.0255
:t12to:t15
26
16
:t12to:t15
26
16
:tl2 to :tIS
26
16
:t14.5 to :t16.5
50
35
:t145 to :t16.5
50
35
:t14.5 to :t16.5
50
35
0.0001
0.001
0.2
0.0001
0.001
0.15
0.0001
0.001
0.15
0.003
0.01
0.15
0.003
0.01
0.15
0.003
0.01
0.15
-30 to +85
-55 to +125
-30 to +85
-55 to +125
-30 to +85
-55 to +125
-30 to +85
-55 to +125
-30 to +85
-55 to +125
-30 to +85
-55 to +125
112
119
129
204
214
224
-1.6
.
.
-1.6
.
.
.
I
.
.
TE
.
Page 3 of 8
~--
D/A CONVERTERS
-~
.
.~-
---
1935
Dimensions
Dimensions
shown L'1inches and (rom).
shown in inches and (mm).
2.3 (58.01
---j
1-
.L
+
0.0411.0210IA
MOS.'2..
MOSL<l825
Dimensions
0.'
110.2)
MOSL.'035
MOSL.""
G.02 10.508)
.L
I
WiIIl
T
OBS
r-°.'
12.54IGRIO
OF PIN
POSITION
,.
.
ON
TOP
INDICATES
FOSITION
I
7
2.0
(50..'
'°
0.25
I
16.4'
.L
16
,.
.-
OOTTOMVIEW
OOTTOMVIEW-11-0.'1254'GRI0
DOT
_II
-,
INDICATES
:
1
1 1 I I
(50.8)
.L
TOP
I 1 I I 1 I
3
0.25
(OA)
ON
~
12.0
L."
I
3>1
_J
a++++IIIIIIII1
23
;58.01
DOT
0.'
110.2'
MOH.I202
0.02 10.508)
:t"
321 I I I I I I I I I I I I II I. I
mil
BOTTOMVIEW
2.0""I.8)---1i
MOH.(J870MOH.'OO'.
Lo.25(...,
t1
'°
shown in inches and (mm).
r
--L
2.0 150.8)
0.43
"o.")
MO"""
MOS-'O2O
MOS-CIO'" MOS-'...'
MDH-o870, 1001, 1202
OUTLINE DIMENSIONS
MD5-1240, MDSL-O825, 1035, 1250
OUTLINE DIMENSIONS
MDS-o815, 0815E, 1020, 1020E
OUTLINE DIMENSIONS
-11-
0.1(254)
j
GRID
OOT ON TOP INDICATES POSITION OF PIN ,.
OF PIN ,.
MATING SOCKET MSA-l
MATING
SOCKET MSA-1
MATING SOCKET MSB-11713
PIN DESIGNATIONS
MDS-o81 5E, 1020E
PIN
1
2
3
4
5
6
7
8
FUNCTION
BIT 1 (MSB)
BIT 2
BIT 3
BIT4
BIT5
BIT6
BIT 7
BIT 8
PIN
9
10
11
12
13
14
15
16
FUNCTION
BIT 9
BIT 10
+15V
OFFSET
COMMON
OUTPUT
COMMON
-15V
PIN DESIGNATIONS
MDS-1240, MDSL-O825, 1035, 1250
PIN DESIGNATIONS
MD5-0815, MDS-I020
OLE
PIN
1
2
3
4
5
6
7
8
FUNCTION
BIT 1(MSBI
BIT 2
BIT3
BIT 4
BIT5
BIT 6
BIT7
BIT8
PIN
9
10
11
12
13
14
15
16
PIN
3
4
5
6
7
10
11
12
13
14
FUNCTION
BIT9
BIT 10
-15V
OFFSET
COMMON
OUTPUT
COMMON
+15V
FUNCTION
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
PIN
15
16
17
18
28
29
30
31
32
1 INPUT (MSBI
2 INPUT
3 INPUT
4 INPUT
5 INPUT
6 INPUT
7 INPUT
8 INPUT
9 INPUT
10 INPUT
FUNCTION
BIT 11 INPUT
BIT 12 INPUT
REFERENCE INPUT
REFERENCE OUTPUT
ANALOG OUTPUT
OFFSET
GROUND
-15V POWER INPUT
+15V POWER INPUT
TE
PIN DESIGNATIONS
MDH-o870, 1001, 1202
1",581
BIT 1
BIT2
DIGITAL
INPUTS
PIN
3
4
5
6
7
10
11
12
13
14
15
16
14
---COUTPUT
BIT3
BIT4
BITS
BIT6
BIT7
BITS
BIT9
12
OFFSET
COMMON
BIT 10
(lSBI
COMMON
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
FUNCTION
1 INPUT (MSB)
2 INPUT
3 INPUT
4 INPUT
5 INPUT
6 INPUT
7 INPUT
8 INPUT
9 INPUT
10 INPUT
11 INPUT
12 INPUT
MDS and MDSE Block Diagram
BIT2
DIGITAL
INPUTS
HYBRID
CURRENT
OUTPUT
DIA
CONVERTER
BIT6
BIT7
22
";8;
tlOV (MAX)
'SOMA (MAXI
25
- -IN
BIT9
OFFSET
BIT 10
FIXED
GAIN
BIT 11
+ISV
~ISV
BIT 12
ILSBI
REFINe
10 to ~.2V0 TO SMA
OUTPUT'
17
OFFSET
Z,N
= 4.641<
+ISV
-ISV
18
REF
OUT
MDS-1240 and MDSL Series Block Diagram
"-,-"""""-""-~'-",,,,,,",,"--
24 - +IN
BIT 8
HYBRID
CURRENT
OUTPUT
DIA
CONVERTER
1945 D/A CONVERTERS
gT
BIT4
BITS
CURRENT
OUTPUT
-SMA F.S.
3.16k
BIT 3
GROUND
FUNCTION
REFERENCE IfIIPUT
REFERENCE OUTPUT
ANALOG OUTPUT
+INPUT
-INPUT
FIXED GAIN
CURRENT OUTPUT
OFFSET
GROUND
-15V POWER INPUT
+15V POWER INPUT
Zo-soon '"
(M581
BIT 1
MSB
BIT 1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
BIT 12
lSB
PIN
17
18
22
24
25
26
28
29
30
31
32
REF OUT
Page 4 of 8
IS
eND
MDHSeries Block Diagram
MDH SERIES APPLICATIONS
By using external feedback resistor and capacitor as shown
in Figures 15 and 16, other full scale output ranges from 2V
to 10V may be obtained.
+1SV
.
MAVBE
OMITTED
1',
}
DIGITIAL
INPUTS
MSB
BIT 1
I
I
I
I
I
I
I
I
I
I
I
BIT 12
LSB
Vo
.
MSB
UP TO 10V >6OmA
OUTPUT CURRENT ISEE BELOWI
MDH
DIA
CONVERTER
soon
DIGITAL
INPUTS
USE INVERTER OR
FF aFaR 2'S COMPL.
DIGITAL INPUTS
I' -.
..."
24
4
'5
ill
ill
12
~~::
CONVERTER
BIT 12
LSB
-16V
+16V
NOTES'
1. VALUE OF C IS APPROXIMATE.
A FIXED
CAPACITOR
WITH TOLERANCE
OF >1pF MAV
BE USED IF 601< DEGRADATION
OF SETTLING
TIME IS PERMITTED
IF SETTLING TIME IS
TO BE OPTIMIZED,AN
ADJUSTABLE
CAPACITOR SHOULD BE USED FOR C AND ADJUSTED
FOR MINIMUM SETTLING
TIME.
2. OFFSET NULLING MAV BE ACCOMPLISHED
BV
CONNECTING
A 1Ok POTENTIOMETER
BETWEEN
+16V AND -16V, AND CONNECTING
ITS ADJUSTABLE T;.p TO A 1Ok RESISTOR.
THE OTHER END
OF THE RESISTOR
IS CONNECTED
TO PIN 2B.
TVPICAL UNCOMPENSATED
OFFSET
IS '" OF
FULL SCALE.
1. Tho 200n POTENTIOMETER
IS ADJUSTED
FOR AN CUTPUT OF -FS WITH ALL ZEROES
IN THE DIGITAL INPUT.
3. FOR TWO'S COMPLEMENT
12SC! OPERATION,
AN EXTERNAL
INVERTER
MUST BE USED TO
COMPLEMENT
BIT 1IMSBI-
2. THE soon POTENTIOMETER
IS ADJUSTED
FOR AN OUTPUT OF +F5-1LSB
WITH ALL
ONE'S IN THE DIGITAL INPUT.
4. AN ADJUSTABLE
CAPACITOR
MAV BE USED
FOR C AND ADJUSTED
TO OPTIMIZE SETTLING TIME.
OLE
VOLTAGE
OUTPUT
SETTLING
TIME
OFFSET
TEMPCO
R
0 to +2V
0 to +5V
Oto+lOV
70ns
lOOns
200ns
lOOV/C
250vfc
500V!'C
2k
8k
18k
Figure 15. Binary Coding Unipolar Output
C
VOLTAGE
OUTPUT
SETTLING
TIME
OFFSET
TEMPCO
10pF
2pF
0.5pF
:tlV
:t2V
:t5V
:tlOV
70ns
lOOns
lOOns
200ns
100V fc
200V /C
250vfc
500vfc
Configuration
Page 5 of 8
19B5 DIA CONVERTERS
+1SV
NOTES'
OBS
-16V
+INPUT
i3
i4
is
ii
ll
} FS ADJ
,,!
i
'7
fT
I
I
I
I
30 - ~~DDUTPUT
20011
OFFSET ADJ
29 _OFFSET
RL
383
383
9.1k
9.1k
C
R
lOpF
2pF
2pF
0.5pF
2k
6k
8k
18k
TE
Figure 16. Offset Binary Coding or 2'$ Comp Coding
Bipolar Output Configuration
DIGITIAL
INPUTS
MDSL
1035, 1250 continued)
(MDS-1240, MDSL-0825,
SEE
NOTE
Mse
BIT 1
I
I
I
I
I
I
I
I
I
I
I
BIT 12
LSB
soon
ZERO
OUTPUT
11V FS
DIA
CONVERTER
2.321<11(75011
MOS.I240)
GROUNO
DIGITIAL
INPUTS
REF IN
31
32
-15V
CALIBRATION
OBS
VOLTAGE OUTPUT
MDS/MDSE-81S, 1040
'.~
12
OFFSET
«::~1
BIT2~
[
I
DIA
CONVERTER
BIT S o:il
BIT 10
ILSB)
-
VOLTAGE
OUTPUT
Vou,
- R3
}
SOOI1
REF IN
OLE
DIGITAL
INPUTS
10
GROUND
18 REFOUT
FS
ADJ
EXT
4. FOR BIPOLAR
OUTPUT CONNECT
50011
POTENTIOMETER
BETWEEN
PINS 29 AND
28 AND UNGROUND
PIN 29. R2ISSE1..1O
2.32kl1,
AND VOUT (p-p) = 2 (RI IIN Wi "1,
5. CIIS
APPROXIMATELY
lOpF AND
ADJUSTED
FOR BEST TRANSIENT
MAY BE
RESPONSE,
APPLICA nONS
MDS-1240, MDSL (all)
-'5V,'5V
OUTPUT VOLTAGE
SETTLING TIME.
20no
TE
'3
MSB 3
---.
:[
MSB
I
I
I
I
I
I
I
I
I
I
I
LSB
TWO
}
..f.
OUTPUTS
UP
TO
2V
(F-p)
1
14574
INPUT
REGISTER
STROBE
STWBE
r-L
-I~~
I-
IT
11
i2
i3
14
15
LSii16
DGM
1040
MDS.
1240
R2
200n
9
NOTES ON DEGLITCHED
~6'~~6f:~~;':;;C'y"MH'
D/A,
,. CONSULT DGM DATA SHEET FOR
DEGLITCH CIRCUIT DETAILS.
2. R' IS VARIED TO OBTAIN DESIRED
OUTPUT LEVEL
FOR 0 TO'W
OUT.
RI
DIGITIAL
INPUTS
.
Figure 73. Noninverting Unipolar or Bipolar Voltage Output
Figure 77. Voltage Output
MSB
BIT I
I
I
I
I
I
I
I
I
I
I
I
BIT 12
LSB
I
DIA
CONVERTER
.
R111NkOi
+1 VOLTS FS
UNIPOLAR
110V (MAXI
AT 1100mA
R2
300n
NOTES,
,. CIRCUIT SHOWN FOR UNIPOLAR POSITIVE
OUTPUT. OUTPUT SETTLING TIME IS APPROXI.
MATELY lSOns.
2. FOR OTO +IOV OUTPUT R2- 30011, RI=Skl1.
3. R3 IS ADJUSTED FOR DESIRED OUTPUT,
RANGE IS APPROXIMATELY +5%.
PROCEDURE
Figure 70. Bipolar Current Output
I
MSB
BIT 1
I
I
I
I
I
I
I
I
I
I
I
BIT 12
LSB
+15V
WITH INPUT CODE 000000000000
ADJUST
THE SOOI1 (RI) POTENTIOMETER
FOR -1.0000
VOLTS
OUTPUT.
WITH
INPUT CODE 1111
I 1111111
ADJUST
THE 10011 (RZI POTENTIOMETER
FOR
+0.99976
VOLTS
OUTPUT.
DIGITAL
INPUTS
-15V "5\'
R1
PUT,R'. ,oon.
26
VOLTAGE
OUTPUT
(Vou,
.
-RI x 101
DIA
CONVERTER
Figure 74. Ultra High-Speed Deglitched D/A
GROUND
R3
loon
TO 1kn
REF IN
}
EXT
FS
ADJ
NOTE,
FOR UNIPOLAR
VOL TAGE OUTPUT
CONNECT
JUMPER
BETWEEN
PINS 29 AND 30. FOR BIPOLAR
VOI.TAGE
OUTPUT
CONNECT
A SOOI1 POTENTIO.
METER
BETWEEN
PINS 28 AND 29 AND ADJUST
FOR
ZERO OUTPUT
WITH 100000000000
INPUT.
/'"
Figure 72. Inverting Unipolar or Bipolar Voltage Output
Page 6 of 8
D/A CONVERTERS
-~
1975
ANALOG OUTPUT
BIPOLAR, NONINVERTING
OFFSET BINARY
111
110
100
010
000
+FS,-lLSB
+1/2 FS
0
-1/2 FS
-FS
ANALOG OUTPUT
UNIPOLAR, NONINVERTING
1
0
0
0
0
+FS,
+3/4
+ 1/2
+1/4
0
STRAIGHT
BINARY
111
110
100
010
000
-lLSB
FS
FS
FS
1
.. 0
0
0
0
Table 2. Input Coding
\
"B"
TRACE
2OMv/DIV
\
\
\
OJ!
0.1
~
0.7
§
0.6
..
"A"
TRACE
2V/DIV
OBS
.. 0.5
I
"0.4
5ns
-
Figure
\
0.3
DIV
'\.
0.2
2.
..........
0,1
INTERNAL CURRENT DAC CHARACTERISTICS
'I
1
ROFFSET
I
I
I
I
I
I
L-I
20
OLE
CURRENT
INPUT
I
,-a'To 10
J
CONTROLLED
BY
DIGITAL
CODE
I
I
I
I
I
20
2S
- MDS and MDSE
BASIC CONNECTIONS AND CALIBRATIONS
'OUTPUT
TE
MDS/MDSE-o815.1020
~~~B,J
.
BIT 2
DIGITAL
INPUTS
BIT 9
{
BIT 10
ILSBI
.2.
1
I
I
19
I
12
DIA
CONVERTER
10
Figure 7. Unipolar Output Current
,
ROFFSET
-
15
TIME.. ns
6. Accuracy vs. Time
Figure
Figure 3. Current Equivalent Circuit
r
I
10
OFFSET
GROUND
/
\
OffSET
12
\:'i~1
Zo
OUTPUT
BIT 2
L-
I
[
J
I
I
DIGITAL
INPUTS
GROUND
2
VOLTAGE CONTROLLED BY
DIGITAL INPUT CODE
BIT 9
BIT 13
ILSBI
OFFSET
~
200"
I
DIA
CONVERTER
14
i.!
1
WIl'H
INPUT CODE OF
'000000000
ADJUST
POTENTIOMETER FOR
ZERO VOLTS OUTPUT
OUTPUT
".IV MAX
Rl
10
Figure 8. Bipolar Output Current
Figure 4. Voltage Equivalent Circuit
MDS-1240,
MDSL-o825,
1035, 1250
MSB
29
GROUND
28
1.5
DIGITIAL
>
I
~
INPUTS
fT
is
>
i
0.5
I
I
I
I
I
BIT '2
lSB
DIA
CONVERTER
RL - 1!
300
350 4("",;
Figure 5. VOUT vs. Load Resistance
MDS.0815, -1020
MDS.,240
REF OUT
10011
TO
"1!
REF IN
}
EXT
FS
ADJ
32
-'5V
Tho '0011 POTENTIOMETER
MAY BE OMITTED
IF ABSOLUTE ACCURACY
OF FUll
SCALE IS
NOT REOUIRED.
IN THIS CASE PINS 17 AND
'8 SHOULD BE SHORTFD
AND THE FULL SCALE
CURRENl' WilL BE SImA .5%. IMDS 1240.
'O.2mA
'5%1
3k
2-
MDSL. ,oon
GROUND
17
-15V
250
130
'B
31
200
OUTPUT
OVTO"VFS
300n
4-
Figure 9. Unipolar Current Output
Page 7 of 8
1965 D/A CONVERTERS
"",-~;.;.~.._~
-~
~~
going inputs on all forms of saturated logic. The TTL or DTL
driving logic, and the D/A input circuits for current-switching
D/A's are subject to this same characteristic.
Thus, the time skew of the individual current switches within
the converter is worse when one or more input bits are out of
phase with the others. This is true even for ideal inputs in
which the digital inputs arrive simultaneously; if there is time
skew among the bit inputs, of course, the problem becomes
more pronounced.
(continued from page 1915)
Each DIA is housed in industry standard size cases, and each has
an internal precision reference. Bipolar operation is achieved
by external pin interconnection. In normal circumstances, no
external components are required for operation into [ow impedance loads. Designed primarily for PCB mounting, these
D/A's may also be plugged into standard DIL sockets mounted
on 1.8" centers (MDS series 2" centers).
For ultra-high reliability, this D/A series is optionally available with burn-in extended beyond the Analog Devices
standard of 96 hours at +2SoC.
Note, settling times even better than those specified for the
MDS series become possible if digital input bit arrivals are
deskewed.
NOTES ON FAST-SETTLING D/A CONVERTERS
Invariably, fast-settling D/A converters use current rather than
voltage switching.
These differences among the switches cause a discontinuity or
"glitch" in the output. The true "worst case" glitch always
occurs at the switching point of the Most Significant Bit or the
center point of the output range, because nearly equal and
opposite currents are being switched within the converter.
!n addition, all "0" to all "1" switching overlooks the practical aspects involved. There are relatively few times when all
of the input bits will be changing from one state to the other
on successive input changes; however, the MSB will switch out
of phase with all other bits each time the analog output of the
converter crosses the midpoint.
OBS
There are inherent advantages to current-switching converters,
since it eliminates an output amplifier. If there is no output
amplifier, there is no slew rate limitation which slows settling.
The absence of an output amplifier also means there are no
overshoot and ringing problems often associated with feedback amplifiers.
OLE
The settling time of a current-switching D/A converter, then,
is based on:
TE
1. The RC time constant of the converter output.
In considering the choice of a "fast-settling" D/A converter,
then, the user should look for the following points in the
data sheet:
2. The settling time of the output current change.
If the settling time of the D/A converter under consideration
is determined by the RC time consta~t, the output capacitance
and output impedance become very important.
1. If the settling time spec has all bits changing state identic~ly, it neglects the phenomenon associated with saturated
logic discussed earlier.
As a typical example in the Analog Devices' D/A converters,
output capacitance is SpF, and nominal output impedance
is 16Sn.
2. Is the settling time specified with an impractically-Iowimpedance load?
For teSt purposes, the output of these D/A converters are
loaded with approximately IS0n . (There is no "trick" or
"gimmick" in loading the output of the converter; it is done
to provide an output voltage of approximately 1.OV to 1.2V.)
This loading means RC = 80 X S X 10-12 = DAns. Since settling time is approximately 7 RC, the overall settling time, if
determined by the RC time constant, would be 2.8ns.
Based on this, it becomes obvious the RC time constant of such
converters outputs is not the limiting factor in establishing settling time. Instead, the settling time of the converters is based
primarily on the settling time of the overall (outpu t) current
change, since the effect of the RC time constant is "swamped."
Expressed in another way, this means settling time for the
MDS series converters is relatively independent of load resistance, unless substantial load capacitance is present. The settling time of the output current, in turn, is based on:
If the RC time constant of the converter output is the major
factor in establishing settling time (because of high output
capacitance and lor resistance), a low impedance load helps
make settling time look better.
A low impedance load means the voltage being dev<:loped at
the output is oftentimes too small to be useful.
A higher-impedance load which can develop a useable output
of 1.OV or more sometimes negates the fast settling time of
the spec sheet.
A test setup for this worst-case measurement is shown in Figure 1. Two pulse generators are used to generate the required
out-of-phase pulses, and the delays are adjusted for minimum
skew. Figure 2 is an unretouched photo of the oscilloscope
trance of an MDS-81S under test.
1. The settling time of each switch within the converter.
EXT. TRIG
2. The time skew among the digital inputs which cause the
switching action.
MDS.O.'S
Some manufacturers of fast-settling D/A converters spec settling time under the conditions of all digital inputs changing
from "0" to "1 H,or vice versa. At first glance, it would appear
this is the "worst case" condition for measuring settling time,
since maximum current is being switched.
Unfortunately, this method of specifying neglects an important
characteristic of saturated logic. . . the propagation delay for
negative-going inputs is different from the delay for
positivePage
8 of
OSCillOSCOPE
HIGH SPEEO
TTllOGICGATES
OR INVERTERS
SUCH AS'.H04
OR 10500 TYPE
Figure 1.
8
O/A CONVERTERS
-~~---
-
-
-~-
---
~~
-
1955