Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
Future Technology Devices
International Ltd.
FT81x
(Advanced Embedded Video Engine)
The FT81x is a series of easy to
use graphic controllers targeted at
embedded applications to generate
high-quality
Human
Machine
Interfaces (HMIs). It has the
following features:
Programmable timing to adjust HSYNC and VSYNC
timing, enabling interface to numerous displays
Support for LCD display with resolution up to SVGA
(800x600) and formats with data enable (DE) mode
or VSYNC/HSYNC mode
Support landscape and portrait orientations
Display enable control output to LCD panel
Integrated 1MByte graphics RAM, no frame buffer
RAM required
Advanced Embedded Video Engine(EVE)
with high resolution graphics and video
playback
FT81x
functionality
includes
graphic
control, audio control, and touch control
interface.
Support
videos
Mono audio channel output with PWM output
Pinout backward compatible with FT800
(FT810) and FT801 (FT811).
Built-in sound synthesizer
Support multiple widgets for simplified
design implementation
Built-in graphics operations allow users
with little expertise to create high-quality
displays
Audio wave playback for mono 8-bit linear PCM, 4bit ADPCM and µ-Law coding format at sampling
frequencies from 8kHz to 48kHz. Built-in digital filter
reduces the system design complexity of external
filtering
PWM output for display backlight dimming control
resistive
touch
playback
of
motion-JPEG
encoded
AVI
Support 4-wire
(FT810/FT812)
screen
Advanced object oriented architecture enables low
cost MPU/MCU as system host using SPI interfaces
Support capacitive touch screen with up to
5 touches detection (FT811/FT813)
Support SPI data lines in single, dual or quad mode;
SPI clock up to 30MHz
Hardware engine can recognize touch tags
and track touch movement. Provides
notification for up to 255 touch tags.
Power mode control allows the chip to be put in
power down, sleep and standby states
Enhanced sketch processing
Supports I/O voltage from 1.8V to 3.3V
Programmable interrupt controller provides
interrupts to host MCU
Internal voltage regulator supplies 1.2V to the digital
core
Built-in 12MHz crystal oscillator with PLL
providing programmable system clock up
to 60MHz
Build-in Power-on-reset circuit
-40°C to 85°C extended operating temperature
range
Clock switch command for internal or
external clock source. External 12MHz
crystal or clock input can be used for
higher accuracy.
Available in a compact Pb-free, VQFN-48 and VQFN56 package, RoHS compliant
Video RGB parallel output; configurable to
support PCLK up to 60MHz and R/G/B
output of 1 to 8 bits
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
Disclaimer:
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or
reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its
documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made
or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of
use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in
any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal
injury. This document provides preliminary information that may be subject to change without notice. No freedom to use
patents or other intellectual property rights is implied by the publication of this document.
Future Technology Devices International Ltd
Unit 1, 2 Seaward Place
Centurion Business Park
Glasgow G41 1HH
United Kingdom
Scotland Registered Company Number: SC136640
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
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Typical Applications
Point of Sales Machines
Breathalyzers
Multi-function Printers
Gas chromatographs
Instrumentation
Power meter
Home Security Systems
Home appliance devices
Graphic touch pad – remote, dial pad
Set-top box
Tele / Video Conference Systems
Thermostats
Phones and Switchboards
Sprinkler system displays
Medical Appliances
Medical Appliances
Blood Pressure displays
GPS / Satnav
Heart monitors
Vending Machine Control Panels
Glucose level displays
Elevator Controls
……and many more
1.1 Part Numbers
Part Number
Description
Package
FT810Q-x
EVE with 18 bit RGB, resistive touch
48 Pin VQFN, body 7 x 7 mm, pitch 0.5mm
FT811Q-x
EVE with 18 bit RGB, capacitive touch
48 Pin VQFN, body 7 x 7 mm, pitch 0.5mm
FT812Q-x
EVE with 24 bit RGB, resistive touch
56 Pin VQFN, body 8 x 8 mm, pitch 0.5mm
FT813Q-x
EVE with 24 bit RGB, capacitive touch
56 Pin VQFN, body 8 x 8 mm, pitch 0.5mm
Table 1- FT81x Embedded Video Engine Part Numbers
Note: Packaging codes for x is:
-R: Taped and Reel (3000pcs per reel)
-T: Tray packing (260 pcs per tray for VQFN-48, 348 pcs per tray for VQFN-56)
For example: FT810Q-R is 3000 VQFN pieces in taped and reel packaging
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
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Block Diagram
Figure 2-1 FT81x Block Diagram
For a description of each function please refer to Section 4.
Figure 2-2 FT81x System Design Diagram
FT81x with EVE (Embedded Video Engine) technology simplifies the system architecture for advanced
human machine interfaces (HMIs) by providing support for display, audio, and touch as well as an object
oriented architecture approach that extends from display creation to the rendering of the graphics.
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
Contents
1
Typical Applications ...................................................................... 3
1.1
Part Numbers...................................................................................... 3
2
Block Diagram .............................................................................. 4
3
Device Pin Out and Signal Description .......................................... 7
3.1
FT810 VQFN-48 Package Pin Out ........................................................ 7
3.2
FT811 VQFN-48 Package Pin Out ........................................................ 7
3.3
FT812 VQFN-56 Package Pin Out ........................................................ 8
3.4
FT813 VQFN-56 Package Pin Out ........................................................ 8
3.5
Pin Description ................................................................................... 9
4
Function Description................................................................... 13
4.1
Quad SPI Host Interface ................................................................... 13
4.1.1
QSPI Interface........................................................................................................... 13
4.1.2
Serial Data Protocol ................................................................................................... 15
4.1.3
Host Memory Read ..................................................................................................... 15
4.1.4
Host Memory Write .................................................................................................... 16
4.1.5
Host Command .......................................................................................................... 16
4.1.6
Interrupts ................................................................................................................. 20
4.2
System Clock .................................................................................... 20
4.2.1
Clock Source ............................................................................................................. 20
4.2.2
Phase Locked Loop..................................................................................................... 21
4.2.3
Clock Enable ............................................................................................................. 21
4.2.4
Clock Frequency ........................................................................................................ 22
4.3
Graphics Engine ................................................................................ 22
4.3.1
Introduction .............................................................................................................. 22
4.3.2
ROM and RAM Fonts ................................................................................................... 22
4.4
Parallel RGB Interface ...................................................................... 26
4.5
Miscellaneous Control ....................................................................... 28
4.5.1
Backlight Control Pin .................................................................................................. 29
4.5.2
DISP Control Pin ........................................................................................................ 29
4.5.3
General Purpose IO pins ............................................................................................. 29
4.5.4
Pins Drive Current Control .......................................................................................... 29
4.6
Audio Engine..................................................................................... 30
4.6.1
Sound Synthesizer ..................................................................................................... 30
4.6.2
Audio Playback .......................................................................................................... 32
4.7
Touch-Screen Engine ........................................................................ 32
4.7.1
Resistive Touch Control .............................................................................................. 32
4.7.2
Capacitive Touch Control ............................................................................................ 33
4.7.3
Compatibility mode .................................................................................................... 34
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4.7.4
Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
Extended mode ......................................................................................................... 34
4.7.5
Short-circuit protection ............................................................................................... 35
4.7.6
Capacitive touch configuration ..................................................................................... 35
4.7.7
Touch detection in none-ACTIVE state .......................................................................... 35
4.8
Power Management .......................................................................... 35
4.8.1
Power supply............................................................................................................. 35
4.8.2
Internal Regulator and POR ......................................................................................... 36
4.8.3
Power Modes ............................................................................................................. 37
4.8.4
Reset and boot-up sequence ....................................................................................... 38
4.8.5
Pin Status at Different Power States ............................................................................. 38
5
Memory Map ............................................................................... 40
5.1
Registers .......................................................................................... 40
5.2
Chip ID ............................................................................................. 45
6
Devices Characteristics and Ratings ........................................... 46
6.1
Absolute Maximum Ratings............................................................... 46
6.2
ESD and Latch-up Specifications ....................................................... 46
6.3
DC Characteristics............................................................................. 46
6.4
AC Characteristics ............................................................................. 49
6.4.1
System clock and reset............................................................................................... 49
6.4.2
SPI interface timing ................................................................................................... 49
6.4.3
RGB Interface Timing ................................................................................................. 50
7
Application Examples ................................................................. 52
8
Package Parameters ................................................................... 54
9
8.1
VQFN-48 Package Dimensions .......................................................... 54
8.2
VQFN-56 Package Dimensions .......................................................... 54
8.3
Solder Reflow Profile ........................................................................ 55
Contact Information ................................................................... 56
Appendix A – References ........................................................................... 57
Appendix B - List of Figures and Tables ..................................................... 58
Appendix C - Revision History .................................................................... 60
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
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Device Pin Out and Signal Description
3.1 FT810 VQFN-48 Package Pin Out
Figure 3-1 Pin Configuration FT810 VQFN-48 (top view)
3.2 FT811 VQFN-48 Package Pin Out
Figure 3-1 Pin Configuration FT811 VQFN-48 (top view)
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
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3.3 FT812 VQFN-56 Package Pin Out
Figure 3-1 Pin Configuration FT812 VQFN-56 (top view)
3.4 FT813 VQFN-56 Package Pin Out
Figure 3-1 Pin Configuration FT813 VQFN-56 (top view)
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
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3.5 Pin Description
Table 3-1 FT81x pin description
Pin Number
Pin Name
Type
FT810
FT811
FT812
FT813
-
-
1
1
R1
O
-
-
2
2
R0
O
1
1
3
3
AUDIO_L
O
2
2
4
4
GND
P
3
3
5
5
SCK
I
4
4
6
6
MISO/IO1
I/O
Description
Bit 1 of Red RGB signals
Powered from pin VCCIO2
Bit 0 of Red RGB signals
Powered from pin VCCIO2
Audio PWM out
Powered from pin VCC
Ground
SPI clock input
Powered from pin VCCIO1
SPI Single mode: SPI MISO output
SPI Dual/Quad mode: SPI data line 1
Powered from pin VCCIO1
SPI Single mode: SPI MOSI input
5
5
7
7
MOSI/IO0
I/O
SPI Dual/Quad mode: SPI data line 0
Powered from pin VCCIO1
SPI slave select input
6
6
8
8
CS_N
I
Powered from pin VCCIO1
SPI Single/Dual mode: General purpose IO 0
7
7
9
9
GPIO0/IO2
I/O
SPI Quad mode: SPI data line 2
Powered from pin VCCIO1
SPI Single/Dual mode: General purpose IO 1
8
8
10
10
GPIO1/IO3
I/O
SPI Quad mode: SPI data line 3
Powered from pin VCCIO1
9
9
11
11
VCCIO1
P
10
10
12
12
GPIO2
I/O
11
11
13
13
INT_N
OD/
O
I/O power supply for host interface pins.
Support 1.8V, 2.5V or 3.3V.
General purpose IO 2
12
12
14
14
PD_N
I
Powered from pin VCCIO1
Interrupt to host, open drain output(default) or
push-pull output, active low
Chip power down mode control input, active
low. Connect to MCU GPIO for power
management or hardware reset function, or
pulled up to VCCIO1 through 47kΩ resistor and
100nF to ground.
Powered from pin VCCIO1
General purpose IO 3
-
-
15
15
GPIO3
I/O
Powered from pin VCCIO1
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
Pin Number
Pin Name
FT810
FT811
FT812
Type
Description
FT813
Crystal oscillator or clock input; Connect to
GND if not used.
13
13
16
16
X1/CLK
I
3.3V peak input allowed.
Powered from pin VCC.
14
14
17
17
X2
O
Crystal oscillator output; leave open if not
used.
Powered from pin VCC.
15
15
18
18
GND
P
Ground
16
16
19
19
VCC
P
3.3V power supply input.
17
17
20
20
VOUT1V2
O
1.2V regulator output pin. Connect a 4.7uF
decoupling capacitor to GND.
21
21
VCC
P
3.3V power supply input.
I/O power supply for RGB and touch pins.
18
For QFN-48 package, VCCIO2 is bonded
together with VCC pin;
18
22
19
22
23
VCCIO2
XP
P
AI/O
For QFN-56 package, VCCIO2 is separate from
VCC pin. VCCIO2 supports 1.8V, 2.5V or 3.3V.
VCCIO2 can be connected to different voltage
with VCCIO1.
Connect to X right electrode of 4-wire resistive
touch-screen panel.
Powered from pin VCCIO2.
20
24
YP
AI/O
Connect to Y top electrode of 4-wire resistive
touch-screen panel.
Powered from pin VCCIO2.
21
25
XM
AI/O
Connect to X left electrode of 4-wire resistive
touch-screen panel.
Powered from pin VCCIO2.
22
26
YM
AI/O
Connect to Y bottom electrode of 4-wire
resistive touch-screen panel.
Powered from pin VCCIO2.
Connect to reset pin of the CTPM.
-
19
-
23
CTP_RST_N
O
-
20
-
24
CTP_INT_N
I
-
21
-
25
CTP_SCL
I/OD
-
22
-
26
CTP_SDA
I/OD
23
23
27
27
GND
P
Ground
24
24
28
28
BACKLIGHT
O
LED Backlight brightness PWM control signal.
Powered from pin VCCIO2.
Connect to interrupt pin of the CTPM.
Powered from pin VCCIO2.
Connect to I2C SCL pin of the CTPM.
Powered from pin VCCIO2.
Connect to I2C SDA pin of the CTPM.
Powered from pin VCCIO2.
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Datasheet Version 1.2
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Pin Number
Pin Name
FT810
FT811
FT812
Type
Description
FT813
Powered from pin VCCIO2.
LCD Data Enable.
25
25
29
29
DE
O
26
26
30
30
VSYNC
O
27
27
31
31
HSYNC
O
28
28
32
32
DISP
O
29
29
33
33
PCLK
O
30
30
34
34
B7
O
31
31
35
35
B6
O
32
32
36
36
B5
O
33
33
37
37
B4
O
34
34
38
38
B3
O
35
35
39
39
B2
O
-
-
40
40
B1
O
-
-
41
41
B0
O
36
36
42
42
GND
P
37
37
43
43
G7
O
38
38
44
44
G6
O
39
39
45
45
G5
O
40
40
46
46
G4
O
41
41
47
47
G3
O
Powered from pin VCCIO2.
LCD Vertical Sync.
Powered from pin VCCIO2.
LCD Horizontal Sync.
Powered from pin VCCIO2.
LCD Display Enable.
Powered from pin VCCIO2.
LCD Pixel Clock.
Powered from pin VCCIO2.
Bit 7 of Blue RGB signals.
Powered from pin VCCIO2.
Bit 6 of Blue RGB signals.
Powered from pin VCCIO2.
Bit 5 of Blue RGB signals.
Powered from pin VCCIO2.
Bit 4 of Blue RGB signals.
Powered from pin VCCIO2.
Bit 3 of Blue RGB signals.
Powered from pin VCCIO2.
Bit 2 of Blue RGB signals.
Powered from pin VCCIO2.
Bit 1 of Blue RGB signals.
Powered from pin VCCIO2.
Bit 0 of Blue RGB signals.
Powered from pin VCCIO2.
Ground
Bit 7 of Green RGB signals.
Powered from pin VCCIO2.
Bit 6 of Green RGB signals.
Powered from pin VCCIO2.
Bit 5 of Green RGB signals.
Powered from pin VCCIO2.
Bit 4 of Green RGB signals.
Powered from pin VCCIO2.
Bit 3 of Green RGB signals.
Powered from pin VCCIO2.
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
Pin Number
Pin Name
Type
FT810
FT811
FT812
FT813
42
42
48
48
G2
O
-
-
49
49
G1
O
-
-
50
50
G0
O
43
43
51
51
R7
O
44
44
52
52
R6
O
45
45
53
53
R5
O
46
46
54
54
R4
O
47
47
55
55
R3
O
48
48
56
56
R2
O
EP
EP
EP
EP
GND
P
Description
Bit 2 of Green RGB signals.
Powered from pin VCCIO2.
Bit 1 of Green RGB signals.
Powered from pin VCCIO2.
Bit 0 of Green RGB signals.
Powered from pin VCCIO2.
Bit 7 of Red RGB signals.
Powered from pin VCCIO2.
Bit 6 of Red RGB signals.
Powered from pin VCCIO2.
Bit 5 of Red RGB signals.
Powered from pin VCCIO2.
Bit 4 of Red RGB signals.
Powered from pin VCCIO2.
Bit 3 of Red RGB signals.
Powered from pin VCCIO2.
Bit 2 of Red RGB signals.
Powered from pin VCCIO2.
Ground. Exposed thermal pad.
Note:
P
: Power or ground
I
: Input
O
: Output
OD : Open drain output
I/O : Bi-direction Input and Output
AI/O: Analog Input and Output
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FT81X Embedded Video Engine
Datasheet Version 1.2
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4
Function Description
The FT81x is a single chip, embedded video controller with the following function blocks:
Quad SPI Host Interface
System Clock
Graphics Engine
Parallel RGB video interface
Audio Engine
Touch-screen support and interface
Power Management
The functions for each block are briefly described in the following subsections.
4.1 Quad SPI Host Interface
The FT81x uses a quad serial parallel interface (QSPI) to communicate with host microcontrollers and
microprocessors.
4.1.1 QSPI Interface
The QSPI slave interface operates up to 30MHz. Only SPI mode 0 is supported. Refer to section 6.4.2 for
detailed timing specification. The QSPI can be configured as a SPI slave in SINGLE, DUAL or QUAD
channel modes.
By default the SPI slave operates in the SINGLE channel mode with MOSI as input from the master and
MISO as output to the master. DUAL and QUAD channel modes can be configured through the SPI slave
itself. To change the channel modes, write to register REG_SPI_WIDTH. The table below depicts the
setting.
Table 4-1 QSPI channel selection
REG_SPI_WIDTH[1:0]
Channel Mode
Data pins
Max bus speed
00
SINGLE – default mode
MISO, MOSI
30 MHz
01
DUAL
IO0, IO1
30 MHz
10
QUAD
IO0, IO1, IO2, IO3
25 MHz
11
Reserved
-
-
With DUAL/QUAD channel modes, the SPI data ports are now unidirectional. In these modes, each SPI
transaction (signified by CS_N going active low) will begin with the data ports set as inputs.
Hence, for writing to the FT81x, the protocol will operate as in FT800, with “WR-Command/Addr2, Addr1,
Addr0, DataX, DataY, DataZ …” The write operation is considered complete when CS_N goes inactive
high.
For reading from the FT81x, the protocol will still operate as in FT800, with “RD-Command/Addr2, Addr1,
Addr0, Dummy-Byte, DataX, DataY, DataZ”. However as the data ports are now unidirectional, a change
of port direction will occur before DataX is clocked out of the FT81x. Therefore it is important that the
firmware controlling the SPI master changes the SPI master data port direction to “input” after
transmitting Addr0. The FT81x will not change the port direction till it starts to clock out DataX. Hence,
the Dummy-Byte cycles will be used as a change-over period when neither the SPI master nor slave will
be driving the bus; the data paths thus must have pull-ups/pull-downs. The SPI slave from the FT81x will
reset all its data ports’ direction to input once CS_N goes inactive high (i.e. at the end of the current SPI
master transaction).
The diagram depicts the behaviour of both the SPI master and slave in the master read case.
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SS
WR /
Addr2
Addr
1
Addr
2
Dum
my
Data
X
Data
0
SPI Slave drives the
data bus
SPI Slave resets data
ports into inputs
SPI Master drives
the data bus
Bus not
driven
SPI Master changes
data ports into inputs
Data
Y
SPI Slave changes
data ports into outputs
Figure 4-1 SPI master and slave in the master read case
In the DUAL channel mode, MISO (MSB) and MOSI are used while in the QUAD channel mode. IO3
(MSB), IO2, MISO and MOSI are used.
Figure 4-2 illustrates a direct connection to a 1.8-3.3V IO MPU/MCU with single or dual SPI interface.
Figure 4-3 illustrates a direct connection to a 1.8-3.3V IO MPU/MCU with Quad SPI interface.
1.8-3.3V
MPU/MCU
SCLK
3.3V
VCCIO1
4.7k
FT81x
SCK
MISO
MISO/IO1
MOSI
MOSI/IO0
SS#
CS_N
PD#
PD_N
INT#
INT_N
GND
VCC
GND
Figure 4-2 Single/Dual SPI Interface connection
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Datasheet Version 1.2
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1.8-3.3V
3.3V
VCCIO1
MPU/MCU
4.7k
VCC
FT81x
SCLK
SCK
MISO
IO1
MOSI
IO0
IO2
IO2
IO3
IO3
SS#
CS_N
PD#
PD_N
INT#
INT_N
GND
GND
Figure 4-3 Quad SPI Interface connection
4.1.2 Serial Data Protocol
The FT81x appears to the host MPU/MCU as a memory-mapped SPI device. The host communicates with
the FT81x using reads and writes to a large (4 megabyte) address space. Within this address space are
dedicated areas for graphics, audio and touch control. Refer to section 5 for the detailed memory map.
The host reads and writes the FT81x address space using SPI transactions. These transactions are
memory read, memory write and command write. Serial data is sent by the most significant bit first.
Each transaction starts with CS_N goes low, and ends when CS_N goes high. There’s no limit on data
length within one transaction, as long as the memory address is continuous.
4.1.3 Host Memory Read
For SPI memory read transactions, the host sends two zero bits, followed by the 22-bit address. This is
followed by a dummy byte. After the dummy byte, the FT81x responds to each host byte with read data
bytes.
Table 4-2 Host memory read transaction
7
6
0
0
5
4
3
2
1
0
Address [21:16]
Address [15:8]
Write
Address
Address [7:0]
Dummy byte
Byte 0
Read Data
Byte n
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4.1.4 Host Memory Write
For SPI memory write transactions, the host sends a ‘1’ bit and ‘0’ bit, followed by the 22-bit address.
This is followed by the write data.
Table 4-3 Host memory write transaction
7
6
1
0
5
4
3
2
1
0
Address [21:16]
Write
Address
Address [15:8]
Address [7:0]
Byte 0
Write Data
Byte n
4.1.5 Host Command
When sending a command, the host transmits a 3 byte command. Table 4-5 Host command lists all the
host command functions.
For SPI command transactions, the host sends a ‘0’ bit and ‘1’ bit, followed by the 6-bit command code.
The 2nd byte can be either 00h, or the parameter of that command. The 3rd byte is fixed at 00h.
All SPI commands except the system reset can only be executed when the SPI is in the Single channel
mode. They will be ignored when the SPI is in either Dual or Quad channel mode.
Some commands are used to configure the device and these configurations will be reset upon receiving
the SPI PWRDOWN command, except those that configure the pin state during power down. These
commands will be sticky unless reconfigured or power-on-reset (POR) occurs.
Table 4-4 Host command transaction
7
6
0
1
5
4
3
2
1
0
Command [5:0]
1st Byte
2nd Byte
Parameter for the command
0
0
0
0
0
0
0
0
3rd Byte
Table 4-5 Host command list
1st Byte
2nd byte
3rd byte
Command
Description
Power Modes
00000000b
00000000b
00000000b
00h
ACTIVE
Switch from Standby/Sleep/PWRDOWN
modes to active mode. Dummy memory
read from address 0(read twice) generates
ACTIVE command.
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1st Byte
2nd byte
3rd byte
Command
Description
01000001b
00000000b
00000000b
41h
STANDBY
01000010b
00000000b
00000000b
42h
SLEEP
Put FT81x core to standby mode. Clock gate
off, PLL and Oscillator remain on (default).
ACTIVE command to wake up.
Put FT81x core to sleep mode. Clock gate
off, PLL and Oscillator off. ACTIVE command
to wake up.
00000000b
00000000b
43h/50h
PWRDOWN
01000011b
01010000b
Switch off 1.2V core voltage to the digital
core circuits. Clock, PLL and Oscillator off.
SPI is alive. ACTIVE command to wake up.
Select power down individual ROMs; Byte2
determines which ROM to power down or
up. A 1 on a bit powers down the
corresponding block; a 0 on a bit powers up
the corresponding block. As these are not
readable, the host must remember the
setting on its own.
01000100b
xx
00000000b
49h
PD_ROMS
Byte2[7]
ROM_MAIN
Byte2[6]
ROM_RCOSATAN
Byte2[5]
ROM_SAMPLE
Byte2[4]
ROM_JABOOT
Byte2[3]
ROM_J1BOOT
Byte2[20]
reserved
Clock and Reset
01000100b
00000000b
00000000b
44h
CLKEXT
01001000b
00000000b
00000000b
48h
CLKINT
Select PLL input from external crystal
oscillator or external input clock. No effect if
external clock is already selected, otherwise
a system reset will be generated
Select PLL input from internal relaxation
oscillator (default). No effect if internal clock
is already selected, otherwise a system
reset will be generated
This command will only be effective when
the PLL is stopped (SLEEP mode).
For compatibility to FT800/FT801, set Byte2
to 0x00. This will set the PLL clock back to
default (60 MHz).
01100001b
01100010b
xx
00000000b
61h/62h
CLKSEL
Byte2
[5:0]
sets the clock frequency
0
Set to default clock speed
1
Reserved
2 to 5
2 to 5 times the osc
frequency (i.e. 24 to 60MHz
with 12MHz oscillator)
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1st Byte
01101000b
2nd byte
00000000b
3rd byte
00000000b
Command
68h
RST_PULSE
Description
Byte2
[7:6]
sets the PLL range
0
When Byte2[5:0] = 0, 2, 3
1
When Byte2[5:0] = 4, 5
Send reset pulse to FT81x core. The
behaviour is the same as POR except that
settings done through SPI commands will
not be affected
Configuration
This will set the drive strength for various
pins. For FT800/FT801 compatibility, by
default those settings are from the GPIO
registers. FT81x supports setting the drive
strength via SPI command instead.
When PINDRIVE for a pin from the SPI
command is not updated, the drive strength
will be determined by its corresponding
GPIO register bits, if they exist. If they don’t
exist, a hard coded setting is used. Please
refer to Table 4-20 for default values.
When PINDRIVE for a pin from the SPI
command is updated, it will override the
corresponding setting in the GPIO register
bits.
Byte2 determines which pin and the setting
are to be updated.
Byte2[1:0] determine the drive strength:
01110000b
xx
00000000b
70h
PINDRIVE
Byte2
[1:0]
Drive Strength
0h
5mA
1h
10.0mA
2h
15.0mA
3h
20.0mA
Byte[7:2] determine which pin/pin group to
set:
Byte2
[7:2]
Pin / Pin Group
00h
GPIO 0
01h
GPIO 1
02h
GPIO 2
03h
GPIO 3
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1st Byte
2nd byte
3rd byte
Command
Description
04-07h
Reserved
08h
DISP
09h
DE
0Ah
VSYNC / HSYNC
0Bh
PCLK
0Ch
BACKLIGHT
0Dh
R[7:0], G[7:0], B[7:0]
0Eh
AUDIO_L
0Fh
INT_N
10h
CTP_RST_N
11h
CTP_SCL
12h
CTP_SDA
13h
SPI MISO/MOSI/IO2/IO3
Others
Reserved
Note: GPIO0 shares the same pin as SPI
IO2 and GPIO1 with SPI IO3. When SPI is
set in Quad mode, IO2 and IO3 will inherit
the drive strength set in GROUP 13h;
otherwise GPIO0 and GPIO1 will inherit the
drive strength from GROUP 00h and 01h
respectively.
During power down, all output and in/out
pins will not be driven. Please refer to Table
4-20 for their default power down state.
01110001b
xx
00000000b
71h
PIN_PD_STA
TE
These settings will only be effective during
power down and will not affect normal
operations.
Also
note
that
these
configuration bits are sticky and, unlike
other configuration bits, will not reset to
default values upon exiting power down.
Only POR will reset them.
Byte2 determines which pin and the setting
are to be updated.
Byte2[1:0] determine the pin state.
Byte2 [1:0]
Pin Setting
0h
Float
1h
Pull-Down
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1st Byte
2nd byte
3rd byte
Command
Description
2h
Pull-Up
3h
Reserved
Byte2[7:2] determine which pin/pin group
to set.
Please refer to the
PINDRIVE entry.
table
in
command
NOTE: Any command code not specified is reserved and should not be used by the software
4.1.6 Interrupts
The interrupt output pin is enabled by REG_INT_EN. When REG_INT_EN is 0, INT_N is tri-state (pulled to
high by external pull-up resistor). When REG_INT_EN is 1, INT_N is driven low when any of the interrupt
flags in REG_INT_FLAGS are high, after masking with REG_INT_MASK. Writing a ‘1’ in any bit of
REG_INT_MASK will enable the corresponding interrupt. Each bit in REG_INT_FLAGS is set by a
corresponding interrupt source. REG_INT_FLAGS is readable by the host at any time, and clears when
read.
The INT_N pin is open-drain (OD) output by default. It can be configured to push-pull output by register
REG_GPIOX.
Table 4-6 Interrupt Flags bit assignment
Bit
7
6
5
4
Interrupt Sources
CONVCOMPLETE
CMDFLAG
CMDEMPTY
PLAYBACK
Conditions
Touch-screen
conversions
completed
Command FIFO
flag
Command FIFO
empty
Audio playback
ended
Bit
3
2
1
0
Interrupt Sources
SOUND
TAG
TOUCH
SWAP
Conditions
Sound effect
ended
Touch-screen tag
value change
touch detected
Display list swap
occurred
4.2 System Clock
4.2.1 Clock Source
The FT81x can be configured to use any of the three clock sources for system clock:
Internal relaxation oscillator clock (default)
External 12MHz crystal
External 12MHz square wave clock
Figure 4-4, Figure 4-5 and Figure 4-6 show the pin connections for these clock options.
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Figure 4-4 Internal relaxation oscillator connection
Figure 4-5 Crystal oscillator connection
Figure 4-6 External clock input
4.2.2 Phase Locked Loop
The internal PLL takes an input clock from the oscillator, and generates clocks to all internal circuits,
including the graphics engine, audio engine and touch engine.
4.2.3 Clock Enable
At power-on the FT81x enters sleep mode. The internal relaxation oscillator is selected for the PLL clock
source. The system clock will be enabled when the following step is executed:
Host sends an “ACTIVE” command
If the application chooses to use the external clock source (12MHz crystal or clock), the following steps
shall be executed:
Host sends a “CLKEXT” command
Host sends an “ACTIVE” command
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4.2.4 Clock Frequency
By default the system clock is 60MHz when the input clock is 12MHz. The host is allowed to switch the
system clock to other frequencies (48MHz, 36MHz, 24MHz) by the host command “CLKSEL”. The clock
switching command shall be sent in SLEEP mode only.
When using the internal relaxation oscillator, its clock frequency is trimmed to be 12MHz at factory.
Software is allowed to change the frequency to a lower value by programming the register REG_TRIM.
Note that software shall not change the internal oscillator frequency to be higher than 12MHz.
4.3 Graphics Engine
4.3.1 Introduction
The graphics engine executes the display list once for every horizontal line. It executes the primitive
objects in the display list and constructs the display line buffer. The horizontal pixel content in the line
buffer is updated if the object is visible at the horizontal line.
Main features of the graphics engine are:
The primitive objects supported by the graphics processor are: lines, points, rectangles, bitmaps
(comprehensive set of formats), text display, plotting bar graph, edge strips, and line strips, etc.
Operations such as stencil test, alpha blending and masking are useful for creating a rich set of
effects such as shadows, transitions, reveals, fades and wipes.
Anti-aliasing of the primitive objects (except bitmaps) gives a smoothing effect to the viewer.
Bitmap transformations enable operations such as translate, scale and rotate.
Display pixels are plotted with 1/16th pixel precision.
Four levels of graphics states
Tag buffer detection
The graphics engine also supports customized built-in widgets and functionalities such as jpeg decode,
screen saver, calibration etc. The graphics engine interprets commands from the MPU host via a 4 Kbyte
FIFO in the FT81x memory at RAM_CMD. The MPU/MCU writes commands into the FIFO, and the graphics
engine reads and executes the commands. The MPU/MCU updates the register REG_CMD_WRITE to
indicate that there are new commands in the FIFO, and the graphics engine updates REG_CMD_READ
after commands have been executed.
Main features supported are:
Drawing of widgets such as buttons, clock, keys, gauges, text displays, progress bars, sliders,
toggle switches, dials, gradients, etc.
JPEG and motion-JPEG decode
Inflate functionality (zlib inflate is supported)
Timed interrupt (generate an interrupt to the host processor after a specified number of
milliseconds)
In-built animated functionalities such as displaying logo, calibration, spinner, screen saver and
sketch
Snapshot feature to capture the current graphics display
For
a
complete
list
of
graphics
engine
FT81x_Series_Programmer_Guide, Chapter 4.
display
commands
and
widgets
refer
to
4.3.2 ROM and RAM Fonts
The FT81x has built in ROM character bitmaps as font metrics. The graphics engine can use these metrics
when drawing text fonts. There are a total of 19 ROM fonts, numbered with font handle 16-34. The user
can define and load customized font metrics into RAM_G, which can be used by display command with
handle 0-15.
Each font metric block has a 148 byte font table which defines the parameters of the font and the pointer
of font image. The font table format is shown in Table 4-7.
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Table 4-7 Font table format
Address Offset
0
128
132
136
140
144
Size(byte)
128
4
4
4
4
4
Parameter Description
width of each font character, in pixels
font bitmap format, for example L1, L4 or L8
font line stride, in bytes
font width, in pixels
font height, in pixels
pointer to font image data in memory
The ROM fonts are stored in the memory space ROM_FONT. The ROM font table is also stored in the
ROM. The starting address of the ROM font table for font index 16 is stored at ROM_FONT_ADDR, with
other font tables following. The ROM font table and individual character width (in pixel) are listed in Table
4-8 through Table 4-10. Font index 16, 18 and 20-31 are for basic ASCII characters (code 0-127), while
font index 17 and 19 are for Extended ASCII characters (code 128-255). The character width for font
index 16 through 19 is fixed at 8 pixels for any of the ASCII characters.
Table 4-8 ROM font table
2
6
L
4
2
7
L
4
2
8
L
4
Line stride
1
1
1
1
2
2
2
3
3
4
7
8
9
Font width
(max)
8
8
8
8
1
1
1
3
1
7
1
8
2
5
3
4
1
3
1
5
Font height
8
8
1
6
1
6
1
3
1
7
2
0
2
2
2
9
3
8
1
6
Image
pointer start
address
(hex)
2FE7FC
2FEFFC
2FDAFC
2FCD3C
2F3D1C
2F181C
2FA17C
3
2
L
4
2
3
4
9
3
3
L
4
3
0
6
3
2
0
2
5
2
8
3
6
4
9
6
3
8
3
2
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
4
L
4
3
9
8
2
1
0
8
1E1B5C
2
5
L
1
251E1C
2
4
L
1
2945FC
2
3
L
1
2BAC3C
2
2
L
1
2D263C
2
1
L
1
2FFBFC
3
1
L
4
1
8
3
7
2DFBBC
2
0
L
1
2FF7FC
1
9
3
0
L
4
1
4
2
8
2E799C
1
9
L
1
Font format
2
9
L
4
1
1
2
1
2ED61C
1
8
L
1
2F7E3C
1
7
L
1
2FBD7C
1
6
L
1
Font Index
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-9 ROM font ASCII character width in pixels
ASCII Character width in pixels
Font Index
=>
0
NULL
1
SOH
2
STX
3
ETX
4
EOT
5
ENQ
6
ACK
7
BEL
8
BS
9
HT
10
LF
11
VT
12
FF
13
CR
14
SO
15
SI
16
DLE
17
DC1
18
DC2
19
DC3
20
DC4
16/
18
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Copyright © 2015 Future Technology Devices International Limited
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
23
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Font Index
=>
21
NAK
22
SYN
23
ETB
24
CAN
25
EM
26
SUB
27
ESC
28
FS
29
GS
30
RS
31
US
spac
32
e
33
!
34
"
35
#
36
$
37
%
38
&
39
'
40
(
41
)
42
*
43
+
44
,
45
46
.
47
/
48
0
49
1
50
2
51
3
52
4
53
5
54
6
55
7
56
8
57
9
58
:
59
;
60
<
61
=
62
>
63
?
64
@
65
A
66
B
67
C
68
D
69
E
70
F
71
G
72
H
73
I
74
J
75
K
16/
18
8
8
8
8
8
8
8
8
8
8
8
2
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
0
0
0
0
0
0
0
0
0
0
2
2
0
0
0
0
0
0
0
0
0
0
0
2
3
0
0
0
0
0
0
0
0
0
0
0
2
4
0
0
0
0
0
0
0
0
0
0
0
2
5
0
0
0
0
0
0
0
0
0
0
0
2
6
0
0
0
0
0
0
0
0
0
0
0
2
7
0
0
0
0
0
0
0
0
0
0
0
2
8
0
0
0
0
0
0
0
0
0
0
0
2
9
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
0
3
1
0
0
0
0
0
0
0
0
0
0
0
3
2
0
0
0
0
0
0
0
0
0
0
0
3
3
0
0
0
0
0
0
0
0
0
0
0
3
4
0
0
0
0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3
3
4
6
6
9
8
2
4
4
4
6
3
4
3
3
6
6
6
6
6
6
6
6
6
6
3
3
6
5
6
6
11
7
7
8
8
7
6
8
8
3
5
7
4
4
5
8
8
12
10
3
5
5
7
9
3
4
3
4
8
8
8
8
8
8
8
8
8
8
3
4
8
9
8
8
13
9
9
10
10
9
8
11
10
4
7
9
5
5
6
9
9
14
11
3
6
6
6
10
4
5
4
5
9
9
9
9
9
9
9
9
9
9
4
4
10
10
10
9
17
11
11
12
12
11
10
13
12
4
8
11
5
6
5
10
10
16
13
3
6
6
7
10
5
6
5
5
10
10
10
10
10
10
10
10
10
10
5
5
10
11
10
10
18
13
13
14
14
13
12
15
14
6
10
13
6
6
8
14
13
22
17
6
8
8
10
14
6
8
6
7
13
13
13
13
13
13
13
13
13
13
6
6
15
15
15
12
25
17
17
18
18
16
14
19
18
8
13
18
9
9
12
19
18
29
22
6
11
11
13
19
9
11
9
9
18
18
18
18
18
18
18
18
18
18
9
9
19
19
19
18
34
22
22
24
24
22
20
25
24
9
16
22
3
3
5
10
8
11
9
3
5
5
7
9
3
6
3
6
8
8
8
8
8
8
8
8
8
8
3
3
8
8
8
7
13
9
9
9
9
7
7
9
9
4
8
9
4
4
6
11
10
13
11
4
6
6
8
10
4
7
4
7
10
10
10
10
10
10
10
10
10
10
4
4
9
9
9
9
15
11
10
11
11
9
9
11
11
5
9
11
5
6
7
14
11
16
14
4
7
8
10
12
4
10
6
9
12
12
12
12
12
12
12
12
12
12
6
6
11
13
11
10
19
13
14
13
14
12
12
14
15
6
12
14
6
6
8
15
15
17
15
5
9
8
11
14
5
11
7
10
14
14
14
14
14
14
14
14
14
14
6
6
12
14
13
12
21
15
15
15
17
13
13
16
17
7
13
16
8
9
12
19
18
23
19
7
11
10
14
17
7
15
8
13
17
17
17
17
17
17
17
17
17
17
7
8
16
18
16
15
28
20
19
20
22
16
17
22
23
9
17
19
10
11
15
26
25
31
26
10
15
14
18
24
9
18
11
17
24
24
24
24
24
24
24
24
24
24
10
10
21
23
22
20
37
27
27
26
28
23
22
28
29
12
23
26
13
15
19
33
31
40
34
11
18
18
24
30
12
24
14
22
30
30
30
30
30
30
30
30
30
30
13
14
28
30
29
26
49
34
34
34
36
29
29
37
37
15
30
34
18
19
25
44
41
52
44
15
24
24
31
41
16
32
19
29
40
40
40
40
40
40
40
40
40
40
18
18
36
40
37
34
63
45
45
45
48
39
39
48
50
20
40
45
23
25
33
57
54
68
57
20
31
31
40
52
20
41
24
38
52
52
52
52
52
52
52
52
52
52
23
23
46
52
48
44
82
58
58
58
63
50
50
62
65
26
50
58
Copyright © 2015 Future Technology Devices International Limited
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
Font Index
=>
76
L
77
M
78
N
79
O
80
P
81
Q
82
R
83
S
84
T
85
U
86
V
87
W
88
X
89
Y
90
Z
91
[
92
\
93
]
94
^
95
_
96
`
97
a
98
b
99
c
100
d
101
e
102
f
103
g
104
h
105
i
106
j
107
k
108
l
109
m
110
n
111
o
112
p
113
q
114
r
115
s
116
t
117
u
118
v
119
w
120
x
121
y
122
z
123
{
124
|
125
}
126
~
127
DEL
16/
18
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2
0
6
9
8
8
7
8
7
7
5
8
7
9
7
7
7
3
3
3
6
6
3
5
6
5
6
5
4
6
6
2
2
5
2
8
6
6
6
6
4
5
4
5
6
8
6
5
5
3
3
3
7
0
2
1
8
12
10
11
9
11
10
9
9
10
9
13
9
9
9
4
4
4
7
8
5
8
7
7
8
8
4
8
8
3
3
7
3
11
8
8
8
8
5
7
4
7
7
10
7
7
7
5
3
5
8
0
2
2
9
13
12
13
11
13
12
11
10
12
11
15
11
11
10
5
5
5
8
9
6
9
9
8
9
9
5
9
9
3
4
8
3
14
9
9
9
9
5
8
5
9
8
12
8
8
8
6
4
6
10
0
2
3
11
16
14
15
13
15
14
13
12
14
13
18
13
13
12
5
5
5
9
11
4
11
11
10
11
10
6
11
10
4
4
9
4
16
10
11
11
11
6
9
6
10
10
14
10
10
9
6
5
6
10
0
2
4
14
21
18
18
16
18
17
16
16
18
17
22
17
16
15
7
7
7
12
14
7
13
14
12
14
13
8
14
13
6
6
12
6
20
14
13
14
14
9
12
8
14
13
18
12
13
12
8
6
8
14
0
2
5
18
27
24
25
22
26
24
22
20
24
22
31
22
22
20
9
9
9
16
18
11
18
18
16
18
18
9
18
18
7
7
16
7
27
18
18
18
18
11
16
9
18
16
23
16
16
16
11
9
11
19
0
2
6
7
11
9
10
9
10
9
9
10
9
9
12
9
9
9
4
6
4
6
8
4
8
8
8
8
8
6
8
8
3
3
7
3
11
8
8
8
8
5
7
6
8
7
11
7
7
8
5
3
5
10
3
2
7
9
14
11
12
10
12
11
11
12
11
11
15
11
10
11
5
7
5
7
10
5
9
9
9
10
9
7
10
9
4
4
9
4
15
9
10
9
10
6
9
7
9
9
13
9
9
9
6
4
6
11
4
2
8
12
19
15
14
14
14
13
12
14
13
14
18
13
14
13
6
9
7
9
11
7
11
11
11
12
11
8
11
11
6
6
11
6
18
11
12
11
12
7
11
8
12
11
16
11
11
11
8
5
7
14
5
2
9
13
21
17
16
15
17
15
14
15
17
15
21
15
15
14
7
10
7
10
13
8
13
14
12
14
12
10
14
14
6
6
13
6
21
14
13
14
13
9
12
9
14
12
18
12
12
12
8
6
9
15
6
3
0
17
26
23
22
19
22
19
20
19
21
20
27
20
19
18
9
13
9
13
16
10
17
17
16
17
16
12
18
17
7
8
16
7
27
17
17
17
17
11
17
11
17
16
23
16
16
15
11
7
10
21
5
3
1
22
35
29
28
26
29
27
26
26
28
27
36
27
26
25
12
18
12
18
21
13
23
24
22
24
22
15
24
24
10
11
22
10
36
24
24
24
24
15
22
14
24
21
32
21
21
22
15
10
15
29
10
3
2
29
46
37
37
34
38
33
33
32
37
34
46
34
34
32
15
22
15
23
26
17
30
31
28
31
29
19
31
31
13
14
28
13
47
31
31
31
31
19
29
17
31
27
41
27
27
27
18
14
18
36
13
3
3
39
62
50
49
45
50
45
43
42
48
45
61
45
45
42
19
29
19
30
34
22
39
40
37
40
37
25
41
41
18
18
36
18
63
41
40
40
40
25
38
23
41
36
54
36
36
36
24
18
24
47
18
3
4
51
79
65
63
58
64
58
56
56
62
58
79
58
58
55
25
38
25
38
43
29
50
52
48
52
48
31
52
52
23
23
47
23
80
52
52
51
52
32
48
29
52
46
70
46
46
46
31
23
31
63
23
Table 4-10 ROM font Extended ASCII characters
Copyright © 2015 Future Technology Devices International Limited
25
Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
î
ì
░
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
└
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
Æ
ô
ö
ò
û
ù
ÿ
Ö
Ü
ø
£
Ø
ó
ú
ñ
Ñ
ª
º
¿
®
¬
½
¼
¡
▒
▓
│
┤
Á
Â
À
©
╣
║
╗
╝
¢
┴
┬
├
─
┼
ã
Ã
╚
╔
╩
╦
╠
═
ð
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
Ó
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
Ð
Ê
Ë
È
ı
Í
Î
Ï
┘
┌
█
▄
¦
ß
Ô
Ò
õ
Õ
µ
þ
Þ
Ú
Û
Ù
ý
Ý
Symbol
ï
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
í
Decimal
è
á
Symbol
ë
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
Decimal
ê
É
æ
Symbol
ç
Decimal
å
Symbol
à
Decimal
ä
Symbol
â
Decimal
é
Symbol
Decimal
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
ü
Decimal
Symbol
Ç
Symbol
Decimal
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
±
‗
¾
¶
§
÷
¸
°
¨
·
¹
³
²
×
«
¥
Ì
¯
╬
■
Å
ƒ
»
┐
¤
´
nbsp
▀
Note: Font 17 and 19 are extended ASCII characters, with width fixed at 8 pixels for all characters.
Ä
Note: All fonts included in the FT81x ROM are widely available to the market-place for general usage. See
section nine for specific copyright data and links to the corresponding license agreements.
4.4 Parallel RGB Interface
The RGB parallel interface consists of 23 or 29 signals - DISP, PCLK, VSYNC, HSYNC, DE, 6 or 8 signals
each for R, G and B.
A set of RGB registers configure the LCD operation and timing parameters.
REG_PCLK is the PCLK divisor. The default value is 0, which means the PCLK output is disabled. When
REG_PCLK is none 0 (1-1023), the PCLK frequency can be calculated as:
PCLK frequency = System Clock frequency / REG_PCLK
The FT81x system clock frequency is programmable. Some of the possible PCLK frequencies that FT81x
supports are listed in Table 4-11.
Table 4-11 RGB PCLK frequency
System Clock Frequency (MHz)
REG_PCLK
60(default)
48
36
24
1
60
48
36
24
2
30
24
18
12
3
20
16
12
8.0
4
15
12
9.0
6.0
5
12
9.6
7.2
4.8
6
10
8.0
6.0
4.0
7
8.6
6.9
5.1
3.4
Copyright © 2015 Future Technology Devices International Limited
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
System Clock Frequency (MHz)
REG_PCLK
60(default)
48
36
24
8
7.5
6.0
4.5
3.0
9
6.7
5.3
4.0
2.7
10
6.0
4.8
3.6
2.4
REG_PCLK_POL defines the clock polarity, with 0 for positive active clock edge, and 1 for negative clock
edge.
REG_CSPREAD controls the transition of RGB signals with respect to the PCLK active clock edge. When
REG_CSPREAD=0, R[7:0], G[7:0] and B[7:0] signals change following the active edge of PCLK. When
REG_CSPREAD=1, R[7:0] changes a PCLK clock early and B[7:0] a PCLK clock later, which helps reduce
the switching noise.
REG_DITHER enables colour dither. This option improves the half-tone appearance on displays.
Internally, the graphics engine computes the colour values at an 8 bit precision; however, the LCD colour
at a lower precision is sufficient. The FT810/FT811 output is only 6 bits per colour in 6:6:6 formats and a
2X2 dither matrix allow the truncated bits to contribute to the final colour values.
REG_OUTBITS gives the bit width of each colour channel, the default is 6/6/6(for FT810/FT811) or
8/8/8(for FT812/FT813) bits for each R/G/B colour. A lower value means fewer bits are output for each
channel allowing dithering on lower precision LCD displays.
REG_SWIZZLE controls the arrangement of the output colour pins, to help the PCB route different LCD
panel arrangements. Bit 0 of the register causes the order of bits in each colour channel to be reversed.
Bits 1-3 control the RGB order. Setting Bit 1 causes R and B channels to be swapped. Setting Bit 3 allows
rotation to be enabled. If Bit 3 is set, then (R,G,B) is rotated right if bit 2 is one, or left if bit 2 is zero.
Table 4-12 REG_SWIZZLE RGB Pins Mapping
REG_SWIZZLE
b3 b2 b1 b0
PINS (FT810/FT811, 6 bits)
R7, R6, R5,
G7, G6, G5,
B7, B6, B5,
R4, R3, R2
G4, G3, G2
B4, B3, B2
0
0
0
0
1
1
1
1
1
1
1
1
R[7:2]
R[2:7]
B[7:2]
B[2:7]
B[7:2]
B[2:7]
G[7:2]
G[2:7]
G[7:2]
G[2:7]
R[7:2]
R[2:7]
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
G[7:2]
G[2:7]
G[7:2]
G[2:7]
R[7:2]
R[2:7]
R[7:2]
R[2:7]
B[7:2]
B[2:7]
B[7:2]
B[2:7]
B[7:2]
B[2:7]
R[7:2]
R[2:7]
G[7:2]
G[2:7]
B[7:2]
B[2:7]
R[7:2]
R[2:7]
G[7:2]
G[2:7]
PINS (FT812/FT813, 8 bits)
R7, R6,
G7, G6,
B7, B6,
R5, R4,
G5, G4,
B5, B4,
R3, R2,
G3, G2,
B3, B2,
R1, R0
G1, G0
B1, B0
R[7:0]
G[7:0]
B[7:0]
R[0:7]
G[0:7]
B[0:7]
B[7:0]
G[7:0]
R[7:0]
B[0:7]
G[0:7]
R[0:7]
B[7:0]
R[7:0]
G[7:0]
B[0:7]
R[0:7]
G[0:7]
G[7:0]
R[7:0]
B[7:0]
G[0:7]
R[0:7]
B[0:7]
G[7:0]
B[7:0]
R[7:0]
G[0:7]
B[0:7]
R[0:7]
R[7:0]
B[7:0]
G[7:0]
R[0:7]
B[0:7]
G[0:7]
REG_HCYCLE, REG_HSIZE, REG_HOFFSET, REG_HSYNC0 and REG_HSYNC1 define the LCD horizontal
timings. Each register has 12 bits to allow programmable range of 0-4095 PCLK cycles. REG_VCYCLE,
REG_VSIZE, REG_VOFFSET, REG_VSYNC0 and REG_VSYNC1 define the LCD vertical timings. Each
register has 12 bits to allow programmable range of 0-4095 lines.
Table 4-13 Registers for RGB horizontal and vertical timings
Copyright © 2015 Future Technology Devices International Limited
27
Vertical
Horizontal
Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
Register
Display
Parameter
Description
REG_HCYCLE
TH
Total length of line (visible and non-visible) (in PCLKs)
REG_HSIZE
THD
Length of visible part of line (in PCLKs)
REG_HOFFSET
THF + THP + THB
Length of non-visible part of line (in PCLK cycles)
REG_HSYNC0
THF
Horizontal Front Porch (in PCLK cycles)
REG_HSYNC1
THF + THP
Horizontal Front Porch plus Hsync Pulse width (in PCLK
cycles)
REG_VCYCLE
TV
Total number of lines (visible and non-visible) (in lines)
REG_VSIZE
TVD
Number of visible lines (in lines)
REG_VOFFSET
TVF + TVP + TVB
Number of non-visible lines (in lines)
REG_VSYNC0
TVF
Vertical Front Porch (in lines)
REG_VSYNC1
TVF + TVP
Vertical Front Porch plus Vsync Pulse width (in lines)
Figure 4-7 RGB timing waveforms
4.5 Miscellaneous Control
Copyright © 2015 Future Technology Devices International Limited
28
Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
4.5.1 Backlight Control Pin
The backlight dimming control pin (BACKLIGHT) is a pulse width modulated (PWM) signal controlled by
two registers: REG_PWM_HZ and REG_PWM_DUTY. REG_PWM_HZ specifies the PWM output frequency,
the range is 250-10000 Hz. REG_PWM_DUTY specifies the duty cycle; the range is 0-128. A value of 0
means that the PWM is completely off and 128 means completely on.
The BACKLIGHT pin will output low when the DISP pin is not enabled (i.e. logic 0).
4.5.2 DISP Control Pin
The DISP pin is a general purpose output that can be used to enable, or reset the LCD display panel. The
pin is controlled by writing to Bit 7 of the REG_GPIO register, or bit 15 of REG_GPIOX.
4.5.3 General Purpose IO pins
Depending on the package, the FT81x can be configured to use up to 4 GPIO pins. These GPIO pins are
controlled by the REG_GPIOX_DIR and REG_GPIOX registers. Alternatively the GPIO0 and GPIO1 pins
can also be controlled by REG_GPIO_DIR and REG_GPIO to maintain backward compatibility with the
FT800/FT801.
When the QSPI is enabled in Quad mode, GPIO0/IO2 and GPIO1/IO3 pins are used as data lines of the
QSPI.
4.5.4 Pins Drive Current Control
The output drive current of output pins can be changed as per the following table by writing to bit[6:2] of
REG_GPIO register or bit[14:10] of REG_GPIOX register. Alternatively, use the SPI command PINDRIVE
to change the individual pin drive strength.
Table 4-14 Output drive current selection
REG_GPIO
Bit[6:5]
Bit[4]
Bit[3:2]
REG_GPIOX
Bit[14:13]
Bit[12]
Bit[11:10]
Value
00b
#
01b
10b
11b
0b#
1b
00b#
01b
10b
11b
Drive
Current
5m
A
10mA
15mA
20mA
5mA
10mA
5mA
10mA
15mA
20mA
Pins
GPIO0
PCLK
MISO
GPIO1
DISP
MOSI
GPIO2
VSYNC
IO2
GPIO3
HSYNC
IO3
CTP_RST_N
DE
INT_N
R7..R0
G7..G0
B7..B0
BACKLIGHT
Note: #Default value
Copyright © 2015 Future Technology Devices International Limited
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
4.6 Audio Engine
FT81x provides mono audio output through a PWM output pin, AUDIO_L. It outputs two audio sources,
the sound synthesizer and audio file playback.
4.6.1 Sound Synthesizer
A sound processor, AUDIO ENGINE, generates the sound effects from a small ROM library of waves table.
To play a sound effect listed in Table 4.3, load the REG_SOUND register with a code value and write 1 to
the REG_PLAY register. The REG_PLAY register reads 1 while the effect is playing and returns a ‘0’ when
the effect ends. Some sound effects play continuously until interrupted or instructed to play the next
sound effect. To interrupt an effect, write a new value to REG_SOUND and REG_PLAY registers; e.g. write
0 (Silence) to REG_SOUND and 1 to PEG_PLAY to stop the sound effect.
The sound volume is controlled by register REG_VOL_SOUND. The 16-bit REG_SOUND register takes an
8-bit sound in the low byte. For some sounds, marked "pitch adjust" in the table below, the high 8 bits
contain a MIDI note value. For these sounds, a note value of zero indicates middle C. For other sounds
the high byte of REG_SOUND is ignored.
Table 4-15 Sound Effect
Value
Effect
Conti
nuous
Y
00h
Silence
Y
01h
square wave
Y
02h
sine wave
Y
03h
sawtooth wave
Y
04h
triangle wave
Y
05h
Beeping
Y
06h
Alarm
Y
07h
Warble
Y
08h
Carousel
N
10h
1 short pip
N
11h
2 short pips
N
12h
3 short pips
N
13h
4 short pips
N
14h
5 short pips
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
6 short pips
7 short pips
8 short pips
9 short pips
10 short pips
11 short pips
12 short pips
13 short pips
14 short pips
15 short pips
16 short pips
23h
2Ch
30h
31h
DTMF #
DTMF *
DTMF 0
DTMF 1
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Pitch
adjust
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Value
Effect
32h
33h
34h
35h
36h
37h
38h
39h
40h
41h
42h
43h
44h
DTMF 2
DTMF 3
DTMF 4
DTMF 5
DTMF 6
DTMF 7
DTMF 8
DTMF 9
harp
xylophone
tuba
glockenspiel
organ
Y
45h
trumpet
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
46h
47h
48h
49h
50h
51h
52h
53h
54h
55h
56h
piano
chimes
music box
bell
click
switch
cowbell
notch
hihat
kickdrum
pop
N
N
N
N
57h
58h
60h
61h
clack
chack
mute
unmute
Conti
nuous
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
Pitch
adjust
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
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Table 4-16 MIDI
MIDI
ANSI
note
note
21
A0
22
A#0
23
B0
24
C1
25
C#1
26
D1
27
D#1
28
E1
29
F1
30
F#1
31
G1
32
G#1
33
A1
34
A#1
35
B1
36
C2
37
C#2
38
D2
39
D#2
40
E2
41
F2
42
F#2
43
G2
44
G#2
45
A2
46
A#2
47
B2
48
C3
49
C#3
50
D3
51
D#3
52
E3
53
F3
54
F#3
55
G3
56
G#3
57
A3
58
A#3
59
B3
60
C4
61
C#4
62
D4
63
D#4
64
E4
Note Effect
Freq
(Hz)
27.5
29.1
30.9
32.7
34.6
36.7
38.9
41.2
43.7
46.2
49.0
51.9
55.0
58.3
61.7
65.4
69.3
73.4
77.8
82.4
87.3
92.5
98.0
103.8
110.0
116.5
123.5
130.8
138.6
146.8
155.6
164.8
174.6
185.0
196.0
207.7
220.0
233.1
246.9
261.6
277.2
293.7
311.1
329.6
MIDI
note
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
ANSI
note
F4
F#4
G4
G#4
A4
A#4
B4
C5
C#5
D5
D#5
E5
F5
F#5
G5
G#5
A5
A#5
B5
C6
C#6
D6
D#6
E6
F6
F#6
G6
G#6
A6
A#6
B6
C7
C#7
D7
D#7
E7
F7
F#7
G7
G#7
A7
A#7
B7
C8
Freq (Hz)
349.2
370.0
392.0
415.3
440.0
466.2
493.9
523.3
554.4
587.3
622.3
659.3
698.5
740.0
784.0
830.6
880.0
932.3
987.8
1046.5
1108.7
1174.7
1244.5
1318.5
1396.9
1480.0
1568.0
1661.2
1760.0
1864.7
1975.5
2093.0
2217.5
2349.3
2489.0
2637.0
2793.8
2960.0
3136.0
3322.4
3520.0
3729.3
3951.1
4186.0
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4.6.2 Audio Playback
The FT81x can play back recorded sound through its audio output. To do this, load the original sound
data into the FT81x’s RAM, and set registers to start the playback.
The registers controlling audio playback are:
REG_PLAYBACK_START:
the start address of the audio data
REG_PLAYBACK_LENGTH:
the length of the audio data, in bytes
REG_PLAYBACK_FREQ:
the playback sampling frequency, in Hz
REG_PLAYBACK_FORMAT:
the playback format, one of LINEAR SAMPLES, uLAW
SAMPLES, or ADPCM SAMPLES
REG_PLAYBACK_LOOP:
if zero, the sample is played once. If one, the sample is repeated
indefinitely
REG_PLAYBACK_PLAY:
a write to this location triggers the start of audio playback,
regardless of writing ‘0’ or ‘1’. Read back ‘1’ when playback
is ongoing, and ‘0’ when playback finishes
REG_VOL_PB:
playback volume, 0-255
The mono audio formats supported are 8-bits PCM, 8-bits uLAW and 4-bits IMA-ADPCM.
For
ADPCM_SAMPLES, each sample is 4 bits, so two samples are packed per byte, the first sample is in bits
0-3 and the second is in bits 4-7.
The current audio playback read pointer can be queried by reading the REG_PLAYBACK_READPTR. Using
a large sample buffer, looping, and this read pointer, the host MPU/MCU can supply a continuous stream
of audio.
4.7 Touch-Screen Engine
The FT81x touch-screen engine supports both resistive and capacitive touch panels. FT810 and FT812
support resistive touch, while FT811 and FT813 support capacitive touch.
4.7.1 Resistive Touch Control
The resistive touch-screen consists of a touch screen engine, ADC, Axis-switches, and ADC input
multiplexer. The touch screen engine reads commands from the memory map register and generates the
required control signals to the axis-switches and inputs mux and ADC. The ADC data are acquired,
processed and updated in the respective register for the MPU/MCU to read.
FT810/
Y+
FT812
XP
YP
XM
YM
X-
Resistive Touch Screen
X+
Y-
Figure 4-8 Resistive Touch screen connection
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The host controls the TOUCH SCREEN ENGINE operation mode by writing the REG_TOUCH_MODE.
Table 4-17 Resistive Touch Controller Operating Mode
REG_TOUCH_MODE
Mode
Description
0
OFF
Acquisition stopped, only touch detection interrupt is still valid.
1
ONE-SHOT
Perform acquisition once every time the MPU writes '1' to
REG_TOUCH_MODE.
2
FRAME-SYNC
Perform acquisition for every frame sync (~60 data
acquisition/second.
3
CONTINUOUS
Perform acquisition continuously at approximately 1000 data
acquisition / second.
The Touch Screen Engine captures the raw X and Y coordinate and writes to register REG_TOUCH_RAW
XY. The range of these values is 0-1023. If the touch screen is not being pressed, both registers read
65535 (FFFFh).
These touch values are transformed into screen coordinates using the matrix in registers
REG_TOUCH_TRANSFORM_A-F.
The
post-transform
coordinates
are
available
in
register
REG_TOUCH_SCREEN_XY. If the touch screen is not being pressed, both registers read -32768 (8000h).
The values for REG TOUCH TRANSFORM A-F may be computed using an on-screen calibration process.
If the screen is being touched, the screen coordinates are looked up in the screen's tag buffer, delivering
a final 8-bit tag value, in REG TOUCH TAG. Because the tag lookup takes a full frame, and touch
coordinates change continuously, the original (x; y) used for the tag lookup is also available in
REG_TOUCH_TAG_XY.
Screen touch pressure is available in REG_TOUCH_RZ. The value is relative to the resistance of the touch
contact, a lower value indicates more pressure. The register defaults to 32767 when touch is not
detected. The REG_TOUCH_THRESHOLD can be set to accept a touch only when the force threshold is
exceeded.
4.7.2 Capacitive Touch Control
The Capacitive Touch Screen Engine (CTSE) of the FT81x communicates with the external capacitive
touch panel module (CTPM) through an I2C interface. The CTPM will assert its interrupt line when there is
a touch detected. Upon detecting CTP_INT_N line active, the FT81x will read the touch data through I2C.
Up to 5 touches can be reported and stored in FT81x registers.
For a supported CTPM list please consult FTDI website.
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VCCIO2
(1.8-3.3V)
FT811/
1K
FT813
1K
CTP_SCL
SCL
CTP_SDA
SDA
CTP_INT_N
INTN
CTP_RST_N
RSTN
Capacitive Touch
Panel Module
Figure 4-9 Touch screen connection
The host controls the CTSE operation mode by writing the REG_CTOUCH_MODE.
Table 4-18 Capacitive Touch Controller Operating Mode
REG_CTOUCH_MODE
Mode
Description
0
OFF
Acquisition stopped
1-2
Reserved
Reserved
3
CONTINUOUS
Perform acquisition continuously at the reporting rate of the
connected CTPM.
The FT81x CTSE supports compatibility mode and extended mode. By default the CTSE runs in
compatibility mode where the touch system provides an interface very similar to the resistive touch
engine. In this mode the same application code can run on FT810/FT812 and FT811/FT813 without
alteration. In extended mode, the touch register meanings are modified, and a second set of registers are
exposed. These allow multi-touch detection (up to 5 touches).
4.7.3 Compatibility mode
The CTSE reads the X and Y coordinates from the CTPM and writes to register REG_CTOUCH_RAW_XY. If
the touch screen is not being pressed, both registers read 65535 (FFFFh).
These touch values are transformed into screen coordinates using the matrix in
REG_CTOUCH_TRANSFORM_A-F.
The
post-transform
coordinates
are
available
in
REG_CTOUCH_SCREEN_XY. If the touch screen is not being pressed, both registers read -32768
The values for REG_CTOUCH_TRANSFORM_A-F may be computed using an on-screen calibration
registers
register
(8000h).
process.
If the screen is being touched, the screen coordinates are looked up in the screen's tag buffer, delivering
a final 8-bit tag value, in REG_TOUCH_TAG. Because the tag lookup takes a full frame, and touch
coordinates change continuously, the original (x; y) used for the tag lookup is also available in
REG_TOUCH_TAG_XY.
4.7.4 Extended mode
Setting REG_CTOUCH_EXTENDED to 1b’0 enables extended mode. In extended mode a new set of
readout registers are available, allowing gestures and up to five touches to be read. There are two
classes of registers: control registers and status registers. Control registers are written by the MCU.
Status registers can be read out by the MCU and the FT81x’s hardware tag system.
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The five touch coordinates are packed in REG_CTOUCH_TOUCH0_XY, REG_CTOUCH_TOUCH1_XY,
REG_CTOUCH_TOUCH2_XY, REG_CTOUCH_TOUCH3_XY, REG_CTOUCH4_X and REG_CTOUCH4_Y.
Coordinates stored in these registers are signed 16-bit values, so have range -32768 to 32767. The notouch condition is indicated by x=y= -32768. These coordinates are already transformed into screen
coordinates based on the raw data read from the CTPM, using the matrix in registers
REG_CTOUCH_TRANSFORM_A-F. To obtain raw (x,y) coordinates read from CTPM, the user sets the
REG_CTOUCH_TRANSFORM_A-F registers to the identity matrix.
The FT81x tag mechanism is implemented by hardware, where up to 5 tags can be looked up.
4.7.5 Short-circuit protection
For resistive touch it is useful to protect the chip from permanent damage due to potential short-circuits
on the 4 XY lines. When a short circuit on the touch screen happens, the FT81x can detect it and stop the
touch detection operation, leaving the 4 XY pins in the high impedance state.
The short-circuit protection can be enabled/disabled by the REG_TOUCH_CONFIG.
4.7.6 Capacitive touch configuration
On capacitive touch system some users may need to adjust the CTPM default values, such as the
registers affecting touch sensitivity. To do this the following sequence shall be executed once after chip
reset:
-
Hold the touch engine in reset (set REG_CPURESET = 2)
Write the CTPM configure register address and value to FT81x designated memory location
Up to 10 register address/value can be added
Release the touch engine reset (set REG_CPURESET = 0)
The CTPM can be enabled in low power state when the touch function is not required by the application.
Setting the low-power bit in REG_TOUCH_CONFIG will enable the low power mode of the CTPM. When
the low-power bit is cleared, the FT81x touch engine will send a reset to the CTPM, thus re-enabling the
touch detection function.
4.7.7 Touch detection in none-ACTIVE state
When FT81x is in none-ACTIVE state, a touch event can still be detected and reported to the host
through the INT_N pin. In other words, a touch event can wake-up the host if needed.
For resistive touch, the INT_N pin will be asserted low when the screen is touched, regardless of the
setting of the interrupt registers. This will happen when the FT81x is in STANDBY or SLEEP state, but not
in POWERDOWN state.
For capacitive touch, the INT_N pin will follow CTP_INT_N pin when the FT81x is in STANDBY, SLEEP or
POWERDOWN state.
4.8 Power Management
4.8.1 Power supply
The FT81x may be operated with a single supply of 3.3V applied to VCC and VCCIO pins. For operation
with a host MPU/MCU at a lower supply, connect the VCCIO1 to the MPU IO supply to match the interface
voltage. For operation with LCD/touch panels at lower voltages, connect the VCCIO2 to the LCD/touch IO
supply.
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Table 4-19 Power supply
Symbol
Typical
Description
VCCIO1
1.8V, or 2.5V, or 3.3V
Supply for Host interface digital I/O pins
VCCIO2
1.8V, or 2.5V, or 3.3V
Supply for RGB and touch interface I/O pins
VCC
3.3V
Supply for 3.3V circuits and internal regulator
VOUT1V2
1.2V
Supply for digital core. Generated by internal regulator
4.8.2 Internal Regulator and POR
The internal regulator provides power to the core circuit. A 47kΩ resistor is recommended to pull the
PD_N pin up to VCCIO1, together with a 100nF capacitor to ground in order to delay the internal
regulator powering up after the VCC and VCCIO are stable.
The internal regulator requires a compensation capacitor to be stable. A typical design requires a 4.7uF
capacitor between the VOUT1V2 and GND pins. Do not connect any other load to the VOUT1V2 pin.
The internal regulator will generate a Power-On-Reset (POR) pulse when the output voltage rises above
the POR threshold. The POR will reset all the core digital circuits.
It is possible to use PD_N pin as an asynchronous hardware reset input. Drive PD_N low for at least 5ms
and then drive it high will reset the FT81x chip.
VCCIO1
VCC
R1
47k
C2
C1
10uF
GND
VOUT1V2
FT81x
C3
4.7uF
GND
GND
PD_N
GND
100nF
VCC
GND
Figure 4-10 Internal regulator
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4.8.3 Power Modes
When the supply to VCCIO and VCC is applied, the internal regulator is powered by VCC. An internal POR
pulse will be generated during the regulator power up until it is stable. After the initial power up, the
FT81x will stay in the SLEEP state. When needed, the host can set the FT81x to the ACTIVE state by
performing a SPI ACTIVE command. The graphics engine, the audio engine and the touch engine are only
functional in the ACTIVE state. To save power the host can send a command to put the FT81x into any of
the low power modes: STANDBY, SLEEP and POWERDOWN. In addition, the host is allowed to put the
FT81x in POWERDOWN mode by driving the PD_N pin to low, regardless of what state it is currently in.
Refer to Figure 4-11 for the power state transitions.
Toggle PD_N from high
to low
VCC/VCCIO
Power ON
Toggle PD_N from low
to high
POWERDOWN
SLEEP
Write command
“ACTIVE”
Toggle PD_N from high to low or
Write command “POWERDOWN”
Toggle PD_N from high
to low
Write command
“SLEEP”
Write command
“ACTIVE”
STANDBY
ACTIVE
Write command “STANDBY”
Figure 4-11 Power State Transition
4.8.3.1 ACTIVE state
In ACTIVE state, the FT81x is in normal operation. The clock oscillator and PLL are functioning. The
system clock applied to the FT81x core engines is enabled.
4.8.3.2 STANDBY state
In STANDBY state, the clock oscillator and PLL remain functioning; the system clock applied to the FT81x
core engines is disabled. All register contents are retained.
4.8.3.3 SLEEP state
In SLEEP state, the clock oscillator, PLL and system clock applied to the FT81x core engines are disabled.
All register contents are retained.
4.8.3.4 POWERDOWN state
In POWERDOWN state, the clock oscillator, the PLL and the system clock applied to the FT81x core is
disabled. The core engines are powered down while the SPI interface for host commands remains
functional. All register contents are lost and reset to default when the chip is next switched on. The
internal regulator remains on.
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4.8.3.5 Wake up to ACTIVE from other power states
When in the POWER DOWN state, if the device enters this state via an SPI command, then only the SPI
ACTIVE command will bring the device back to the ACTIVE state, provided PD_N pin is also high.
However, if PD_N is used instead, then making PD_N high followed by a SPI ACTIVE command will wake
up the device. Upon exiting this state, the device will perform a global reset, and will go through the
same power up sequence. All settings from SPI commands will be reset except those that pertain to pin
states during power down. The clock enable sequence mentioned in section 4.2.3 shall be executed to
properly select and enable the system clock.
From the SLEEP state, the host MPU sends an SPI ACTIVE command to wake the FT81x into the ACTIVE
state. The host needs to wait for at least 20ms before accessing any registers or commands. This is to
guarantee the clock oscillator and PLL are up and stable.
From the STANDBY state, the host MPU sends SPI ACTIVE command to wake the FT81x into the ACTIVE
state. The host can immediately access any register or command.
4.8.4 Reset and boot-up sequence
There are a few hardware and software reset events which can be triggered to reset the FT81x.
Hardware reset events:
Power-on-Reset(POR)
Toggle the PD_N pin
Software reset events:
SPI command RST_PULSE
SPI command to switch between the internal clock and the external clock
SPI command to enter POWERDOWN then wakeup
After reset the FT81x will be in the SLEEP state. Upon receiving an SPI ACTIVE command, the internal
oscillator and PLL will start up. Once the clock is stable, the chip will check and repair its internal RAM,
running the configuration and release the clock to the system. The chip will exit the reset and boot-up
state and enter into normal operations. The boot-up may take up to 300ms to complete.
4.8.5 Pin Status at Different Power States
The FT81x pin status depends on the power state of the chip. See the following table for more details. At
the power transition from ACTIVE to STANDBY or ACTIVE to SLEEP, all pins retain their previous status.
The software needs to set AUDIO_L, BACKLIGHT to a known state before issuing power transition
commands.
The pin status in the power down state can be changed by SPI command PIN_PD_STATE.
Table 4-20 Pin Status
Pin Name
Default Drive
Reset
Normal
Power Down
(Default)
AUDIO_L
20mA
Out, Float
Out
Pull Low
SCK
-
In
In
In
MISO
5mA
IO
Out, Float
MOSI
5mA
In
IO
In
CS_N
-
In
In
In
Out, Float
(CS_N = 1)
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Pin Name
Default Drive
Reset
Normal
Power Down
(Default)
IO2
5mA
In
IO
Float
GPIO0
5mA
In
IO
Float
IO3
5mA
In
IO
Float
GPIO1
5mA
In
IO
Float
GPIO2
5mA
In
IO
Float
INT_N
5mA
OD, Float
OD / Out
Float
PD_N
-
In
In
In
GPIO3
5mA
In
IO
Float
X1/CLK
-
In
In
In
XP
-
IO, Float
IO
Float
YP
-
IO, Float
IO
Float
XM
-
IO, Float
IO
Float
YM
-
IO, Float
IO
Float
CTP_RST_N
5mA
Out
Out
Pull Low
CTP_INT_N
-
In (internal
pull-up)
In (internal
pull-up)
In (internal
pull-up)
CTP_SCL
20mA
OD
IO
Float
CTP_SDA
20mA
OD
IO
Float
BACKLIGHT
5mA
Out
Out
Pull Low
DE
5mA
Out
Out
Pull Low
VSYNC
5mA
Out
Out
Pull Low
HSYNC
5mA
Out
Out
Pull Low
DISP
5mA
Out
Out
Pull Low
PCLK
5mA
Out
Out
Pull Low
R/G/B
5mA
Out
Out
Pull Low
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5
Memory Map
All memory and registers in the FT81x core are memory mapped in 22-bit address space with a 2-bit SPI
command prefix. Prefix 0'b00 for read and 0'b10 for write to the address space, 0'b01 is reserved for
Host Commands and 0'b11 undefined. The following are the memory space definition.
Table 5-1 FT81x Memory Map
Start
Address
End
Address
Size
NAME
Description
00 0000h
0F FFFFh
1024 kB
RAM_G
General purpose graphics RAM
1E 0000h
2F FFFBh
1152 kB
ROM_FONT
Font table and bitmap
2F FFFCh
2F FFFFh
4B
ROM_FONT_ADDR
Font table pointer address
30 0000h
30 1FFFh
8 kB
RAM_DL
Display List RAM
30 2000h
30 2FFFh
4 kB
RAM_REG
Registers
30 8000h
30 8FFFh
4 kB
RAM_CMD
Command buffer
Note 1: The addresses beyond this table are reserved and shall not be read or written unless otherwise
specified.
5.1 Registers
Table 5-2 shows the complete list of the FT81x registers. Refer to FT81x_Series_Programmers_Guide,
Chapter 2 for details of the register function.
Table 5-2 Overview of FT81x Registers
Address
(hex)
302000h
Register Name
REG_ID
Bit
s
r/
w
Reset
value
8
r/o
7Ch
Description
Identification register, always reads
as 7Ch
302004h
REG_FRAMES
32
r/o
0
Frame counter, since reset
302008h
REG_CLOCK
32
r/o
0
Clock cycles, since reset
30200Ch
REG_FREQUENCY
28
r/w
60000000
302010h
REG_RENDERMODE
1
r/w
0
Rendering mode: 0 = normal, 1 =
single-line
302014h
REG_SNAPY
11
r/w
0
Scanline select for RENDERMODE 1
302018h
REG_SNAPSHOT
1
r/w
-
Trigger for RENDERMODE 1
30201Ch
REG_SNAPFORMAT
6
r/w
20h
302020h
REG_CPURESET
3
r/w
2
Graphics, audio and touch engines
reset control. Bit2: audio, bit1:
touch, bit0: graphics
302024h
REG_TAP_CRC
32
r/o
-
Live video tap crc. Frame CRC is
Main clock frequency (Hz)
Pixel format for scanline readout
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Address
(hex)
Register Name
Bit
s
r/
w
Reset
value
Description
computed every DL SWAP.
302028h
REG_TAP_MASK
32
r/w
FFFFFFFFh
Live video tap mask
30202Ch
REG_HCYCLE
12
r/w
224h
Horizontal total cycle count
302030h
REG_HOFFSET
12
r/w
02Bh
Horizontal display start offset
302034h
REG_HSIZE
12
r/w
1E0h
Horizontal display pixel count
302038h
REG_HSYNC0
12
r/w
000h
Horizontal sync fall offset
30203Ch
REG_HSYNC1
12
r/w
029h
Horizontal sync rise offset
302040h
REG_VCYCLE
12
r/w
124h
Vertical total cycle count
302044h
REG_VOFFSET
12
r/w
00Ch
Vertical display start offset
302048h
REG_VSIZE
12
r/w
110h
Vertical display line count
30204Ch
REG_VSYNC0
10
r/w
000h
Vertical sync fall offset
302050h
REG_VSYNC1
10
r/w
00Ah
Vertical sync rise offset
302054h
REG_DLSWAP
2
r/w
0
Display list swap control
302058h
REG_ROTATE
3
r/w
0
Screen rotation control. Allow
normal/mirrored/inverted for
landscape or portrait orientation.
30205Ch
REG_OUTBITS
9
r/w
1B6h/000h
302060h
REG_DITHER
1
r/w
1
Output dither enable
302064h
REG_SWIZZLE
4
r/w
0
Output RGB signal swizzle
302068h
REG_CSPREAD
1
r/w
1
Output clock spreading enable
30206Ch
REG_PCLK_POL
1
r/w
0
PCLK polarity:
Output bit resolution, 3 bits each for
R/G/B. Default is 6/6/6 bits for
FT810/FT811, and 8/8/8 bits for
FT812/FT813 (0b’000 means 8 bits)
0 = output on PCLK rising edge,
1 = output on PCLK falling edge
302070h
REG_PCLK
8
r/w
0
PCLK frequency divider, 0 = disable
302074h
REG_TAG_X
11
r/w
0
Tag query X coordinate
302078h
REG_TAG_Y
11
r/w
0
Tag query Y coordinate
30207Ch
REG_TAG
8
r/o
0
Tag query result
302080h
REG_VOL_PB
8
r/w
FFh
Volume for playback
302084h
REG_VOL_SOUND
8
r/w
FFh
Volume for synthesizer sound
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Address
(hex)
Register Name
302088h
REG_SOUND
30208Ch
302090h
Bit
s
r/
w
Reset
value
16
r/w
0
REG_PLAY
1
r/w
0h
REG_GPIO_DIR
8
r/w
80h
Description
Sound effect select
Start effect playback
Legacy GPIO pin direction,
0 = input , 1 = output
302094h
REG_GPIO
302098h
REG_GPIOX_DIR
8
r/w
00h
16
r/w
8000h
Legacy GPIO read/write
Extended GPIO pin direction,
0 = input , 1 = output
30209Ch
REG_GPIOX
16
3020A0h
3020A4h
Reserved
-
-
3020A8h
REG_INT_FLAGS
8
r/o
00h
3020Ach
REG_INT_EN
1
r/w
0
3020B0h
REG_INT_MASK
8
r/w
FFh
3020B4h
REG_PLAYBACK_START
20
r/w
0
Audio playback RAM start address
3020B8h
REG_PLAYBACK_LENGTH
20
r/w
0
Audio playback sample length
(bytes)
3020BCh
REG_PLAYBACK_READPTR
20
r/o
-
Audio playback current read pointer
3020C0h
REG_PLAYBACK_FREQ
16
r/w
8000
3020C4h
REG_PLAYBACK_FORMAT
2
r/w
0
Audio playback format
3020C8h
REG_PLAYBACK_LOOP
1
r/w
0
Audio playback loop enable
3020CCh
REG_PLAYBACK_PLAY
1
r/w
0
Start audio playback
3020D0h
REG_PWM_HZ
14
r/w
250
BACKLIGHT PWM output frequency
(Hz)
3020D4h
REG_PWM_DUTY
8
r/w
128
BACKLIGHT PWM output duty cycle
0=0%, 128=100%
3020D8h
REG_MACRO_0
32
r/w
0
Display list macro command 0
3020DCh
REG_MACRO_1
32
r/w
0
Display list macro command 1
3020E0h
–
3020F4h
Reserved
-
-
Reserved
3020F8h
REG_CMD_READ
r/w
0
Command buffer read pointer
-
12
r/w
0080h
-
Extended GPIO read/write
Reserved
Interrupt flags, clear by read
Global interrupt enable, 1=enable
Individual interrupt enable,
1=enable
Audio playback sampling frequency
(Hz)
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Address
(hex)
Register Name
Bit
s
r/
w
Reset
value
3020FCh
REG_CMD_WRITE
12
r/o
0
Command buffer write pointer
302100h
REG_CMD_DL
13
r/w
0
Command display list offset
302104h
REG_TOUCH_MODE
2
r/w
3
Touch-screen sampling mode
302108h
REG_TOUCH_ADC_MODE
1
r/w
1
Set Touch ADC mode
REG_CTOUCH_EXTENDED
Description
Set capacitive touch operation
mode:
0: extended mode (multi-touch)
1: FT800 compatibility mode (single
touch).
30210Ch
REG_TOUCH_CHARGE
16
r/w
9000
302110h
REG_TOUCH_SETTLE
4
r/w
3
Touch settle time, units of 6 clocks
302114h
REG_TOUCH_OVERSAMPL
E
4
r/w
7
Touch oversample factor
302118h
REG_TOUCH_RZTHRESH
16
r/w
FFFFh
30211Ch
REG_TOUCH_
32
r/o
-
RAW_XY
REG_TOUCH_RZ
Touch resistance threshold
Compatibility mode: touch-screen
raw (x-MSB16; y-LSB16)
Extended mode: touch-screen
screen data for touch 1 (x-MSB16;
y-LSB16)
REG_CTOUCH_TOUCH1_X
Y
302120h
Touch charge time, units of 6 clocks
16
r/o
-
REG_CTOUCH_TOUCH4_Y
Compatibility mode: touch-screen
resistance
Extended mode: touch-screen
screen Y data for touch 4
302124h
REG_TOUCH_
32
r/o
-
SCREEN_XY
Extended mode: touch-screen
screen data for touch 0 (x-MSB16;
y-LSB16)
REG_CTOUCH_TOUCH0_X
Y
302128h
REG_TOUCH_
32
r/o
-
Touch-screen screen (x-MSB16; yLSB16) used for tag 0 lookup
8
r/o
-
Touch-screen tag result 0
32
r/o
-
Touch-screen screen (x-MSB16; yLSB16) used for tag 1 lookup
8
r/o
-
Touch-screen tag result 1
32
r/o
-
Touch-screen screen (x-MSB16; yLSB16) used for tag 2 lookup
8
r/o
-
Touch-screen tag result 2
TAG_XY
30212Ch
REG_TOUCH_TAG
302130h
REG_TOUCH_
TAG1_XY
302134h
REG_TOUCH_TAG1
302138h
REG_TOUCH_
TAG2_XY
30213Ch
REG_TOUCH_TAG2
Compatibility mode: touch-screen
screen (x-MSB16; y-LSB16)
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Address
(hex)
Register Name
302140h
REG_TOUCH_
Bit
s
r/
w
Reset
value
32
r/o
-
Touch-screen screen (x-MSB16; yLSB16) used for tag 3 lookup
8
r/o
-
Touch-screen tag result 3
32
r/o
-
Touch-screen screen (x-MSB16; yLSB16) used for tag 4 lookup
8
r/o
-
Touch-screen tag result 4
TAG3_XY
302144h
REG_TOUCH_TAG3
302148h
REG_TOUCH_
Description
TAG4_XY
30214Ch
REG_TOUCH_TAG4
302150h
REG_TOUCH_TRANSFORM
_A
32
r/w
00010000h
Touch-screen transform coefficient
(s15.16)
302154h
REG_TOUCH_TRANSFORM
_B
32
r/w
00000000h
Touch-screen transform coefficient
(s15.16)
302158h
REG_TOUCH_TRANSFORM
_C
32
r/w
00000000h
Touch-screen transform coefficient
(s15.16)
30215Ch
REG_TOUCH_TRANSFORM
_D
32
r/w
00000000h
Touch-screen transform coefficient
(s15.16)
302160h
REG_TOUCH_TRANSFORM
_E
32
r/w
00010000h
Touch-screen transform coefficient
(s15.16)
302164h
REG_TOUCH_TRANSFORM
_F
32
r/w
00000000h
Touch-screen transform coefficient
(s15.16)
302168h
REG_TOUCH_CONFIG
16
r/w
8381h(FT8
10/FT812)
Touch configuration.
0381h(FT8
11/FT813)
RTP/CTP select
RTP: short-circuit, sample clocks
CTP: I2C address, CTPM type, lowpower mode
30216Ch
REG_CTOUCH_TOUCH4_X
302170h
Reserved
302174h
REG_BIST_EN
16
r/o
-
Extended mode: touch-screen
screen X data for touch 4
-
-
-
Reserved
1
r/w
0
BIST memory mapping enable
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Address
(hex)
Register Name
Bit
s
r/
w
Reset
value
Description
302178h
Reserved
-
-
-
Reserved
30217Ch
Reserved
-
-
-
Reserved
302180h
REG_TRIM
8
r/w
0
Internal relaxation clock trimming
302184h
REG_ANA_COMP
8
r/w
0
Analogue control register
302188h
REG_SPI_WIDTH
3
r/w
0
QSPI bus width setting
Bit [2]: extra dummy cycle on read
Bit [1:0]: bus width (0=1-bit, 1=2bit, 2=4-bit)
30218Ch
REG_TOUCH_DIRECT_XY
32
r/o
-
REG_CTOUCH_TOUCH2_X
Y
302190h
REG_TOUCH_DIRECT_Z1Z
2
Extended mode: touch-screen
screen data for touch 2 (x-MSB16;
y-LSB16)
32
r/o
-
Reserved
302564h
REG_DATESTAMP
302574h
302578h
Compatibility mode: Touch screen
direct (z1-MSB16; z2-LSB16)
conversions
Extended mode: touch-screen
screen data for touch 3 (x-MSB16;
y-LSB16)
REG_CTOUCH_TOUCH3_X
Y
302194h
302560h
Compatibility mode: Touch screen
direct (x-MSB16; y-LSB16)
conversions
-
-
-
Reserved
128
r/o
-
Stamp date code
REG_CMDB_SPACE
12
r/w
FFCh
REG_CMDB_WRITE
32
w/o
0
Command DL (bulk) space available
Command DL (bulk) write
Note: All register addresses are 4-byte aligned. The value in the “Bits” column refers to the number of
valid bits from bit 0 unless otherwise specified; other bits are reserved.
5.2 Chip ID
The FT81x Chip ID can be read at memory location 0C0000h – 0C0003h. The reset values of these bytes
are:
-
0C0000h:
0C0001h:
0C0002h:
0C0003h:
08h
10h (FT810), 11h(FT811), 12h(FT812), 13h(FT813)
01h
00h
Note that the Chip ID location can be over-written by software.
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Datasheet Version 1.2
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6
Devices Characteristics and Ratings
6.1 Absolute Maximum Ratings
The absolute maximum ratings for the FT81x device are as follows. These are in accordance with the
Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the
device.
Table 6-1 Absolute Maximum Ratings
Parameter
Value
Unit
Storage Temperature
-65 to +150
°C
Floor Life (Out of Bag) At Factory Ambient
168 (IPC/JEDEC J-STD-033A MSL Level 3
Compliant)*
Hours
Ambient Temperature (Power Applied)
-40 to +85
°C
VCC Supply Voltage
0 to +4
V
VCCIO Supply Voltage
0 to +4
V
DC Input Voltage
-0.5 to + (VCCIO + 0.3)
V
(30°C / 60% Relative Humidity)
* If the devices are stored out of the packaging, beyond this time limit, the devices should be baked
before use. The devices should be ramped up to a temperature of +125°C and baked for up to 17 hours.
6.2 ESD and Latch-up Specifications
Table 6-2 ESD and Latch-Up Specifications
Description
Specification
Human Body Mode (HBM)
> ± 2kV
Machine mode (MM)
> ± 200V
Charged Device Mode (CDM)
> ± 500V
Latch-up
> ± 200mA
6.3 DC Characteristics
Table 6-3 Operating Voltage and Current
Parameter
Description
VCCIO1/
VCCIO operating
supply voltage
VCCIO2
VCC
VCC operating supply
voltage
Minimum
Typical
Maximum
Units
1.62
1.80
1.98
V
2.25
2.50
2.75
V
2.97
3.30
3.63
V
2.97
3.30
3.63
V
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Conditions
Normal Operation
Normal Operation
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Parameter
Description
Minimum
Typical
Maximum
Units
Icc1
Conditions
Power Down current
-
0.17
-
mA
Power down mode
Icc2
Sleep current
-
0.76
-
mA
Sleep Mode
Icc3
Standby current
-
1.8
-
mA
Standby Mode
Icc4
Operating current
-
22
-
mA
Normal Operation
Table 6-4 Digital I/O Pin Characteristics (VCCIO = +3.3V)
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
Voh
Output Voltage High
VCCIO0.4
-
-
V
Ioh=5mA
Vol
Output Voltage Low
-
-
0.4
V
Iol=5mA
Vih
Input High Voltage
2.0
-
-
V
Vil
Input Low Voltage
-
-
0.8
V
Vth
Schmitt Hysteresis
Voltage
0.22
-
0.3
V
Iin
Input leakage current
-10
-
10
uA
Ioz
-10
-
10
uA
Rpu
Tri-state output
leakage current
Pull-up resistor
-
42
-
kΩ
Rpd
Pull-down resistor
-
44
-
kΩ
Vin = VCCIO or 0
Vin = VCCIO or 0
Table 6-5 Digital I/O Pin Characteristics (VCCIO = +2.5V)
Parameter
Description
Voh
Output Voltage High
VCCIO0.4
-
-
V
Ioh=5mA
Vol
Output Voltage Low
-
-
0.4
V
Iol=5mA
Vih
Input High Voltage
1.7
-
-
V
-
Vil
Input Low Voltage
-
-
0.7
V
-
Vth
Schmitt Hysteresis
Voltage
0.2
-
0.3
V
-
Iin
Input leakage current
-10
-
10
uA
Ioz
Tri-state output
leakage current
Pull-up resistor
-10
-
10
uA
-
57
-
kΩ
Rpu
Minimum
Typical
Maximum
Units
Copyright © 2015 Future Technology Devices International Limited
Conditions
Vin = VCCIO or 0
Vin = VCCIO or 0
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Clearance No.: FTDI#440
Rpd
Pull-down resistor
-
59
-
kΩ
Table 6-6 Digital I/O Pin Characteristics (VCCIO = +1.8V)
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
Voh
Output Voltage High
VCCIO0.4
-
-
V
Ioh=5mA
Vol
Output Voltage Low
-
-
0.4
V
Iol=5mA
Vih
Input High Voltage
1.2
-
-
V
-
Vil
Input Low Voltage
-
-
0.6
V
-
Vth
Schmitt Hysteresis
Voltage
Input leakage current
0.17
-
0.3
V
-10
-
10
uA
-10
-
10
uA
-
90
-
kΩ
-
97
-
kΩ
Iin
Ioz
Rpu
Tri-state output
leakage current
Pull-up resistor
Rpd
Pull-down resistor
Vin = VCCIO or 0
Vin = VCCIO or 0
Table 6-7 Touch Sense Characteristics
Parameter
Description
Rsw-on
X-,X+,Y- and Y+
Drive On resistance
Minimum
Typical
Maximum
Units
Conditions
-
6
10
Ω
VCCIO=3.3V
-
9
16
Ω
VCCIO=1.8V
Rsw-off
X-,X+,Y- and Y+
Drive Off resistance
10
-
-
MΩ
Rpu
Touch sense pull up
resistance
78
100
125
kΩ
Vth+
Touch Detection
rising-edge threshold
on XP pin
1.59
-
2.04
V
VCCIO=3.3V
0.58
-
0.68
V
VCCIO=1.8V
Touch Detection
falling-edge threshold
on XP pin
1.23
-
1.55
V
VCCIO=3.3V
0.51
-
0.56
V
VCCIO=1.8V
X-axis and Y-axis
drive load resistance
200
-
-
Ω
Vth-
Rl
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6.4 AC Characteristics
6.4.1 System clock and reset
Table 6-8 System clock characteristics
Value
Parameter
Units
Minimum
Typical
Maximum
Trimmed frequency
-
12
-
MHz
Frequency variation
-5.5
-
+5.5
%
-
12.000
-
MHz
-
-
10
pF
Frequency
-
12.000
-
MHz
Duty cycle
45
50
55
%
-
3.3
-
V
Internal Relaxation Clock
Crystal
Frequency
X1/X2
Capacitance
External clock input
Input voltage on
X1/CLK
Reset
Reset pulse on PD_N
5
ms
6.4.2 SPI interface timing
Figure 6-1 SPI Interface Timing
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Table 6-9 SPI Interface Timing Specification
VCCIO=1.8V
VCCIO=2.5V
VCCIO=3.3V
Min
Min
Min
Units
Parameter
Description
Tsclk
SPI clock period
(SINGLE/DUAL
mode)
33.3
33.3
33.3
ns
Tsclk
SPI clock period
(QUAD mode)
40
40
40
ns
Tsclkl
SPI clock low
duration
13
13
13
ns
Tsclkh
SPI clock high
duration
13
13
13
ns
Tsac
SPI access time
4
3.5
3
ns
Tisu
Input Setup
4
3.5
3
ns
Tih
Input Hold
0
0
0
ns
Tzo
Output enable delay
16
13
11
ns
Toz
Output disable delay
13
11
10
ns
Tod
Output data delay
15
12
11
ns
Tcsnh
CSN hold time
Max
0
Max
0
Max
0
ns
6.4.3 RGB Interface Timing
Table 6-10 RGB interface timing characteristics
Value
Parameter
Description
Tpclk
Pixel Clock period
15.7
Tpclkdc
Pixel Clock duty cycle
40
Td
Output delay relative to PCLK rising
edge (REG_PCLK_POL=0) or falling
edge (REG_PCLK_POL=1). Applied for
all the RGB output pins.
Th
Output hold time relative to PCLK
rising edge (REG_PCLK_POL=0) or
falling edge (REG_PCLK_POL=1).
Applied for all the RGB output pins.
Min
Typ
Max
Units
ns
50
60
%
4
ns
0.5
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ns
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Figure 6-2 RGB Interface Timing
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Clearance No.: FTDI#440
Application Examples
J1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
D3V3
EP
56
55
54
53
52
51
50
49
48
47
46
45
44
43
D3V3 LEDK
LEDA
GND
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
U1
IC_FT812Q
QSPI master
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SPI_SCK
SPI_MISO
SPI_MOSI
SPI_CS#
SPI_IO2
SPI_IO3
GND
B0
B1
B2
B3
B4
B5
B6
B7
PCLK
DISP
HSYNC
VSYNC
DE
42
41
40
39
38
37
36
35
34
33
32
31
30
29
B0
B1
B2
B3
B4
B5
B6
B7
PCLK
DISP
HSYNC
VSYNC
DE
D3V3
C2
C4
C5
0.1uF 0.1uF 0.1uF 0.1uF
GND
12MHz
C8
18pF
GND
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
PCLK
DISP
HSYNC
VSYNC
DE
R25
R26
R27
R28
R29
33R
33R
33R
33R
33R
VOUT1V2
Y1
C3
BL_PWM
XP
YP
XM
YM
15
16
17
18
19
20
21
22
23
24
25
26
27
28
AUD_PD#
SPI_INT#
SPI_PD#
R1
R0
AUDIO_L
GND
SCK
MISO/IO1
MOSI/IO0
CS_N
GPIO0/IO2
GPIO1/IO3
VCCIO1
GPIO2
INT_N
PD_N
GPIO3
X1/CLK
X2
GND
VCC
VOUT1V2
VCC
VCCIO2
XP
YP
XM
YM
GND
BACKLIGHT
R1
R0
AUD_PWM
MCU
GND
C1
C7
18pF
GND
XP
YM
XM
YP
C6
4.7uF
0.1uF
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
0
GND
GND
LCD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VLEDVLED+
GND
VDD
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
GND
PCLK
DISP
HSYNC
VSYNC
DE
NC
GND
X1[Right]
Y1[Bottom]
X2[Left]
Y2[Top]
0.5B-40PBS
Figure 7-1 FT812 application circuit
J1
EP
56
55
54
53
52
51
50
49
48
47
46
45
44
43
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
D3V3
GND
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
U1
FT813Q
QSPI master
SPI_SCK
SPI_MISO
SPI_MOSI
SPI_CS#
SPI_IO2
SPI_IO3
AUD_PD#
SPI_INT#
SPI_PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R1
R0
AUDIO_L
GND
SCK
MISO/IO1
MOSI/IO0
CS_N
GPIO0/IO2
GPIO1/IO3
VCCIO1
GPIO2
INT_N
PD_N
GPIO3
X1/CLK
X2
GND
VCC
VOUT1V2
VCC
VCCIO2
CTP_RST_N
CTP_INT_N
CTP_SCL
CTP_SDA
GND
BACKLIGHT
R1
R0
AUD_PWM
MCU
GND
B0
B1
B2
B3
B4
B5
B6
B7
PCLK
DISP
HSYNC
VSYNC
DE
42
41
40
39
38
37
36
35
34
33
32
31
30
29
B0
B1
B2
B3
B4
B5
B6
B7
PCLK
DISP
HSYNC
VSYNC
DE
D3V3
C2
C4
0.1uF 0.1uF 0.1uF
GND
C5
0.1uF
GND
D3V3
LEDK
LEDA
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
PCLK
DISP
HSYNC
VSYNC
DE
R25
R26
R27
R28
R29
33R
33R
33R
33R
33R
J2
12MHz
C8
18pF
GND
D3V3
VOUT1V2
Y1
C3
BL_PWM
CTP_RST#
CTP_INT#
CTP_SCL
CTP_SDA
15
16
17
18
19
20
21
22
23
24
25
26
27
28
7
C1
C7
18pF
GND
4.7uF
C6
0.1uF
GND
R30
4.7k
R31
1k
R32
1k
CTP_SCL
CTP_SDA
CTP_INT#
CTP_RST#
0
1
2
3
4
5
6
0
0
1
2
3
4
5
6
0
GND
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
0
LCD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VLEDVLED+
GND
VDD
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
GND
PCLK
DISP
HSYNC
VSYNC
DE
NC
GND
X1[Right]
Y1[Bottom]
X2[Left]
Y2[Top]
0.5B-40PBS
GND CN_6Pin_FPC Bottom
Figure 7-2 FT813 application circuit
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
D5V
L1
NR3015T220M
U3
2
LED Current Sense R45
ILED=95/1.6 = 60mA
VIN
AGND
PGND
EP
3
1N4148
6
FB
R40
4.7k
LEDK
D1
4
8
9
EN
C16
2.2nF
1
VOUT
BL_PWM
LEDA
7
SW
C17
C18
10uF
0.1uF
GND
MIC2289
R44
10k
GND
GND
R45
1R6
GND
C22
0.22uF
GND GND
Figure 7-3 Backlight drive circuit
D3V3
VDD_AUD
FB1
600R/1A
C9
100uF
FB2
C10
0.1uF
600R/1A
GND
AUD_PWM
R33
R34
AGND
R35
1k
1k
C12
4.7nF
AGND
C11
10nF
1k
C13
4.7nF
AGND
C14
4.7nF
AGND
C15
0.47uF
R36
10k/1%
VDD_AUD
R37
20k/1%
U2
4
3
AUD_PD#
1
2
ININ+
VDD
VO+
VOSHDN GND
BYPASS GND
6
5
8
7
9
SP1
SP+
SP1W/8Ohm
TPA6205A1
R42 20k/1%
R41
10k/1%
R43
47k
AGND
C20
0.47uF
AGND
C21
0.22uF
AGND
C19
1uF
AGND AGND
Figure 7-4 Audio filter and amplifier circuit
Copyright © 2015 Future Technology Devices International Limited
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
8
Package Parameters
The FT81x is available in VQFN-48 and VQFN-56 packages. The package dimensions, markings and solder
reflow profile for all packages are described in following sections.
8.1 VQFN-48 Package Dimensions
A
A1
A3
b
MIN.
0.80
0.00
0.20
NOM.
0.85
0.02
0.20
0.25
MAX.
0.90
0.05
0.30
All dimensions are in millimetres (mm)
D
E
7.00
7.00
D2
5.15
5.20
5.25
E2
5.15
5.20
5.25
e
0.50
L
0.35
0.40
0.45
K
0.20
L
0.30
0.40
0.50
K
0.20
Figure 8-1 VQFN-48 Package Dimensions
8.2 VQFN-56 Package Dimensions
A
A1
A3
b
MIN.
0.80
0.00
0.20
NOM.
0.85
0.02
0.20
0.25
MAX.
0.90
0.05
0.30
All dimensions are in millimetres (mm)
D
E
8.00
8.00
D2
5.85
5.90
5.95
E2
5.85
5.90
5.95
e
0.50
Figure 8-2 VQFN-56 Package Dimensions
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
8.3 Solder Reflow Profile
The FT81x is supplied in a Pb free VQFN-48 or VQFN-56 package. The recommended solder reflow profile
for the package is shown in Figure 8-3.
Temperature, T (Degrees C)
tp
Tp
Critical Zone: when
T is in the range
TL to Tp
Ramp Up
TL
tL
TS Max
Ramp
Down
TS Min
tS
Preheat
25
T = 25º C to TP
Time, t (seconds)
Figure 8-3 FT81x Solder Reflow Profile
The recommended values for the solder reflow profile are detailed in Table 8-1. Values are shown for
both a completely Pb free solder process (i.e. the FT81x is used with Pb free solder), and for a non-Pb
free solder process (i.e. the FT81x is used with non-Pb free solder).
Table 8-1 Reflow Profile Parameter Values
Profile Feature
Average Ramp Up Rate (Ts to Tp)
Pb Free Solder Process
Non-Pb Free Solder Process
3°C / second Max.
3°C / Second Max.
Preheat
- Temperature Min (Ts Min.)
- Temperature Max (Ts Max.)
- Time (ts Min to ts Max)
150°C
100°C
200°C
150°C
60 to 120 seconds
60 to 120 seconds
217°C
183°C 60 to 150 seconds
Time Maintained Above Critical Temperature
TL:
- Temperature (TL)
60 to 150 seconds
- Time (tL)
Peak Temperature (Tp)
260°C
240°C
Time within 5°C of actual Peak Temperature
20 to 40 seconds
20 to 40 seconds
6°C / second Max.
6°C / second Max.
8 minutes Max.
6 minutes Max.
(tp)
Ramp Down Rate
Time for T= 25°C to Peak Temperature, Tp
Copyright © 2015 Future Technology Devices International Limited
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
9
Contact Information
Head Office – Glasgow, UK
Unit 1, 2 Seaward Place, Centurion Business Park
Glasgow G41 1HH
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
[email protected]
[email protected]
[email protected]
Branch Office – Tigard, Oregon, USA
7130 SW Fir Loop
Tigard, OR 97223
USA
Tel: +1 (503) 547 0988
Fax: +1 (503) 547 0987
E-Mail (Sales)
E-Mail (Support)
E-Mail (General Enquiries)
[email protected]
[email protected]
[email protected]
Branch Office – Shanghai, China
Branch Office – Taipei, Taiwan
2F, No. 516, Sec. 1, NeiHu Road
Taipei 114
Taiwan, R.O.C.
Tel: +886 (0) 2 8797 1330
Fax: +886 (0) 2 8751 9737
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
[email protected]
[email protected]
[email protected]
Room 1103, No. 666 West Huaihai Road,
Changning District
Shanghai, 200052
China
Tel: +86 21 62351596
Fax: +86 21 62351595
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
[email protected]
[email protected]
[email protected]
Web Site
http://www.ftdichip.com
Distributor and Sales Representatives
Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales
representative(s) in your country.
System and equipment manufacturers and designers are responsible to ensure that their systems, and any Future Technology
Devices International Ltd (FTDI) devices incorporated in their systems, meet all applicable safety, regulatory and system-level
performance requirements. All application-related information in this document (including application descriptions, suggested
FTDI devices and other materials) is provided for reference only. While FTDI has taken care to assure it is accurate, this
information is subject to customer confirmation, and FTDI disclaims all liability for system designs and for any applications
assistance provided by FTDI. Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the
user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from
such use. This document is subject to change without notice. No freedom to use patents or other intellectual property rights is
implied by the publication of this document. Neither the whole nor any part of the information contained in, or the product
described in this document, may be adapted or reproduced in any material or electronic form without the prior written consent
of the copyright holder. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park,
Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number: SC136640
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
Appendix A – References
Useful Application Notes
FT81x_Series_Programmer_Guide
AN_252 FT800 Audio Primer
AN_254 FT800 Designs with Visual TFT
AN_259 FT800 Example with 8-bit MCU
AN_275 FT800 Example with Arduino
AN_276 Audio File Conversion
AN_277 FT800 Create User Defined Font
AN_291 FT800 Create Multi-Language Font
AN_299 FT800 FT801 Internal Clock Trimming
AN_303 - FT800 Image File Conversion
AN_308 FT800 Example with an 8-bit MCU
AN_312 FT800 Example with ARM
AN_314 FT800 Advanced Techniques - Working with Bitmaps
AN_318 Arduino Library for FT800 Series
AN_320 FT800 Example with PIC
AN_327 EVE Screen Editor Installation Guide
AN_281 FT800 Emulator Library User Guide
AN_333 FT800 and FT801 Touch Capabilities
AN_336 FT800 - Selecting an LCD Display
FT800 Series Sample Application
EVE Frequently Asked Questions
Copyright © 2015 Future Technology Devices International Limited
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
Appendix B - List of Figures and Tables
List of Figures
Figure 2-1 FT81x Block Diagram ..................................................................................................... 4
Figure 2-2 FT81x System Design Diagram ....................................................................................... 4
Figure 4-1 SPI master and slave in the master read case ................................................................. 14
Figure 4-2 Single/Dual SPI Interface connection ............................................................................. 14
Figure 4-3 Quad SPI Interface connection ...................................................................................... 15
Figure 4-4 Internal relaxation oscillator connection ......................................................................... 21
Figure 4-5 Crystal oscillator connection ......................................................................................... 21
Figure 4-6 External clock input ..................................................................................................... 21
Figure 4-7 RGB timing waveforms ................................................................................................. 28
Figure 4-8 Resistive Touch screen connection ................................................................................. 32
Figure 4-9 Touch screen connection .............................................................................................. 34
Figure 4-10 Internal regulator ...................................................................................................... 36
Figure 4-11 Power State Transition ............................................................................................... 37
Figure 6-1 SPI Interface Timing .................................................................................................... 49
Figure 6-2 RGB Interface Timing ................................................................................................... 51
Figure 7-1 FT812 application circuit............................................................................................... 52
Figure 7-2 FT813 application circuit............................................................................................... 52
Figure 7-3 Backlight drive circuit .................................................................................................. 53
Figure 7-4 Audio filter and amplifier circuit ..................................................................................... 53
Figure 8-1 VQFN-48 Package Dimensions ...................................................................................... 54
Figure 8-2 VQFN-56 Package Dimensions ...................................................................................... 54
Figure 8-3 FT81x Solder Reflow Profile .......................................................................................... 55
List of Tables
Table 3-1 FT81x pin description ...................................................................................................... 9
Table 4-1 QSPI channel selection .................................................................................................. 13
Table 4-2 Host memory read transaction ....................................................................................... 15
Table 4-3 Host memory write transaction ...................................................................................... 16
Table 4-4 Host command transaction ............................................................................................ 16
Table 4-5 Host command list ........................................................................................................ 16
Table 4-6 Interrupt Flags bit assignment ....................................................................................... 20
Table 4-7 Font table format ......................................................................................................... 23
Table 4-8 ROM font table ............................................................................................................. 23
Table 4-9 ROM font ASCII character width in pixels ......................................................................... 23
Table 4-10 ROM font Extended ASCII characters ............................................................................ 25
Table 4-11 RGB PCLK frequency ................................................................................................... 26
Table 4-12 REG_SWIZZLE RGB Pins Mapping ................................................................................. 27
Table 4-13 Registers for RGB horizontal and vertical timings ............................................................ 27
Table 4-14 Output drive current selection ...................................................................................... 29
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
Table 4-15 Sound Effect .............................................................................................................. 30
Table 4-16 MIDI Note Effect ......................................................................................................... 31
Table 4-17 Resistive Touch Controller Operating Mode .................................................................... 33
Table 4-18 Capacitive Touch Controller Operating Mode .................................................................. 34
Table 4-19 Power supply ............................................................................................................. 36
Table 4-20 Pin Status .................................................................................................................. 38
Table 5-1 FT81x Memory Map ...................................................................................................... 40
Table 5-2 Overview of FT81x Registers .......................................................................................... 40
Table 6-1 Absolute Maximum Ratings ............................................................................................ 46
Table 6-2 ESD and Latch-Up Specifications .................................................................................... 46
Table 6-3 Operating Voltage and Current ....................................................................................... 46
Table 6-4 Digital I/O Pin Characteristics (VCCIO = +3.3V) ............................................................... 47
Table 6-5 Digital I/O Pin Characteristics (VCCIO = +2.5V) ............................................................... 47
Table 6-6 Digital I/O Pin Characteristics (VCCIO = +1.8V) ............................................................... 48
Table 6-7 Touch Sense Characteristics .......................................................................................... 48
Table 6-8 System clock characteristics .......................................................................................... 49
Table 6-9 SPI Interface Timing Specification .................................................................................. 50
Table 6-10 RGB interface timing characteristics .............................................................................. 50
Table 8-1 Reflow Profile Parameter Values ..................................................................................... 55
Copyright © 2015 Future Technology Devices International Limited
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Document No.: FT_001165
FT81X Embedded Video Engine
Datasheet Version 1.2
Clearance No.: FTDI#440
Appendix C - Revision History
Document Title:
FT81X Embedded Video Engine Datasheet
Document Reference No.:
FT_001165
Clearance No.:
FTDI#440
Product Page:
http://www.ftdichip.com/EVE.htm
Document Feedback:
DS_FT81x
Revision
Changes
Date
Draft
Initial Release
2015-02-15
1.0
Revised Release
2015-07-07
1.1
Revised Release
2015-09-14
1.2
Revised Release
2015-09-29
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60