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All flip flops are clocked simultaneously on the low to high to transition (positive edge) of the clock input waveform. These counters may be preset using the load input. Presetting of all four flip flops is synchronous to the rising edge of clock. When load is held low counting is disabled and the data on the A, B, C and D inputs is loaded into the counter on the rising edge clock. If the load input is taken high before the positive edge of clock, the count operation will be unaffected. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • • • • • • • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV161AFPEL HD74LV161ARPEL HD74LV161ATELL SOP–16 pin(JEITA) SOP–16 pin(JEDEC) TSSOP–16 pin FP–16DAV FP–16DNV TTP–16DAV FP RP T EL (2,000 pcs/reel) EL (2,500 pcs/reel) ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Rev.4.00 Jun. 04, 2004 page 1 of 15 HD74LV161A Function Table Inputs Outputs CLR LOAD ENP ENT CLK QA QB QC QD L H H H H H X L H H H X X X X L H X X X L X H X X ↑ ↑ ↑ ↑ ↓ L A No change No change Count up No change L B L C L D Note: H: High level L: Low level X: Immaterial ↑: Low to high transition ↓: High to low transition A, B, C, D: Data input Carry = ENT • QA • QB • QC • QD Pin Arrangement CLR 1 16 VCC 15 CARRY OUTPUT CK 2 A 3 14 QA B 4 13 QB C 5 12 QC D 6 11 QD ENP 7 10 ENT GND 8 9 LOAD (Top view) Rev.4.00 Jun. 04, 2004 page 2 of 15 HD74LV161A Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range VCC Input voltage range*1 Output voltage range*1, 2 VI VO V V V Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at Ta = 25°C (in still air)*3 IIK IOK IO –0.5 to 7.0 –0.5 to 7.0 –0.5 to VCC + 0.5 –0.5 to 7.0 –20 ±50 ±25 ±50 Storage temperature Tstg ICC or IGND PT mA mA mA mA mW 785 500 –65 to 150 Conditions H or L Output: H or L VCC: OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC SOP TSSOP °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage range VCC Input voltage range Output voltage range Output current VI VO IOH 2.0 0 0 — — — — — — — — 0 0 0 5.5 5.5 VCC –50 –2 –6 –12 50 2 6 12 200 100 20 V V V µA mA –40 85 °C IOL Input transition rise or fall rate ∆t /∆v Operating free-air temperature Ta Note: Unused or floating inputs must be held high or low. Rev.4.00 Jun. 04, 2004 page 3 of 15 µA mA ns/V Conditions VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V HD74LV161A Logic Diagram CLK CLR D Q Output QA CK LOAD Enable Q CLR P T A D Q Output QB CK Q CLR B D Q Output QC CK Data Inputs Q CLR C D Q Output QD CK Q CLR D Carry Output Rev.4.00 Jun. 04, 2004 page 4 of 15 HD74LV161A Timing Diagram CLR LOAD A Data Inputs B C D CLK ENP ENT QA Out puts QB QC QD Carry 12 13 14 15 0 Count Clear Rev.4.00 Jun. 04, 2004 page 5 of 15 Preset (Load) 1 2 Inhibit HD74LV161A DC Electrical Characteristics Ta = –40 to 85°C Item Symbol VCC (V)* Min Typ Max Unit Input voltage VIH 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 — — — — VCC – 0.1 2.0 2.48 3.8 — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 — — — — 0.1 0.4 0.44 0.55 ±1 20 V Input current Quiescent supply current IIN ICC 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 2.3 3.0 4.5 0 to 5.5 5.5 Output leakage current IOFF 0 — — Input capacitance CIN 3.3 — 1.7 VIL Output voltage VOH VOL Test Conditions µA µA IOL = –50 µA IOL = –2 mA IOL = –6 mA IOL = –12 mA IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA VIN = 5.5 V or GND VIN = VCC or GND, IO = 0 5 µA VI or VO = 0 V to 5.5 V — pF VI = VCC or GND V Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.4.00 Jun. 04, 2004 page 6 of 15 HD74LV161A Switching Characteristics VCC = 2.5 ± 0.2 V Ta = 25°C Ta = –40 to 85°C Test Conditions Item Symbol Min Typ Max Min Max Unit Maximum clock frequency fmax 50 30 90 60 — — 40 25 — — MHz CL = 15 pF CL = 50 pF Propagation delay time tPLH/tPHL 11.1 14.3 11.5 14.7 16.2 19.2 17.0 20.0 1.0 1.0 1.0 1.0 19.5 22.5 20.5 23.5 ns tPLH/tPHL Count mode — — — — tPLH/tPHL Load mode — — 13.8 17.0 20.6 23.6 1.0 1.0 24.5 27.5 tPLH/tPHL — — — — — — 7.5 10.0 9.5 10.3 14.0 11.7 14.7 11.2 14.4 — — — 15.7 18.7 17.0 20.0 16.6 19.6 — — — 1.0 1.0 1.0 1.0 1.0 1.0 8.5 11.5 11.0 19.0 22.0 20.5 23.5 20.0 23.0 — — — CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 4.5 — — 4.5 — 1.5 7.0 7.0 — — — — — — 1.5 7.0 7.0 — — — tPHL tPHL Setup time Hold time Pulse width tsu th tw Rev.4.00 Jun. 04, 2004 page 7 of 15 ns FROM (Input) TO (Output) CLK Q CLK Carry CLK Carry ENT Carry CLR Q CLR Carry Data before CLK ↑ LOAD before CLK ↑ ENT, ENP before CLK ↑ CLR inactive before CLK ↑ ns ns CLK H or L CLR L HD74LV161A Switching Characteristics (cont) VCC = 3.3 ± 0.3 V Ta = 25°C Ta = –40 to 85°C Test Conditions Item Symbol Min Typ Max Min Max Unit Maximum clock frequency fmax 80 55 130 85 — — 70 50 — — MHz CL = 15 pF CL = 50 pF Propagation delay time tPLH/tPHL 8.3 10.8 8.7 11.2 12.8 16.3 13.6 17.1 1.0 1.0 1.0 1.0 15.0 18.5 16.0 19.5 ns tPLH/tPHL Count mode — — — — tPLH/tPHL Load mode — — 11.0 13.5 17.2 20.7 1.0 1.0 20.0 23.5 tPLH/tPHL — — — — — — 5.5 8.0 7.5 7.5 10.5 8.9 11.2 8.4 10.9 — — — 12.3 15.8 13.6 17.1 13.2 16.7 — — — 1.0 1.0 1.0 1.0 1.0 1.0 6.5 9.5 9.0 14.5 18.0 16.0 19.5 15.5 19.0 — — — CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 2.5 — — 2.5 — 1.0 5.0 5.0 — — — — — — 1.0 5.0 5.0 — — — tPHL tPHL Setup time Hold time Pulse width tsu th tw Rev.4.00 Jun. 04, 2004 page 8 of 15 ns FROM (Input) TO (Output) CLK Q CLK Carry CLK Carry ENT Carry CLR Q CLR Carry Data before CLK ↑ LOAD before CLK ↑ ENT, ENP before CLK ↑ CLR inactive before CLK ↑ ns ns CLK H or L CLR L HD74LV161A Switching Characteristics (cont) VCC = 5.0 ± 0.5 V Ta = 25°C Ta = –40 to 85°C Test Conditions Item Symbol Min Typ Max Min Max Unit Maximum clock frequency fmax 135 95 185 125 — — 115 85 — — MHz CL = 15 pF CL = 50 pF Propagation delay time tPLH/tPHL 4.9 8.7 4.9 6.4 8.1 10.1 8.1 10.1 1.0 1.0 1.0 1.0 9.5 11.5 9.5 11.5 ns tPLH/tPHL Count mode — — — — tPLH/tPHL Load mode — — 6.2 7.7 10.3 12.3 1.0 1.0 12.0 14.0 tPLH/tPHL — — — — — — 4.5 5.0 5.0 4.9 6.4 5.5 7.0 5.0 6.5 — — — 8.1 10.1 9.0 11.0 8.6 10.6 — — — 1.0 1.0 1.0 1.0 1.0 1.0 4.5 6.0 6.0 9.5 11.5 10.5 12.5 10.0 12.0 — — — CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 1.5 — — 1.5 — 1.0 5.0 5.0 — — — — — — 1.0 5.0 5.0 — — — tPHL tPHL Setup time Hold time Pulse width tsu th tw FROM (Input) TO (Output) CLK Q CLK Carry CLK Carry ENT Carry CLR Q CLR Carry Data before CLK ↑ LOAD before CLK ↑ ns ENT, ENP before CLK ↑ CLR inactive before CLK ↑ ns ns CLK H or L CLR L Operating Characteristics CL = 50 pF Item Symbol VCC (V) Ta = 25°C Min Typ Power dissipation capacitance CPD 3.3 5.0 — — Rev.4.00 Jun. 04, 2004 page 9 of 15 17.0 20.4 Max Unit Test Conditions — — pF f = 10 MHz HD74LV161A Noise Characteristics CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Quiet output, maximum dynamic VOL VOL (P) 3.3 — 0.3 0.8 V Quiet output, minimum dynamic VOL VOL (V) 3.3 — –0.3 –0.8 V Quiet output, minimum dynamic VOH VOH (V) 3.3 — 3.0 — V High-level dynamic input voltage VIH (D) 3.3 2.31 — — V Low-level dynamic input voltage VIL (D) 3.3 — — 0.99 V Test Circuit Measurement point CL* Note: Rev.4.00 Jun. 04, 2004 page 10 of 15 1. CL includes the probe and jig capacitance. Test Conditions HD74LV161A Waveforms Waveform − 1 Count mode twH twL VCC CLK 50%VCC 50%VCC GND VOH Q, CARRY 50%VCC 50%VCC VOL tpLH tpHL Waveform − 2 Preset mode VCC LOAD 50%VCC 50%VCC tsu tsu GND th A~D th 50%VCC tsu th VCC CLK 50%VCC 50%VCC GND tpLH,tpHL VOH Q, CARRY 50%VCC VOL Rev.4.00 Jun. 04, 2004 page 11 of 15 HD74LV161A Waveform − 3 Count enable mode VCC ENP ENT 50%VCC 50%VCC tsu tsu GND th th VCC CK 50%VCC 50%VCC GND VOH Q VOL Waveform − 4 Clear mode VCC CLR 50%VCC GND twL VCC CLK 50%VCC GND tsu VOH Q, CARRY 50%VCC tpHL Rev.4.00 Jun. 04, 2004 page 12 of 15 VOL HD74LV161A Waveform − 5 Cascade mode (Set to maximum count number) VCC ENT 50%VCC 50%VCC GND VOH CARRY 50%VCC 50%VCC VOL tpLH tpHL Note: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t r ≤ 3 ns, t f ≤ 3 ns Application Cascade circuitry H: COUNT L: DISABLE INPUTS LD A B C INPUTS D ENP H: COUNT L: DISABLE ENT LD A B C INPUTS D ENP CARRY ENT LD A B C D ENP CARRY ENT CARRY CK CK CK CLR QA QB QC QD CLR QA QB QC QD CLR QA QB QC QD OUTPUT CLR CLK Rev.4.00 Jun. 04, 2004 page 13 of 15 OUTPUT OUTPUT to next stages HD74LV161A Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.40 ± 0.06 0.20 7.80 +– 0.30 1.15 0 ˚ – 8˚ 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 16 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-16DAV — Conforms 0.24 g As of January, 2003 Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.40 ± 0.06 0.15 *0.20 ± 0.05 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0˚ – 8˚ 0.67 0.60 +– 0.20 0.25 M *Ni/Pd/Au plating Rev.4.00 Jun. 04, 2004 page 14 of 15 Package Code JEDEC JEITA Mass (reference value) FP-16DNV Conforms Conforms 0.15 g HD74LV161A As of January, 2003 Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 1.0 0.13 M 6.40 ± 0.20 *Ni/Pd/Au plating Rev.4.00 Jun. 04, 2004 page 15 of 15 0.10 *0.15 ± 0.05 1.10 Max 0.65 Max 0.07 +0.03 –0.04 *0.20 ± 0.05 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-16DAV — — 0.05 g Sales Strategic Planning Div. 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