MP2019 40V, 300mA, Low Quiescent Current Adjustable Output Linear Regulator DESCRIPTION FEATURES The MP2019 is a low-power linear regulator that supplies power to systems with highvoltage batteries. It includes a wide 3V to 40V input range, low-dropout voltage, and a low quiescent-supply current. The low quiescent current and low dropout voltage allow operations at extremely low-power levels. Therefore, the MP2019 is ideal for low-power microcontrollers and battery-powered equipment. The MP2019 provides a wide variety of fixed output-voltage options (if requested): 1.8V, 1.9V, 2.3V, 2.5V, 3.0V, 3.3V, 3.45V, and 5.0V; also, it provides the output-adjustable option (from 1.25V to 15V). The regulator output current is limited internally, and the device is protected against short-circuit, over-load, and over-temperature conditions. The MP2019 includes thermal shutdown (TSD), current-limiting fault protection, and is available in a SOIC-8 EP package. 3V to 40V Input Range 10µA Quiescent Supply Current Stable with Low-Value Output Ceramic Capacitor (> 0.47μF) 300mA Specified Current Fixed 5V, 3.3V, and Adjustable Output (1.2 V to 15 V) Versions Output ±2% Accuracy Over Temperature Specified Current Limit Power Good Programmable Power Good Delay Thermal Shutdown and Short-Circuit Protection -40°C to +125°C Specified JunctionTemperature Range Available in a SOIC-8 EP Package APPLICATIONS Industrial/Automotive Applications Portable/Battery-Powered Equipment Ultra-Low Power Microcontrollers Cellular Handsets Medical Imaging All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION IN IN EN OUT MP2019GN PG FB PGDL EN OUT MP2019GN PG FB PGDL GND Output-Adjustable Version MP2019 Rev. 1.01 1/10/2018 Vout Vout GND Output-Fixed Version www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 1 MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR ORDERING INFORMATION Part Number* Package MP2019GN SOIC-8 EP MP2019GN-33 SOIC-8 EP MP2019GN-5 SOIC-8 EP Top Marking See Below * For Tape & Reel, add suffix –Z (e.g. MP2019GN–Z); TOP MARKING MP2019: part code of MP2019GN; LLLLLLLL: lot number; MPS: MPS prefix: Y: year code; WW: week code: TOP MARKING MP2019-33: part code of MP2019GN-33 LLLLLLLL: lot number; MPS: MPS prefix: Y: year code; WW: week code: TOP MARKING MP2019-5: part code of MP2019GN-5 LLLLLLLL: lot number; MPS: MPS prefix: Y: year code; WW: week code: MP2019 Rev. 1.01 1/10/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 2 MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR PACKAGE REFERENCE FB OUT PGDL NC GND PG VIN EN SOIC-8 EP ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance IN, EN .......................................... -0.3V to +42V OUT ............................................. -0.3V to +17V PG .............................................. -0.3V to +15V PGDL, FB ...................................... -0.3V to +6V Junction Temperature ............................ +150C Lead Temperature ................................. +260C Storage Temperature ............... -65C to +150C (2) Continuous Power Dissipation (TA = +25°C) SOIC-8 EP .................................................2.5W SOIC-8 EP.............................. 50 ...... 10 ... C/W Notes: 1) 2) ESD SUSCEPTIBILITY (3) HBM (Human Body Mode) ...........................4kV MM (Machine Mode)...................................200V Recommended Operating Conditions (4) 3) 4) 5) (5) θJA θJC Exceeding these ratings may damage the device. The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-to-ambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)TA)/θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. Devices are ESD sensitive. Handle with precaution. The device is not guaranteed to function outside of its operating conditions. Measured on JESD51-7, 4-layer PCB. Supply Voltage VIN ............................. 3V to 40V Output Voltage VOUT ..................... 1.25V to 15V Operating Temperature ...... TJ=-40°C to +125°C MP2019 Rev. 1.01 1/10/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 3 MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE ELECTRICAL CHARACTERISTICS VIN = VEN = 13.5V, TJ =+25°C, unless otherwise noted. Parameter Symbol Condition Input Voltage Output-Voltage Range Max Units VIN 3 40 V 1.25 V IGND MP2019GN-33 MP2019GN-5 Shutdown Supply Current Typ VOUT MP2019GN GND Current Min IS 0<ILOAD<1mA 1mA<ILOAD<30mA 30mA<ILOAD<300mA 0<ILOAD<1mA 10 15 65 12 15 15 21 95 16 1mA<ILOAD<30mA 30mA<ILOAD<300mA 0<ILOAD<1mA 1mA<ILOAD<30mA 30mA<ILOAD<300mA 16 65 12 16 65 22 95 16 22 95 µA 1 µA VEN =0V Load Current Limit ILIMIT VIN=7V, VOUT = 0V FB Voltage VFB MP2019GN, FB = OUT, ILOAD=5mA 1000 1350 mA 1.225 1.25 1.275 V MP2019GN-33, ILOAD=5mA 3.2 3.3 3.4 MP2019GN-5, ILOAD=5mA 4.85 5 5.15 200 400 420 550 230 430 V MP2019GN (6) VDROPOUT MP2019GN-33 MP2019GN-5 FB Input Current Line Regulation MP2019 Rev. 1.01 1/10/2018 µA 600 Output Voltage Accuracy Dropout Voltage µA IFB VOUT=5V, ILOAD = 150mA VOUT=5V, ILOAD = 300mA VOUT=3.3V, ILOAD = 150mA VOUT=3.3V, ILOAD = 300mA VOUT=5V, ILOAD = 150mA VOUT=5V, ILOAD = 300mA mV 480 640 230 430 480 640 MP2019GN VFB = 1.3V 50 MP2019GN VIN = 3V to 40V, ILOAD = 5mA, VOUT = VFB -10 1 10 MP2019GN-33 VIN = 5V to 40V, ILOAD = 5mA, VOUT = 3.3V -10 1 10 MP2019GN-5 VIN = 6V to 40V, ILOAD = 5mA, VOUT = 6V -10 1 10 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. nA mV 4 MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE ELECTRICAL CHARACTERISTICS (continued) VIN = VEN = 13.5V, TJ =+25°C, unless otherwise noted. Parameter Symbol Condition Load Regulation Output Voltage PSRR (7) Start-Up Response Time EN Threshold Voltage VIL VIH EN Input Current PG Reaction Time CPGDL=47nF Notes: 6) 7) Shutdown 15 1 15 1 15 0.9 1.5 0.5 1 0.9 1.5 89% 88% 88% 0.1 93% 92% 92% CPGDL=47nF 0.1 3 1.4 0.2 5 mV dB dB dB 0.5 97% 96% 96% 5% Sink 1mA Current VPG=5V VPGDL=1V Thermal (7) Hysteresis 1 0.3 PG Low Voltage PG Leakage Current PGDL Charging Current PGDL Rising Threshold PGDL Falling Threshold PG Delay Time (7) Max Units 57 45 51 Threshold Thermal Shutdown Typ 1.8 EN = 0V or 15V MP2019GN MP2019GN-33 MP2019GN-5 PG Rising Threshold PG Rising Hysteresis Min ILOAD = 5mA to 300mA, MP2019GN VOUT = 5V ILOAD = 5mA to 300mA, MP2019GN-33 VOUT = 3.3V ILOAD = 5mA to 300mA, MP2019GN-5 VOUT = 5V 100Hz, COUT = 10μF, ILOAD=10mA 1kHz, COUT = 10μF, ILOAD=10mA 100kHz, COUT = 10μF, ILOAD=10mA RLOAD=500Ω, VOUT = 5V, MP2019GN COUT=22µF, VOUT from 10% to 90% RLOAD=500Ω,VOUT=3.3V, MP2019GN-33 COUT=22µF, VOUT from 10% to 90% RLOAD=500Ω,VOUT=5V, MP2019GN-5 COUT=22µF, VOUT from 10% to 90% ms V V μA VFB VFB 5.5 1.7 0.4 10 0.4 1 9 2 0.7 15 V µA µA V V ms 0.5 2 µs TSD 165 C ΔTSD 30 C Dropout Voltage: Measured when the output voltage VOUT has dropped 100mV from the nominal value obtained at VIN=13.5V. Derived from bench characterization. Not tested in production. MP2019 Rev. 1.01 1/10/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 5 MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE PIN FUNCTIONS Pin # Name 1 OUT 2 3 4 NC GND VIN 5 EN 6 7 PG PGDL 8 FB MP2019 Rev. 1.01 1/10/2018 Description Regulated Output Voltage. Only a low-value ceramic capacitor (≥ 0.47μF) on the output is required for stability. No Connection. Do NOT connect. Ground. Connect the exposed pad and GND to the same ground plane. Input Voltage. Connect a 3V to 40V supply to VIN. Regulator On/Off Control Input. Logic low shuts down the IC; logic high starts up the IC. Connect EN to VIN for automatic start-up. Power Good. If not used, pin can be left floating. Programmable Power-Good Delay Time. If not used, pin can be left floating. Feedback Input for Output Adjustable Version. FB is regulated to 1.25V nominally. This terminal is used to set the output voltage. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 6 MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE TYPICAL PERFORMANCE CHARACTERISTICS MP2019 Rev. 1.01 1/10/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 7 MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE TYPICAL PERFORMANCE CHARACTERISTICS CIN = 1µF, COUT = 22µF, VOUT = 5V, TA = 25°C, unless otherwise noted. MP2019 Rev. 1.01 1/10/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 8 MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE TYPICAL PERFORMANCE CHARACTERISTICS (continued) CIN = 1µF, COUT = 22µF, VOUT = 5V, TA = 25°C, unless otherwise noted. MP2019 Rev. 1.01 1/10/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 9 MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE TYPICAL PERFORMANCE CHARACTERISTICS (continued) CIN = 1µF, COUT = 22µF, VOUT = 5V, TA = 25°C, unless otherwise noted. MP2019 Rev. 1.01 1/10/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 10 MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE OPERATION The MP2019 is a linear regulator that supplies power to systems with high-voltage batteries. It includes a wide 3V to 40V input range, low dropout voltage, and a low quiescent-supply current (see Fig. 1). The MP2019 provides a wide variety of fixed output-voltage options: 1.8V, 1.9V, 2.3V, 2.5V, 3.0V, 3.3V, 3.45V, and 5.0V; also, it provides the output-adjustable option (from 1.25V to 15V). The output-adjustable version has an output that is adjustable from 1.25V to 15V with a simple resistor divider. It uses external feedback, allowing the user to set the output voltage with an external resistor divider. The FB threshold is 1.25V, typically. The IC enters shutdown mode when EN is low. In shutdown mode, the pass transistor, control circuitry, reference, and all biases turn off; this reduces the supply current to <1µA. Connect EN to VIN for automatic start-up. The regulator output current is limited internally, and the device is protected against short-circuit, over-load, and over-temperature conditions (see Fig. 2). which shuts down the IC. The IC will re-start when the temperature has cooled sufficiently. The maximum power output current is a function of the package’s maximum power dissipation for a given temperature. The maximum power dissipation is dependent on the thermal resistance of the case and the circuit board, the temperature difference between the die junction and the ambient air, and the rate of air flow. GND and the exposed pad must be connected to the ground plane for proper dissipation. MP2019 has one power good (PG) pin. The PG pin is the open drain of an internal MOSFET. It should be connected to VOUT or external voltage source(<15V) through a resistor (i.e. 100kohm). After the VFB reaches 93% of nominal value, the MOSFET turns off and PG pin is pulled to high by VOUT or external voltage source. When the VFB drops to 88% of nominal value, the PG voltage is pulled to GND. There is a delay time when PG asserts high. The delay time can be programmed by adding a capacitor on PGDL. To select a capacitor for PGDL, use below equation: CPGDL (nF) tPGDL (ms) IPGDL ( A) Vth_PGDL (V) The peak output current is limited to around 1000mA, which exceeds the 300mA recommended continuous output current. Where tPGDL is the desired delay time for PG asserts high, IPGDL is the PGDL charging current and Vth_PGDL is 1.7V. When the junction temperature is too high, the thermal sensor sends a signal to the control logic Figure 2 shows the power good timing. VIN UVLO Vreference EA VOUT EN For Fixed Output Version Only FB PG PG PGDL GND Figure 1. Functional Block Diagram MP2019 Rev. 1.01 1/10/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 11 MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE IIN 4 VIN IN CIN 1uF 5 EN OUT MP2019GN IOUT 1 Vo R1 FB 8 COUT 22uF RPG 100K R2 IPGDL 7 VPGDL CPGDL 47nF IPG PG PGDL GND VPG 6 3 IGND VIN t < tPGR VOUT VPG-High t d∆V/d∆t =IPGDL/CPGDL VPGDL VPGDL-High VPGDL-Low t VPG tPGD tPGR t Power-On Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Overload at Spike Output Figure 2. Power Good Timing MP2019 Rev. 1.01 1/10/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 12 MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR APPLICATION INFORMATION COMPONENT SELECTION Setting the Output Voltage Set the output voltage of the MP2019 by using a resistor divider (see Fig. 3). OUT VOUT MP2019 GND R1 R2 Choose R2=1MΩ to maintain a 1.215µA minimum load. Calculate the value for R1 using the following equation: V R1 R2 OUT 1 1.25V For a fixed-output version, VOUT can be adjusted by adding an external resistor divider (see Fig. 4). When choosing an external divider, take the internal FB resistor divider into consideration. OUT VOUT R1_IN R2_IN GND R1 FB R2 Figure 4. FB Divider for Fixed-Output Version When R2 is selected, R1 can be calculated with the equation below: R1_ IN R1 1.25 R1_ IN R2 R2 _ IN 1 VOUT 1.25 R2 R2 _ IN Table 1 below shows the internal FB resistor dividers for different fixed-output versions. Table 1. Internal FB Resistor Divider Fixed-Output Voltage 3.3V 5V MP2019 Rev. 1.01 1/10/2018 Table 2. 3.3V Fixed-Output Version with External FB Divider VOUT(V) 11 8.5 8 6.5 5 R1 (k) 80.6 59 54.9 43 30.1 R2 (k) 10 10 10 10 10 FB Figure 3. FB Resistor Divider to Set VOUT MP2019 Table 2 below shows various output voltages for a fixed-output version with an external FB divider.. R1_IN 1.64MΩ 3MΩ R2_IN 1MΩ 1MΩ Enable Control (EA) EN is a digital control pin that turns the regulator on and off. When EN is pulled below 0.3V, the chip shuts down. When EN is pulled above 1.8V, the chip starts up. If this function is not used, EN can be connected to VIN directly. Input Capacitor For efficient operation, place a ceramic capacitor, (C1) between 1µF and 10µF of dielectric type (X5R or X7R) between the input pin and ground. Larger values in this range improve line transient response. Output Capacitor For stable operation, use a ceramic capacitor (C2) of type X5R or X7R between 1µF and 22µF. Larger values in this range improve load transient response and reduce noise. Output capacitors of other dielectric types may be used, but they are not recommended as their capacitance can deviate greatly from their rated value over temperature. To improve load transient response, add a small ceramic (X5R, X7R, or Y5V dielectric) 2.2nF feed-forward capacitor in parallel with R1. The feed-forward capacitor is not required for stable operation. Output Noise The MP2019 exhibits noise on the output during normal operation. This noise is negligible for most applications. However, in applications that include analog-to-digital converters (ADCs) of more than 12 bits, consider the ADC’s power supply rejection specifications. The feed-forward capacitor C2 across R1 reduces significantly the output noise. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 13 MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR External Reverse Voltage Protection In some situations, e.g. a backup battery is connected as MP2019 load, the output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is floating. Thus, the output voltage is higher than input voltage. Since the MP2019 PMOS pass element has a body diode, a current will conduct from the output to input and is not internally limited. It’s possible that the IC will be damaged by this unlimited reverse current. To avoid this, it’s recommended to place an external diode at input like below. VIN D1 VOUT OUT IN MP2019 Top Layer GND PCB Layout Guidelines Efficient PCB layout is critical to achieve good regulation, ripple rejection, transient response, and thermal performance. It is recommended highly to duplicate the EVB layout for optimum performance. If changes are necessary, refer to Fig. 5 and follow the guidelines below: 1) Place input and output bypass ceramic capacitors close to IN and OUT, respectively. 2) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the chip as possible. 3) Connect IN, OUT, and especially, GND, respectively, to a large copper area to cool the chip. This improves thermal performance and long-term reliability. VIN IN EN C4 PGDL GND C2 PG Fig. 6 is a design example following the application guidelines for VOUT=3.3V with a feedforward cap: VIN IN C1 1uF R2 R3 C3 C4 47nF VOUT OUT MP2019 R1 FB C1 DESIGN EXAMPLE VOUT OUT MP2019 Bottom Layer Figure 5. Recommended PCB Layout EN FB PGDL GND PG C2 2.2nF R1 1.64MΩ R2 1MΩ R3 3.3V C3 22uF 100KΩ Figure 6. Design Example MP2019 Rev. 1.01 1/10/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 14 MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR TYPICAL APPLICATION CIRCUITS VIN IN VOUT OUT R1 1.64MΩ MP2019 EN C1 1uF C3 47nF PGDL GND R2 1MΩ FB R3 PG 3.3V C2 22uF 100KΩ Figure 7. 3.3V Output Typical Application Circuit VIN IN MP2019 EN C1 1uF C4 47nF VOUT OUT PGDL GND FB PG C2 2.2nF R1 1.64MΩ R2 1MΩ R3 3.3V C3 22uF 100KΩ Figure 8. 3.3V Output with Feed-Forward Capacitor MP2019 Rev. 1.01 1/10/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 15 MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR PACKAGE INFORMATION SOIC-8 EP 0.189(4.80) 0.197(5.00) 8 0.124(3.15) 0.136(3.45) 5 0.150(3.80) 0.157(4.00) PIN 1 ID 1 0.228(5.80) 0.244(6.20) 0.089(2.26) 0.101(2.56) 4 TOP VIEW BOTTOM VIEW SEE DETAIL "A" 0.013(0.33) 0.020(0.51) 0.051(1.30) 0.067(1.70) SEATING PLANE 0.000(0.00) 0.006(0.15) 0.0075(0.19) 0.0098(0.25) SIDE VIEW 0.050(1.27) BSC FRONT VIEW 0.010(0.25) x 45o 0.020(0.50) GAUGE PLANE 0.010(0.25) BSC 0.050(1.27) 0.024(0.61) 0o-8o 0.016(0.41) 0.050(1.27) 0.063(1.60) DETAIL "A" 0.103(2.62) 0.138(3.51) RECOMMENDED LAND PATTERN 0.213(5.40) NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKETS IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION BA. 6) DRAWING IS NOT TO SCALE. NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2019 Rev. 1.01 1/10/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 16