Holtek HT32F52331 32-bit arm cortex-m0 microcontroller Datasheet

HT32F52231/HT32F52241
HT32F52331/HT32F52341
Datasheet
32-Bit ARM® Cortex™-M0+ Microcontroller,
up to 64 KB Flash and 8 KB SRAM with 1 MSPS ADC,
USART, UART, SPI, I2C, MCTM, GPTM, SCTM, BFTM,
SCI, CRC, RTC, WDT, and USB2.0 FS
Revision: V1.51
Date: April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Table of Contents
1 General Description................................................................................................. 6
2 Features.................................................................................................................... 7
Core........................................................................................................................................ 7
Flash Memory Controller – FMC............................................................................................. 7
Reset Control Unit – RSTCU.................................................................................................. 8
Clock Control Unit – CKCU..................................................................................................... 8
Power Management – PWRCU.............................................................................................. 8
External Interrupt/Event Controller – EXTI............................................................................. 9
Analog to Digital Converter – ADC......................................................................................... 9
I/O Ports – GPIO..................................................................................................................... 9
Motor Control Timer – MCTM............................................................................................... 10
PWM Generation and Capture Timers – GPTM................................................................... 10
Single Channel Generation and Capture Timers – SCTM.................................................... 11
Basic Function Timer – BFTM.............................................................................................. 11
Watchdog Timer – WDT........................................................................................................ 11
Real Time Clock – RTC........................................................................................................ 12
Inter-integrated Circuit – I2C................................................................................................. 12
Serial Peripheral Interface – SPI.......................................................................................... 12
Universal Synchronous Asynchronous Receiver Transmitter – USART............................... 13
Universal Asynchronous Receiver Transmitter – UART....................................................... 13
Smart Card Interface – SCI (HT32F52331/52341 only)....................................................... 14
Cyclic Redundancy Check – CRC........................................................................................ 14
Universal Serial Bus Device Controller – USB (HT32F52331/52341 only).......................... 15
Debug Support...................................................................................................................... 15
Package and Operation Temperature................................................................................... 15
3 Overview................................................................................................................. 16
Device Information................................................................................................................ 16
Block Diagram...................................................................................................................... 17
Memory Map......................................................................................................................... 18
Clock Structure..................................................................................................................... 21
4 Pin Assignment...................................................................................................... 22
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Table of Contents
On-chip Memory..................................................................................................................... 7
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
5 Electrical Characteristics...................................................................................... 32
Absolute Maximum Ratings.................................................................................................. 32
Recommended DC Operating Conditions............................................................................ 32
On-Chip LDO Voltage Regulator Characteristics.................................................................. 32
Power Consumption............................................................................................................. 33
External Clock Characteristics.............................................................................................. 36
Internal Clock Characteristics............................................................................................... 37
PLL Characteristics............................................................................................................... 37
Memory Characteristics........................................................................................................ 37
I/O Port Characteristics......................................................................................................... 38
ADC Characteristics............................................................................................................. 39
SCTM/GPTM/MCTM Characteristics.................................................................................... 40
I2C Characteristics................................................................................................................ 41
SPI Characteristics............................................................................................................... 42
USB Characteristics.............................................................................................................. 44
6 Package Information............................................................................................. 45
24-pin SSOP (150mil) Outline Dimensions........................................................................... 46
28-pin SSOP (150mil) Outline Dimensions........................................................................... 47
SAW Type 33-pin (4mm×4mm) QFN Outline Dimensions.................................................... 48
48-pin LQFP (7mm×7mm) Outline Dimensions.................................................................... 49
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Table of Contents
Reset and Supply Monitor Characteristics............................................................................ 35
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
List of Tables
Rev. 1.51
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April 11, 2017
List of Tables
Table 1. Features and Peripheral List....................................................................................................... 16
Table 2. Register Map .............................................................................................................................. 19
Table 3. HT32F52231/52241 Series Pin Assignment for 24/28SSOP, 33QFN, 48LQFP Package........... 28
Table 4. HT32F52331/52341 Series Pin Assignment for 33QFN, 48LQFP Package............................... 29
Table 5. HT32F52231/52241 Pin Description........................................................................................... 30
Table 6. HT32F52331/52341 Pin Description........................................................................................... 31
Table 7. Absolute Maximum Ratings......................................................................................................... 32
Table 8. Recommended DC Operating Conditions................................................................................... 32
Table 9. LDO Characteristics.................................................................................................................... 32
Table 10. HT32F52231/52241 Power Consumption Characteristics........................................................ 33
Table 11. HT32F52331/52341 Power Consumption Characteristics........................................................ 34
Table 12. VDD Power Reset Characteristics.............................................................................................. 35
Table 13. LVD/BOD Characteristics.......................................................................................................... 35
Table 14. High Speed External Clock (HSE) Characteristics.................................................................... 36
Table 15. Low Speed External Clock (LSE) Characteristics..................................................................... 36
Table 16. High Speed Internal Clock (HSI) Characteristics...................................................................... 37
Table 17. Low Speed Internal Clock (LSI) Characteristics........................................................................ 37
Table 18. PLL Characteristics................................................................................................................... 37
Table 19. Flash Memory Characteristics................................................................................................... 37
Table 20. I/O Port Characteristics............................................................................................................. 38
Table 21. ADC Characteristics.................................................................................................................. 39
Table 22. SCTM/GPTM/MCTM Characteristics........................................................................................ 40
Table 23. I2C Characteristics..................................................................................................................... 41
Table 24. SPI Characteristics.................................................................................................................... 42
Table 25. USB DC Electrical Characteristics............................................................................................ 44
Table 26. USB AC Electrical Characteristics............................................................................................. 44
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
List of Figures
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April 11, 2017
List of Figures
Figure 1. Block Diagram........................................................................................................................... 17
Figure 2. Memory Map.............................................................................................................................. 18
Figure 3. Clock Structure.......................................................................................................................... 21
Figure 4. HT32F52231/52241 24-pin SSOP Pin Assignment................................................................... 22
Figure 5. HT32F52231/52241 28-pin SSOP Pin Assignment................................................................... 23
Figure 6. HT32F52231/52241 33-pin QFN Pin Assignment..................................................................... 24
Figure 7. HT32F52231/52241 48-pin LQFP Pin Assignment................................................................... 25
Figure 8. HT32F52331/52341 33-pin QFN Pin Assignment..................................................................... 26
Figure 9. HT32F52331/52341 48-pin LQFP Pin Assignment................................................................... 27
Figure 10. ADC Sampling Network Model................................................................................................ 40
Figure 11. I2C Timing Diagrams................................................................................................................ 41
Figure 12. SPI Timing Diagrams – SPI Master Mode............................................................................... 42
Figure 13. SPI Timing Diagrams – SPI Slave Mode with CPHA=1........................................................... 43
Figure 14. USB Signal Rise Time and Fall Time and Cross-point Voltage (VCRS) Definition.................. 44
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
1
General Description
The HOLTEK HT32F522x1/523x1 devices are high performance, low power consumption 32-bit
microcontrollers based around an ARM® Cortex™-M0+ processor core. The Cortex™-M0+ is a
next-generation processor core which is tightly coupled with Nested Vectored Interrupt Controller
(NVIC), SysTick timer, and including advanced debug support.
The above features ensure that the devices are suitable for use in a wide range of applications,
especially in areas such as white goods application control, power monitors, alarm systems,
consumer products, handheld equipment, data logging applications, motor control and so on.
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General Description
The devices operate at a frequency of up to 40MHz for HT32F52231/52241 and 48MHz for
HT32F52331/52341 with a Flash accelerator to obtain maximum efficiency. It provides up to
64KB of embedded Flash memory for code/data storage and 8 KB of embedded SRAM memory
for system operation and application program usage. A variety of peripherals, such as ADC, I2C,
USART, UART, SPI, MCTM, GPTM, SCTM, CRC-16/32, RTC, WDT, SCI, USB2.0 FS, SW-DP
(Serial Wire Debug Port), etc., are also implemented in the device series. Several power saving
modes provide the flexibility for maximum optimization between wakeup latency and power
consumption, an especially important consideration in low power applications.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
2
Features
Core
■■ 32-bit ARM® Cortex™-M0+ processor core
■■ Up to 40MHz operating frequency for HT32F52231/52241 or 48MHz for HT32F52331/52341
Features
■■ 0.93 DMIPS/MHz (Dhrystone v2.1)
■■ Single-cycle multiplication
■■ Integrated Nested Vectored Interrupt Controller (NVIC)
■■ 24-bit SysTick timer
The Cortex-M0+ processor is a very low gate count, highly energy efficient processor that is
intended for microcontroller and deeply embedded applications that require an area optimized,
low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb®
instruction sets; single-cycle I/O port; hardware multiplier and low latency interrupt respond time.
On-chip Memory
■■ Up to 64 KB on-chip Flash memory for instruction/data and options storage
■■ 8 KB on-chip SRAM
■■ Supports multiple boot modes
The ARM® Cortex™-M0+ processor accesses and debug accesses share the single external
interface to external AHB peripheral. The processor accesses take priority over debug accesses.
The maximum address range of the Cortex™-M0+ is 4 GB since it has a 32-bit bus address
width. Additionally, a pre-defined memory map is provided by the Cortex™-M0+ processor to
reduce the software complexity of repeated implementation by different device vendors. However,
some regions are used by the ARM® Cortex™-M0+ system peripherals. Refer to the ARM®
Cortex™-M0+ Technical Reference Manual for more information. Figure 2 shows the memory
map of the HT32F52231/52241 and HT32F52331/52341 series of devices, including code, SRAM,
peripheral, and other pre-defined regions.
Flash Memory Controller – FMC
■■ Flash accelerator for maximum efficiency
■■ 32-bit word programming with In System Programming Interface (ISP) and In Application
Programming (IAP)
■■ Flash protection capability to prevent illegal access
The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer
for the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower
than the CPU, a wide access interface with a pre-fetch buffer and cache are provided for the Flash
Memory in order to reduce the CPU waiting time which will cause CPU instruction execution
delays. Flash Memory word program/page erase functions are also provided.
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April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Reset Control Unit – RSTCU
■■ Supply supervisor:
●● Power On Reset / Power Down Reset – POR/PDR
●● Brown-out Detector – BOD
●● Programmable Low Voltage Detector – LVD
Clock Control Unit – CKCU
■■ External 4 to 16MHz crystal oscillator
■■ External 32,768 Hz crystal oscillator
■■ Internal 8MHz RC oscillator trimmed to ±2 % accuracy at 3.3V operating voltage and 25°C operating
temperature
■■ Internal 32 kHz RC oscillator
■■ Integrated system clock PLL
■■ Independent clock divider and gating bits for peripheral clock sources
The Clock Control unit, CKCU, provides a range of oscillator and clock functions. These include
a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a Low
Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), a Phase Lock
Loop (PLL), a HSE clock monitor, clock prescalers, clock multiplexers, APB clock divider and
gating circuitry. The AHB, APB and CortexTM-M0+ clocks are derived from the system clock (CK_
SYS) which can come from the HSI, HSE or PLL. The Watchdog Timer and Real Time Clock (RTC)
use either the LSI or LSE as their clock source.
Power Management – PWRCU
■■ Single VDD power supply: 2.0V to 3.6V
■■ Integrated 1.5V LDO regulator for CPU core, peripherals and memories power supply
■■ VDD power supply for RTC.
■■ Two power domains: VDD, 1.5 V
■■ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down
Power consumption can be regarded as one of the most important issues for many embedded
system applications. Accordingly the Power Control Unit, PWRCU, in these devices provides many
types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down mode.
These operating modes reduce the power consumption and allow the application to achieve the best
trade-off between the conflicting demands of CPU operating time, speed and power consumption.
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Features
The Reset Control Unit, RSTCU, has three kinds of reset, a power on reset, a system reset and an
APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.
A system reset resets the processor core and peripheral IP components with the exception of the
SW-DP controller. The resets can be triggered by an external signal, internal events and the reset
generators.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
External Interrupt/Event Controller – EXTI
■■ Up to 16 EXTI lines with configurable trigger source and type
■■ All GPIO pins can be selected as EXTI trigger source
■■ Source trigger type includes high level, low level, negative edge, positive edge, or both edge
■■ Individual interrupt enable, wakeup enable and status bits for each EXTI line
■■ Integrated deglitch filter for short pulse blocking
The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate
a wake-up event or interrupt requests independently. Each EXTI line can also be masked
independently.
Analog to Digital Converter – ADC
■■ 12-bit SAR ADC engine
■■ Up to 1 Msps conversion rate
■■ Up to 12 external analog input channels
A 12-bit multi-channel ADC is integrated in the device. There are multiplexed channels, which
include 12 external analog signal channels and 2 internal channels which can be measured. If
the input voltage is required to remain within a specific threshold window, an Analog Watchdog
function will monitor and detect these signals. An interrupt will then be generated to inform the
device that the input voltage is not within the preset threshold levels. There are three conversion
modes to convert an analog signal to digital data. The ADC can be operated in one shot, continuous
and discontinuous conversion modes.
I/O Ports – GPIO
■■ Up to 40 GPIOs
■■ Port A, B, C are mapped as 16 external interrupts – EXTI
■■ Almost all I/O pins have a configurable output driving current.
There are up to 40 General Purpose I/O pins, GPIO, named from PA0 ~ PA15 to PC0 ~ PC7 for
the implementation of logic input/output functions. Each of the GPIO ports has a series of related
control and configuration registers to maximize flexibility and to meet the requirements of a wide
range of applications.
The GPIO ports are pin-shared with other alternative functions to obtain maximum functional
flexibility on the package pins. The GPIO pins can be used as alternative functional pins by
configuring the corresponding registers regardless of the input or output pins. The external
interrupts on the GPIO pins of the device have related control and configuration registers in the
External Interrupt Control Unit, EXTI.
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Features
■■ Software interrupt trigger mode for each EXTI line
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Motor Control Timer – MCTM
■■ One 16-bit up, down, up/down auto-reload counter
■■ 16-bit programmable prescaler allowing counter clock frequency division by any factor between
1 and 65536
■■ Input Capture function
■■ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes
■■ Single Pulse Mode Output
■■ Complementary Outputs with programmable dead-time insertion
■■ Supports 3-phase motor control and hall sensor interface
■■ Break input to force the timer’s output signals into a reset or fixed condition
The Motor Control Timer consists of a single 16-bit up/down counter, four 16-bit CCRs (Capture/
Compare Registers), single one 16-bit counter-reload register (CRR), single 8-bit repetition counter
and several control/status registers. It can be used for a variety of purposes including measuring
the pulse widths of input signals or generating output waveforms such as compare match outputs,
PWM outputs or complementary PWM outputs with dead-time insertion. The MCTM is capable of
offering full functional support for motor control, hall sensor interfacing and brake input.
PWM Generation and Capture Timers – GPTM
■■ One 16-bit up, down, up/down auto-reload counter
■■ 16-bit programmable prescaler allowing counter clock frequency division by any factor between
1 and 65536
■■ Input Capture function
■■ Compare Match Output
■■ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes
■■ Single Pulse Mode Output
■■ Encoder interface controller with two inputs using quadrature decoder
The General Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/Compare
Registers (CCRs), one 16-bit Counter Reload Register (CRR) and several control/status registers.
They can be used for a variety of purposes including general time measurement, input signal pulse
width measurement, output waveform generation such as single pulse generation, or PWM output
generation. The GPTM supports an Encoder Interface using a decoder with two inputs.
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Features
■■ Compare Match Output
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Single Channel Generation and Capture Timers – SCTM
■■ One 16-bit up and auto-reload counter
■■ One channel for each timer
■■ 16-bit programmable prescaler allowing counter clock frequency division by any factor between
1 and 65536
Features
■■ Input Capture function
■■ Compare Match Output
■■ PWM waveform generation with Edge-aligned
■■ Single Pulse Mode Output
The Single-Channel Timer consists of one 16-bit up-counter, one 16-bit Capture/Compare Register
(CCR), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be
used for a variety of purposes including general timer, input signal pulse width measurement or
output waveform generation such as single pulse generation or PWM output.
Basic Function Timer – BFTM
■■ One 32-bit compare/match count-up counter - no I/O control features
■■ One shot mode - counting stops after a match condition
■■ Repetitive mode - restart counter after a match condition
The Basic Function Timer is a simple count-up 32-bit counter designed to measure time intervals
and generate a one shot or repetitive interrupts. The BFTM operates in two functional modes,
repetitive or one shot mode. In the repetitive mode the BFTM restarts the counter when a compare
match event occurs. The BFTM also supports a one shot mode which forces the counter to stop
counting when a compare match event occurs.
Watchdog Timer – WDT
■■ 12-bit down counter with 3-bit prescaler
■■ Reset event for the system
■■ Programmable watchdog timer window function
■■ Register write protection function
The Watchdog Timer is a hardware timing circuit that can be used to detect system failures due
to software malfunctions. It includes a 12-bit count-down counter, a prescaler, a WDT delta value
register, WDT operation control circuitry and a WDT protection mechanism. If the software does
not reload the counter value before a Watchdog Timer underflow occurs, a reset will be generated
when the counter underflows. In addition, a reset is also generated if the software reloads the
counter when the counter value is greater than the WDT delta value. This means the counter must
be reloaded within a limited timing window using a specific method. The Watchdog Timer counter
can be stopped while the processor is in the debug mode. There is a register write protect function
which can be enabled to prevent it from changing the Watchdog Timer configuration unexpectedly.
Rev. 1.51
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April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Real Time Clock – RTC
■■ 24-bit up-counter with a programmable prescaler
■■ Alarm function
■■ Interrupt and Wake-up event
Inter-integrated Circuit – I2C
■■ Supports both master and slave modes with a frequency of up to 1MHz
■■ Provide an arbitration function and clock synchronization
■■ Supports 7-bit and 10-bit addressing modes and general call addressing
■■ Supports slave multi-addressing mode with maskable address
The I2C is an internal circuit allowing communication with an external I2C interface which is an
industry standard two line serial interface used for connection to external hardware. These two
serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I 2C module
provides three data transfer rates: (1) 100kHz in the Standard mode, (2) 400kHz in the Fast mode
and (3) 1MHz in the Fast plus mode. The SCL period generation register is used to setup different
kinds of duty cycle implementations for the SCL pulse.
The SDA line which is connected directly to the I2C bus is a bi-directional data line between the
master and slave devices and is used for data transmission and reception. The I 2C also has an
arbitration detect function and clock synchronization to prevent situations where more than one
master attempts to transmit data to the I2C bus at the same time.
Serial Peripheral Interface – SPI
■■ Supports both master and slave mode
■■ Frequency of up to (fPCLK/2)MHz for the master mode and (fPCLK/3)MHz for the slave mode
■■ FIFO Depth: 8 levels
■■ Multi-master and multi-slave operation
The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function
in both master and slave mode. The SPI interface uses 4 pins, which are the serial data input and
output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device
acts as a master device which controls the data flow using the SEL and SCK signals to indicate the
start of data communication and the data sampling rate. To receive a data byte, the streamed data
bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data
transmission is carried out in a similar way but in a reverse sequence. The mode fault detection
provides a capability for multi-master applications.
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Features
The Real Time Clock, RTC, includes an APB interface, a 24-bit count-up counter, a control
register, a prescaler, a compare register and a status register. Most of the RTC circuits are located in
the Backup Domain except for the APB interface. The APB interface is located in the V DD15 power
domain. Therefore, it is necessary to be isolated from the ISO signal that comes from the power
control unit when the V DD15 power domain is powered off, that is when the device enters the PowerDown mode. The RTC counter is used as a wakeup timer to generate a system resume signal from
the Power-Down mode.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Universal Synchronous Asynchronous Receiver Transmitter – USART
■■ Supports both asynchronous and clocked synchronous serial communication modes
■■ Asynchronous operating baud rate up to (fPCLK/16)MHz and synchronous operating rate up to
(fPCLK/8)MHz
■■ Full duplex communication
Features
■■ Fully programmable serial communication characteristics including:
●● Word length: 7, 8, or 9-bit character
●● Parity: Even, odd, or no-parity bit generation and detection
●● Stop bit: 1 or 2 stop bit generation
●● Bit order: LSB-first or MSB-first transfer
■■ Error detection: Parity, overrun, and frame error
■■ Auto hardware flow control mode – RTS, CTS
■■ IrDA SIR encoder and decoder
■■ RS485 mode with output enable control
■■ FIFO Depth: 8×9 bits for both receiver and transmitter
The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full
duplex data exchange using synchronous or asynchronous data transfer. The USART is used to
translate data between parallel and serial interfaces, and is commonly used for RS232 standard
communication. The USART peripheral function supports four types of interrupt including Line
Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt
and Time Out Interrupt. The USART module includes a transmitter FIFO, (TX_FIFO) and receiver
FIFO (RX_FIFO). The software can detect a USART error status by reading the Line Status
Register, LSR. The status includes the type and the condition of transfer operations as well as
several error conditions resulting from Parity, Overrun, Framing and Break events.
Universal Asynchronous Receiver Transmitter – UART
■■ Asynchronous serial communication operating baud-rate up to fPCLK/16MHz
■■ Full duplex communication
■■ Fully programmable serial communication characteristics including:
●● Word length: 7, 8, or 9-bit character
●● Parity: Even, odd, or no-parity bit generation and detection
●● Stop bit: 1 or 2 stop bit generation
●● Bit order: LSB-first or MSB-first transfer
■■ Error detection: Parity, overrun, and frame error
The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data
exchange using asynchronous transfer. The UART is used to translate data between parallel and
serial interfaces, and is commonly used for RS232 standard communication. The UART peripheral
function supports Line Status Interrupt. The software can detect a UART error status by reading
the Line Status Register, LSR. The status includes the type and the condition of transfer operations
as well as several error conditions resulting from Parity, Overrun, Framing and Break events.
Rev. 1.51
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April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Smart Card Interface – SCI (HT32F52331/52341 only)
■■ Supports ISO 7816-3 standard
■■ Character mode
■■ Single transmit buffer and single receive buffer
■■ 11-bit ETU (elementary time unit) counter
Features
■■ 9-bit guard time counter
■■ 24-bit general purpose waiting time counter
■■ Parity generation and checking
■■ Automatic character retry on parity error detection in transmission and reception modes
The Smart Card Interface is compatible with the ISO 7816-3 standard. This interface includes
Card Insertion/Removal detection, SCI data transfer control logic and data buffers, internal
Timer Counters and corresponding control logic circuits to perform all the necessary Smart Card
operations. The Smart Card interface acts as a Smart Card Reader to facilitate communication
with the external Smart Card. The overall functions of the Smart Card interface are controlled
by a series of registers including control and status registers together with several corresponding
interrupts which are generated to get the attention of the microcontroller for SCI transfer status.
Cyclic Redundancy Check – CRC
■■ Support CRC16 polynomial: 0x8005,
X16+X15+X2+1
■■ Support CCITT CRC16 polynomial: 0x1021,
X16+X12+X5+1
■■ Support IEEE-802.3 CRC32 polynomial: 0x04C11DB7,
X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1
■■ Supports 1’s complement, byte reverse & bit reverse operation on data and checksum
■■ Supports byte, half-word & word data size
■■ Programmable CRC initial seed value
■■ CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit
data
■■ Supports PDMA to complete a CRC computation of a block of memory
The CRC calculation unit is an error detection technique test algorithm which is used to verify data
transmission or storage data correctness. A CRC calculation takes a data stream or a block of data
as its input and generates a 16- or 32-bit output remainder. Ordinarily, a data stream is suffixed by
a CRC code and used as a checksum when being sent or stored. Therefore, the received or restored
data stream is calculated by the same generator polynomial as described above. If the new CRC
code result does not match the one calculated earlier, then this means that the data stream contains
a data error.
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32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Universal Serial Bus Device Controller – USB (HT32F52331/52341 only)
■■ Complies with USB 2.0 full-speed (12 Mbps) specification
■■ On-chip USB full-speed transceiver
■■ 1 control endpoint (EP0) for control transfer
■■ 3 single-buffered endpoints for bulk and interrupt transfer
■■ 1,024 bytes EP-SRAM used as the endpoint data buffers
The USB device controller is compliant with the USB 2.0 full-speed specification. There is one
control endpoint known as Endpoint 0 and seven configurable endpoints. A 1024-byte SRAM
is used as the endpoint buffer. Each endpoint buffer size is programmable using corresponding
registers, which provides maximum flexibility for various applications. The integrated USB fullspeed transceiver helps to minimize the overall system complexity and cost. The USB functional
block also contains the resume and suspend feature to meet the requirements of low-power
consumption.
Debug Support
■■ Serial Wire Debug Port – SW-DP
■■ 4 comparators for hardware breakpoint or code / literal patch
■■ 2 comparators for hardware watchpoints
Package and Operation Temperature
■■ 24/28-pin SSOP, 33-pin QFN, 48-pin LQFP for HT32F52231/52241
■■ 33-pin QFN, 48-pin LQFP package for HT32F52331/52341
■■ Operation temperature range: -40°C to +85°C
Rev. 1.51
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April 11, 2017
Features
■■ 4 double-buffered endpoints for bulk, interrupt and isochronous transfer
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
3
Overview
Device Information
Table 1. Features and Peripheral List
HT32F52231
32
HT32F52241
63
HT32F52341
63
Option Bytes Flash (KB)
1
1
1
1
SRAM (KB)
4
8
4
8
Timers
MCTM
1
GPTM
1
SCTM
4
BFTM
2
RTC
1
WDT
1
Communication
USB
—
1
SPI
2
USART
1
UART
2
I2C
2
SCI (ISO7816-3)
—
1
CRC-16/32
1
EXTI
16
1
12-bit ADC
Number of channels
GPIO
CPU frequency
12 Channels
Up to 40
Up to 38
Up to 40MHz
Up to 48MHz
Operating voltage
2.0 V ~ 3.6 V
-40° C ~ +85° C
Operating temperature
Package
Rev. 1.51
HT32F52331
32
24/28-pin SSOP
33-pin QFN, 48-pin LQFP
16 of 50
33-pin QFN, 48-pin LQFP
April 11, 2017
Overview
Peripherals
Main Flash (KB)
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Block Diagram
PA ~ PB[15:0]; PC[7:0]
SWCLK SWDIO
BOOT
AF
AF
Powered by VDD15
SRAM
Controller
XTALIN
XTALOUT
HSI
CKCU/RSTCU
Control Registers
8 MHz
USB
Control/Data
Registers
SRAM
CLDO
LDO
Clock and reset control
Bus Matrix
AHB
Peripherals
CRC
-16/32
HSE
4 ~ 16 MHz
CAP.
1.5 V
BOD
LVD
Interrupt request
Powered by VDD
AHB to APB
Bridge
USB
Device
PLL
HT32F52331/41 only
AF
AF
UART0
UART0~ 1
SPI1
SPI1~~00
SDA
SCL
I2C0 ~ 1
EXTI
GPTM
AF
AF
MCTM
BFTM0 ~ 1
AF
SCI
APB
SCTM0 ~ 3
AF
RTC
AF
CLK, DIO
DET
AF
WDT
AFIO
CH0 ~CH2
CH0N ~ CH2N
CH3, BRK
MOSI, MISO
SCK, SEL
Power control
USART
AF
TX, RX
AF
TX, RX
RTS/TXE
CTS/SCK
DP
DM
CH3 ~ CH0
SCTM0 ~
SCTM3
HT32F52331/41 only
AF
ADC_IN0
...
ADC_IN11
12-bit
SAR ADC
ADC
VDD
VSS
PWRCU
32 kHz
Powered by VDDA
LSE
AF
LSI
VDDA
VSSA
RTCOUT
WAKEUP
32,768 Hz
nRST
Powered by VDD15
Powered by VDD
AF
X32KIN
X32KOUT
Power supply:
Bus:
Control signal:
Alternate function:
AF
Figure 1. Block Diagram
Rev. 1.51
17 of 50
April 11, 2017
Overview
Flash
Memory
FMC
Control Registers
System
NVIC
IO Port
CortexTM-M0+
Processor
GPIO
VSS
AF
Flash Memory
Interface
SW-DP
VDD
POR
/PDR
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Memory Map
0xFFFF_FFFF
0x400F_FFFF
0xE010_0000
0xE000_0000
Private peripheral bus
Reserved
0x4010_0000
Peripheral
0x4008_0000
0x4000_0000
AHB peripherals
512 KB
APB peripherals
512 KB
Reserved
SRAM
0x2000_2000
Up to
8 KB on-chip SRAM
8 KB
0x2000_0000
0x1FF0_0400
0x1FF0_0000
0x1F00_0800
Code
0x1F00_0000
0x0001_0000
Reserved
Option byte alias
1 KB
Reserved
Boot loader
2 KB
Reserved
Up to
64 KB on-chip Flash
Up to
64 KB
0x4007_8000
0x4007_7000
0x4007_6000
0x4007_5000
0x4007_4000
0x4006_F000
0x4006_E000
0x4006_B000
0x4006_A000
0x4006_9000
0x4006_8000
0x4004_A000
0x4004_9000
0x4004_8000
0x4004_5000
0x4004_4000
0x4004_3000
0x4004_2000
0x4004_1000
0x4003_6000
0x4003_5000
0x4003_4000
0x4002_D000
0x4002_C000
0x4002_5000
0x4002_4000
0x4002_3000
0x4002_2000
0x4001_1000
0x4001_0000
0x4000_5000
0x4000_4000
0x4000_2000
0x4000_1000
0x4000_0000
Reserved
GPIO A ～ C
Reserved
USB SRAM Note
USB Note
Reserved
CRC
CKCU/RSTCU
Reserved
FMC
Reserved
BFTM1
BFTM0
SCTM3
SCTM1
Reserved
GPTM
Reserved
RTC & PWRCU
Reserved
WDT
Reserved
I2C1
I2C0
Reserved
SPI1
SCI Note
Reserved
UART1
Reserved
SCTM2
SCTM0
Reserved
MCTM
Reserved
EXTI
Reserved
AFIO
Reserved
ADC
Reserved
SPI0
Reserved
UART0
USART
AHB
APB
Note: HT32F52331/HT32F52341 only
0x0000_0000
Figure 2. Memory Map
Rev. 1.51
18 of 50
April 11, 2017
Overview
0x400B_6000
0x400B_0000
0x400A_C000
0x400A_A000
0x400A_8000
0x4008_C000
0x4008_A000
0x4008_8000
0x4008_2000
0x4008_0000
Reserved
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Table 2. Register Map
End Address
0x4000_0FFF
Peripheral
USART0
0x4000_1000
0x4000_1FFF
UART0
0x4000_2000
0x4000_3FFF
Reserved
0x4000_4000
0x4000_4FFF
SPI0
0x4000_5000
0x4001_9FFF
Reserved
0x4001_0000
0x4001_0FFF
ADC
0x4001_1000
0x4002_1FFF
Reserved
0x4002_2000
0x4002_2FFF
AFIO
0x4002_3000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
EXTI
0x4002_5000
0x4002_BFFF
Reserved
0x4002_C000
0x4002_CFFF
MCTM
0x4002_D000
0x4003_3FFF
Reserved
0x4003_4000
0x4003_4FFF
SCTM0
0x4003_5000
0x4003_5FFF
SCTM2
0x4003_6000
0x4004_0FFF
Reserved
0x4004_1000
0x4004_1FFF
UART1
0x4004_2000
0x4004_2FFF
Reserved
0x4004_3000
0x4004_3FFF
SCI Note
0x4004_4000
0x4004_4FFF
SPI1
0x4004_5000
0x4004_7FFF
Reserved
0x4004_8000
0x4004_8FFF
I2C0
0x4004_9000
0x4004_9FFF
I2C1
0x4004_A000
0x4006_7FFF
Reserved
0x4006_8000
0x4006_8FFF
WDT
0x4006_9000
0x4006_9FFF
Reserved
0x4006_A000
0x4006_AFFF
RTC/PWRCU
0x4006_B000
0x4006_DFFF
Reserved
0x4006_E000
0x4006_EFFF
GPTM
0x4006_F000
0x4007_3FFF
Reserved
0x4007_4000
0x4007_4FFF
SCTM1
0x4007_5000
0x4007_5FFF
SCTM3
0x4007_6000
0x4007_6FFF
BFTM0
0x4007_7000
0x4007_7FFF
BFTM1
0x4007_8000
0x4007_FFFF
Reserved
19 of 50
Bus
Overview
Rev. 1.51
Start Address
0x4000_0000
APB
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Start Address
End Address
Peripheral
0x4008_0000
0x4008_1FFF
FMC
0x4008_2000
0x4008_7FFF
Reserved
0x4008_8000
0x4008_9FFF
CKCU/RSTCU
0x4008_BFFF
CRC
0x400A_7FFF
Reserved
0x400A_8000
0x400A_BFFF
USB Note
0x400A_C000
0x400A_FFFF
Reserved
0x400B_0000
0x400B_1FFF
GPIOA
0x400B_2000
0x400B_3FFF
GPIOB
0x400B_4000
0x400B_5FFF
GPIOC
0x400B_6000
0x400F_FFFF
Reserved
AHB
Overview
0x4008_A000
0x4008_C000
Bus
Note: HT32F52331/HT32F52341 only.
Rev. 1.51
20 of 50
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Clock Structure
Prescaler
1 ~ 32
CK_LSE
HSI Auto
Trimming
Controller
Divider
2
CK_REF
CKREFPRE
CKREFEN
USB REF Pulse
fCK_USB = 48 MHz
CK_USB
PLLEN
1
HSIEN
STCLK
(to SysTick)
8
CK_PLL
SW[2:0]
4-16 MHz
HSE XTAL
fCK_SYS,max = 40 MHz for
HT32F52231/52241
fCK_SYS,max = 48 MHz for
HT32F52331/52241
00x
CK_HSI
HSEEN
HT32F52331/52341 only
f CK_PLL,max = 48 MHz
PLL
0
Overview
USBEN
PLLSRC
8 MHz
HSI RC
CK_GPIO
( to GPIO port)
GPIOAEN
GPIODEN
011
CK_HSE
010
CK_SYS AHB Prescaler
1,2,4,8,16,32
FCLK
( free running clock)
111
110
CK_AHB
Clock
Monitor
HCLKC
( to CortexTM-M0+)
CM0PEN
(control by HW)
CK_CRC
( to CRC)
CRCEN
CK_LSE
32.768 kHz
LSE OSC
LSEEN(Note1)
32 kHz
LSI RC
WDTSRC
1
0
CK_LSI
CK_WDT
HCLKF
( to Flash)
CM0PEN
FMCEN
WDTEN
RTCSRC(Note1)
HCLKS
( to SRAM)
LSIEN(Note1)
1
0
CK_RTC
CM0PEN
SRAMEN
RTCEN(Note1)
HCLKBM
( to Bus Matrix)
CM0PEN
CKOUTSRC[2:0]
BMEN
CKOUT
000
CK_REF
001
010
CK_AHB/16
CK_SYS/16
011
CK_HSE/16
100
CK_HSI/16
101
CK_LSE
110
CK_LSI
Legend:
HSE = High Speed External clock
HSI = High Speed Internal clock
LSE = Low Speed External clock
LSI = Low Speed Internal clock
HCLKAPB
( to APB Bridge)
CM0PEN
APBEN
Peripherals
Clock
Prescaler
1,2,4,8
PCLK
00
PCLK/2
01
PCLK/4
10
PCLK/8
11
PCLK (AFIO, ADC,
SPIx, USART, UARTx,
I2Cx, MCTM, GPTM,
SCTMx, BFTMx, EXTI,
SCI, WDT, RTC)
SPIEN
SCIEN
ADC
Prescaler
1,2,3,4,8,...
CK_ADC IP
ADCEN
Figure 3. Clock Structure
Rev. 1.51
21 of 50
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
4
Pin Assignment
HT32F52231/HT32F52241
24 SSOP-A
AF1
Pin Assignment
AF0
(Default)
AF0
(Default)
33V
24
PB4
33V
23
PB3
33V
22
PB2
33V
21
PB1
33V
20
PB0
33V
19
SWDIO
PA13
33V
18
SWCLK
PA12
33V
17
PA9_BOOT
33V
33V
16
XTALOUT
PB14
10
P15
33V
15
XTALIN
PB13
VDD
11
P33
33V
14
RTCOUT
PB12
VSS
12
P33
33V
13
nRST
PB7
1
33V
PB8
2
33V
VDDA
3
AP
PA0
4
33V
PA1
5
33V
PA2
6
33V
PA3
7
33V
PA4
8
33V
PA5
9
CLDO
P33 3.3 V Digital Power Pad
AP
3.3 V Analog Power Pad
P15 1.5 V Power Pad
33V 3.3 V Digital & Analog IO Pad
33V 3.3 V Digital I/O Pad
Figure 4. HT32F52231/52241 24-pin SSOP Pin Assignment
Rev. 1.51
22 of 50
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
HT32F52231/HT32F52241
28 SSOP-A
AF0
(Default)
AF0
(Default)
AF1
28
PB4
33V
27
PB3
33V
26
PB2
33V
25
PB1
33V
24
PB0
33V
23
PA15
33V
22
PA14
33V
21
SWDIO
PA13
33V
33V
20
SWCLK
PA12
10
33V
33V
19
PA9_BOOT
PA7
11
33V
33V
18
XTALOUT
PB14
CLDO
12
P15
33V
17
XTALIN
PB13
VDD
13
P33
33V
16
RTCOUT
PB12
VSS
14
P33
33V
15
nRST
1
33V
PB8
2
33V
VDDA
3
AP
PA0
4
33V
PA1
5
33V
PA2
6
33V
PA3
7
33V
PA4
8
33V
PA5
9
PA6
P33 3.3 V Digital Power Pad
AP
3.3 V Analog Power Pad
P15 1.5 V Power Pad
33V 3.3 V Digital & Analog IO Pad
33V 3.3 V Digital I/O Pad
Pin Assignment
33V
PB7
Figure 5. HT32F52231/52241 28-pin SSOP Pin Assignment
Rev. 1.51
23 of 50
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
HT32F52231/HT32F52241
33 QFN-A
31
30
29
28
27
26
25
AP
AP
33V
AF1
33V 33V 33V 33V 33V 33V
P33 3.3 V Digital Power Pad
AP
AF0
(Default)
Pin Assignment
32
AF0
(Default)
3
PB2
PA2
PB3
33V
PB4
2
PB5
PA1
PB7
33V
PB8
1
VDDA
PA0
VSSA
AF0
(Default)
3.3 V Analog Power Pad
P15 1.5 V Power Pad
33V
24
PB1
33V
23
PB0
33V
22
PA15
33V
21
PA14
PA3
4
33V
PA4
5
33V
33V 3.3 V Digital & Analog IO Pad
33V
20
SWDIO
PA13
PA5
6
33V
33V 3.3 V Digital I/O Pad
33V
19
SWCLK
PA12
33V
18
PA9_
BOOT
33V
17
XTALOUT
PA6
7
33V
PA7
8
33V
VDD VDD Domain Pad
33 VSS
P15 P33 P33
PB14
VDD VDD VDD VDD
33V
33V 33V 33V 33V
9
10
11
12
13
14
15
16
CLDO
VDD
VSS
nRST
X32KIN
X32KOUT
RTCOUT
XTALIN
AF0
(Default)
PB10
PB11
PB12
PB13
AF1
Figure 6. HT32F52231/52241 33-pin QFN Pin Assignment
Rev. 1.51
24 of 50
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
HT32F52231/HT32F52241
48 LQFP-A
5
33V
PA5
6
33V
PA6
7
33V
PA7
8
33V
PC4
9
33V
PC5
10
33V
PC6
11
33V
PC7
12
33V
47
46
45
44
43
42
41
40
39
38
37
AP
AP
33V
33V
33V
33V
33V
33V
33V
33V
33V
33V
P33
3.3 V Digital Power Pad
AP
3.3 V Analog Power Pad
P15
1.5 V Power Pad
33V
3.3 V Digital & Analog IO Pad
33V
3.3 V Digital I/O Pad
VDD
VDD Domain Pad
24
PB15
PC0
18
19
P33
36
VSS_2
P33
35
VDD_2
33V
34
PB1
33V
33
PB0
33V
32
PA15
33V
31
PA14
33V
30
SWDIO
PA13
33V
29
SWCLK
PA12
33V
28
PA11
33V
27
PA10
33V
26
PA9_
BOOT
33V
25
PA8
AF1
23
PB14
17
AF1
AF0
(Default)
22
XTALOUT
16
PB10
21
PB13
15
X32KIN
20
XTALIN
14
PB9
33V
PB12
13
nRST
33V
RTCOUT
P33
VSS_1
33V
PB11
P33
VDD_1
33V
X32KOUT
P15
CLDO
VDD VDD VDD VDD VDD
33V 33V 33V 33V 33V
AF0
(Default)
Figure 7. HT32F52231/52241 48-pin LQFP Pin Assignment
Rev. 1.51
25 of 50
April 11, 2017
Pin Assignment
PA4
48
AF0
(Default)
33V
PB2
4
PB3
PA3
PB4
33V
PB5
3
PC1
PA2
PC2
33V
PC3
2
PB6
PA1
PB7
33V
PB8
1
VDDA
PA0
VSSA
AF0
(Default)
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
HT32F52331/HT32F52341
33 QFN-A
PA3
4
33V
PA4
5
33V
PA5
6
33V
USBDM
7
USB
USBDP
8
USB
31
30
29
28
27
26
25
AP
AP
AF1
33V 33V 33V 33V 33V 33V
P33 3.3 V Digital Power Pad
AP
AF0
(Default)
Pin Assignment
33V
32
AF0
(Default)
3
PB2
PA2
PB3
33V
PB4
2
PB5
PA1
PB7
33V
PB8
1
VDDA
PA0
VSSA
AF0
(Default)
3.3 V Analog Power Pad
P15 1.5 V Power Pad
33V 3.3 V Digital & Analog IO Pad
33V 3.3 V Digital I/O Pad
VDD VDD Domain Pad
USB USB PHY Pad
P15 P33 P33
33 VSS
33V
24
PB1
33V
23
PB0
33V
22
PA15
33V
21
PA14
33V
20
SWDIO
PA13
33V
19
SWCLK
PA12
33V
18
PA9_
BOOT
33V
17
XTALOUT
PB14
VDD VDD VDD VDD
33V
33V 33V 33V 33V
9
10
11
12
13
14
15
16
CLDO
VDD
VSS
nRST
X32KIN
X32KOUT
RTCOUT
XTALIN
AF0
(Default)
PB10
PB11
PB12
PB13
AF1
Figure 8. HT32F52331/52341 33-pin QFN Pin Assignment
Rev. 1.51
26 of 50
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
HT32F52331/HT32F52341
48 LQFP-A
5
33V
PA5
6
33V
PA6
7
33V
PA7
8
33V
PC4
9
33V
PC5
10
33V
USBDM
11
USB
USBDP
12
USB
47
46
45
44
43
42
41
40
39
38
37
AP
AP
33V
33V
33V
33V
33V
33V
33V
33V
33V
33V
P33
3.3 V Digital Power Pad
AP
3.3 V Analog Power Pad
P15
1.5 V Power Pad
33V
3.3 V Digital & Analog IO Pad
33V
3.3 V Digital I/O Pad
USB
USB PHY Pad
VDD
VDD Domain Pad
24
PB15
PC0
19
P33
36
VSS_2
P33
35
VDD_2
33V
34
PB1
33V
33
PB0
33V
32
PA15
33V
31
PA14
33V
30
SWDIO
PA13
33V
29
SWCLK
PA12
33V
28
PA11
33V
27
PA10
33V
26
PA9_
BOOT
33V
25
PA8
AF1
23
PB14
18
AF1
AF0
(Default)
22
XTALOUT
17
PB10
21
PB13
16
X32KIN
20
XTALIN
15
PB9
33V
PB12
14
nRST
33V
RTCOUT
13
VSS_1
33V
PB11
P33
VDD_1
33V
X32KOUT
P33
CLDO
VDD VDD VDD VDD VDD
33V 33V 33V 33V 33V
P15
AF0
(Default)
Figure 9. HT32F52331/52341 48-pin LQFP Pin Assignment
Rev. 1.51
27 of 50
April 11, 2017
Pin Assignment
PA4
48
AF0
(Default)
33V
PB2
4
PB3
PA3
PB4
33V
PB5
3
PC1
PA2
PC2
33V
PC3
2
PB6
PA1
PB7
33V
PB8
1
VDDA
PA0
VSSA
AF0
(Default)
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Table 3. HT32F52231/52241 Series Pin Assignment for 24/28SSOP, 33QFN, 48LQFP Package
HT32F52231/52241 Alternate Function Mapping
Package
AF0
48
LQFP
33
QFN
28
SSOP
24
SSOP
System
Default
1
1
4
4
PA0
AF1
GPIO
AF2
ADC
ADC_IN2
AF3
AF4
AF5
AF6
AF7
N/A
GPTM
/MCTM
SPI
USART
/UART
IC
GT_CH0
SPI1_SCK
USR_RTS
I2C1_SCL
I2C1_SDA
2
2
5
5
PA1
ADC_IN3
GT_CH1
SPI1_MOSI
USR_CTS
3
6
6
PA2
ADC_IN4
GT_CH2
SPI1_MISO
USR_TX
4
4
7
7
PA3
ADC_IN5
GT_CH3
SPI1_SEL
USR_RX
5
5
8
8
PA4
ADC_IN6
GT_CH0
SPI0_SCK
UR1_TX
I2C0_SCL
6
6
9
9
PA5
ADC_IN7
GT_CH1
SPI0_MOSI
UR1_RX
I2C0_SDA
7
7
10
PA6
ADC_IN8
GT_CH2
SPI0_MISO
8
8
11
PA7
ADC_IN9
GT_CH3
SPI0_SEL
9
PC4
ADC_IN10
USR_TX
10
PC5
ADC_IN11
USR_RX
11
PC6
MT_CH2
UR0_TX
I2C0_SCL
PC7
MT_CH2N
UR0_RX
I2C0_SDA
12
13
9
12
10
CLDO
14
10
15
11
13
11
VDD_1
14
12
16
12
VSS_1
15
13
nRST
17
PB9
N/A
AF9
N/A
AF10 AF11
N/A
N/A
AF12
N/A
AF13
SCTM
MT_CH3
X32KIN
PB10
GT_CH0
SPI1_SEL
USR_TX
SCTM2
19
14
X32KOUT
PB11
GT_CH1
SPI1_SCK
USR_RX
SCTM3
20
15
16
14
RTCOUT
PB12
SPI0_MISO
UR0_RX
21
16
17
15
XTALIN
PB13
22
17
18
16
XTALOUT
PB14
SCTM0
UR0_TX
I2C0_SCL
UR0_RX
I2C0_SDA
23
PB15
MT_CH0
SPI0_SEL
I2C1_SCL
24
PC0
MT_CH0N
SPI0_SCK
I2C1_SDA
25
PA8
19
17
27
29
USR_TX
PA9_
BOOT
PA11
19
20
18
SWCLK
PA12
19
SWDIO
PA13
MT_CH1
SPI0_MOSI
MT_CH1N
SPI0_MISO
SCTM3
SCTM3
CKOUT
USR_RX
SCTM0
30
20
21
31
21
22
PA14
MT_CH0
SPI1_SEL
USR_RTS
I2C1_SCL
32
22
23
PA15
MT_CH0N
SPI1_SCK
USR_CTS
I2C1_SDA
33
23
24
20
PB0
MT_CH1
SPI1_MOSI
USR_TX
I2C0_SCL
34
24
25
21
PB1
MT_CH1N
SPI1_MISO
USR_RX
I2C0_SDA
35
WAKEUP
SCTM2
SPI0_MOSI
PA10
28
N/A
SCTM1
13
18
AF15
System
Other
SCTM0
18
26
AF14
Pin Assignment
2
3
AF8
SCTM1
SCTM2
VDD_2
36
33
37
25
26
22
VSS_2
PB2
MT_CH2
SPI0_SEL
UR1_TX
38
26
27
23
PB3
MT_CH2N
SPI0_SCK
UR1_RX
SCTM1
39
27
28
24
PB4
MT_BRK
SPI0_MOSI
UR1_TX
SCTM0
40
28
PB5
GT_CH2
SPI0_MISO
UR1_RX
41
PC1
MT_CH0
SPI1_SEL
UR1_TX
42
PC2
MT_CH0N
SPI1_SCK
43
PC3
MT_BRK
SPI1_MOSI
UR1_RX
44
PB6
GT_CH3
SPI1_MISO
UR0_TX
45
29
1
1
PB7
ADC_IN0
MT_CH1
SPI0_MISO
UR0_TX
I2C1_SCL
46
30
2
2
PB8
ADC_IN1
MT_CH1N
SPI0_SEL
UR0_RX
I2C1_SDA
47
31
3
3
VDDA
48
32
VSSA
Note: The pin number 33 of the 33-pin QFN package is located at the bottom metal of the QFN package.
Rev. 1.51
28 of 50
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Table 4. HT32F52331/52341 Series Pin Assignment for 33QFN, 48LQFP Package
Package
HT32F52331/52341 Alternate Function Mapping
AF0
AF1
AF2
AF3
AF4
AF5
AF6
N/A
GPTM
/MCTM
AF7
AF8
33
QFN
System
Default
SPI
USART
/UART
I2C
SCI
1
1
PA0
ADC_IN2
GT_CH0
SPI1_SCK
USR_RTS
I2C1_SCL
SCI_CLK
2
2
PA1
ADC_IN3
GT_CH1
SPI1_MOSI
USR_CTS
I2C1_SDA
SCI_DIO
3
3
PA2
ADC_IN4
GT_CH2
SPI1_MISO
USR_TX
4
4
PA3
ADC_IN5
GT_CH3
SPI1_SEL
USR_RX
5
5
PA4
ADC_IN6
GT_CH0
SPI0_SCK
UR1_TX
I2C0_SCL
SCI_CLK
6
6
PA5
ADC_IN7
GT_CH1
SPI0_MOSI
UR1_RX
I2C0_SDA
PA6
ADC_IN8
GT_CH2
SPI0_MISO
GT_CH3
SPI0_SEL
7
GPIO
ADC
AF9
N/A
AF10
N/A
AF11
N/A
AF12
N/A
AF13
SCTM
PA7
ADC_IN9
PC4
ADC_IN10
USR_TX
SCTM0
10
PC5
ADC_IN11
USR_RX
SCTM1
11
7
USBDM
12
8
USBDP
13
9
CLDO
14
10
VDD_1
15
11
VSS_1
16
12
nRST
18
13
X32KIN
PB10
GT_CH0
SPI1_SEL
USR_TX
SCTM2
19
14
X32KOUT
PB11
GT_CH1
SPI1_SCK
USR_RX
SCTM3
20
15
RTCOUT
PB12
SPI0_MISO
UR0_RX
21
16
XTALIN
PB13
22
17
XTALOUT
PB14
MT_CH3
SCTM0
UR0_TX
I2C0_SCL
UR0_RX
I2C0_SDA
23
PB15
MT_CH0
SPI0_SEL
I2C1_SCL
24
PC0
MT_CH0N
SPI0_SCK
I2C1_SDA
25
PA8
26
18
27
USR_TX
PA9_BOOT
SPI0_MOSI
PA10
28
PA11
MT_CH1
SPI0_MOSI
MT_CH1N
SPI0_MISO
USR_RX
WAKEUP
SCTM3
SCI_CLK
SCTM2
SCI_DIO
SCTM3
CKOUT
SCI_DET
SCI_DET
29
19
SWCLK
PA12
30
20
SWDIO
PA13
31
21
PA14
MT_CH0
SPI1_SEL
USR_RTS
I2C1_SCL
SCI_CLK
32
22
PA15
MT_CH0N
SPI1_SCK
USR_CTS
I2C1_SDA
SCI_DIO
33
23
PB0
MT_CH1
SPI1_MOSI
USR_TX
I2C0_SCL
34
24
PB1
MT_CH1N
SPI1_MISO
USR_RX
I2C0_SDA
35
N/A
SCI_DIO
8
PB9
AF15
System
Other
SCI_DET
9
17
AF14
Pin Assignment
48
LQFP
SCTM0
SCTM1
SCTM2
VDD_2
36
33
37
25
VSS_2
PB2
MT_CH2
SPI0_SEL
UR1_TX
38
26
PB3
MT_CH2N
SPI0_SCK
UR1_RX
SCTM1
39
27
PB4
MT_BRK
SPI0_MOSI
UR1_TX
SCTM0
40
28
PB5
GT_CH2
SPI0_MISO
UR1_RX
UR1_TX
41
PC1
MT_CH0
SPI1_SEL
42
PC2
MT_CH0N
SPI1_SCK
43
PC3
MT_BRK
SPI1_MOSI
44
PB6
GT_CH3
SPI1_MISO
UR0_TX
45
29
46
47
48
UR1_RX
SCI_CLK
PB7
ADC_IN0
MT_CH1
SPI0_MISO
UR0_TX
I2C1_SCL
SCI_DET
30
PB8
ADC_IN1
MT_CH1N
SPI0_SEL
UR0_RX
I2C1_SDA
SCI_DIO
31
VDDA
32
VSSA
Note: The pin number 33 of the 33-pin QFN package is located at the bottom metal of the QFN package.
Rev. 1.51
29 of 50
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Table 5. HT32F52231/52241 Pin Description
Pin number
48LQFP
33QFN
28SSOP
24SSOP
Pin
Name
Type
(Note1)
IO
Structure
(Note2)
Description
Output
Driving
Default function (AF0)
1
1
4
4
PA0
AI/O
33V
4/8/12/16 mA
PA0
2
2
5
5
PA1
AI/O
33V
4/8/12/16 mA
PA1
3
3
6
6
PA2
AI/O
33V
4/8/12/16 mA
PA2
4
4
7
7
PA3
AI/O
33V
4/8/12/16 mA
PA3
5
8
8
PA4
AI/O
33V
4/8/12/16 mA
PA4
6
9
9
PA5
AI/O
33V
4/8/12/16 mA
PA5
PA6
7
10
PA6
AI/O
33V
4/8/12/16 mA
8
11
PA7
AI/O
33V
4/8/12/16 mA
PA7
PC4
AI/O
33V
4/8/12/16 mA
PC4
PC5
9
10
PC5
AI/O
33V
4/8/12/16 mA
11
7
PC6
AI/O
—
—
PC6
12
8
PC7
AI/O
—
—
PC7
13
9
10
CLDO
P
—
—
Core power LDO 1.5 V output
It is recommended to connect a 1 μF capacitor as close as
possible between this pin and VSS_1.
Voltage for digital I/O
12
14
10
13
11
VDD_1
P
—
—
15
11
14
12
VSS_1
P
—
—
Ground reference for digital I/O
16
12
15
13
External reset pin and external wakeup pin in the PowerDown mode
17
I
33V_PU
—
PB9 Note 3
I/O (VDD)
33V
4/8/12/16 mA
PB9
PB10 Note 3
AI/O (VDD)
33V
4/8/12/16 mA
X32KIN
X32KOUT
nRST
Note 3
18
13
19
14
PB11 Note 3
AI/O (VDD)
33V
4/8/12/16 mA
20
15
16
14
PB12 Note 3
I/O (VDD)
33V
4/8/12/16 mA
RTCOUT
21
16
17
15
PB13
AI/O
33V
4/8/12/16 mA
XTALIN
22
17
18
16
PB14
AI/O
33V
4/8/12/16 mA
XTALOUT
23
PB15
I/O
33V
4/8/12/16 mA
PB15
24
PC0
I/O
33V
4/8/12/16 mA
PC0
25
PA8
I/O
33V
4/8/12/16 mA
PA8
PA9
I/O
33V_PU
4/8/12/16 mA
PA9_BOOT
27
PA10
I/O
33V
4/8/12/16 mA
PA10
28
PA11
I/O
33V
4/8/12/16 mA
PA11
SWCLK
26
18
19
17
29
19
20
18
PA12
I/O
33V_PU
4/8/12/16 mA
30
20
21
19
PA13
I/O
33V_PU
4/8/12/16 mA
SWDIO
31
21
22
PA14
I/O
33V
4/8/12/16 mA
PA14
32
22
23
33
23
24
20
34
24
25
21
35
36
33
37
25
26
22
PA15
I/O
33V
4/8/12/16 mA
PA15
PB0
I/O
33V
4/8/12/16 mA
PB0
PB1
I/O
33V
4/8/12/16 mA
VDD_2
P
—
—
VSS_2
P
—
—
PB2
I/O
33V
4/8/12/16 mA
PB1
Voltage for digital I/O
Ground reference for digital I/O
PB2
38
26
27
23
PB3
I/O
33V
4/8/12/16 mA
PB3
39
27
28
24
PB4
I/O
33V
4/8/12/16 mA
PB4
40
28
PB5
I/O
33V
4/8/12/16 mA
PB5
41
PC1
I/O
33V
4/8/12/16 mA
PC1
42
PC2
I/O
33V
4/8/12/16 mA
PC2
43
PC3
I/O
33V
4/8/12/16 mA
PC3
44
PB6
I/O
33V
4/8/12/16 mA
PB6
PB7
AI/O
33V
4/8/12/16 mA
PB7
45
29
1
1
46
30
2
2
PB8
AI/O
33V
4/8/12/16 mA
47
31
3
3
VDDA
P
—
—
Analog voltage for ADC and Comparator
PB8
48
32
VSSA
P
—
—
Ground reference for the ADC and Comparator
Note: 1. I = input, O = output, A = Analog port, P = power supply, PU = pull-up, VDD = VDD Power
2. 33V = 3.3V tolerant.
3. These pins are located at the VDD power domain.
Rev. 1.51
30 of 50
April 11, 2017
Pin Assignment
5
6
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Table 6. HT32F52331/52341 Pin Description
Pin number
Pin Name
Type
(Note1)
IO Structure
(Note2)
Description
Output
Driving
33QFN
Default function (AF0)
1
1
PA0
AI/O
33V
4/8/12/16 mA
PA0
2
2
PA1
AI/O
33V
4/8/12/16 mA
PA1
3
3
PA2
AI/O
33V
4/8/12/16 mA
PA2
4
4
PA3
AI/O
33V
4/8/12/16 mA
PA3
5
5
PA4
AI/O
33V
4/8/12/16 mA
PA4
6
6
PA5
AI/O
33V
4/8/12/16 mA
PA5
7
PA6
AI/O
33V
4/8/12/16 mA
PA6
8
PA7
AI/O
33V
4/8/12/16 mA
PA7
9
PC4
AI/O
33V
4/8/12/16 mA
PC4
10
PC5
AI/O
33V
4/8/12/16 mA
PC5
11
7
USBDM
AI/O
—
—
USB Differential data bus conforming to the Universal Serial Bus standard.
12
8
USBDP
AI/O
—
—
USB Differential data bus conforming to the Universal Serial Bus standard.
13
9
CLDO
P
—
—
Core power LDO 1.5 V output
It is recommended to connect a 1 μF capacitor as close as possible
between this pin and VSS_1.
14
10
VDD_1
P
—
—
Voltage for digital I/O
15
11
VSS_1
P
—
—
Ground reference for digital I/O
16
12
nRST Note 3
I
33V_PU
--
External reset pin and external wakeup pin in the Power-Down mode
PB9 Note 3
I/O (VDD)
33V
4/8/12/16 mA
PB9
18
13
PB10 Note 3
AI/O (VDD)
33V
4/8/12/16 mA
X32KIN
19
14
PB11 Note 3
AI/O (VDD)
33V
4/8/12/16 mA
X32KOUT
20
15
PB12 Note 3
I/O (VDD)
33V
4/8/12/16 mA
RTCOUT
21
16
PB13
AI/O
33V
4/8/12/16 mA
XTALIN
22
17
PB14
AI/O
33V
4/8/12/16 mA
XTALOUT
23
PB15
I/O
33V
4/8/12/16 mA
PB15
24
PC0
I/O
33V
4/8/12/16 mA
PC0
25
PA8
I/O
33V
4/8/12/16 mA
PA8
PA9
I/O
33V_PU
4/8/12/16 mA
PA9_BOOT
27
PA10
I/O
33V
4/8/12/16 mA
PA10
28
PA11
I/O
33V
4/8/12/16 mA
PA11
17
26
18
29
19
PA12
I/O
33V_PU
4/8/12/16 mA
SWCLK
30
20
PA13
I/O
33V_PU
4/8/12/16 mA
SWDIO
31
21
PA14
I/O
33V
4/8/12/16 mA
PA14
32
22
PA15
I/O
33V
4/8/12/16 mA
PA15
33
23
PB0
I/O
33V
4/8/12/16 mA
PB0
34
24
PB1
I/O
33V
4/8/12/16 mA
VDD_2
P
—
—
Voltage for digital I/O
Ground reference for digital I/O
35
PB1
36
33
VSS_2
P
—
—
37
25
PB2
I/O
33V
4/8/12/16 mA
PB2
38
26
PB3
I/O
33V
4/8/12/16 mA
PB3
39
27
PB4
I/O
33V
4/8/12/16 mA
PB4
40
28
PB5
I/O
33V
4/8/12/16 mA
PB5
41
PC1
I/O
33V
4/8/12/16 mA
PC1
42
PC2
I/O
33V
4/8/12/16 mA
PC2
43
PC3
I/O
33V
4/8/12/16 mA
PC3
44
PB6
I/O
33V
4/8/12/16 mA
PB6
PB7
45
29
PB7
AI/O
33V
4/8/12/16 mA
46
30
PB8
AI/O
33V
4/8/12/16 mA
47
31
VDDA
P
—
—
Analog voltage for ADC and Comparator
48
32
VSSA
P
—
—
Ground reference for the ADC and Comparator
PB8
Note: 1. I = input, O = output, A = Analog port, P = power supply, PU = pull-up, VDD = VDD Power
2. 33V = 3.3V tolerant.
3. These pins are located at the VDD power domain.
Rev. 1.51
31 of 50
April 11, 2017
Pin Assignment
48LQFP
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
5
Electrical Characteristics
Absolute Maximum Ratings
Table 7. Absolute Maximum Ratings
Min
Max
Unit
VDD
Symbol
External Main Supply Voltage
Parameter
VSS - 0.3
VSS + 3.6
V
VDDA
External Analog Supply Voltage
VSSA - 0.3
VSSA + 3.6
V
VIN
Input Voltage on I/O
VSS - 0.3
VSS + 0.3
V
TA
Ambient Operating Temperature Range
-40
+85
°C
TSTG
Storage Temperature Range
-55
+150
°C
TJ
Maximum Junction Temperature
—
+125
°C
PD
Total Power Dissipation
—
500
mW
VESD
Electrostatic Discharge Voltage - Human Body Mode
-4000
+4000
V
Recommended DC Operating Conditions
Table 8. Recommended DC Operating Conditions
Symbol
VDD
Parameter
I/O OPerating Voltage
VDDA
Analog Operating Voltage
TA = 25°C, unless otherwise specified.
Conditions
—
Min
2.0
Typ
3.3
Max
3.6
Unit
V
—
2.5
3.3
3.6
V
On-Chip LDO Voltage Regulator Characteristics
Table 9. LDO Characteristics
Symbol
Rev. 1.51
Parameter
VLDO
Internal Regulator Output
Voltage
ILDO
Output Current
CLDO
TA = 25°C, unless otherwise specified.
Conditions
VDD ≥ 2.0V Regulator input @
ILDO = 35mA and voltage variant = ±5%, After trimming.
Min
Typ Max Unit
1.425
1.5
1.57
V
VDD = 2.0V Regulator input @
VLDO = 1.5V
—
30
35
mA
External Filter Capacitor
The capacitor value is depenValue For Internal Core Power dent on the core power curSupply
rent consumption
—
1
—
μF
32 of 50
April 11, 2017
Electrical Characteristics
The following table shows the absolute maximum ratings of the device. These are stress ratings
only. Stresses beyond absolute maximum ratings may cause permanent damage to the device. Note
that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the
absolute maximum rating conditions for extended periods may affect device reliability.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Power Consumption
Table 10. HT32F52231/52241 Power Consumption Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
Conditions
VDD = 3.3V, HSE = 8MHz, PLL = 40MHz,
fHCLK = 40MHz, fPCLK = 48MHz,
All peripherals enabled
12
—
mA
VDD = 3.3V, HSE = 8MHz, PLL = 40MHz,
fHCLK = 40MHz, fPCLK = 40MHz,
All peripherals disabled
—
7
—
mA
VDD = 3.3V, HSE off, PLL off, LSI on,
fHCLK = 32kHz, fPCLK = 32kHz,
All peripherals enabled
—
45
—
μA
VDD = 3.3V, HSE off, PLL off, LSI on,
fHCLK = 32kHz, fPCLK = 32kHz,
All peripherals disabled
—
40
—
μA
VDD = 3.3V, HSE = 8MHz, PLL = 40MHz,
fHCLK = 0MHz, fPCLK = 40MHz,
All peripherals enabled
—
7.5
—
mA
VDD = 3.3V, HSE = 8MHz, PLL = 40MHz,
fHCLK = 0MHz, fPCLK = 40MHz,
All peripherals disabled
—
2
—
mA
Supply Current
VDD = 3.3V, All clock off (HSE/PLL/fHCLK),
(Deep-sleep1 Mode) LDO in low power mode, LSI on, RTC on
—
35
—
μA
Supply Current
VDD = 3.3V, All clock off (HSE/PLL/fHCLK),
(Deep-sleep2 Mode) LDO off DMOS on, LSI on, RTC on
—
5
—
μA
—
—
—
μA
—
1.5
—
μA
IDD
Supply Current
(Sleep Mode)
VDD = 3.3V, LDO off, DMOS off, LSE on,
LSI on, RTC on
Supply Current
(Power-down Mode) VDD = 3.3V, LDO off, DMOS off, LSE off,
LSI on, RTC off
33 of 50
April 11, 2017
Electrical Characteristics
—
Supply Current
(Run Mode)
Rev. 1.51
Min Typ Max Unit
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Table 11. HT32F52331/52341 Power Consumption Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
Conditions
VDD = 3.3V, HSE = 8MHz, PLL = 48MHz,
fHCLK = 48MHz, fPCLK = 48MHz,
All peripherals enabled
Min Typ Max Unit
16
—
mA
VDD = 3.3V, HSE = 8MHz, PLL = 48MHz,
fHCLK = 48MHz, fPCLK = 48MHz,
All peripherals disabled
—
8.5
—
mA
VDD = 3.3V, HSE off, PLL off, LSI on,
fHCLK = 32kHz, fPCLK = 32kHz,
All peripherals enabled
—
45
—
μA
VDD = 3.3V, HSE off, PLL off, LSI on,
fHCLK = 32kHz, fPCLK = 32kHz,
All peripherals disabled
—
40
—
μA
VDD = 3.3V, HSE = 8MHz, PLL = 48MHz,
fHCLK = 0MHz, fPCLK = 48MHz,
All peripherals enabled
—
10
—
mA
VDD = 3.3V, HSE = 8MHz, PLL = 48MHz,
fHCLK = 0MHz, fPCLK = 48MHz,
All peripherals disabled
—
2.5
—
mA
Supply Current
VDD = 3.3V, All clock off (HSE/PLL/fHCLK),
(Deep-Sleep1 Mode) LDO in low power mode, LSI on, RTC on
—
35
—
μA
Supply Current
VDD = 3.3V, All clock off (HSE/PLL/fHCLK),
(Deep-Sleep2 Mode) LDO off DMOS on, LSI on, RTC on
—
5
—
μA
—
—
—
μA
—
1.5
—
μA
Supply Current
(Run Mode)
IDD
Supply Current
(Sleep Mode)
VDD = 3.3V, LDO off, DMOS off, LSE on,
LSI on, RTC on
Supply Current
(Power-Down Mode) VDD = 3.3V, LDO off, DMOS off, LSE off,
LSI on, RTC off
Note: 1. HSE means high speed external oscillator. HSI means 8MHz high speed internal oscillator.
2. LSE means 32.768kHz low speed external oscillator. LSI means 32kHz low speed internal
oscillator.
3. RTC means real time clock.
4. Code = while (1) { 208 NOP } executed in Flash.
Rev. 1.51
34 of 50
April 11, 2017
Electrical Characteristics
—
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Reset and Supply Monitor Characteristics
Table 12. VDD Power Reset Characteristics
Symbol
VPOR
Parameter
Power on Reset Threshold
(Rising Voltage on VDD)
TA = 25°C, unless otherwise specified.
Conditions
Power down Reset Threshold
(Falling Voltage on VDD)
VPORHYST
POR Hysteresis
tPOR
Reset Delay Time
Typ
Max
Unit
1.66
1.79
1.90
V
1.49
1.64
1.78
V
—
150
—
0.1
TA = -40°C~ +85°C
—
VDD = 3.3V
mV
0.2
ms
Note: 1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.
3. If the LDO is turned on, the VDD POR has to be in the de-assertion condition. When the
VDD POR is in the assertion state then the LDO will be turned off.
Table 13. LVD/BOD Characteristics
Symbol
VBOD
VLVD
Parameter
TA = 25°C, unless otherwise specified.
Min
Typ
Max
Unit
2.02
2.1
2.18
V
LVDS = 000
2.17
2.25
2.33
V
LVDS = 001
2.32
2.4
2.48
V
LVDS = 010
2.47
2.55
2.63
V
Voltage of Low Voltage TA = -40°C ~ 85°C LVDS = 011
Detection
(VDD Falling edge) LVDS = 100
2.62
2.7
2.78
V
2.77
2.85
2.93
V
Voltage of Brown Out
Detection
Conditions
TA = -40°C ~ 85°C
After factory-trimmed
(VDD Falling edge)
LVDS = 101
2.92
3.0
3.08
V
LVDS = 110
3.07
3.15
3.23
V
LVDS = 111
3.22
3.3
3.38
V
VLVDHTST
LVD Hysteresis
VDD = 3.3V
—
—
100
—
mV
tsuLVD
LVD Setup time
VDD = 3.3V
—
—
—
5
μs
tatLVD
LVD Active Delay Time VDD = 3.3V
—
—
—
—
μs
IDDLVD
Operation Current NOTE3 VDD = 3.3V
—
—
5
15
μA
Note: 1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.
3. Bandgap current is not included.
4. LVDS field is in the PWRCU LVDCSR register
Rev. 1.51
35 of 50
April 11, 2017
Electrical Characteristics
VPDR
Min
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
External Clock Characteristics
Table 14. High Speed External Clock (HSE) Characteristics
TA = 25°C, unless otherwise specified.
Parameter
Operation Range
Conditions
—
fHSE
High Speed External Oscillator
Frequency (HSE)
CLHSE
Load capacitance
RFHSE
Internal Feedback Resistor between
XTALIN and XTALOUT pins
Min Typ Max Unit
2.0 — 3.6
V
—
VDD = 3.3V, RESR = 100Ω
@ 16MHz
—
VDD = 3.3V, CL = 12pF
@ 16MHz, HSEDR = 0
4
—
16
MHz
—
—
22
pF
—
1
—
MΩ
—
—
160
Ω
RESR
Equivalent Series Resistance*
DHSE
HSE Oscillator Duty Cycle
40
—
60
%
IDDHSE
HSE Oscillator Current Consumption VDD = 3.3V @ 16MHz
—
TBD
—
mA
IPWDHSE
HSE Oscillator Power Down Current VDD = 3.3V
—
—
0.01
μA
tSUHSE
HSE Oscillator STartup Time
—
—
4
ms
VDD = 2.4V, CL = 12pF
@ 16MHz, HSEDR = 1
—
VDD = 3.3V
Table 15. Low Speed External Clock (LSE) Characteristics
TA = 25°C, unless otherwise specified.
Symbol
VDD
Parameter
Operation Range
fCK_LSE
LSE Frequency
Conditions
—
VBAK = 2.0V ~ 3.6V
Min
2.0
Typ
—
—
32.768
—
RF
Internal Feedback Resistor
Equivalent Series Resistance
VBAK = 3.3V
30
—
TBD
kΩ
CL
Recommended Load
Capacitances
VBAK = 3.3V
6
—
TBD
pF
Oscillator Supply Current
(High Current Mode)
FCK_LSE = 32.768kHz,
RESR = 50KΩ, CL >= 7pF
VBAK = 2.0V ~ 2.7V
TA = -40°C ~ +85°C
—
3.3
6.3
μA
Oscillator Supply Current
(Low Current Mode)
FCK_LSE = 32.768kHz,
RESR = 50KΩ, CL < 7pF
VBAK = 2.0V ~ 3.6V
TA = -40°C ~ +85°C
—
1.8
3.3
μA
—
—
0.01
μA
500
—
—
ms
Power Down Current
tsuLSE
Startup Time
( Low Current Mode)
—
fCK_LSI = 32.768kHz,
VBAK = 2.0V ~ 3.6V
10
kHz
RESR
IDDLSE
—
Max Unit
3.6
V
MΩ
Note: The following guidelines are recommended to increase the stability of the crystal circuit of the
HSE / LSE clock in the PCB layout:
●● The crystal oscillator should be located as close as possible to the MCU to keep the trace
lengths as short as possible to reduce any parasitic capacitance.
●● Shield lines in the vicinity of the crystal by using a ground plane to isolate signals and
reduce noise.
●● Keep any high frequency signal lines away from the crystal area to prevent any crosstalk
adverse effects.
Rev. 1.51
36 of 50
April 11, 2017
Electrical Characteristics
Symbol
VDD
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Internal Clock Characteristics
Table 16. High Speed Internal Clock (HSI) Characteristics
TA = 25°C, unless otherwise specified.
Symbol
VDD
Parameter
Operation Range
fHSI
HSI Frequency
Duty
IDDHSI
tsuHSI
Min
2.0
Typ
—
Max
3.6
Unit
V
VDD = 3.3V @ 25°C
—
8
—
MHz
VDD = 3.3V, TA = 25°C
-2
—
2
%
-3
—
3
%
-4
—
4
%
35
—
65
%
Factory Calibrated ������������
HSI Oscilla- VDD = 2.5V ~ 3.6V,
TA = -40°C ~ +85°C
tor FRequency Accuracy
VDD = 2.0V ~ 3.6V
TA = -40°C ~ +85°C
fHSI = 8MHz
Duty Cycle
Oscillator Supply Current
fHSI = 8MHz
Power down Current
Startup Time
fHSI = 8MHz
—
300
500
μA
—
—
0.05
μA
—
—
10
μs
Table 17. Low Speed Internal Clock (LSI) Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
Low Speed Internal Oscillator
Frequency (LSI)
Conditions
VDD = 3.3V,
TA = -40°C ~ +85°C
Min
Typ
Max
Unit
21
32
43
kHz
ACCLSI
LSI Frequency Accuracy
After factory-trimmed,
VDD = 3.3V, TA = 25°C
-10
—
+10
%
IDDLSI
LSI Oscillator Operating Current VDD = 3.3V, TA = 25°C
—
0.4
0.8
μA
tSULSI
LSI Oscillator Startup Time
—
—
100
μs
fLSI
VDD = 3.3V, TA = 25°C
PLL Characteristics
Table 18. PLL Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
PLL Input Clock
fPLLIN
Conditions
—
Min
4
Typ
—
Max
16
Unit
MHz
fCK_PLL
PLL Output Clock
—
16
—
48
MHz
tLOCK
PLL Lock Time
—
—
200
—
μs
Memory Characteristics
Table 19. Flash Memory Characteristics
Symbol
NENDU
Rev. 1.51
TA = 25°C, unless otherwise specified.
Parameter
Conditions
Number of Guaranteed Program/Erase
TA = -40°C ~ +85°C
Cycles Before Failure. (Endurance)
Min
Typ
Max
Unit
10
—
—
K cycles
tRET
Data Retention Time
TA = -40°C ~ +85°C
10
—
—
Years
tPROG
Word Programming Time
TA = -40°C ~ +85°C
20
—
—
μs
tERASE
Page Erase Time
TA = -40°C ~ +85°C
2
—
—
ms
tMERASE
Mass Erase Time
TA = -40°C ~ +85°C
10
—
—
ms
37 of 50
April 11, 2017
Electrical Characteristics
ACCHSI
Conditions
—
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
I/O Port Characteristics
Table 20. I/O Port Characteristics
Symbol
IIH
High Level Input Current
VHYS
IOL
IOH
VOL
VOH
Conditions
3.3V IO
Min
Typ Max Unit
VI = VSS, On-chip
pull-up resister
disabled.
—
—
3
μA
—
—
3
μA
VI = VDD, On-chip
pull-down resister
disabled.
—
—
3
μA
—
—
3
μA
3.3V IO
- 0.5
—
VDD ×
0.35
V
Reset pin
- 0.5
—
VDD ×
0.35
V
3.3V IO
VDD ×
0.65
—
VDD +
0.5
V
Reset pin
VDD ×
0.65
—
VDD +
0.5
V
3.3V IO
—
VDD ×
0.12
—
mV
Reset pin
—
VDD ×
0.12
—
mV
Reset pin
3.3V IO
Reset pin
Low Level Input Voltage
High Level Input Voltage
Schmitt Trigger Input
Voltage Hysteresis
Low Level Output Current
(GPIO Sink Current)
3.3V IO 4mA drive, VOL = 0.4V
4
—
—
mA
3.3V IO 8mA drive, VOL = 0.4V
8
—
—
mA
3.3V IO 12mA drive, VOL = 0.4V
12
—
—
mA
3.3V IO 16mA drive, VOL = 0.4V
16
—
—
mA
3.3V I/O 4mA drive, VOH = VDD - 0.4V
4
—
—
mA
High Level Output Current 3.3V I/O 8mA drive, VOH = VDD - 0.4V
(GPIO Source Current)
3.3V I/O 12mA drive, VOH = VDD - 0.4V
8
—
—
mA
12
—
—
mA
3.3V I/O 16mA drive, VOH = VDD - 0.4V
16
—
—
mA
3.3V 4mA drive IO, IOL = 4mA
—
—
0.4
V
3.3V 8mA drive IO, IOL = 8mA
—
—
0.4
V
3.3V 12mA drive IO, IOL = 12mA
—
—
0.4
V
3.3V 16mA drive IO, IOL = 16mA
—
—
0.4
V
3.3V 4mA drive IO, IOH = 4mA
VDD 0.4
—
—
V
3.3V 8mA drive IO, IOH = 8mA
VDD 0.4
—
—
V
3.3V 12mA drive IO, IOL = 12mA
VDD 0.4
—
—
V
3.3V 16mA drive IO, IOL = 16mA
VDD 0.4
—
—
V
Low Level Output Voltage
High Level Output Voltage
RPU
Internal Pull-up Resistor
3.3V I/O
—
46
—
kΩ
RPD
Internal Pull-down Resistor 3.3V I/O
—
46
—
kΩ
38 of 50
April 11, 2017
Electrical Characteristics
Low Level Input Current
VIH
Rev. 1.51
Parameter
IIL
VIL
TA = 25°C, unless otherwise specified.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
ADC Characteristics
Table 21. ADC Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
Operating Voltage
VDDA
Conditions
—
Min
2.5
—
0
Typ Max
3.3 3.6
A/D Converter Input Voltage Range
VREF+
A/D Converter Reference Voltage
IADC
Current Consumption
VDDA = 3.3V
—
1
TBD
mA
IADC_DN
Power Down Current Consumption VDDA = 3.3V
—
—
0.1
μA
—
VREF+
VDDA VDDA
V
V
fADC
A/D Converter Clock
—
0.7
—
16
MHz
fS
Sampling Rate
—
0.05
—
1
MHz
tDL
Data Latency
—
—
12.5
—
1/fADC
Cycles
tS&H
Sampling & Hold Time
—
—
3.5
—
1/fADC
Cycles
tADCCONV
A/D Converter Conversion Time
—
—
16
—
1/fADC
Cycles
RI
Input Sampling Switch Resistance
CI
Input Sampling Capacitance
tSU
Startup Up Time
—
—
—
1
kΩ
No pin/pad capacitance
included
—
16
—
pF
—
—
—
1
μs
N
Resolution
—
—
12
—
bits
INL
Integral Non-linearity Error
fS = 750kHz, VDDA = 3.3V
—
±2
±5
LSB
DNL
Differential Non-linearity Error
fS = 750kHz, VDDA = 3.3V
—
±1
—
LSB
EO
Offset Error
—
—
—
±10
LSB
EG
Gain Error
—
—
—
±10
LSB
Note: 1. Guaranteed by design, not tested in production.
2. The figure below shows the equivalent circuit of the A/D Converter Sample-and-Hold input
stage where CI is the storage capacitor, RI is the resistance of the sampling switch and RS
is the output impedance of the signal source VS. Normally the sampling phase duration is
approximately, 3.5/fADC. The capacitance, CI, must be charged within this time frame and it
must be ensured that the voltage at its terminals becomes sufficiently close to VS for accuracy. To guarantee this, RS is not allowed to have an arbitrarily large value.
Rev. 1.51
39 of 50
April 11, 2017
Electrical Characteristics
VADCIN
—
—
Unit
V
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
SAR ADC
sample
RS
RI
Figure 10. ADC Sampling Network Model
The worst case occurs when the extremities of the input range (0V and V REF ) are sampled
consecutively. In this situation a sampling error below ¼ LSB is ensured by using the following
equation:
RS 
3.5
 RI
f ADC C I ln( 2 N  2 )
Where fADC is the ADC clock frequency and N is the ADC resolution (N = 12 in this case). A safe
margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for
in this simple model.
If, in a system where the A/D Converter is used, there are no rail-to-rail input voltage variations
between consecutive sampling phases, RS may be larger than the value indicated by the equation
above.
SCTM/GPTM/MCTM Characteristics
Table 22. SCTM/GPTM/MCTM Characteristics
Symbol
Parameter
Timer Clock Source for GPTM and MCTM
fTM
Rev. 1.51
Conditions
—
Min
—
Typ
—
Max
48
Unit
MHz
tRES
Timer Resolution Time
—
1
—
—
fTM
fEXT
External Single Frequency on Channel 1 ~ 4
—
—
—
1/2
fTM
RES
Timer Resolution
—
—
—
16
bits
40 of 50
April 11, 2017
Electrical Characteristics
CI
VS
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
I2C Characteristics
Table 23. I2C Characteristics
Symbol
Standard mode
Parameter
Fast mode
Fast mode plus
Max
100
Min
—
Max
400
Min
—
Max
1000
Unit
fSCL
SCL Clock Frequency
Min
—
tSCL(H)
SCL Clock High Time
4.5
—
1.125
—
0.45
—
μs
tSCL(L)
SCL Clock Low Time
4.5
—
1.125
—
0.45
—
μs
tFALL
SCL and SDA Fall Time
—
1.3
—
0.34
—
0.135
μs
tRISE
SCL and SDA Rise Time
—
1.3
—
0.34
—
0.135
μs
tSU(SDA)
SDA Data Setup Time
500
—
125
—
50
—
ns
tH(SDA)
SDA Data Hold Time
tSU(STA)
START Condition Setup Time
tH(STA)
START Condition Hold Time
0
—
0
—
0
—
ns
tSU(STO)
STOP Condition Setup Time
500
—
125
—
50
—
ns
kHz
—
0
—
0
—
ns
—
125
—
50
—
ns
Note: 1. Guaranteed by design, not tested in production.
2. To achieve 100 kHz standard mode, the peripheral clock frequency must be higher than 2MHz.
3. To achieve 400 kHz fast mode, the peripheral clock frequency must be higher than 8MHz.
4. To achieve 1MHz fast mode plus, the peripheral clock frequency must be higher than
20MHz.
5. The above characteristic parameters of the I2C bus timing are based on: SEQ_FILTER = 01
and COMB_FILTER_En is disabled.
tFALL
tRISE
SCL
tSCL(L)
tH(STA)
tSCL(H)
tH(SDA)
tSU(SDA)
tSU(STO)
SDA
tSU(STA)
Figure 11. I2C Timing Diagrams
Rev. 1.51
41 of 50
April 11, 2017
Electrical Characteristics
0
500
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
SPI Characteristics
Table 24. SPI Characteristics
Symbol
Parameter
SPI Master Mode
Min
Typ
Max
Unit
Master mode, SPI peripheral
clock frequency fPCLK
—
—
fPCLK/2
MHz
tSCK/2
-2
—
tSCK/2
+1
ns
fSCK
(1/tSCK)
SPI master output SCK
clock frequency
tSCK(H)
tSCK(L)
SCK clock high and low time
tV(MO)
Data output valid time
—
—
—
5
ns
tH(MO)
Data output hold time
—
2
—
—
ns
tSU(MI)
Data input setup time
—
5
—
—
ns
tH(MI)
Data input hold time
—
5
—
—
ns
—
—
fPCLK/3
MHz
30
—
70
%
SPI Slave Mode
fSCK
(1/tSCK)
SPI master output SCK
clock frequency
Slave mode, SPI peripheral
clock frequency fPCLK
DutySCK
SPI slave input SCK clock
duty cycle
tSU(SEL)
SEL enable setup time
—
3 tPCLK
—
—
ns
tH(SEL)
SEL enable hold time
—
2 tPCLK
—
—
ns
tA(SO)
Data output access time
—
—
—
3 tPCLK
ns
tDIS(SO)
Data output disable time
—
—
—
10
ns
tV(SO)
Data output valid time
—
—
—
25
ns
tH(SO)
Data output hold time
—
15
—
—
ns
tSU(SI)
Data input setup time
—
5
—
—
ns
tH(SI)
Data input hold time
—
4
—
—
ns
Note: tSCK= 1/fSCK; tPCLK= 1/fPCLK. SPI output (input) clock frequency fSCK; SPI peripheral clock frequency fPCLK.
tSCK
SCK (CPOL = 0)
tSCK(H)
tSCK(L)
SCK (CPOL = 1)
tV(MO)
MOSI
DATA VALID
tSU(MI )
MISO
MOSI
MISO
DATA VALID
DATA VALID
tH(MI )
CPHA = 1
DATA VALID
DATA VALID
tV(MO)
tH(MO)
DATA VALID
tSU(MI )
tH(MO)
DATA VALID
DATA VALID
DATA VALID
tH(MI )
DATA VALID
CPHA = 0
DATA VALID
DATA VALID
Figure 12. SPI Timing Diagrams – SPI Master Mode
Rev. 1.51
42 of 50
April 11, 2017
Electrical Characteristics
Conditions
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
SEL
tSU(SEL)
tH(SEL)
tSCK
tSCK(H)
tSCK(L)
SCK
(CPOL=1)
tSU(SI)
MOSI
LSB/MSB IN
MSB/LSB IN
tA(SO)
MISO
tH(SI)
tV(SO)
tH(SO)
MSB/LSB OUT
tDIS(SO)
LSB/MSB OUT
Figure 13. SPI Timing Diagrams – SPI Slave Mode with CPHA=1
Rev. 1.51
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April 11, 2017
Electrical Characteristics
SCK
(CPOL=0)
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
USB Characteristics
The USB interface is USB-IF certified – Full Speed.
Table 25. USB DC Electrical Characteristics
Symbol
Parameter
USB Operating Voltage
VDD
Conditions
—
| USBDP - USBDM |
Min
3.0
Typ
—
Max Unit
3.6
V
Differential Input Sensitivity
0.2
—
—
V
VCM
Common Mode Voltage Range
—
0.8
—
2.5
V
VSE
Single-ended Receiver Threshold
—
0.8
—
2.0
V
VOL
Pad Output Low Voltage
0
—
0.3
V
VOH
Pad Output High Voltage
2.8
—
3.6
V
VCRS
Differential Output Signal Cross-point
Voltage
1.3
—
2.0
V
ZDRV
Driver Output Resistance
—
—
10
—
Ω
CIN
Transceiver Pad Capacitance
—
—
—
20
pF
RL of 1.5kΩ to VDD33
Note: 1. Guaranteed by design, not tested in production.
2. The USB functionality is ensured down to 2.7V but for not the full USB electrical characteristics which will experience degradation in the 2.7V to 3.0V VDD voltage range.
3. RL is the load connected to the USB driver USBDP.
Rise Time
Fall Time
Tr
Tf
90%
90%
VCRS
10%
10%
Figure 14. USB Signal Rise Time and Fall Time and Cross-point Voltage (VCRS) Definition
Table 26. USB AC Electrical Characteristics
Symbol
Rise time
tr
Rev. 1.51
Parameter
Conditions
CL = 50pF
Min
4
Typ
—
Max Unit
20
ns
tf
Fall time
CL = 50pF
4
—
20
ns
tr/f
Rise time / fall time matching
tr/f = tr / tf
90
—
110
%
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April 11, 2017
Electrical Characteristics
VDI
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
6
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website
for the latest version of the Package/Carton Information.
• Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• The Operation Instruction of Packing Materials
• Carton information
Rev. 1.51
45 of 50
April 11, 2017
Package Information
Additional supplementary information with regard to packaging is listed below. Click on the
relevant section to be transferred to the relevant website page.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
24-pin SSOP (150mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
—
A
—
0.236 BSC
B
—
0.154 BSC
—
C
0.008
—
0.012
C’
—
0.341 BSC
—
D
—
—
0.069
E
—
0.025 BSC
—
F
0.004
—
0.010
G
0.016
—
0.050
H
0.004
—
0.010
α
0°
—
8°
Symbol
A
Rev. 1.51
Dimensions in mm
Min.
Nom.
Max.
—
6.000 BSC
—
B
—
3.900 BSC
—
C
0.200
—
0.300
C’
—
8.660 BSC
—
D
—
—
1.750
E
—
0.635 BSC
—
F
0.100
—
0.250
G
0.410
—
1.270
H
0.100
—
0.250
α
0°
—
8°
46 of 50
April 11, 2017
Package Information
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
28-pin SSOP (150mil) Outline Dimensions
Package Information
Symbol
Dimensions in inch
Min.
Nom.
Max.
—
A
—
0.236 BSC
B
—
0.154 BSC
—
C
0.008
—
0.012
C’
—
0.390 BSC
—
D
—
—
0.069
E
—
0.025 BSC
—
F
0.004
—
0.0098
G
0.016
—
0.050
H
0.004
—
0.010
α
0°
—
8°
Symbol
A
Rev. 1.51
Dimensions in mm
Min.
Nom.
Max.
—
6.000 BSC
—
B
—
3.900 BSC
—
C
0.200
—
0.300
C’
—
9.900 BSC
—
D
—
—
1.750
E
—
0.635 BSC
—
F
0.100
—
0.250
G
0.410
—
1.270
H
0.100
—
0.250
α
0°
—
8°
47 of 50
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
SAW Type 33-pin (4mm×4mm) QFN Outline Dimensions
Package Information
33
Symbol
Nom.
Max.
A
0.028
0.030
0.031
A1
0.000
0.001
0.002
A3
—
0.008 BSC
—
b
0.006
0.008
0.010
D
—
0.157 BSC
—
E
—
0.157 BSC
—
e
—
0.016 BSC
—
D2
0.104
0.106
0.108
E2
0.104
0.106
0.108
L
0.014
0.016
0.018
K
0.008
—
—
Symbol
Rev. 1.51
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
0.700
0.750
0.800
A1
0.000
0.020
0.050
A3
—
0.203 BSC
—
b
0.150
0.200
0.250
D
—
4.000 BSC
—
E
—
4.000 BSC
—
e
—
0.400 BSC
—
D2
2.650
2.700
2.750
E2
2.650
2.700
2.750
L
0.350
0.400
0.450
K
0.200
—
—
48 of 50
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
48-pin LQFP (7mm×7mm) Outline Dimensions
Package Information
Symbol
Dimensions in inch
Min.
Nom.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.020 BSC
—
F
0.007
0.009
0.011
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
―
7°
Symbol
Rev. 1.51
Max.
Dimensions in mm
Min.
Nom.
Max.
A
—
9.000 BSC
—
B
—
7.000 BSC
—
C
—
9.000 BSC
—
D
—
7.000 BSC
—
E
—
0.500 BSC
—
F
0.170
0.220
0.270
G
1.350
1.400
1.450
H
—
—
1.600
I
0.050
—
0.150
J
0.450
0.600
0.750
K
0.090
—
0.200
α
0°
―
7°
49 of 50
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Package Information
Copyright© 2017 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw/en/home.
Rev. 1.51
50 of 50
April 11, 2017