Product Folder Sample & Buy Technical Documents Tools & Software Support & Community MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 MSP430FR59xx Mixed-Signal Microcontrollers 1 Device Overview 1.1 Features 1 • Embedded Microcontroller – 16-Bit RISC Architecture up to 16‑MHz Clock – Wide Supply Voltage Range (1.8 V to 3.6 V)(1) • Optimized Ultra-Low-Power Modes – Active Mode: Approximately 100 µA/MHz – Standby (LPM3 With VLO): 0.4 µA (Typical) – Real-Time Clock (LPM3.5): 0.25 µA (Typical)(2) – Shutdown (LPM4.5): 0.02 µA (Typical) • Ultra-Low-Power Ferroelectric RAM (FRAM) – Up to 64KB of Nonvolatile Memory – Ultra-Low-Power Writes – Fast Write at 125 ns Per Word (64KB in 4 ms) – Unified Memory = Program + Data + Storage in One Single Space – 1015 Write Cycle Endurance – Radiation Resistant and Nonmagnetic • Intelligent Digital Peripherals – 32-Bit Hardware Multiplier (MPY) – Three-Channel Internal DMA – Real-Time Clock (RTC) With Calendar and Alarm Functions – Five 16-Bit Timers With up to Seven Capture/Compare Registers Each – 16-Bit Cyclic Redundancy Checker (CRC) • High-Performance Analog – 16-Channel Analog Comparator – 12-Bit Analog-to-Digital Converter (ADC) With Internal Reference and Sample-and-Hold and up to 16 External Input Channels • Multifunction Input/Output Ports – All Pins Support Capacitive Touch Capability With No Need for External Components – Accessible Bit-, Byte-, and Word-Wise (in Pairs) – Edge-Selectable Wake From LPM on All Ports – Programmable Pullup and Pulldown on All Ports 1.2 • • • • Code Security and Encryption – 128-Bit or 256-Bit AES Security Encryption and Decryption Coprocessor – Random Number Seed for Random Number Generation Algorithms • Enhanced Serial Communication – eUSCI_A0 and eUSCI_A1 Support • UART With Automatic Baud-Rate Detection • IrDA Encode and Decode • SPI at Rates up to 10 Mbps – eUSCI_B0 Supports • I2C With Multiple Slave Addressing • SPI at Rates up to 8 Mbps – Hardware UART and I2C Bootstrap Loader (BSL) • Flexible Clock System – Fixed-Frequency DCO With 10 Selectable Factory-Trimmed Frequencies – Low-Power Low-Frequency Internal Clock Source (VLO) – 32-kHz Crystals (LFXT) – High-Frequency Crystals (HFXT) • Development Tools and Software – Free Professional Development Environments With EnergyTrace++™ Technology – Development Kit (MSP-TS430RGZ48C) • Family Members – Table 3-1 Summarizes 11 Variants in 3 Available Package Types • For Complete Module Descriptions, See the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide (SLAU367) (1) Minimum supply voltage is restricted by SVS levels. (2) RTC is clocked by a 3.7-pF crystal. Applications Metering Energy Harvested Sensor Nodes Wearable Electronics • • Sensor Management Data Logging 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 1.3 www.ti.com Description The MSP430™ ultra-low-power (ULP) FRAM platform combines uniquely embedded FRAM and a holistic ultra-low-power system architecture, allowing innovators to increase performance at lowered energy budgets. FRAM technology combines the speed, flexibility, and endurance of SRAM with the stability and reliability of flash at much lower power. The MSP430 ULP FRAM portfolio consists of a diverse set of devices featuring FRAM, the ULP 16-bit MSP430 CPU, and intelligent peripherals targeted for various applications. The ULP architecture showcases seven low-power modes, optimized to achieve extended battery life in energy-challenged applications. Device Information (1) PART NUMBER MSP430FR5969RGZ BODY SIZE (2) VQFN (48) 7 mm x 7 mm MSP430FR5959RHA VQFN (40) 6 mm x 6 mm MSP430FR5959DA TSSOP (38) 12.5 mm x 6.2 mm (1) (2) 2 PACKAGE For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 9, or see the TI web site at www.ti.com. The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 9. Device Overview Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com 1.4 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Functional Block Diagram Figure 1-1 shows the functional block diagram of the devices. LFXIN, HFXIN LFXOUT, HFXOUT P1.x, P2.x P3.x, P4.x 2x8 2x8 PJ.x 1x8 Capacitive Touch IO 0/1 ADC12_B MCLK Clock System ACLK SMCLK Comp_E (up to 16 inputs) DMA Controller 3 Channel Bus Control Logic MAB REF_A (up to 16 standard inputs, up to 8 differential inputs) Voltage Reference I/O Ports P1, P2 2x8 I/Os I/O Ports P3, P4 2x8 I/Os PA 1x16 I/Os PB 1x16 I/Os I/O Port PJ 1x8 I/Os MAB MDB CPUXV2 incl. 16 Registers MPU IP Encap MDB EEM (S: 3 + 1) FRAM RAM 64KB 48KB 32KB 2KB 1KB LDO SVS Brownout TA2 TA3 AES256 Power Mgmt CRC16 MPY32 Security Encryption, Decryption (128, 256) Watchdog Timer_A 2 CC Registers (int. only) EnergyTrace++ MDB JTAG Interface MAB Spy-Bi-Wire TB0 TA0 TA1 Timer_B 7 CC Registers (int, ext) Timer_A 3 CC Registers (int, ext) Timer_A 3 CC Registers (int, ext) eUSCI_A0 eUSCI_A1 (UART, IrDA, SPI) eUSCI_B0 (I2C, SPI) RTC_B RTC_A LPM3.5 Domain A. B. The low-frequency (LF) crystal oscillator and the corresponding LFXIN and LFXOUT pins are available only in MSP430FR5x6x and MSP430FR5x4x devices. RTC_B is available only in conjunction with the LF crystal oscillator in MSP430FR5x6x and MSP430FR5x4x devices. The high-frequency (HF) crystal oscillator and the corresponding HFXIN and HFXOUT pins are available only in MSP430FR5x6x and MSP430FR5x5x devices. MSP430FR5x5x devices with the HF crystal oscillator only do not include the RTC_B module. Figure 1-1. Functional Block Diagram Device Overview Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 3 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table of Contents 1 Device Overview ......................................... 1 Description ............................................ 2 5.11 Thermal Packaging Characteristics Functional Block Diagram ............................ 3 5.12 Timing and Switching Characteristics ............... 24 5.13 Emulation and Debug ............................... 50 1.2 Applications ........................................... 1 1.3 Revision History ......................................... 4 Device Comparison ..................................... 5 Terminal Configuration and Functions .............. 6 4.1 4.2 4.3 4.4 4.5 5 Currents ............................................. 22 Typical Characteristics, Current Consumption per Module .............................................. 23 Features .............................................. 1 1.4 2 3 4 5.10 1.1 6 Pin Diagram – RGZ Package – MSP430FR596x and MSP430FR596x1 ................................ 6 Pin Diagram – RHA Package – MSP430FR594x and MSP430FR594x1 (LFXT Only) ................. 7 Pin Diagram – DA Package – MSP430FR594x (LFXT Only) .......................................... 8 Pin Diagram – RHA Package – MSP430FR595x (HFXT Only) ......................................... 9 Pin Diagram – DA Package – MSP430FR595x (HFXT Only) ........................................ 10 ................ 23 Detailed Description ................................... 51 6.8 ............................................ ................................................. Operating Modes .................................... Interrupt Vector Table and Signatures .............. Memory Organization ............................... Bootstrap Loader (BSL) ............................. JTAG Operation ..................................... FRAM Memory ...................................... 6.9 Memory Protection Unit Including IP Encapsulation 58 6.1 Overview 51 6.2 CPU 51 6.3 6.4 6.5 6.6 6.7 52 53 56 56 57 58 5.1 Absolute Maximum Ratings ......................... 17 .......................................... 59 ........................... 79 6.12 Device Descriptors (TLV) .......................... 106 6.13 Identification........................................ 108 Applications, Implementation, and Layout ...... 109 7.1 Device Connection and Layout Fundamentals .... 109 5.2 Handling Ratings .................................... 17 7.2 5.3 5.4 Recommended Operating Conditions ............... Active Mode Supply Current Into VCC Excluding External Current .................................... Typical Characteristics - Active Mode Supply Currents ............................................. Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current ................ Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current .... Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into VCC) Excluding External Current .... Typical Characteristics, Low-Power Mode Supply 4.6 Signal Descriptions .................................. 11 4.7 Pin Multiplexing 4.8 Connection of Unused Pins ......................... 16 ..................................... 16 Specifications ........................................... 17 5.5 5.6 5.7 5.8 5.9 7 17 8 18 19 19 20 9 21 6.10 Peripherals 6.11 Input/Output Schematics Peripheral- and Interface-Specific Design Information ......................................... 112 Device and Documentation Support .............. 114 8.1 Device Support..................................... 114 8.2 Documentation Support ............................ 117 8.3 Trademarks ........................................ 118 8.4 Electrostatic Discharge Caution 8.5 Export Control Notice .............................. 118 8.6 Glossary............................................ 118 ................... 118 Mechanical Packaging and Orderable Information ............................................. 118 9.1 Packaging Information ............................. 118 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 4 DATE REVISION June 2014 C Revision History NOTES Section 6.8, Added the paragraph that starts "For important software design information regarding FRAM..." Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 3 Device Comparison Table 3-1 summarizes the available family members. Table 3-1. Device Comparison (1) (2) FRAM SRAM Clock (KB) (KB) System Device eUSCI ADC12_ B Comp_ E Timer_ A (3) Timer_ B (4) A (5) B (6) AES BSL I/O Package Type MSP430FR5969 64 2 DCO HFXT LFXT 16 ext, 2 int ch. 16 ch. 3, 3 (7) 2, 2 (8) 7 2 1 yes UART 40 48 RGZ MSP430FR59691 64 2 DCO HFXT LFXT 16 ext, 2 int ch. 16 ch. 3, 3 (7) 2, 2 (8) 7 2 1 yes I2C 40 48 RGZ MSP430FR5968 48 2 DCO HFXT LFXT 16 ext, 2 int ch. 16 ch. 3, 3 (7) 2, 2 (8) 7 2 1 yes UART 40 48 RGZ MSP430FR5967 32 1 DCO HFXT LFXT 16 ext, 2 int ch. 16 ch. 3, 3 (7) 2, 2 (8) 7 2 1 yes UART 40 48 RGZ 40 RHA 16 ch. 3, 3 (7) 2, 2 (8) 33 2 DCO LFXT 7 2 1 yes UART 31 38 DA 3, 3 (7) 2, 2 (8) 33 40 RHA 7 31 38 DA 3, 3 (7) 2, 2 (8) 33 40 RHA 7 31 38 DA 16 ch. 3, 3 (7) 2, 2 (8) 7 2 1 yes I2C 33 40 RHA 3, 3 (7) 2, 2 (8) 33 40 RHA 16 ch. 7 2 1 yes UART 31 38 DA 3, 3 (7) 2, 2 (8) 33 40 RHA 7 31 38 DA 3, 3 (7) 2, 2 (8) 33 40 RHA 7 31 38 DA MSP430FR5949 MSP430FR5948 MSP430FR5947 64 48 32 2 1 DCO LFXT DCO LFXT MSP430FR59471 32 1 DCO LFXT MSP430FR5959 64 2 DCO HFXT MSP430FR5958 MSP430FR5957 (1) (2) (3) (4) (5) (6) (7) (8) 48 32 2 1 DCO HFXT DCO HFXT 14 ext, 2 int ch. 12 ext, 2 int ch. 14 ext, 2 int ch. 12 ext, 2 int ch. 14 ext, 2 int ch. 12 ext, 2 int ch. 14 ext, 2 int ch. 14 ext, 2 int ch. 12 ext, 2 int ch. 14 ext, 2 int ch. 12 ext, 2 int ch. 14 ext, 2 int ch. 12 ext, 2 int ch. 16 ch. 16 ch. 16 ch. 16 ch. 2 2 2 2 1 1 1 1 yes yes yes yes UART UART UART UART For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging. Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare registers and PWM output generators, respectively. Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare registers and PWM output generators, respectively. eUSCI_A supports UART with automatic Baud-rate detection, IrDA encode and decode, and SPI. eUSCI_B supports I2C with multiple slave addresses, and SPI. Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs. Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any). Device Comparison Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 5 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Diagram – RGZ Package – MSP430FR596x and MSP430FR596x1 DVCC P2.7 P2.3/TA0.0/UCA1STE/A6/C10 P2.4/TA1.0/UCA1CLK/A7/C11 AVSS PJ.6/HFXIN PJ.7/HFXOUT AVSS PJ.4/LFXIN PJ.5/LFXOUT AVSS AVCC Figure 4-1 shows the 48-pin RGZ package. 48 47 46 45 44 43 42 41 40 39 38 37 P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- 1 36 DVSS P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ 2 35 P4.6 P1.2/TA1.1/TA0CLK/COUT/A2/C2 3 34 P4.5 P3.0/A12/C12 4 33 P4.4/TB0.5 P3.1/A13/C13 5 32 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0 P3.2/A14/C14 6 31 P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0 P3.3/A15/C15 7 30 P3.7/TB0.6 P4.7 8 29 P3.6/TB0.5 P1.3/TA1.2/UCB0STE/A3/C3 9 28 P3.5/TB0.4/COUT P1.4/TB0.1/UCA0STE/A4/C4 10 27 P3.4/TB0.3/SMCLK P1.5/TB0.2/UCA0CLK/A5/C5 11 26 P2.2/TB0.2/UCB0CLK P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0 P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK RST/NMI/SBWTDIO TEST/SBWTCK P2.6/TB0.1/UCA1RXD/UCA1SOMI P2.5/TB0.0/UCA1TXD/UCA1SIMO P4.3/A11 P4.1/A9 P4.2/A10 P4.0/A8 PJ.3/TCK/SRCPUOFF/C9 PJ.2/TMS/ACLK/SROSCOFF/C8 12 25 13 14 15 16 17 18 19 20 21 22 23 24 PJ.1/TDI/TCLK/MCLK/SRSCG0/C7 PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6 NOTE: QFN package pad connection to VSS recommended. On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL Figure 4-1. 48-Pin RGZ Package (Top View) – MSP430FR596x and MSP430FR596x1 6 Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com 4.2 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Pin Diagram – RHA Package – MSP430FR594x and MSP430FR594x1 (LFXT Only) DVSS DVCC P2.7 P2.3/TA0.0/UCA1STE/A6/C10 P2.4/TA1.0/UCA1CLK/A7/C11 AVSS PJ.4/LFXIN PJ.5/LFXOUT AVSS AVCC Figure 4-2 shows the 40-pin RHA package. 40 39 38 37 36 35 34 33 32 31 4 27 P3.7/TB0.6 P3.1/A13/C13 5 26 P3.6/TB0.5 P3.2/A14/C14 6 25 P3.5/TB0.4/COUT P3.3/A15/C15 7 24 P3.4/TB0.3/SMCLK P1.3/TA1.2/UCB0STE/A3/C3 8 23 P2.2/TB0.2/UCB0CLK P1.4/TB0.1/UCA0STE/A4/C4 9 22 P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0 P1.5/TB0.2/UCA0CLK/A5/C5 10 21 11 12 13 14 15 16 17 18 19 20 P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK RST/NMI/SBWTDIO TEST/SBWTCK P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0 P3.0/A12/C12 P2.6/TB0.1/UCA1RXD/UCA1SOMI 28 P2.5/TB0.0/UCA1TXD/UCA1SIMO 3 P4.1/A9 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0 P1.2/TA1.1/TA0CLK/COUT/A2/C2 P4.0/A8 29 PJ.3/TCK/SRCPUOFF/C9 P4.4/TB0.5 2 PJ.2/TMS/ACLK/SROSCOFF/C8 30 P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ PJ.1/TDI/TCLK/MCLK/SRSCG0/C7 1 PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6 P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- NOTE: QFN package pad connection to VSS recommended. On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL Figure 4-2. 40-Pin RHA Package (Top View) – MSP430FR594x and MSP430FR594x1 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 7 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 4.3 www.ti.com Pin Diagram – DA Package – MSP430FR594x (LFXT Only) Figure 4-3 shows the 38-pin DA package. PJ.4/LFXIN 1 38 AVSS PJ.5/LFXOUT 2 37 P2.4/TA1.0/UCA1CLK/A7/C11 AVSS 3 36 P2.3/TA0.0/UCA1STE/A6/C10 AVCC 4 35 P2.7 P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- 5 34 DVCC P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ 6 33 DVSS P1.2/TA1.1/TA0CLK/COUT/A2/C2 7 32 P4.4/TB0.5 P3.0/A12/C12 8 31 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0 P3.1/A13/C13 9 30 P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0 P3.2/A14/C14 10 29 P3.7/TB0.6 P3.3/A15/C15 11 28 P3.6/TB0.5 P1.3/TA1.2/UCB0STE/A3/C3 12 27 P3.5/TB0.4/COUT P1.4/TB0.1/UCA0STE/A4/C4 13 26 P3.4/TB0.3/SMCLK P1.5/TB0.2/UCA0CLK/A5/C5 14 25 P2.2/TB0.2/UCB0CLK PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6 15 24 P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0 PJ.1/TDI/TCLK/MCLK/SRSCG0/C7 16 23 P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK PJ.2/TMS/ACLK/SROSCOFF/C8 17 22 RST/NMI/SBWTDIO PJ.3/TCK/SRCPUOFF/C9 18 21 TEST/SBWTCK P2.5/TB0.0/UCA1TXD/UCA1SIMO 19 20 P2.6/TB0.1/UCA1RXD/UCA1SOMI On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX Figure 4-3. 38-Pin DA Package (Top View) – MSP430FR594x 8 Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com 4.4 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Pin Diagram – RHA Package – MSP430FR595x (HFXT Only) DVSS DVCC P2.7 P2.3/TA0.0/UCA1STE/A6/C10 P2.4/TA1.0/UCA1CLK/A7/C11 AVSS PJ.6/HFXIN PJ.7/HFXOUT AVSS AVCC Figure 4-4 shows the 40-pin RHA package. 40 39 38 37 36 35 34 33 32 31 4 27 P3.7/TB0.6 P3.1/A13/C13 5 26 P3.6/TB0.5 P3.2/A14/C14 6 25 P3.5/TB0.4/COUT P3.3/A15/C15 7 24 P3.4/TB0.3/SMCLK P1.3/TA1.2/UCB0STE/A3/C3 8 23 P2.2/TB0.2/UCB0CLK P1.4/TB0.1/UCA0STE/A4/C4 9 22 P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0 P1.5/TB0.2/UCA0CLK/A5/C5 10 21 11 12 13 14 15 16 17 18 19 20 P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK RST/NMI/SBWTDIO TEST/SBWTCK P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0 P3.0/A12/C12 P2.5/TB0.0/UCA1TXD/UCA1SIMO 28 P2.6/TB0.1/UCA1RXD/UCA1SOMI 3 P4.1/A9 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0 P1.2/TA1.1/TA0CLK/COUT/A2/C2 P4.0/A8 29 PJ.3/TCK/SRCPUOFF/C9 P4.4/TB0.5 2 PJ.2/TMS/ACLK/SROSCOFF/C8 30 P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ PJ.1/TDI/TCLK/MCLK/SRSCG0/C7 1 PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6 P1.0/TA0.1/DMAE0/A0/C0/VREF-/VeREF- NOTE: QFN package pad connection to VSS recommended. On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX Figure 4-4. 40-Pin RHA Package (Top View) – MSP430FR595x Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 9 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 4.5 www.ti.com Pin Diagram – DA Package – MSP430FR595x (HFXT Only) Figure 4-5 shows the 38-pin DA package. PJ.6/HFXIN 1 38 AVSS PJ.7/HFXOUT 2 37 P2.4/TA1.0/UCA1CLK/A7/C11 AVSS 3 36 P2.3/TA0.0/UCA1STE/A6/C10 AVCC 4 35 P2.7 P1.0/TA0.1/DMAE0/A0/C0/VREF-/VeREF- 5 34 DVCC P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ 6 33 DVSS P1.2/TA1.1/TA0CLK/COUT/A2/C2 7 32 P4.4/TB0.5 P3.0/A12/C12 8 31 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0 P3.1/A13/C13 9 30 P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0 P3.2/A14/C14 10 29 P3.7/TB0.6 P3.3/A15/C15 11 28 P3.6/TB0.5 P1.3/TA1.2/UCB0STE/A3/C3 12 27 P3.5/TB0.4/COUT P1.4/TB0.1/UCA0STE/A4/C4 13 26 P3.4/TB0.3/SMCLK P1.5/TB0.2/UCA0CLK/A5/C5 14 25 P2.2/TB0.2/UCB0CLK PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6 15 24 P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0 PJ.1/TDI/TCLK/MCLK/SRSCG0/C7 16 23 P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK PJ.2/TMS/ACLK/SROSCOFF/C8 17 22 RST/NMI/SBWTDIO PJ.3/TCK/SRCPUOFF/C9 18 21 TEST/SBWTCK P2.5/TB0.0/UCA1TXD/UCA1SIMO 19 20 P2.6/TB0.1/UCA1RXD/UCA1SOMI On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX Figure 4-5. 38-Pin DA Package (Top View) – MSP430FR595x 10 Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com 4.6 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Signal Descriptions Table 4-1 describes the signals for all device variants and package options. Table 4-1. Signal Descriptions TERMINAL NAME NO. (2) RGZ RHA I/O (1) DESCRIPTION DA General-purpose digital I/O with port interrupt and wakeup from LPMx.5 TA0 CCR1 capture: CCI1A input, compare: Out1 External DMA trigger P1.0/TA0.1/DMAE0/ RTCCLK/A0/C0/VREF-/ VeREF- 1 1 5 I/O RTC clock calibration output (not available on MSP430FR5x5x devices) Analog input A0 – ADC Comparator input C0 Output of negative reference voltage Input for an external negative reference voltage to the ADC General-purpose digital I/O with port interrupt and wakeup from LPMx.5 TA0 CCR2 capture: CCI2A input, compare: Out2 TA1 input clock P1.1/TA0.2/TA1CLK/ COUT/A1/C1/VREF+/ VeREF+ 2 2 6 I/O Comparator output Analog input A1 – ADC Comparator input C1 Output of positive reference voltage Input for an external positive reference voltage to the ADC General-purpose digital I/O with port interrupt and wakeup from LPMx.5 TA1 CCR1 capture: CCI1A input, compare: Out1 P1.2/TA1.1/TA0CLK/ COUT/A2/C2 3 3 7 I/O TA0 input clock Comparator output Analog input A2 – ADC Comparator input C2 General-purpose digital I/O with port interrupt and wakeup from LPMx.5 P3.0/A12/C12 4 4 8 I/O Analog input A12 – ADC Comparator input C12 General-purpose digital I/O with port interrupt and wakeup from LPMx.5 P3.1/A13/C13 5 5 9 I/O Analog input A13 – ADC Comparator input C13 General-purpose digital I/O with port interrupt and wakeup from LPMx.5 P3.2/A14/C14 6 6 10 I/O Analog input A14 – ADC Comparator input C14 General-purpose digital I/O with port interrupt and wakeup from LPMx.5 P3.3/A15/C15 7 7 11 I/O Analog input A15 – ADC Comparator input C15 (1) (2) I = input, O = output N/A = not available Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 11 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 4-1. Signal Descriptions (continued) TERMINAL NAME P4.7 NO. (2) I/O (1) RGZ RHA DA 8 N/A N/A I/O DESCRIPTION General-purpose digital I/O with port interrupt and wakeup from LPMx.5 General-purpose digital I/O with port interrupt and wakeup from LPMx.5 TA1 CCR2 capture: CCI2A input, compare: Out2 P1.3/TA1.2/UCB0STE/ A3/C3 9 8 12 I/O Slave transmit enable – eUSCI_B0 SPI mode Analog input A3 – ADC Comparator input C3 General-purpose digital I/O with port interrupt and wakeup from LPMx.5 TB0 CCR1 capture: CCI1A input, compare: Out1 P1.4/TB0.1/UCA0STE/ A4/C4 10 9 13 I/O Slave transmit enable – eUSCI_A0 SPI mode Analog input A4 – ADC Comparator input C4 General-purpose digital I/O with port interrupt and wakeup from LPMx.5 TB0 CCR2 capture: CCI2A input, compare: Out2 P1.5/TB0.2/UCA0CLK/ A5/C5 11 10 14 I/O Clock signal input – eUSCI_A0 SPI slave mode; Clock signal output – eUSCI_A0 SPI master mode Analog input A5 – ADC Comparator input C5 General-purpose digital I/O Test data output port PJ.0/TDO/TB0OUTH/ SMCLK/SRSCG1/C6 12 11 15 I/O Switch all PWM outputs high impedance input – TB0 SMCLK output Low Power Debug: CPU Status Register Bit SCG1 Comparator input C6 General-purpose digital I/O Test data input or test clock input PJ.1/TDI/TCLK/MCLK/ SRSCG0/C7 13 12 16 I/O MCLK output Low Power Debug: CPU Status Register Bit SCG0 Comparator input C7 General-purpose digital I/O Test mode select PJ.2/TMS/ACLK/ SROSCOFF/C8 14 13 17 I/O ACLK output Low Power Debug: CPU Status Register Bit OSCOFF Comparator input C8 General-purpose digital I/O PJ.3/TCK/SRCPUOFF/ C9 15 14 18 I/O Test clock Low Power Debug: CPU Status Register Bit CPUOFF Comparator input C9 12 Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 4-1. Signal Descriptions (continued) TERMINAL NAME P4.0/A8 NO. (2) I/O (1) RGZ RHA DA 16 15 N/A I/O DESCRIPTION General-purpose digital I/O with port interrupt and wakeup from LPMx.5 Analog input A8 – ADC P4.1/A9 17 16 N/A I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5 Analog input A9 – ADC P4.2/A10 18 N/A N/A I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5 Analog input A10 – ADC P4.3/A11 19 N/A N/A I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5 Analog input A11 – ADC General-purpose digital I/O with port interrupt and wakeup from LPMx.5 P2.5/TB0.0/UCA1TXD/ UCA1SIMO 20 17 19 I/O TB0 CCR0 capture: CCI0B input, compare: Out0 Transmit data – eUSCI_A1 UART mode Slave in, master out – eUSCI_A1 SPI mode General-purpose digital I/O with port interrupt and wakeup from LPMx.5 P2.6/TB0.1/UCA1RXD/ UCA1SOMI 21 18 20 I/O TB0 CCR1 compare: Out1 Receive data – eUSCI_A1 UART mode Slave out, master in – eUSCI_A1 SPI mode TEST/SBWTCK 22 19 21 I RST/NMI/SBWTDIO 23 20 22 I/O Test mode pin – select digital I/O on JTAG pins Spy-Bi-Wire input clock Reset input active low Non-maskable interrupt input Spy-Bi-Wire data input/output General-purpose digital I/O with port interrupt and wakeup from LPMx.5 TB0 CCR6 capture: CCI6B input, compare: Out6 P2.0/TB0.6/UCA0TXD/ UCA0SIMO/TB0CLK/ ACLK Transmit data – eUSCI_A0 UART mode 24 21 23 I/O BSL Transmit (UART BSL) Slave in, master out – eUSCI_A0 SPI mode TB0 clock input ACLK output General-purpose digital I/O with port interrupt and wakeup from LPMx.5 TB0 CCR0 capture: CCI0A input, compare: Out0 P2.1/TB0.0/UCA0RXD/ UCA0SOMI/TB0.0 25 22 24 I/O Receive data – eUSCI_A0 UART mode BSL Receive (UART BSL) Slave out, master in – eUSCI_A0 SPI mode TB0 CCR0 capture: CCI0A input, compare: Out0 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 13 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 4-1. Signal Descriptions (continued) TERMINAL NAME NO. (2) RGZ RHA I/O (1) DESCRIPTION DA General-purpose digital I/O with port interrupt and wakeup from LPMx.5 P2.2/TB0.2/UCB0CLK 26 23 25 I/O TB0 CCR2 compare: Out2 Clock signal input – eUSCI_B0 SPI slave mode Clock signal output – eUSCI_B0 SPI master mode General-purpose digital I/O with port interrupt and wakeup from LPMx.5 P3.4/TB0.3/SMCLK 27 24 26 I/O TB0 CCR3 capture: CCI3A input, compare: Out3 SMCLK output General-purpose digital I/O with port interrupt and wakeup from LPMx.5 P3.5/TB0.4/COUT 28 25 27 I/O TB0 CCR4 capture: CCI4A input, compare: Out4 Comparator output P3.6/TB0.5 29 26 28 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5 TB0 CCR5 capture: CCI5A input, compare: Out5 P3.7/TB0.6 30 27 29 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5 TB0 CCR6 capture: CCI6A input, compare: Out6 General-purpose digital I/O with port interrupt and wakeup from LPMx.5 TB0 CCR3 capture: CCI3B input, compare: Out3 P1.6/TB0.3/UCB0SIMO/ UCB0SDA/TA0.0 31 28 30 I/O Slave in, master out – eUSCI_B0 SPI mode I2C data – eUSCI_B0 I2C mode BSL Data (I2C BSL) TA0 CCR0 capture: CCI0A input, compare: Out0 General-purpose digital I/O with port interrupt and wakeup from LPMx.5 TB0 CCR4 capture: CCI4B input, compare: Out4 P1.7/TB0.4/UCB0SOMI/ UCB0SCL/TA1.0 32 29 31 I/O Slave out, master in – eUSCI_B0 SPI mode I2C clock – eUSCI_B0 I2C mode BSL Clock (I2C BSL) TA1 CCR0 capture: CCI0A input, compare: Out0 P4.4/TB0.5 33 30 32 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5 TB0CCR5 capture: CCI5B input, compare: Out5 P4.5 34 N/A N/A I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5 P4.6 35 N/A N/A I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5 DVSS 36 31 33 Digital ground supply DVCC 37 32 34 Digital power supply P2.7 38 33 35 14 Terminal Configuration and Functions I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5 Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 4-1. Signal Descriptions (continued) TERMINAL NAME NO. (2) RGZ RHA I/O (1) DESCRIPTION DA General-purpose digital I/O with port interrupt and wakeup from LPMx.5 TA0 CCR0 capture: CCI0B input, compare: Out0 P2.3/TA0.0/UCA1STE/ A6/C10 39 34 36 I/O Slave transmit enable – eUSCI_A1 SPI mode Analog input A6 – ADC Comparator input C10 General-purpose digital I/O with port interrupt and wakeup from LPMx.5 TA1 CCR0 capture: CCI0B input, compare: Out0 P2.4/TA1.0/UCA1CLK/ A7/C11 40 35 37 I/O Clock signal input – eUSCI_A1 SPI slave mode Clock signal output – eUSCI_A1 SPI master mode Analog input A7 – ADC Comparator input C11 AVSS 41 36 38 PJ.6/HFXIN 42 37 1 I/O PJ.7/HFXOUT 43 38 2 I/O AVSS 44 N/A N/A PJ.4/LFXIN 45 37 1 I/O PJ.5/LFXOUT 46 38 2 I/O AVSS 47 39 3 Analog ground supply AVCC 48 40 4 Analog power supply Pad Pad N/A Analog ground supply General-purpose digital I/O Input for high-frequency crystal oscillator HFXT (in RHA and DA: MSP430FR595x devices only) General-purpose digital I/O Output for high-frequency crystal MSP430FR595x devices only) oscillator HFXT (in RHA and DA: Analog ground supply General-purpose digital I/O Input for low-frequency crystal oscillator LFXT (in RHA and DA: MSP430FR594x devices only) General-purpose digital I/O QFN Pad Output of low-frequency crystal oscillator LFXT (in RHA and DA: MSP430FR594x devices only) QFN package exposed thermal pad. Connection to VSS is recommended. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 15 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 4.7 www.ti.com Pin Multiplexing Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the device is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see Section 6.11. 4.8 Connection of Unused Pins The correct termination of all unused pins is listed in Table 4-2. Table 4-2. Connection of Unused Pins (1) PIN POTENTIAL AVCC DVCC AVSS DVSS Px.0 to Px.7 Open Switched to port function, output direction (PxDIR.n = 1) RST/NMI DVCC or VCC 47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF (2)) pulldown PJ.0/TDO PJ.1/TDI PJ.2/TMS PJ.3/TCK Open The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used, these should be switched to port function, output direction. When used as JTAG pins, these pins should remain open. TEST Open This pin always has an internal pulldown enabled. (1) (2) 16 COMMENT Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection guidelines. The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers. Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 5 Specifications Absolute Maximum Ratings (1) 5.1 over operating free-air temperature range (unless otherwise noted) Voltage applied at DVCC and AVCC pins to VSS –0.3 V to 4.1 V Voltage difference between DVCC and AVCC pins (2) Voltage applied to any pin ±0.3V –0.3 V to (VCC + 0.3 V), 4.1 V Max (3) Diode current at any device pin (1) (2) (3) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM. All voltages referenced to VSS. 5.2 Handling Ratings Storage temperature range (1) Tstg (1) ±2 mA MIN MAX UNIT -40 125 °C Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. 5.3 Recommended Operating Conditions Typical data are based on VCC = 3.0 V, TA = 25°C, unless otherwise noted MIN VCC Supply voltage range applied at all DVCC and AVCC pins (1) (2) (3) VSS Supply voltage applied at all DVSS and AVSS pins TA Operating free-air temperature CDVCC Capacitor value at DVCC (5) fSYSTEM Processor frequency (maximum MCLK frequency) fACLK Maximum ACLK frequency fSMCLK Maximum SMCLK frequency (1) (2) (3) (4) (5) (6) (7) (8) (9) NOM 1.8 (4) MAX 3.6 V 85 °C 0 -40 V 1-20% (6) UNIT µF No FRAM wait states (NWAITSx = 0) 0 8 (7) With FRAM wait states (NWAITSx = 1) (8) 0 16 (9) MHz 50 kHz 16 (9) MHz It is recommended to power AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM. See Table 5-1 for additional important information. Modules may have a different supply voltage range specification. Refer to the specification of the respective module in this data sheet. The minimum supply voltage is defined by the supervisor SVS levels. See Table 5-2 for the exact values. Connect a low-ESR capacitor with at least the value specified and a maximum tolerance of 20% as close as possible to the DVCC pin. Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet. DCO settings and HF crystals with a typical value less or equal the specified MAX value are permitted. Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always executed without wait states. DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted. If a clock source with a higher typical value is used, the clock must be divided in the clock system. Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 17 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 5.4 www.ti.com Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted) (1) (2) FREQUENCY (fMCLK = fSMCLK) PARAMETER EXECUTION MEMORY VCC 1 MHz 0 wait states (NWAITSx = 0) TYP IAM, FRAM_UNI (Unified memory) (3) (4) (5) MAX 4 MHz 0 wait states (NWAITSx = 0) TYP MAX 8 MHz 0 wait states (NWAITSx = 0) TYP MAX 12 MHz 1 wait states (NWAITSx = 1) TYP MAX 16 MHz 1 wait states (NWAITSx = 1) TYP UNIT MAX FRAM 3.0 V 210 640 1220 1475 1845 µA FRAM 0% cache hit ratio 3.0 V 370 1280 2510 2080 2650 µA IAM, FRAM(0%) IAM, FRAM(50%) (4) (5) FRAM 50% cache hit ratio 3.0 V 240 745 1440 1575 1990 µA IAM, FRAM(66%) (4) (5) FRAM 66% cache hit ratio 3.0 V 200 560 1070 1300 1620 µA IAM, FRAM(75%) (4) (5) FRAM 75% cache hit ratio 3.0 V 170 480 890 IAM, FRAM(100% FRAM 100% cache hit ratio 3.0 V 110 235 420 640 730 IAM, RAM RAM 3.0 V 130 320 585 890 1070 RAM 3.0 V 100 290 555 860 1040 (6) IAM, RAM only (1) (2) (3) (4) (5) (6) (7) 18 (4) (5) (7) (5) 255 180 1085 1155 1310 1420 1620 µA µA µA 1300 µA All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical data processing. fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO= 24 MHz and fMCLK = fSMCLK = fDCO/2. At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency (fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait states or the cache hit ratio. The following equation can be used to compute fMCLK,eff: fMCLK,eff = fMCLK / [wait states × (1 - cache hit ratio) + 1] For example, with 1 wait state and 75% cache hit ratio fMCKL,eff = fMCLK / [1 × (1 - 0.75) + 1] = fMCLK / 1.25. Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM. Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesess divided by the total number of FRAM accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are FRAM accesses. See Figure 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best linear fit using the typical data shown in Section 5.4. Program and data reside entirely in RAM. All execution is from RAM. Program and data reside entirely in RAM. All execution is from RAM. FRAM is off. Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com 5.5 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Typical Characteristics - Active Mode Supply Currents 3000 I(AM,0%) I(AM,50%) 2500 I(AM,66%) Active Mode Current [µA] I(AM,75%) 2000 I(AM,100%) I(AM,75%)[uA] = 103*f[MHz] + 68 I(AM,RAMonly) 1500 1000 500 0 0 1 2 3 4 5 6 7 8 9 MCLK Frequency [MHz] C001 Figure 5-1. Typical Active Mode Supply Currents vs MCLK frequency, No Wait States 5.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted) (1) (2) FREQUENCY (fSMCLK) PARAMETER VCC 1 MHz TYP ILPM0 ILPM1 (1) (2) 2.2 V 70 3.0 V 80 2.2 V 35 3.0 V 35 4 MHz MAX 115 60 TYP 8 MHz MAX TYP 12 MHz MAX TYP 16 MHz MAX TYP 95 150 250 215 105 160 260 225 60 115 215 180 60 115 215 180 UNIT MAX 260 205 µA µA All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Current for watchdog timer clocked by SMCLK included. fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO at specified frequency - except for 12 MHz: here fDCO=24MHz and fSMCLK = fDCO/2. Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 19 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 5.7 www.ti.com Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC -40 °C TYP MAX 25 °C TYP ILPM2,XT12 Low-power mode 2, 12-pF crystal (2) (3) (4) 2.2 V 0.5 0.9 3.0 V 0.5 0.9 ILPM2,XT3.7 Low-power mode 2, 3.7-pF cyrstal (2) (5) (4) 2.2 V 0.5 3.0 V 0.5 ILPM2,VLO Low-power mode 2, VLO, includes SVS (6) 2.2 V 0.3 0.7 3.0 V 0.3 0.7 Low-power mode 3, 12-pF crystal, includes SVS (2) (3) 2.2 V 0.5 0.6 ILPM3,XT12 (7) 3.0 V 0.5 0.6 Low-power mode 3, 3.7pF cyrstal, excludes SVS (2) (5) 2.2 V 0.4 3.0 V ILPM3,XT3.7 (8) (also refer to Figure 5-2) (1) 60 °C MAX TYP MAX 85°C TYP 2.2 6.1 2.2 6.1 0.9 2.2 6.0 0.9 2.2 6.0 1.9 5.8 1.9 5.8 0.9 1.85 0.9 1.85 0.5 0.8 1.7 0.4 0.5 0.8 1.7 0.7 1.6 0.7 1.6 0.8 1.7 0.8 1.7 0.6 1.5 0.6 1.5 ILPM3,VLO Low-power mode 3, VLO, excludes SVS (9) 2.2 V 0.3 0.4 3.0 V 0.3 0.4 Low-power mode 4, includes SVS (10) (also refer to Figure 5-3) 2.2 V 0.4 0.5 ILPM4,SVS 3.0 V 0.4 0.5 ILPM4 Low-power mode 4, excludes SVS (11) 2.2 V 0.2 0.3 3.0 V 0.2 0.3 1.8 1.6 0.9 0.7 0.8 0.6 MAX 17 UNIT μA μA 16.7 4.9 μA μA μA 4.7 4.8 4.6 μA μA μA (1) (2) (3) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Not applicable for devices with HF crystal oscillator only. Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5-pF load. (4) Low-power mode 2, crystal oscillator test conditions: Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout and SVS are included. CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2), fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz (5) Characterized with a SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are chosen to closely match the required 3.7-pF load. (6) Low-power mode 2, VLO test conditions: Current for watchdog timer clocked by ACLK is included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS are included. CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2), fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz (7) Low-power mode 3, 12-pF crystal, includes SVS test conditions: Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout and SVS are included (SVSHE=1). CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz (8) Low-power mode 3, 3.7-pF crystal, excludes SVS test conditions: Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout is included. SVS disabled (SVSHE = 0). CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz (9) Low-power mode 3, VLO, excludes SVS test conditions: Current for watchdog timer clocked by ACLK is included. RTC disabled (RTCHOLD = 1). Current for brownout is included. SVS is disabled (SVSHE = 0). CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz (10) Low-power mode 4, includes SVS test conditions: Current for brownout and SVS are included (SVSHE = 1). CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4), fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz (11) Low-power mode 4, excludes SVS test conditions: Current for brownout is included. SVS is disabled (SVSHE = 0). CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4), fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz 20 Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) -40 °C 25 °C (1) 60 °C 85°C PARAMETER VCC IIDLE,GroupA Additional idle current if one or more modules from Group A (refer to Table 6-2) are activated in LPM3 or LPM4. 3.0V 0.02 0.33 1.3 μA IIDLE,GroupB Additional idle current if one or more modules from Group B (refer to Table 6-2) are activated in LPM3 or LPM4 3.0V 0.015 0.25 1.0 μA 5.8 TYP MAX TYP MAX TYP MAX TYP MAX UNIT Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER VCC -40 °C TYP 25 °C MAX TYP ILPM3.5,XT12 Low-power mode 3.5, 12-pF crystal, includes SVS (2) (3) (4) 2.2 V 0.4 0.45 3.0 V 0.4 0.45 Low-power mode 3.5, 3.7-pF cyrstal, excludes SVS (2) (5) (6) (also refer to Figure 5-4) 2.2 V 0.2 ILPM3.5,XT3.7 3.0 V ILPM4.5,SVS Low-power mode 4.5, includes SVS (7) (also refer to Figure 5-5) ILPM4.5 Low-power mode 4.5, excludes SVS (8) (also refer to Figure 5-5) (1) (2) (3) (4) (5) (6) (7) (8) 60 °C MAX TYP 85°C MAX TYP 0.5 0.7 0.5 0.7 0.25 0.3 0.45 0.2 0.25 0.3 0.5 2.2 V 0.2 0.2 0.2 0.3 3.0 V 0.2 0.2 0.2 0.3 2.2 V 0.02 0.02 0.02 0.08 3.0 V 0.02 0.02 0.02 0.08 0.7 0.4 MAX 1.2 UNIT μA μA 0.55 0.35 μA μA All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Not applicable for devices with HF crystal oscillator only. Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5-pF load. Low-power mode 3.5, 12-pF crystal, includes SVS test conditions: Current for RTC clocked by XT1 is included. Current for brownout and SVS are included (SVSHE = 1). Core regulator is disabled. PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5), fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz Characterized with a SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are chosen to closely match the required 3.7-pF load. Low-power mode 3.5, 3.7-pF crystal, excludes SVS test conditions: Current for RTC clocked by XT1 is included. Current for brownout is included. SVS is disabled (SVSHE = 0). Core regulator isdisabled. PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5), fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz Low-power mode 4.5, includes SVS test conditions: Current for brownout and SVS are included (SVSHE = 1). Core regulator is disabled. PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5), fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz Low-power mode 4.5, excludes SVS test conditions: Current for brownout is included. SVS is disabled (SVSHE = 0). Core regulator is disabled. PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5), fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 21 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 5.9 www.ti.com Typical Characteristics, Low-Power Mode Supply Currents 2.5 2.5 @ 3.0V, SVS on @ 3.0V, SVS on @ 2.2V, SVS on @ 2.2V, SVS on @ 3.0V, SVS off 2 @ 2.2V, SVS off LPM4 Supply Current [µA] LPM3 Supply Current [µA] 2 1.5 1 0.5 1.5 1 0.5 0 0 -50 0 50 100 -50 0 Temperature [°C] Figure 5-2. LPM3,XT3.7 Supply Current vs Temperature 0.7 @ 3.0V, SVS on @ 2.2V, SVS on @ 3.0V, SVS off @ 2.2V, SVS off @ 3.0V, SVS off @ 2.2V, SVS off LPM4.5 Supply Current [µA] LPM3.5 Supply Current [µA] 0.6 0.5 0.4 0.3 0.2 0.5 0.4 0.3 0.2 0.1 0.1 0 0 -50 0 50 100 Temperature [°C] Figure 5-4. LPM3.5,XT3.7 Supply Current vs Temperature 22 100 Figure 5-3. LPM4,SVS Supply Current vs Temperature 0.7 0.6 50 Temperature [°C] Specifications -50 0 50 100 Temperature [°C] Figure 5-5. LPM4.5 Supply Current vs Temperature Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 5.10 Typical Characteristics, Current Consumption per Module (1) MODULE TEST CONDITIONS REFERENCE CLOCK Timer_A Module input clock MIN TYP MAX UNIT 3 μA/MHz Module input clock 5 μA/MHz eUSCI_A UART mode Module input clock 5.5 μA/MHz eUSCI_A SPI mode Module input clock 3.5 μA/MHz eUSCI_B SPI mode Module input clock 3.5 μA/MHz eUSCI_B I2C mode, 100 kbaud Module input clock 3.5 μA/MHz 32 kHz 100 nA Timer_B RTC_B MPY Only from start to end of operation MCLK 25 μA/MHz AES Only from start to end of operation MCLK 21 μA/MHz CRC Only from start to end of operation MCLK 2.5 μA/MHz (1) For other module currents not listed here, refer to the module specific parameter sections. 5.11 Thermal Packaging Characteristics PARAMETER PARAMETER PACKAGE (1) VALUE UNIT θJA Junction-to-ambient thermal resistance, still air 30.6 °C/W θJC(TOP) Junction-to-case (top) thermal resistance (2) 17.2 °C/W θJB Junction-to-board thermal resistance (3) 7.2 °C/W ΨJB Junction-to-board thermal characterization parameter 7.2 °C/W ΨJT Junction-to-top thermal characterization parameter 0.2 °C/W θJC(BOTTOM) Junction-to-case (bottom) thermal resistance (4) 1.2 °C/W θJA Junction-to-ambient thermal resistance, still air (1) 30.1 °C/W θJC(TOP) Junction-to-case (top) thermal resistance (2) 18.7 °C/W θJB Junction-to-board thermal resistance (3) 6.4 °C/W ΨJB Junction-to-board thermal characterization parameter 6.3 °C/W ΨJT Junction-to-top thermal characterization parameter 0.3 °C/W θJC(BOTTOM) Junction-to-case (bottom) thermal resistance (4) 1.5 °C/W θJA Junction-to-ambient thermal resistance, still air (1) 65.5 °C/W 12.5 °C/W 32.3 °C/W 31.8 °C/W QFN-48 (RGZ) QFN-40 (RHA) (2) θJC(TOP) Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (3) ΨJB Junction-to-board thermal characterization parameter ΨJT Junction-to-top thermal characterization parameter 0.3 °C/W θJC(BOTTOM) Junction-to-case (bottom) thermal resistance (4) N/A °C/W (1) (2) (3) (4) TSSOP-38 (DA) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 23 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 5.12 Timing and Switching Characteristics 5.12.1 Power Supply Sequencing It is recommended to power AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM. Table 5-1. Brownout and Device Reset Power Ramp Requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VVCC_BOR– Brownout power-down level (1) (2) VVCC_BOR+ Brownout power-up level (2) (1) (2) (3) (4) MIN | dDVCC/dt | < 3 V/s (3) | dDVCC/dt | > 300 V/s TYP 0.7 (3) MAX UNIT 1.66 V 0 | dDVCC/dt | < 3 V/s (4) V 0.79 1.68 V In case of a supply voltage brownout scenario, the device supply voltages need to ramp down to the specified brownout power-down level VVCC_BOR- before the voltage is ramped up again to ensure a reliable device startup and performance according to the data sheet including the correct operation of the on-chip SVS module. Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for capacitor CDVCC should limit the slopes accordingly. The brownout levels are measured with a slowly changing supply. With faster slopes the MIN level required to reset the device properly can decrease to 0 V. Use the graph in Figure 5-6 to estimate the VVCC_BOR- level based on the down slope of the supply voltage. After removing VCC the down slope can be estimated based on the current consumption and the capacitance on DVCC: dV/dt = I/C with dV/dt: slope, I: current, C: capacitance. The brownout levels are measured with a slowly changing supply. 2 Brownout power-down level [V] Process-Temp. Corner Case 1 1.5 Typical 1 Process-Temp. Corner Case 2 MIN Limit 0.5 VVCC_BOR- for reliable device startup. 0 1 10 100 1000 10000 100000 Supply Voltage Power Down Slope [V/s] Figure 5-6. Brownout Power-Down Level vs Supply Voltage Down Slope Table 5-2. SVS over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ISVSH,LPM SVSH current consumption, low power modes VSVSH- SVSH power-down level VSVSH+ SVSH power-up level VSVSH_hys SVSH hysteresis tPD,SVSH, AM SVSH propagation delay, active mode 24 Specifications TEST CONDITIONS MIN TYP MAX UNIT 170 300 nA 1.75 1.80 1.85 V 1.77 1.88 1.99 V 120 mV 10 µs 40 dVVcc/dt = -10 mV/µs Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 5.12.2 Reset Timing Table 5-3. Reset Input over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER t(RST) (1) External reset pulse duration on RST TEST CONDITIONS VCC MIN 2.2 V, 3.0 V (1) TYP MAX 2 UNIT µs Not applicable if RST/NMI pin configured as NMI. 5.12.3 Clock Specifications Table 5-4. Low-Frequency Crystal Oscillator, LFXT (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER IVCC.LFXT Current consumption TEST CONDITIONS VCC fOSC = 32768 Hz LFXTBYPASS = 0, LFXTDRIVE = {0}, TA = 25°C, CL,eff = 3.7 pF ESR ~ 44 kΩ 3.0 V 180 nA fOSC = 32768 Hz LFXTBYPASS = 0, LFXTDRIVE = {1}, TA = 25°C, CL,eff = 6 pF ESR ~ 40 kΩ 3.0 V 185 nA fOSC = 32768 Hz LFXTBYPASS = 0, LFXTDRIVE = {2}, TA = 25°C, CL,eff = 9 pF, ESR ~ 40 kΩ 3.0 V 225 nA fOSC = 32768 Hz LFXTBYPASS = 0, LFXTDRIVE = {3}, TA = 25°C, CL,eff = 12.5 pF, ESR ~ 40 kΩ 3.0 V 330 nA 32768 Hz fLFXT LFXT oscillator crystal frequency LFXTBYPASS = 0 DCLFXT LFXT oscillator duty cycle Measured at ACLK, fLFXT = 32768 Hz fLFXT,SW LFXT oscillator logic-level square-wave input frequency LFXTBYPASS = 1 (2) DCLFXT, SW LFXT oscillator logic-level square-wave input duty cycle LFXTBYPASS = 1 (1) (2) (3) MIN TYP 30 (3) 10.5 30 32.768 MAX UNIT 70 % 50 kHz 70 % To improve EMI on the LFXT oscillator, the following guidelines should be observed. • Keep the trace between the device and the crystal as short as possible. • Design a good ground plane around the oscillator pins. • Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT. • Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins. • Use assembly materials and praxis to avoid any parasitic load on the oscillator LFXIN and LFXOUT pins. • If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this datasheet. Duty cycle requirements are defined by DCLFXT, SW. Maximum frequency of operation of the entire device cannot be exceeded. Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 25 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Low-Frequency Crystal Oscillator, LFXT(1) (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Oscillation allowance for LF crystals (4) OALFXT VCC MIN TYP LFXTBYPASS = 0, LFXTDRIVE = {1}, fLFXT = 32768 Hz, CL,eff = 6 pF 210 LFXTBYPASS = 0, LFXTDRIVE = {3}, fLFXT = 32768 Hz, CL,eff = 12.5 pF 300 MAX UNIT kΩ CLFXIN Integrated load capacitance at LFXIN terminal (5) (6) 2 pF CLFXOUT Integrated load capacitance at LFXOUT terminal (5) (6) 2 pF tSTART,LFXT fFault,LFXT (4) (5) (6) (7) (8) (9) 26 Startup time (7) Oscillator fault frequency (8) (9) fOSC = 32768 Hz LFXTBYPASS = 0, LFXTDRIVE = {0}, TA = 25°C, CL,eff = 3.7 pF 3.0 V fOSC = 32768 Hz LFXTBYPASS = 0, LFXTDRIVE = {3}, TA = 25°C, CL,eff = 12.5 pF 3.0 V 800 ms 1000 0 3500 Hz Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application: • For LFXTDRIVE = {0}, CL,ef f = 3.7 pF. • For LFXTDRIVE = {1}, CL,ef f = 6 pF • For LFXTDRIVE = {2}, 6 pF ≤ CL,ef f ≤ 9pF • For LFXTDRIVE = {3}, 9 pF ≤ CL,ef f ≤ 12.5 pF This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT is the total capacitance at the LFXIN and LFXOUT terminals, respectively. Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended effective load capacitance values supported are 3.7 pF, 6 pF, 9pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds additional capacitance, so it must also be considered in the overall capacitance. It is recommended to verify that the recommended effective load capacitance of the selected crystal is met. Includes startup counter of 1024 clock cycles. Frequencies above the MAX specification do not set the fault flag. Frequencies in between the MIN and MAX specification may set the flag. A static condition or stuck at fault condition will set the flag. Measured with logic-level input frequency but also applies to operation with crystals. Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 5-5. High-Frequency Crystal Oscillator, HFXT (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN fOSC = 4 MHz, HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1 (2) TA = 25°C CL,eff = 18 pF, typical ESR, Cshunt IDVCC.HFXT fOSC = 8 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 1 TA = 25°C HFXT oscillator crystal current HF CL,eff = 18 pF, typical ESR, Cshunt mode at typical ESR fOSC = 16 MHz, HFXTBYPASS = 0, HFXTDRIVE = 2, HFFREQ = 2 TA = 25°C CL,eff = 18 pF, typical ESR, Cshunt μA 3.0 V 190 250 HFXTBYPASS = 0, HFFREQ = 1 (2) 4 8 HFXT oscillator crystal frequency, crystal mode HFXTBYPASS = 0, HFFREQ = 2 (3) 8.01 16 HFXTBYPASS = 0, HFFREQ = 3 (3) 16.01 24 HFXT oscillator duty cycle. Measured at SMCLK, fHFXT = 16 MHz HFXTBYPASS = 1, HFFREQ = 0 40 fHFXT,SW HFXTBYPASS = 1, HFFREQ = 1 (4) (3) HFXTBYPASS = 1, HFFREQ = 2 HFXT oscillator logic-level square-wave input duty cycle tSTART,HFXT Startup time (5) (1) (2) (3) (4) (5) % 0.9 4 4.01 8 8.01 16 16.01 24 40 60 MHz (3) (3) SW 60 (4) HFXTBYPASS = 1, HFFREQ = 3 (4) DCHFXT, 50 MHz (4) (3) HFXT oscillator logic-level square-wave input frequency, bypass mode UNIT 120 (3) DCHFXT MAX 75 fOSC = 24 MHz HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3 TA = 25°C CL,eff = 18 pF, typical ESR, Cshunt fHFXT TYP HFXTBYPASS = 1 fOSC = 4 MHz HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1 TA = 25°C, CL,eff = 16 pF 3.0 V fOSC = 24 MHz HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3 TA = 25°C, CL,eff = 16 pF 3.0 V % 1.6 ms 0.6 To improve EMI on the HFXT oscillator the following guidelines should be observed. • Keep the traces between the device and the crystal as short as possible. • Design a good ground plane around the oscillator pins. • Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT. • Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins. • Use assembly materials and praxis to avoid any parasitic load on the oscillator HFXIN and HFXOUT pins. • If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. HFFREQ = {0} is not supported for HFXT crystal mode of operation. Maximum frequency of operation of the entire device cannot be exceeded. When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this datasheet. Duty cycle requirements are defined by DCHFXT, SW. Includes startup counter of 1024 clock cycles. Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 27 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com High-Frequency Crystal Oscillator, HFXT(1) (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT CHFXIN Integrated load capacitance at HFXIN terminaI (6) (7) 2 pF CHFXOUT Integrated load capacitance at HFXOUT terminaI (6) (7) 2 pF fFault,HFXT (6) (7) (8) (9) 28 Oscillator fault frequency (8) (9) 0 800 kHz This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT is the total capacitance at the HFXIN and HFXOUT terminals, respectively. Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended effective load capacitance values supported are 14 pF, 16pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds additional capacitance, so it must also be considered in the overall capacitance. It is recommended to verify that the recommended effective load capacitance of the selected crystal is met. Frequencies above the MAX specification do not set the fault flag. Frequencies in between the MIN and MAX might set the flag. A static condition or stuck at fault condition will set the flag. Measured with logic-level input frequency but also applies to operation with crystals. Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 5-6. DCO over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 1 ±3.5% MHz fDCO1 DCO frequency range 1MHz, trimmed Measured at SMCLK, divide by 1 DCORSEL = 0, DCOFSEL = 0 DCORSEL = 1, DCOFSEL = 0 fDCO2.7 DCO frequency range 2.7MHz, trimmed Measured at SMCLK, divide by 1 DCORSEL = 0, DCOFSEL = 1 2.667 ±3.5% MHz fDCO3.5 DCO frequency range 3.5MHz, trimmed Measured at SMCLK, divide by 1 DCORSEL = 0, DCOFSEL = 2 3.5 ±3.5% MHz fDCO4 DCO frequency range 4MHz, trimmed Measured at SMCLK, divide by 1 DCORSEL = 0, DCOFSEL = 3 fDCO5.3 DCO frequency range 5.3MHz, trimmed Measured at SMCLK, divide by 1 DCORSEL = 0, DCOFSEL = 4 DCORSEL = 1, DCOFSEL = 1 fDCO7 DCO frequency range 7MHz, trimmed Measured at SMCLK, divide by 1 DCORSEL = 0, DCOFSEL = 5 DCORSEL = 1, DCOFSEL = 2 7 ±3.5% MHz fDCO8 DCO frequency range 8MHz, trimmed Measured at SMCLK, divide by 1 DCORSEL = 0, DCOFSEL = 6 DCORSEL = 1, DCOFSEL = 3 8 ±3.5% MHz fDCO16 DCO frequency range 16MHz, trimmed Measured at SMCLK, divide by 1 DCORSEL = 1, DCOFSEL = 4 16 fDCO21 DCO frequency range 21MHz, trimmed Measured at SMCLK, divide by 2 DCORSEL = 1, DCOFSEL = 5 21 fDCO24 DCO frequency range 24MHz, trimmed Measured at SMCLK, divide by 2 DCORSEL = 1, DCOFSEL = 6 24 Duty cycle Measured at SMCLK, divide by 1 No external divide, all DCORSEL/DCOFSEL settings except DCORSEL = 1, DCOFSEL = 5 and DCORSEL = 1, DCOFSEL = 6 DCO jitter Based on fsignal = 10 kHz and DCO used for 12 bit SAR ADC sampling source. This achieves > 74 dB SNR due to jitter i.e. limited by ADC performance. fDCO,DC tDCO, JITTER dfDCO/dT (1) (2) DCO temperature drift (2) 4 48 3.0 V ±3.5% MHz 5.333 ±3.5% MHz ±3.5% MHz (1) ±3.5% MHz (1) ±3.5% (1) MHz 50 52 % 2 3 ns 0.01 %/ºC After a wake-up from LPM1, LPM2, LPM3 or LPM4 the DCO frequency fDCO might exceed the specified frequency range for a few clocks cycles by up to 5% before settling into the specified steady state frequency range. Calculated using the box method: (MAX(-40 to 85ºC) - MIN(-40 to 85ºC)) / MIN(-40 to 85ºC) / (85ºC - (-40ºC)) Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 29 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 5-7. Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS IVLO Current consumption fVLO VLO frequency Measured at ACLK dfVLO/dT VLO frequency temperature drift Measured at ACLK (1) dfVLO/dVCC VLO frequency supply voltage drift Measured at ACLK (2) fVLO,DC Duty cycle Measured at ACLK (1) (2) VCC MIN TYP MAX 100 6 9.4 nA 14 0.2 kHz %/°C 0.7 40 UNIT %/V 50 60 % TYP MAX UNIT 5.4 MHz Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C)) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V) Table 5-8. Module Oscillator (MODOSC) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER IMODOSC Current consumption fMODOSC MODOSC frequency fMODOSC/dT MODOSC frequency temperature drift (1) fMODOSC/dVCC MODOSC frequency supply voltage drift (2) DCMODOSC Duty cycle (1) (2) 30 TEST CONDITIONS VCC MIN Enabled 4.0 Measured at SMCLK, divide by 1 μA 25 40 4.8 0.08 %/℃ 1.4 %/V 50 60 % Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C)) Calculated using the box method: (MAX(1.8V to 3.6V) – MIN(1.8V to 3.6V)) / MIN(1.8V to 3.6V) / (3.6V – 1.8V) Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 5.12.4 Wake-Up Characteristics Table 5-9. Wake-Up Times From Low-Power Modes and Reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS PARAMETER VCC MIN TYP MAX 6 10 tWAKE-UP FRAM (Additional) wake-up time to activate the FRAM in AM if previously disabled by the FRAM controller or from an LPM if immediate activation is selected for wake up tWAKE-UP LPM0 Wake-up time from LPM0 to active mode (1) 2.2 V, 3.0 V tWAKE-UP LPM1 Wake-up time from LPM1 to active mode (1) 2.2 V, 3.0 V 6 tWAKE-UP LPM2 Wake-up time from LPM2 to active mode (1) 2.2 V, 3.0 V 6 tWAKE-UP LPM3 Wake-up time from LPM3 to active mode (1) 2.2 V, 3.0 V 7 tWAKE-UP LPM4 (1) 2.2 V, 3.0 V 2.2 V, 3.0 V SVSHE = 1 2.2 V, 3.0 V SVSHE = 0 Wake-up time from LPM4 to active mode tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode (2) tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode (2) UNIT μs 400 ns + 1.5/fDCO μs μs 10 μs 7 10 μs 250 350 μs 250 350 μs 2.2 V, 3.0 V 1 1.5 ms tWAKE-UP-RST Wake-up time from a RST pin triggered reset to active mode (2) 2.2 V, 3.0 V 250 350 μs tWAKE-UP-BOR Wake-up time from power-up to active mode (2) 2.2 V, 3.0 V 1 1.5 ms (1) (2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first externally observable MCLK clock edge. This time includes the activation of the FRAM during wake up. The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first instruction of the user program is executed. Table 5-10. Typical Wake-Up Charge (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT QWAKE-UP FRAM Charge used for activating the FRAM in AM or during wake-up from LPM0 if previously disabled by the FRAM controller. 15.1 nAs QWAKE-UP LPM0 Charge used for wake-up from LPM0 to active mode (with FRAM active) 4.4 nAs QWAKE-UP LPM1 Charge used for wake-up from LPM1 to active mode (with FRAM active) 15.1 nAs QWAKE-UP LPM2 Charge used for wake-up from LPM2 to active mode (with FRAM active) 15.3 nAs QWAKE-UP LPM3 Charge used for wake-up from LPM3 to active mode (with FRAM active) 16.5 nAs QWAKE-UP LPM4 Charge used for wake-up from LPM4 to active mode (with FRAM active) 16.5 nAs QWAKE-UP LPM3.5 Charge used for wake-up from LPM3.5 to active mode (2) QWAKE-UP LPM4.5 QWAKE-UP-RESET (1) (2) Charge used for wake-up from LPM4.5 to active mode (2) Charge used for reset from RST or BOR event to active mode (2) 76 nAs SVSHE = 1 77 nAs SVSHE = 0 77.5 nAs 75 nAs Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in active mode (for example, for an interrupt service routine). Charge required until start of user code. This does not include the energy required to reconfigure the device. Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 31 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 5.12.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency 10000.00 LPM0 LPM1 Average Wake-up Current [µA] 1000.00 LPM2,XT12 LPM3,XT12 LPM3.5,XT12 100.00 10.00 1.00 0.10 0.001 0.01 0.1 1 10 100 1000 10000 100000 Wake-Up Frequency [Hz] NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt service routine or to reconfigure the device. Figure 5-7. Average LPM Currents vs Wake-up Frequency at 25°C 10000.00 LPM0 LPM1 Average Wake-up Current [µA] 1000.00 LPM2,XT12 LPM3,XT12 LPM3.5,XT12 100.00 10.00 1.00 0.10 0.001 0.01 0.1 1 10 100 1000 10000 100000 Wake-Up Frequency [Hz] NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt service routine or to reconfigure the device. Figure 5-8. Average LPM Currents vs Wake-up Frequency at 85°C 32 Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 5.12.5 Peripherals 5.12.5.1 Digital I/Os Table 5-11. Digital Inputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN 2.2 V 1.2 TYP MAX 1.65 3.0 V 1.65 2.25 2.2 V 0.55 1.00 3.0 V 0.75 1.35 2.2 V 0.44 0.98 3.0 V 0.60 1.30 UNIT VIT+ Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ – VIT–) RPull Pullup or pulldown resistor For pullup: VIN = VSS For pulldown: VIN = VCC CI,dig Input capacitance, digital only port pins VIN = VSS or VCC 3 pF CI,ana Input capacitance, port pins with shared analog VIN = VSS or VCC functions (1) 5 pF Ilkg(Px.y) High-impedance input leakage current (also refer to and ) Refer to notes t(int) External interrupt timing (external trigger pulse duration to set interrupt flag) (4) Ports with interrupt capability (see block diagram and terminal function descriptions). t(RST) External reset pulse duration on RST (5) (1) (2) (3) (4) (5) (2) and (3) 20 35 50 V V V kΩ 2.2 V, 3.0 V -20 2.2 V, 3.0 V 20 ns 2.2 V, 3.0 V 2 µs +20 nA If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ resistor in series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN and/or PJ.5/LFXOUT. The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted. The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled. An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int). Not applicable if RST/NMI pin configured as NMI. Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 33 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 5-12. Digital Outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TYP I(OHmax) = –3 mA (2) VCC – 0.60 VCC I(OHmax) = –2 mA (1) VCC – 0.25 VCC VCC – 0.60 VCC VSS VSS + 0.25 I(OLmax) = 3 mA (2) VSS VSS + 0.60 I(OLmax) = 2 mA (1) VSS VSS + 0.25 VSS VSS + 0.60 2.2 V High-level output voltage 3.0 V I(OHmax) = –6 mA (2) I(OLmax) = 1 mA (1) Low-level output voltage 3.0 V I(OLmax) = 6 mA (2) fPx.y Port output frequency (with load) (3) CL = 20 pF, RL fPort_CLK Clock output frequency (3) ACLK, MCLK, or SMCLK at configured output port CL = 20 pF (5) trise,dig Port output rise time, digital only port pins CL = 20 pF tfall,dig Port output fall time, digital only port pins CL = 20 pF trise,ana Port output rise time, port pins with shared analog functions CL = 20 pF tfall,ana Port output fall time, port pins with shared analog functions CL = 20 pF (1) (2) (3) (4) (5) 34 (4) (5) 2.2 V 16 3.0 V 16 2.2 V 16 3.0 V 16 UNIT V 2.2 V VOL MAX VCC I(OHmax) = –1 mA (1) VOH MIN VCC – 0.25 V MHz MHz 2.2 V 4 15 3.0 V 3 15 2.2 V 4 15 3.0 V 3 15 2.2 V 6 15 3.0 V 4 15 2.2 V 6 15 3.0 V 4 15 ns ns ns ns The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified. The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified. The port can output frequencies at least up to the specified limit - it might support higher frequencies. A resistive divider with 2 × R1 and R1 = 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider. CL = 20 pF is connected from the output to VSS. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 5.12.5.1.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V 30 @ 25°C @ 85°C Low-Level Output Current [mA] Low-Level Output Current [mA] 15 10 5 @ 25°C @ 85°C 20 10 P1.1 P1.1 0 0 0 0.5 1 1.5 2 0 0.5 Low-Level Output Voltage [V] 1 1.5 2 2.5 3 Low-Level Output Voltage [V] C001 C001 VCC = 2.2 V VCC = 3.0 V Figure 5-9. Typical Low-Level Output Current vs Low-Level Output Voltage 0 @ 25°C @ 85°C High-Level Output Current [mA] High-Level Output Current [mA] 0 Figure 5-10. Typical Low-Level Output Current vs Low-Level Output Voltage -5 -10 @ 25°C @ 85°C -10 -20 P1.1 P1.1 -15 -30 0 0.5 1 1.5 2 0 0.5 High-Level Output Voltage [V] 1 1.5 2 2.5 C001 VCC = 2.2 V Figure 5-11. Typical High-Level Output Current vs High-Level Output Voltage C001 VCC = 3.0 V Figure 5-12. Typical High-Level Output Current vs High-Level Output Voltage Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 3 High-Level Output Voltage [V] 35 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 5-13. Pin-Oscillator Frequency, Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER foPx.y (1) TEST CONDITIONS Pin-oscillator frequency VCC MIN TYP MAX UNIT Px.y, CL = 10 pF (1) 3.0 V 1640 kHz (1) 3.0 V 870 kHz Px.y, CL = 20 pF CL is the external load capacitance connected from the output to VSS and includes all parasitic effects such as PCB traces. 1000 fitted fitted 25°C 25°C 85°C Pin Oscillator Frequency [kHz] Pin Oscillator Frequency [kHz] 5.12.5.1.2 Typical Characteristics, Pin-Oscillator Frequency 100 1000 85°C 100 10 100 10 External Load Capacitance (incl. board etc.) [pF] 100 External Load Capacitance (incl. board etc.) [pF] C002 VCC = 2.2 V One output active at a time. Figure 5-13. Typical Oscillation Frequency vs Load Capacitance 36 Specifications C002 VCC = 3.0 V One output active at a time. Figure 5-14. Typical Oscillation Frequency vs Load Capacitance Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 5.12.5.2 Timer_A and Timer_B Table 5-14. Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fTA Timer_A input clock frequency Internal: SMCLK, ACLK External: TACLK Duty cycle = 50% ± 10% 2.2 V, 3.0 V tTA,cap Timer_A capture timing All capture inputs, Minimum pulse duration required for capture 2.2 V, 3.0 V MIN TYP MAX UNIT 16 MHz 20 ns Table 5-15. Timer_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTB Timer_B input clock frequency Internal: SMCLK, ACLK External: TBCLK Duty cycle = 50% ± 10% tTB,cap Timer_B capture timing All capture inputs, Minimum pulse duration required for capture VCC 2.2 V, 3.0 V 2.2 V, 3.0 V MIN TYP MAX UNIT 16 MHz 20 Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated ns 37 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 5.12.5.3 eUSCI Table 5-16. eUSCI (UART Mode) Recommended Operating Conditions PARAMETER feUSCI eUSCI input clock frequency fBITCLK BITCLK clock frequency (equals baud rate in MBaud) CONDITIONS VCC MIN TYP MAX UNIT 16 MHz 4 MHz MAX UNIT Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ± 10% Table 5-17. eUSCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC UCGLITx = 0 2.2 V, 3.0 V UCGLITx = 2 UCGLITx = 3 (1) TYP 5 UCGLITx = 1 UART receive deglitch time (1) tt MIN 30 20 90 35 160 50 220 ns Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch time can limit the maximum useable baud rate. To ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time. Table 5-18. eUSCI (SPI Master Mode) Recommended Operating Conditions PARAMETER feUSCI CONDITIONS VCC MIN TYP MAX UNIT 16 MHz Internal: SMCLK, ACLK Duty cycle = 50% ± 10% eUSCI input clock frequency Table 5-19. eUSCI (SPI Master Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see note PARAMETER TEST CONDITIONS VCC MIN TYP MAX (1) ) UNIT tSTE,LEAD STE lead time, STE active to clock UCSTEM = 1, UCMODEx = 01 or 10 1 tSTE,LAG STE lag time, Last clock to STE inactive UCSTEM = 1, UCMODEx = 01 or 10 1 tSTE,ACC STE access time, STE active to SIMO data out UCSTEM = 0, UCMODEx = 01 or 10 2.2 V, 3.0 V 60 ns tSTE,DIS STE disable time, STE inactive to SOMI high impedance UCSTEM = 0, UCMODEx = 01 or 10 2.2 V, 3.0 V 60 ns tSU,MI SOMI input data setup time tHD,MI SOMI input data hold time tVALID,MO SIMO output data valid time (2) UCLK edge to SIMO valid, CL = 20 pF tHD,MO SIMO output data hold time (3) CL = 20 pF (1) (2) (3) 38 2.2 V 35 3.0 V 35 2.2 V 0 3.0 V 0 UCxCLK cycles ns ns 2.2 V 10 3.0 V 10 2.2 V 0 3.0 V 0 ns ns fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)). For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), refer to the SPI parameters of the attached slave. Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing diagrams in Figure 5-15 and Figure 5-16. Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in Figure 5-15 and Figure 5-16. Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tHD,MO tSTE,ACC tSTE,DIS tVALID,MO SIMO Figure 5-15. SPI Master Mode, CKPH = 0 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tHD,MO tSTE,ACC tVALID,MO tSTE,DIS SIMO Figure 5-16. SPI Master Mode, CKPH = 1 Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 39 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 5-20. eUSCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note PARAMETER TEST CONDITIONS tSTE,LEAD STE lead time, STE active to clock tSTE,LAG STE lag time, Last clock to STE inactive tSTE,ACC STE access time, STE active to SOMI data out tSTE,DIS STE disable time, STE inactive to SOMI high impedance tSU,SI SIMO input data setup time tHD,SI SIMO input data hold time tVALID,SO SOMI output data valid time (2) UCLK edge to SOMI valid, CL = 20 pF tHD,SO SOMI output data hold time (3) CL = 20 pF (1) (2) (3) 40 VCC MIN 2.2 V 45 3.0 V 40 2.2 V 0 3.0 V 0 TYP (1) ns 45 3.0 V 40 2.2 V 40 3.0 V 35 4 3.0 V 4 2.2 V 7 3.0 V 7 35 35 3.0 V 0 ns ns 3.0 V 0 ns ns 2.2 V 2.2 V UNIT ns 2.2 V 2.2 V ) MAX ns ns fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)). For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave. Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing diagrams in Figure 5-17 and Figure 5-18. Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in Figure 5-17 and Figure 5-18. Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tSU,SI tLOW/HIGH tHD,SI SIMO tHD,SO tSTE,ACC tSTE,DIS tVALID,SO SOMI Figure 5-17. SPI Slave Mode, CKPH = 0 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tHD,SI tSU,SI SIMO tHD,SO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 5-18. SPI Slave Mode, CKPH = 1 Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 41 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 5-21. eUSCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-19) PARAMETER TEST CONDITIONS feUSCI eUSCI input clock frequency fSCL SCL clock frequency VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ± 10% 2.2 V, 3.0 V fSCL = 100 kHz UNIT 16 MHz 400 kHz 4.0 tHD,STA Hold time (repeated) START tSU,STA Setup time for a repeated START tHD,DAT Data hold time 2.2 V, 3.0 V 0 ns tSU,DAT Data setup time 2.2 V, 3.0 V 100 ns tSU,STO fSCL > 100 kHz fSCL = 100 kHz fSCL > 100 kHz fSCL = 100 kHz Setup time for STOP fSCL > 100 kHz Pulse duration of spikes suppressed by input filter tSP 2.2 V, 3.0 V 0 MAX 2.2 V, 3.0 V 2.2 V, 3.0 V µs 0.6 4.7 µs 0.6 4.0 µs 0.6 UCGLITx = 0 50 250 ns UCGLITx = 1 25 125 ns 12.5 62.5 ns UCGLITx = 2 2.2 V, 3.0 V UCGLITx = 3 6.3 31.5 UCCLTOx = 1 tTIMEOUT Clock low timeout UCCLTOx = 2 2.2 V, 3.0 V UCCLTOx = 3 tSU,STA tHD,STA tHD,STA ns 27 ms 30 ms 33 ms tBUF SDA tLOW tHIGH tSP SCL tSU,DAT tSU,STO tHD,DAT Figure 5-19. I2C Mode Timing 42 Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 5.12.5.4 ADC Table 5-22. 12-Bit ADC, Power Supply and Input Range Conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER V(Ax) Analog input voltage range TEST CONDITIONS (1) I(ADC12_B) Operating supply current into singleAVCC plus DVCC terminals (2) ended mode I(ADC12_B) Operating supply current into differential AVCC plus DVCC terminals (2) mode MIN All ADC12 analog input pins Ax NOM 0 MAX UNIT AVCC V 3.0 V 145 185 (3) fADC12CLK = MODCLK, ADC12ON = 1, ADC12PWRMD = 0, ADC12DIF = 0, REFON = 0, ADC12SHTx = 0, ADC12DIV = 0 2.2 V 140 180 3.0 V 175 225 (3) fADC12CLK = MODCLK, ADC12ON = 1, ADC12PWRMD = 0, ADC12DIF = 1, REFON = 0, ADC12SHTx= 0, ADC12DIV = 0 2.2 V 170 220 2.2 V 10 15 pF >2 V 0.5 4 kΩ <2 V 1 10 kΩ CI Input capacitance Only one terminal Ax can be selected at one time RI Input MUX ON resistance 0 V ≤ V(Ax) ≤ AVCC (1) (2) (3) VCC µA µA The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results. The internal reference supply current is not included in current consumption parameter I(ADC12_B). Approximately 60% (typical) of the total current into the AVCC and DVCC terminal is from AVCC. Table 5-23. 12-Bit ADC, Timing Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN 0.45 fADC12CLK Frequency for specified performance For specified performance of ADC12 linearity parameters with ADC12PWRMD = 0, If ADC12PWRMD = 1, the maximum is 1/4 of the value shown here fADC12CLK Frequency for reduced performance Linearity parameters have reduced performance fADC12OSC Internal oscillator (1) ADC12DIV = 0, fADC12CLK = fADC12OSC from MODCLK tCONVERT Conversion time See tADC12OFF Time ADC must be off before can be turned on again Note: tADC12OFF must be met to make sure that tADC12ON time holds tSample (1) (2) (3) (4) Sampling time RS = 400 Ω, RI = 4 kΩ, CI = 15 pF, Cpext= 8 pF UNIT 5.4 MHz kHz 5.4 MHz 3.5 µs (2) (3) Turn on settling time of the ADC 4.8 2.6 External fADC12CLK from ACLK, MCLK, or SMCLK, ADC12SSEL ≠ 0 tADC12ON MAX 32.768 4 REFON = 0, Internal oscillator, fADC12CLK = fADC12OSC from MODCLK, ADC12WINC = 0 TYP 100 100 (4) ns ns 1 µs The ADC12OSC is sourced directly from MODOSC inside the UCS. 14 x ADC12DIV x 1/fADC12CLK , if ADC12WINC=1 then 15 x ADC12DIV x 1/fADC12CLK The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already settled. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB: tsample = ln(2n+2) x (RS + RI) x (CI + Cpext), where n = ADC resolution =12, RS= external source resistance, Cpext = external parasitic capacitance. Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 43 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 5-24. 12-Bit ADC, Linearity Parameters with External Reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution Number of no missing code output-code bits EI Integral linearity error (INL) for differential input 1.2 V ≤ VR+ - VR-≤ AVCC ±1.8 LSB EI Integral linearity error (INL) for single ended inputs 1.2 V ≤ VR+ - VR-≤ AVCC ±2.2 LSB ED Differential linearity error (DNL) +1.0 LSB EO Offset error (2) EG,ext (3) Gain error 12 bits -0.99 ADC12VRSEL = 0x2 or 0x4 without TLV calibration, TLV calibration data can be used to improve the parameter (4) ±0.5 ±1.5 mV With external voltage reference without internal buffer (ADC12VRSEL = 0x2 or 0x4) without TLV calibration, TLV calibration data can be used to improve the parameter (4), VR+ = 2.5 V, VR- = AVSS ±0.8 ±2.5 LSB ±1 ±20 LSB With external voltage reference without internal buffer (ADC12VRSEL = 0x2 or 0x4) without TLV calibration, TLV calibration data can be used to improve the parameter (4), VR+ = 2.5 V, VR- = AVSS ±1.4 ±3.5 LSB With external voltage reference with internal buffer (ADC12VRSEL = 0x3), VR+ = 2.5 V, VR- = AVSS ±1.4 ±21.0 LSB With external voltage reference with internal buffer (ADC12VRSEL = 0x3), VR+ = 2.5 V, VR- = AVSS ET,ext (1) (2) (3) (4) Total unadjusted error See Table 5-26 and Table 5-32 electrical sections for more information on internal reference performance and refer to the application report Designing With the MSP430FR59xx and MSP430FR58xx ADC (SLAA624) for details on optimizing ADC performance for your application with the choice of internal versus external reference. Offset is measured as the input voltage (at which ADC output transitions from 0 to 1) minus 0.5 LSB. Offset increases as IR drop increases when VR- is AVSS. For details, see the Device Descriptor Table section in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide (SLAU367). Table 5-25. 12-Bit ADC, Dynamic Performance for Differential Inputs with External Reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN TYP SNR Signal-to-noise PARAMETER VR+ = 2.5 V, VR- = AVSS 68 71 dB ENOB Effective number of bits (2) VR+ = 2.5 V, VR- = AVSS 10.7 11.2 bits (1) (2) TEST CONDITIONS MAX UNIT See Table 5-26 and Table 5-32 electrical sections for more information on internal reference performance and refer to the application report Designing With the MSP430FR59xx and MSP430FR58xx ADC (SLAA624) for details on optimizing ADC performance for your application with the choice of internal versus external reference. ENOB = (SINAD-1.76)/6.02 Table 5-26. 12-Bit ADC, Dynamic Performance for Differential Inputs with Internal Reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ENOB (1) (2) 44 Effective number of bits TEST CONDITIONS (2) VR+ = 2.5 V, VR- = AVSS MIN TYP 10.3 10.7 MAX UNIT Bits See Table 5-32 electrical section for more information on internal reference performance and refer to the application report Designing With the MSP430FR59xx and MSP430FR58xx ADC (SLAA624) for details on optimizing ADC performance for your application with the choice of internal versus external reference. ENOB = (SINAD-1.76)/6.02 Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 5-27. 12-Bit ADC, Dynamic Performance for Single-Ended Inputs with External Reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER SNR ENOB (1) (2) TEST CONDITIONS Signal-to-noise Effective number of bits (2) MIN TYP VR+ = 2.5 V, VR- = AVSS 64 68 MAX UNIT dB VR+ = 2.5 V, VR- = AVSS 10.2 10.7 bits See Table 5-28 and Table 5-32 electrical sections for more information on internal reference performance and refer to the application report Designing With the MSP430FR59xx and MSP430FR58xx ADC (SLAA624) for details on optimizing ADC performance for your application with the choice of internal versus external reference. ENOB = (SINAD-1.76)/6.02 Table 5-28. 12-Bit ADC, Dynamic Performance for Single-Ended Inputs with Internal Reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ENOB (1) (2) TEST CONDITIONS Effective number of bits (2) VR+ = 2.5 V, VR- = AVSS MIN TYP 9.4 10.4 MAX UNIT bits See Table 5-32 electrical section for more information on internal reference performance and refer to the application report Designing With the MSP430FR59xx and MSP430FR58xx ADC (SLAA624) for details on optimizing ADC performance for your application with the choice of internal versus external reference. ENOB = (SINAD-1.76)/6.02 Table 5-29. 12-Bit ADC, Dynamic Performance with 32.768-kHz Clock over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ENOB Effective number of bits (1) MIN TYP MAX 10 UNIT bits ENOB = (SINAD-1.76)/6.02 Typical Temperature Sensor Voltage – mV (1) TEST CONDITIONS Reduced performance with fADC12CLK from ACLK LFXT 32.768 kHz, VR+ = 2.5 V, VR- = AVSS 950 900 850 800 750 700 650 600 550 500 -40 -20 0 20 40 60 80 Ambient Temperature – °C Figure 5-20. Typical Temperature Sensor Voltage Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 45 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 5-30. 12-Bit ADC, Temperature Sensor and Built-In V1/2 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VSENSOR See (1) (2) ADC12ON = 1, ADC12TCMAP=1, TA = 0°C TCSENSOR See (2) ADC12ON = 1, ADC12TCMAP = 1 tSENSOR(sample) Sample time required if ADCTCMAP = 1 and channel MAX-1 is selected (3) ADC12ON = 1, ADC12TCMAP = 1, Error of conversion result ≤ 1 LSB V1/2 AVCC voltage divider for ADC12BATMAP = 1 on MAX input channel ADC12ON = 1, ADC12BATMAP = 1 IV Current for battery monitor during sample time ADC12ON = 1, ADC12BATMAP = 1 1/2 tV 1/2 (sample) (1) (2) (3) (4) Sample time required if ADC12BATMAP = 1 and channel MAX is selected (4) ADC12ON = 1, ADC12BATMAP = 1 MIN TYP MAX 700 mV 2.5 mV/°C 30 47.5 UNIT µs 50 52.5 % 38 63 µA 1.7 µs The temperature sensor offset can be as much as ±30°C. A single-point calibration is recommended in order to minimize the offset error of the built-in temperature sensor. The device descriptor structure contains calibration values for 30°C ± 3°C and 85°C ± 3°C for each of the available reference voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR * (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can be computed from the calibration values for higher accuracy. The typical equivalent impedance of the sensor is 250 kΩ. The sample time required includes the sensor-on time tSENSOR(on). The on-time tV1/2(on) is included in the sampling time tV1/2(sample); no additional on time is needed. Table 5-31. 12-Bit ADC, External Reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VR+ Positive external reference voltage input VeREF+ or VeREF- based on ADC12VRSEL bit VR+ > VR- 1.2 AVCC V VR- Negative external reference voltage input VeREF+ or VeREF- based on ADC12VRSEL bit VR+ > VR- 0 1.2 V (VR+ VR-) Differential external reference voltage input VR+ > VR- 1.2 AVCC V 1.2 V ≤ VeREF+≤ VAVCC, VeREF- = 0 V fADC12CLK = 5 MHz, ADC12SHTx = 1h, ADC12DIF = 0, ADC12PWRMD = 0 ±10 µA 1.2 V ≤ VeREF+≤ VAVCC , VeREF- = 0 V fADC12CLK = 5 MHz, ADC12SHTx = 8h, ADC12DIF = 0, ADC12PWRMD = 01 ±2.5 µA 1.2 V ≤ VeREF+≤ VAVCC, VeREF- = 0 V fADC12CLK = 5 MHz, ADC12SHTx = 1h, ADC12DIF = 1, , ADC12PWRMD = 0 ±20 uA 1.2 V ≤ VeREF+≤ VAVCC , VeREF- = 0 V fADC12CLK = 5 MHz, ADC12SHTx = 8h, ADC12DIF = 1, , ADC12PWRMD = 1 ±5 uA IVeREF+ IVeREF- Static input current singled ended input mode IVeREF+ IVeREF- Static input current differential input mode IVeREF+ Peak input current with single-ended input 0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 0 1.5 mA IVeREF+ Peak input current with differential input 0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 1 3 mA CVeREF+/- Capacitance at VeREF+ or VeREF- terminal See note (1) (2) 46 (2) 10 µF The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. Two decoupling capacitors, 10µF and 470nF, should be connected to VeREF to decouple the dynamic current required for an external reference source if it is used for the ADC12_B. See also the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide (SLAU367). Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 5.12.5.5 Reference Table 5-32. REF, Built-In Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VREF+ TEST CONDITIONS Positive built-in reference voltage output (1) REFVSEL = {1} for 2.0 V REFON = 1 2.2 V 2.0 ±1.5% REFVSEL = {0} for 1.2 V REFON = 1 1.8 V 1.2 ±1.8% VREF ADC BUF_INT buffer TA = 25 °C , ADC ON, REFVSEL = {0}, offset (2) REFON = 1, REFOUT=0 VOS_BUF_EXT VREF ADC BUF_EXT buffer offset (3) AVCC(min) AVCC minimum voltage, Positive built-in reference active Operating supply current into AVCC terminal (4) From 0.1 Hz to 10 Hz, REFVSEL = {0} 110 V µV -12 +12 mV TA = 25 °C, REFVSEL = {0} , REFOUT=1, REFON = 1 or ADC ON -12 +12 mV REFVSEL = {0} for 1.2 V 1.8 REFVSEL = {1} for 2.0 V 2.2 REFVSEL = {2} for 2.5 V 2.7 V REFON = 1 3V 8 15 ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2}, ADC12PWRMD = 0, 3V 225 355 ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2}, ADC12PWRMD = 0 3V 1030 1660 ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2}, ADC12PWRMD = 1 3V 120 185 ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2}, ADC12PWRMD = 1 3V 545 895 ADC OFF, REFON=1, REFOUT=1, REFVSEL = {0, 1, 2} 3V 1085 1780 VREF maximum load current, VREF+ terminal REFVSEL = {0, 1, 2}, AVCC = AVCC(min) for each reference level, REFON = REFOUT = 1 ΔVout/ΔIo (VREF+) Load-current regulation, VREF+ terminal REFVSEL = {0, 1, 2}, IO(VREF+) = +10 µA or -1000 µA AVCC = AVCC(min) for each reference level, REFON = REFOUT = 1 CVREF+/- Capacitance at VREF+ and VREF- terminals REFON = REFOUT = 1 TCREF+ Temperature coefficient of built-in reference REFVSEL = {0, 1, 2}, REFON = REFOUT = 1, TA = -40 to 85 °C (5) 18 PSRR_DC Power supply rejection ratio (dc) AVCC = AVCC (min) - AVCC(max), TA = 25°C REFVSEL = {0, 1, 2}, REFON = REFOUT = 1 120 PSRR_AC Power supply rejection ratio (ac) dAVCC= 0.1 V at 1 kHz 3.0 tSETTLE Settling time of reference voltage (6) AVCC = AVCC (min) - AVCC(max) REFVSEL = {0, 1, 2}, REFON = 0 → 1 75 (2) (3) (4) (5) (6) UNIT 600 IO(VREF+) (1) MAX 2.5 ±1.5% VOS_BUF_INT IREF+_ADC_BUF TYP 2.7 V RMS noise at VREF Operating supply current into AVCC terminal (4) MIN REFVSEL = {2} for 2.5 V REFON = 1 Noise IREF+ VCC -1000 +10 µA µA µA 2500 µV/mA 0 100 pF 50 ppm/K 400 µV/V mV/V 80 µs Internal reference noise affects ADC performance when ADC uses internal reference. Refer to the application report Designing With the MSP430FR59xx and MSP430FR58xx ADC (SLAA624) for details on optimizing ADC performance for your application with the choice of internal versus external reference. Buffer offset affects ADC gain error and thus total unadjusted error. Buffer offset affects ADC gain error and thus total unadjusted error. The internal reference current is supplied through terminal AVCC. Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)). The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 47 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 5.12.5.6 Comparator Table 5-33. Comparator_E over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN CEPWRMD = 00, CEON = 1, CERSx = 00 (fast) IAVCC_COMP Comparator operating supply current into AVCC, excludes reference resistor ladder CEPWRMD = 01, CEON = 1, CERSx = 00 (medium) CEPWRMD = 10, CEON = 1, CERSx = 00 (slow), TA = 30°C 2.2 V, 3.0 V TYP MAX 11 20 9 17 µA 0.5 CEPWRMD = 10, CEON = 1, CERSx = 00 (slow), TA = 85°C IAVCC_REF VREF Quiescent current of resistor ladder into AVCC, including REF module current Reference voltage level CEREFLx = 01, CERSx = 10, REFON = 0, CEON = 0, CEREFACC = 0 CEREFLx = 01, CERSx = 10, REFON = 0, CEON = 0, CEREFACC = 1 VOFFSET Input offset voltage CIN Input capacitance RSIN Series input resistance tPD Propagation delay, response time 1.3 2.2 V, 3.0 V 12 15 5 7 µA CERSx = 11, CEREFLx = 01, CEREFACC = 0 1.8 V 1.17 1.2 1.23 CERSx = 11, CEREFLx = 10, CEREFACC = 0 2.2 V 1.92 2.0 2.08 CERSx = 11, CEREFLx = 11, CEREFACC = 0 2.7 V 2.40 2.5 2.60 CERSx = 11, CEREFLx = 01, CEREFACC = 1 1.8 V 1.10 1.2 1.245 CERSx = 11, CEREFLx = 10, CEREFACC = 1 2.2 V 1.90 2.0 2.08 CERSx = 11, CEREFLx = 11, CEREFACC = 1 2.7 V 2.35 2.5 2.60 Common mode input range VIC 0 VCC-1 CEPWRMD = 00 -32 32 CEPWRMD = 01 -32 32 CEPWRMD = 10 -30 30 CEPWRMD = 00 or CEPWRMD = 01 9 CEPWRMD = 10 9 ON - switch closed OFF - switch open 1 tPD,filter tEN_CMP 48 Comparator enable time Specifications V V mV pF 3 50 kΩ MΩ CEPWRMD = 00, CEF = 0, Overdrive ≥ 20 mV 260 330 CEPWRMD = 01, CEF = 0, Overdrive ≥ 20 mV 350 460 CEPWRMD = 10, CEF = 0, Overdrive ≥ 20 mV Propagation delay with filter active UNIT ns 15 µs 700 1000 ns CEPWRMD = 00 or 01, CEF = 1, Overdrive ≥ 20 mV, CEFDLY = 01 1.0 1.8 CEPWRMD = 00 or 01, CEF = 1, Overdrive ≥ 20 mV, CEFDLY = 10 2.0 3.5 CEPWRMD = 00 or 01, CEF = 1, Overdrive ≥ 20 mV, CEFDLY = 11 4.0 7.0 CEON = 0 → 1, VIN+, VIN- from pins, Overdrive ≥ 20 mV, CEPWRMD = 00 0.9 1.5 CEON = 0 → 1, VIN+, VIN- from pins, Overdrive ≥ 20 mV, CEPWRMD = 01 0.9 1.5 CEON = 0 → 1, VIN+, VIN- from pins, Overdrive ≥ 20 mV, CEPWRMD = 10 15 100 CEPWRMD = 00 or 01, CEF = 1, Overdrive ≥ 20 mV, CEFDLY = 00 µs µs Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Comparator_E (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER tEN_CMP_VREF tEN_CMP_RL VCE_REF TYP MAX CEON = 0 → 1, CEREFLX = 10, CERSx = 11, REFON = 0, Overdrive ≥ 20 mV, CEPWRMD = 00 TEST CONDITIONS VCC MIN 1 2 CEON = 0 → 1, CEREFLX = 10, CERSx = 11, REFON = 0, Overdrive ≥ 20 mV, CEPWRMD = 01 1 2 10 50 CEON = 0 → 1, CEREFLX = 10, CERSx = 11, REFON = 0, Overdrive ≥ 20 mV, Comparator and reference CEPWRMD = 10 ladder and reference CEON = 0 → 1, CEREFLX = 10, CERSx = 10, voltage enable time REFON = 0, CEREF0 = CEREF1 = 0x0F, Overdrive ≥ 20 mV, CEPWRMD = 00 µs 2 5 CEON = 0 → 1, CEREFLX = 10, CERSx = 10, REFON = 0, CEREF0 = CEREF1 = 0x0F, Overdrive ≥ 20 mV, CEPWRMD = 01 2 5 CEON = 0 → 1, CEREFLX = 10, CERSx = 10, REFON = 0, CEREF0 = CEREF1 = 0x0F, Overdrive ≥ 20 mV, CEPWRMD = 10 10 50 CEON = 0 → 1, CEREFLX = 10, CERSx = 10, REFON = 1, CEREF0 = CEREF1 = 0x0F, Overdrive ≥ 20 mV, CEPWRMD = 00 1 2 CEON = 0 → 1, CEREFLX = 10, CERSx = 10, Comparator and reference REFON = 1, CEREF0 = CEREF1 = 0x0F, ladder enable time Overdrive ≥ 20 mV, CEPWRMD = 01 1 2 CEON = 0 → 1, CEREFLX = 10, CERSx = 10, REFON = 1, CEREF0 = CEREF1 = 0x0F, Overdrive ≥ 20 mV, CEPWRMD = 10 10 50 VIN × (n+1) /32 VIN × (n+1.1) /32 Reference voltage for a given tap UNIT VIN × (n+0.9) /32 VIN = reference into resistor ladder, n = 0 to 31 µs V 5.12.5.7 FRAM Table 5-34. FRAM Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Data retention duration TYP MAX 15 Read and write endurance tRetention MIN 10 TJ = 25°C 100 TJ = 70°C 40 TJ = 85°C 10 Specifications Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated UNIT cycles years 49 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 5.13 Emulation and Debug Table 5-35. JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 40 UNIT IJTAG Supply current adder when JTAG active (but not clocked) 2.2 V, 3.0 V 100 μA fSBW Spy-Bi-Wire input frequency 2.2 V, 3.0 V 0 10 MHz tSBW,Low Spy-Bi-Wire low clock pulse duration 2.2 V, 3.0 V 0.04 15 μs tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1) 2.2 V, 3.0 V 110 μs tSBW,Rst Spy-Bi-Wire return to normal operation time 15 100 μs 2.2 V 0 16 MHz 3.0 V 0 16 MHz 2.2 V, 3.0 V 20 fTCK TCK input frequency - 4-wire JTAG (2) Rinternal Internal pulldown resistance on TEST 50 kΩ fTCLK TCLK/MCLK frequency during JTAG access, no FRAM access (limited by fSYSTEM) 16 MHz tTCLK,Low/High TCLK low or high clock pulse duration, no FRAM access 25 ns fTCLK,FRAM TCLK/MCLK frequency during JTAG access, including FRAM access (limited by fSYSTEM with no FRAM wait states) 4 MHz tTCLK,FRAM,Low/Hig TCLK low or high clock pulse duration, including FRAM accesses 35 100 ns h (1) (2) 50 Tools accessing the Spy-Bi-Wire interface need to wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge. fTCK may be restricted to meet the timing requirements of the module selected. Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 6 Detailed Description 6.1 Overview The Texas Instruments MSP430FR59xx family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals. The architecture, combined with seven low-power modes is optimized to achieve extended battery life for example in portable measurement applications. The devices features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The MSP430FR59xx devices are microcontroller configurations with up to five 16-bit timers, Comparator, universal serial communication interfaces (eUSCI) supporting UART, SPI, and I2C, hardware multiplier, AES accelerator, DMA, real-time clock module with alarm capabilities, up to 40 I/O pins, and an highperformance 12-bit analog-to-digital converter (ADC). 6.2 CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 51 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 6.3 www.ti.com Operating Modes The MSP430 has one active mode and seven software selectable low-power modes of operation. An interrupt event can wake up the device from low-power modes LPM0 through LPM4, service the request, and restore back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption. Table 6-1. Operating Modes Mode AM Active, FRAM Off (1) Active Maximum System Clock Typical Current Consumption, TA = 25°C 16 MHz 103 µA/MHz 65 µA/MHz LPM0 LPM1 LPM2 LPM3 LPM4 LPM3.5 LPM4.5 CPU Off (2) CPU Off Standby Standby Off RTC only 16 MHz 16 MHz 50 kHz 50 kHz 0 (3) 50 kHz 70 µA at 1 MHz 35 µA at 1 MHz 0.7 µA 0.4 µA 0.3 µA 0.25 µA 0.2 µA 0.02 µA 250 µs 1000 µs Shutdown with SVS Shutdown without SVS 0 (3) Typical Wake-up Time N/A instant 6 µs 6 µs 7 µs 7 µs 250 µs Wake-Up Events N/A all all LF I/O Comp LF I/O Comp I/O Comp RTC I/O I/O CPU on FRAM on off (1) off off off off off reset reset standby (or off (1)) off off off off off off High-Frequency Peripherals available available available off off off reset reset Low-Frequency Peripherals available available available available available (4) off RTC reset Unclocked Peripherals (5) available available available available available (4) available (4) reset reset MCLK on off off off off off off off optional (6) optional (6) optional (6) off off off off off ACLK on on on on on off off off Full Retention yes yes yes yes yes yes no SVS always always always optional (7) optional (7) optional (7) optional (7) Brownout always always always always always always always SMCLK (1) (2) (3) (4) (5) (6) (7) (8) (9) 52 no on (8) off (9) always FRAM disabled in FRAM controller Disabling the FRAM through the FRAM controller allows the application to lower the LPM current consumption but the wake-up time increases as soon as FRAM is accessed (for example, to fetch an interrupt vector). For a non-FRAM wake-up (for example, DMA transfer to RAM) the wake-up is not delayed. All clocks disabled See Section 6.3.1, which describes the use of peripherals in LPM3 and LPM4. "Unclocked peripherals" are peripherals that do not require a clock source to operate; for example, the comparator and REF, or the eUSCI when operated as an SPI slave. Controlled by SMCLKOFF. Activated SVS (SVSHE = 1) results in higher current consumption. SVS is not included in typical current consumption. SVSHE = 1 SVSHE = 0 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com 6.3.1 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Peripherals in LPM3 and LPM4 Most peripherals can be activated to be operational in LPM3 if clocked by ACLK. Some modules are operational in LPM4, because they do not require a clock to operate (for example, the comparator). Activating a peripheral in LPM3 or LPM4 increases the current consumption due to its active supply current contribution but also due to an additional idle current. To limit the idle current adder, certain peripherals are grouped together. To achieve optimal current consumption, use modules within one group and limit the number of groups with active modules. The grouping is shown in Table 6-2. Modules not listed in this table are either already included in the standard LPM3 current consumption or cannot be used in LPM3 or LPM4. The idle current adder is very small at room temperature (25°C) but increases at high temperatures (85°C); refer to the IIDLE current parameters in the electrical characteristics section for details.. Table 6-2. Peripheral Groups Group A Group B Timer TA1 Timer TA0 Timer TA2 Timer TA3 Timer TB0 Comparator eUSCI_A0 ADC12_B eUSCI_A1 REF_A eUSCI_B0 6.4 Interrupt Vector Table and Signatures The interrupt vectors, the power-up start address and signatures are located in the address range 0FFFFh to 0FF80h. Table 6-3 summarizes the content of this address range. The power-up start address or reset vector is located at 0FFFFh to 0FFFEh. It contains the 16-bit address pointing to the start address of the application program. The interrupt vectors start at 0FFFDh extending to lower addresses. Each vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if enabled by the corresponding signature). The signatures are located at 0FF80h extending to higher addresses. Signatures are evaluated during device start-up. Starting from address 0FF88h extending to higher addresses a JTAG password can programmed. The password can extend into the interrupt vector locations using the interrupt vector addresses as additional bits for the password. Refer to the chapter "System Resets, Interrupts, and Operating Modes, System Control Module (SYS)" in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide (SLAU367) for details. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 53 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 6-3. Interrupt Sources, Flags, Vectors, and Signatures INTERRUPT SOURCE System Reset Power-Up, Brownout, Supply Supervisor External Reset RST Watchdog Timeout (Watchdog mode) WDT, FRCTL MPU, CS, PMM Password Violation FRAM uncorrectable bit error detection MPU segment violation Software POR, BOR System NMI Vacant Memory Access JTAG Mailbox FRAM access time error FRAM bit error detection MPU segment violation (1) (2) (3) (4) 54 INTERRUPT FLAG SVSHIFG PMMRSTIFG WDTIFG WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW UBDIFG MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG PMMPORIFG, PMMBORIFG (SYSRSTIV) (1) (2) VMAIFG JMBNIFG, JMBOUTIFG ACCTEIFG CBDIFG, UBDIFG MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG (SYSSNIV) (1) (3) SYSTEM INTERRUPT WORD ADDRESS PRIORITY Reset 0FFFEh highest (Non)maskable 0FFFCh User NMI External NMI Oscillator Fault NMIIFG, OFIFG (SYSUNIV) (1) (3) (Non)maskable 0FFFAh Comparator_E CEIFG, CEIIFG (CEIV) (1) Maskable 0FFF8h TB0 TB0CCR0.CCIFG Maskable 0FFF6h TB0 TB0CCR1.CCIFG ... TB0CCR6.CCIFG, TB0CTL.TBIFG (TB0IV) (1) Maskable 0FFF4h Watchdog Timer (Interval Timer Mode) WDTIFG Maskable 0FFF2h eUSCI_A0 Receive or Transmit UCA0IFG: UCRXIFG, UCTXIFG (SPI mode) UCA0IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode) (UCA0IV) (1) Maskable 0FFF0h eUSCI_B0 Receive or Transmit UCB0IFG: UCRXIFG, UCTXIFG (SPI mode) UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode) (UCB0IV) (1) Maskable 0FFEEh ADC12_B ADC12IFG0 to ADC12IFG31 ADC12LOIFG, ADC12INIFG, ADC12HIIFG, ADC12RDYIFG, ADC21OVIFG, ADC12TOVIFG (ADC12IV) (1) (4) Maskable 0FFECh TA0 TA0CCR0.CCIFG Maskable 0FFEAh TA0 TA0CCR1.CCIFG, TA0CCR2.CCIFG, TA0CTL.TAIFG (TA0IV) (1) Maskable 0FFE8h eUSCI_A1 Receive or Transmit UCA1IFG: UCRXIFG, UCTXIFG (SPI mode) UCA1IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode) (UCA1IV) (1) Maskable 0FFE6h DMA DMA0CTL.DMAIFG, DMA1CTL.DMAIFG, DMA2CTL.DMAIFG (DMAIV) (1) Maskable 0FFE4h TA1 TA1CCR0.CCIFG Maskable 0FFE2h Multiple source flags A reset is generated if the CPU tries to fetch instructions from within peripheral space (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot disable it. Only on devices with ADC, otherwise reserved. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-3. Interrupt Sources, Flags, Vectors, and Signatures (continued) INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS TA1 TA1CCR1.CCIFG, TA1CCR2.CCIFG, TA1CTL.TAIFG (TA1IV) (1) Maskable 0FFE0h I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV) (1) Maskable 0FFDEh TA2 TA2CCR0.CCIFG Maskable 0FFDCh TA2 TA2CCR1.CCIFG TA2CTL.TAIFG (TA2IV) (1) Maskable 0FFDAh I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV) (1) Maskable 0FFD8h TA3 TA3CCR0.CCIFG Maskable 0FFD6h TA3 TA3CCR1.CCIFG TA3CTL.TAIFG (TA3IV) (1) Maskable 0FFD4h I/O Port P3 P3IFG.0 to P3IFG.7 (P3IV) (1) Maskable 0FFD2h I/O Port P4 P4IFG.0 to P4IFG.2 (P4IV) (5) Maskable 0FFD0h RTC_B RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV) (5) Maskable 0FFCEh AES AESRDYIFG Maskable 0FFCCh PRIORITY lowest 0FFCAh Reserved (6) Reserved ⋮ 0FF8Ch IP Encapsulation Signature2 (6) 0FF8Ah IP Encapsulation Signature1 (6) (8) 0FF88h BSL Signature2 0FF86h Signatures (7) (5) (6) (7) (8) BSL Signature1 0FF84h JTAG Signature2 0FF82h JTAG Signature1 0FF80h Multiple source flags May contain a JTAG password required to enable JTAG access to the device. Signatures are evaluated during device start-up. See the "System Resets, Interrupts, and Operating Modes, System Control Module (SYS)" chapter in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide (SLAU367) for details. Must not contain 0AAAAh if used as JTAG password and IP encapsulation functionality is not desired. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 55 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 6.5 www.ti.com Memory Organization Table 6-4 summarizes the memory organization for all device variants. Table 6-4. Memory Organization (1) MSP430FR59x9 MSP430FR59x8 MSP430FR59x7 63 KB 00FFFFh-00FF80h 013FFFh-004400h 47 KB 00FFFFh-00FF80h 00FF7Fh-004400h 32 KB 00FFFFh-00FF80h 00FF7Fh-008000h RAM 2 KB 0023FFh-001C00h 2 KB 0023FFh-001C00h 1 KB 001FFFh-001C00h Device Descriptor Info (TLV) (FRAM) 256 B 001AFFh-001A00h 256 B 001AFFh-001A00h 256 B 001AFFh-001A00h Info A 128 B 0019FFh-001980h 128 B 0019FFh-001980h 128 B 0019FFh-001980h Info B 128 B 00197Fh-001900h 128 B 00197Fh-001900h 128 B 00197Fh-001900h Info C 128 B 0018FFh-001880h 128 B 0018FFh-001880h 128 B 0018FFh-001880h Info D 128 B 00187Fh-001800h 128 B 00187Fh-001800h 128 B 00187Fh-001800h BSL 3 512 B 0017FFh-001600h 512 B 0017FFh-001600h 512 B 0017FFh-001600h BSL 2 512 B 0015FFh-001400h 512 B 0015FFh-001400h 512 B 0015FFh-001400h BSL 1 512 B 0013FFh-001200h 512 B 0013FFh-001200h 512 B 0013FFh-001200h BSL 0 512 B 0011FFh-001000h 512 B 0011FFh-001000h 512 B 0011FFh-001000h 4 KB 000FFFh-0h 4 KB 000FFFh-0h 4 KB 000FFFh-0h Memory (FRAM) Main: interrupt vectors and signatures Main: code memory Information memory (FRAM) Bootstrap loader (BSL) memory (ROM) Size Peripherals (1) 6.6 Total Size All address space not listed is considered vacant memory. Bootstrap Loader (BSL) The BSL enables users to program the FRAM or RAM using a UART serial interface (FRxxxx devices) or an I2C interface (FRxxxx1 devices). Access to the device memory through the BSL is protected by an user-defined password. Use of the BSL requires four pins as shown in Table 6-5. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319). Table 6-5. BSL Pin Requirements and Functions 56 Detailed Description DEVICE SIGNAL BSL FUNCTION RST/NMI/SBWTDIO Entry sequence signal TEST/SBWTCK Entry sequence signal P2.0 Devices with UART BSL (FRxxxx): Data transmit P2.1 Devices with UART BSL (FRxxxx): Data receive P1.6 Devices with I2C BSL (FRxxxx1): Data P1.7 Devices with I2C BSL (FRxxxx1): Clock VCC Power supply VSS Ground supply Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com 6.7 6.7.1 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 JTAG Operation JTAG Standard Interface The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430 development tools and device programmers. The JTAG pin requirements are shown in Table 66. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320). Table 6-6. JTAG Pin Requirements and Functions 6.7.2 DEVICE SIGNAL DIRECTION FUNCTION PJ.3/TCK IN JTAG clock input PJ.2/TMS IN JTAG state control PJ.1/TDI/TCLK IN JTAG data input, TCLK input PJ.0/TDO OUT JTAG data output TEST/SBWTCK IN Enable JTAG pins RST/NMI/SBWTDIO IN External reset VCC Power supply VSS Ground supply Spy-Bi-Wire Interface In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire interface pin requirements are shown in Table 6-7. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320). Table 6-7. Spy-Bi-Wire Pin Requirements and Functions DEVICE SIGNAL DIRECTION FUNCTION TEST/SBWTCK IN Spy-Bi-Wire clock input RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input and output VCC Power supply VSS Ground supply Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 57 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 6.8 www.ti.com FRAM Memory The FRAM memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or insystem by the CPU. Features of the FRAM memory include: • Ultra-low-power ultra-fast-write nonvolatile memory • Byte and word access capability • Programmable wait state generation • Error correction coding (ECC) NOTE Wait States For MCLK frequencies > 8 MHz, wait states must be configured following the flow described in the "Wait State Control" section of the "FRAM Controller (FRCTRL)" chapter in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide (SLAU367). For important software design information regarding FRAM including but not limited to partitioning the memory layout according to application-specific code, constant, and data space requirements, the use of FRAM to optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to maximize application robustness by protecting the program code against unintended write accesses, see the application report MSP430™ FRAM Technology – How To and Best Practices (SLAA628). 6.9 Memory Protection Unit Including IP Encapsulation The FRAM memory can be protected from inadvertent CPU execution, read access, or write access by the MPU. Features of the MPU include: • IP encapsulation with programmable boundaries in steps of 1KB (prevents reads from "outside"; for example, JTAG or non-IP software). • Main memory partitioning is programmable up to three segments in steps of 1KB. • Each segment's access rights can be individually selected (main and information memory). • Access violation flags with interrupt capability for easy servicing of access violations. 58 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 6.10 Peripherals Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be handled using all instructions. For complete module descriptions, see the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide (SLAU367). 6.10.1 Digital I/O There are up to four 8-bit I/O ports implemented: • All individual I/O bits are independently programmable. • Any combination of input, output, and interrupt conditions is possible. • Programmable pullup or pulldown on all ports. • Edge-selectable interrupt and LPM3.5 and LPM4.5 wakeup input capability is available for all ports. • Read and write access to port control registers is supported by all instructions. • Ports can be accessed byte-wise or word-wise in pairs. • Capacitive Touch functionality is supported on all pins of ports P1, P2, P3, P4, and PJ. • No cross-currents during start-up. NOTE Configuration of Digital I/Os After BOR Reset To prevent any cross currents during start-up of the device, all port pins are high-impedance with Schmitt triggers, and their module functions disabled. To enable the I/O functionality after a BOR reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For details, refer to the "Configuration After Reset" section of the "Digital I/O" chapter in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide (SLAU367). 6.10.2 Oscillator and Clock System (CS) The clock system includes support for a 32-kHz watch-crystal oscillator XT1 (LF), an internal very-lowpower low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements of both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources. The clock system module provides the following clock signals: • Auxiliary clock (ACLK). ACLK can be sourced from a 32-kHz watch crystal (LFXT1), the internal lowfrequency oscillator (VLO), or a digital external low-frequency (<50 kHz) clock source. • Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced from a high-frequency crystal (HFXT2), the internal digitally controlled oscillator DCO, a 32-kHz watch crystal (LFXT1), the internal low-frequency oscillator (VLO), or a digital external clock source. • Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by same sources made available to MCLK. 6.10.3 Power Management Module (PMM) The primary functions of the PMM are: • • • Supply regulated voltages to the core logic Supervise voltages that are connected to the device (at DVCC pins) Give reset signals to the device during power-on and power-off Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 59 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.10.4 Hardware Multiplier (MPY) The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module supports signed multiplication, unsigned multiplication, signed multiply-and-accumulate, and unsigned multiply-and-accumulate operations. 6.10.5 Real-Time Clock (RTC_B) (Only MSP430FR596x and MSP430FR594x) The RTC_B module contains an integrated real-time clock (RTC). It integrates an internal calendar that compensates for months with less than 31 days and includes leap year correction. The RTC_B also supports flexible alarm functions and offset-calibration hardware. RTC operation is available in LPM3.5 modes to minimize power consumption. 6.10.6 Watchdog Timer (WDT_A) The primary function of the WDT_A module is to perform a controlled system restart if a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. Table 6-8. WDT_A Clocks WDTSSELx NORMAL OPERATION (WATCHDOG AND INTERVAL TIMER MODE) 00 SMCLK 01 ACLK 10 VLOCLK 11 LFMODCLK 6.10.7 System Module (SYS) The SYS module manages many of the system functions within the device. These include power on reset (POR) and power up clear (PUC) handling, NMI source selection and management, reset interrupt vector generators, bootstrap loader (BSL) entry mechanisms, and configuration management (device descriptors). The SYS module also includes a data exchange mechanism through JTAG called a JTAG mailbox that can be used in the application. Table 6-9. System Module Interrupt Vector Registers 60 INTERRUPT VECTOR REGISTER ADDRESS INTERRUPT EVENT VALUE SYSRSTIV, System Reset 019Eh No interrupt pending 00h Brownout (BOR) 02h RSTIFG RST/NMI (BOR) 04h PMMSWBOR software BOR (BOR) 06h Detailed Description LPMx.5 wakeup (BOR) 08h Security violation (BOR) 0Ah Reserved 0Ch SVSHIFG SVSH event (BOR) 0Eh Reserved 10h Reserved 12h PMMSWPOR software POR (POR) 14h WDTIFG watchdog timeout (PUC) 16h WDTPW password violation (PUC) 18h PRIORITY Highest Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-9. System Module Interrupt Vector Registers (continued) INTERRUPT VECTOR REGISTER ADDRESS INTERRUPT EVENT FRCTLPW password violation (PUC) 1Ah Uncorrectable FRAM bit error detection (PUC) 1Ch Peripheral area fetch (PUC) 1Eh PMMPW PMM password violation (PUC) 20h MPUPW MPU password violation (PUC) 22h CSPW CS password violation (PUC) 24h MPUSEGPIFG encapsulated IP memory segment violation (PUC) 26h MPUSEGIIFG information memory segment violation (PUC) 28h MPUSEG1IFG segment 1 memory violation (PUC) 2Ah MPUSEG2IFG segment 2 memory violation (PUC) 2Ch MPUSEG3IFG segment 3 memory violation (PUC) 2Eh ACCTEIFG access time error (PUC) SYSSNIV, System NMI SYSUNIV, User NMI (1) 019Ch 019Ah VALUE (1) PRIORITY 30h Reserved 32h to 3Eh No interrupt pending 00h SVS low-power reset entry 02h Uncorrectable FRAM bit error detection 04h Reserved 06h MPUSEGPIFG encapsulated IP memory segment violation 08h MPUSEGIIFG information memory segment violation 0Ah MPUSEG1IFG segment 1 memory violation 0Ch MPUSEG2IFG segment 2 memory violation 0Eh MPUSEG3IFG segment 3 memory violation 10h VMAIFG Vacant memory access 12h JMBINIFG JTAG mailbox input 14h JMBOUTIFG JTAG mailbox output 16h Correctable FRAM bit error detection 18h Reserved 1Ah to 1Eh No interrupt pending 00h NMIFG NMI pin 02h OFIFG oscillator fault 04h Reserved 06h Reserved 08h Reserved 0Ah to 1Eh Lowest Highest Lowest Highest Lowest Indicates incorrect wait state settings. 6.10.8 DMA Controller The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12_B conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 61 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 6-10. DMA Trigger Assignments (1) (1) TRIGGER CHANNEL 0 CHANNEL 1 0 DMAREQ DMAREQ CHANNEL 2 DMAREQ 1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG 2 TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG 3 TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG 4 TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG 5 TA2CCR0 CCIFG TA2CCR0 CCIFG TA2CCR0 CCIFG 6 TA3CCR0 CCIFG TA3CCR0 CCIFG TA3CCR0 CCIFG 7 TB0CCR0 CCIFG TB0CCR0 CCIFG TB0CCR0 CCIFG 8 TB0CCR2 CCIFG TB0CCR2 CCIFG TB0CCR2 CCIFG Reserved 9 Reserved Reserved 10 Reserved Reserved Reserved 11 AES Trigger 0 AES Trigger 0 AES Trigger 0 12 AES Trigger 1 AES Trigger 1 AES Trigger 1 13 AES Trigger 2 AES Trigger 2 AES Trigger 2 14 UCA0RXIFG UCA0RXIFG UCA0RXIFG 15 UCA0TXIFG UCA0TXIFG UCA0TXIFG 16 UCA1RXIFG UCA1RXIFG UCA1RXIFG 17 UCA1TXIFG UCA1TXIFG UCA1TXIFG 18 UCB0RXIFG (SPI) UCB0RXIFG0 (I2C) UCB0RXIFG (SPI) UCB0RXIFG0 (I2C) UCB0RXIFG (SPI) UCB0RXIFG0 (I2C) 19 UCB0TXIFG (SPI) UCB0TXIFG0 (I2C) UCB0TXIFG (SPI) UCB0TXIFG0 (I2C) UCB0TXIFG (SPI) UCB0TXIFG0 (I2C) 20 UCB0RXIFG1 (I2C) UCB0RXIFG1 (I2C) UCB0RXIFG1 (I2C) 21 UCB0TXIFG1 (I2C) UCB0TXIFG1 (I2C) UCB0TXIFG1 (I2C) 22 UCB0RXIFG2 (I2C) UCB0RXIFG2 (I2C) UCB0RXIFG2 (I2C) 23 UCB0TXIFG2 (I2C) UCB0TXIFG2 (I2C) UCB0TXIFG2 (I2C) 24 UCB0RXIFG3 (I2C) UCB0RXIFG3 (I2C) UCB0RXIFG3 (I2C) 25 UCB0TXIFG3 (I2C) UCB0TXIFG3 (I2C) UCB0TXIFG3 (I2C) 26 ADC12 end of conversion ADC12 end of conversion ADC12 end of conversion 27 Reserved Reserved Reserved 28 Reserved Reserved Reserved 29 MPY ready MPY ready MPY ready 30 DMA2IFG DMA0IFG DMA1IFG 31 DMAE0 DMAE0 DMAE0 If a reserved trigger source is selected, no trigger is generated. 6.10.9 Enhanced Universal Serial Communication Interface (eUSCI) The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. The eUSCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, and IrDA. The eUSCI_Bn module provides support for SPI (3 pin or 4 pin) and I2C. Two eUSCI_A modules and one eUSCI_B module are implemented. 62 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 6.10.10 TA0, TA1 TA0 and TA1 are 16-bit timers and counters (Timer_A type) with three capture/compare registers each. Each can support multiple captures or compares, PWM outputs, and interval timing. Each has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-11. TA0 Signal Connections INPUT PORT PIN P1.2 MODULE INPUT SIGNAL TA0CLK TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK P1.2 TA0CLK INCLK P1.6 TA0.0 CCI0A P2.3 TA0.0 CCI0B DVSS GND P1.0 P1.1 (1) DEVICE INPUT SIGNAL MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer N/A N/A OUTPUT PORT PIN P1.6 CCR0 TA0 TA0.0 P2.3 DVCC VCC TA0.1 CCI1A P1.0 COUT (internal) CCI1B ADC12(internal) (1) ADC12SHSx = {1} DVSS GND DVCC VCC TA0.2 CCI2A ACLK (internal) CCI2B DVSS GND DVCC VCC CCR1 TA1 TA0.1 P1.1 CCR2 TA2 TA0.2 Only on devices with ADC. Table 6-12. TA1 Signal Connections INPUT PORT PIN P1.1 MODULE INPUT SIGNAL TA1CLK TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK P1.1 TA1CLK INCLK P1.7 TA1.0 CCI0A P2.4 TA1.0 CCI0B DVSS GND P1.2 P1.3 (1) DEVICE INPUT SIGNAL MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer N/A N/A OUTPUT PORT PIN P1.7 CCR0 TA0 TA1.0 P2.4 DVCC VCC TA1.1 CCI1A P1.2 COUT (internal) CCI1B ADC12(internal) (1) ADC12SHSx = {4} DVSS GND DVCC VCC TA1.2 CCI2A ACLK (internal) CCI2B DVSS GND DVCC VCC CCR1 TA1 TA1.1 P1.3 CCR2 TA2 TA1.2 Only on devices with ADC. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 63 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.10.11 TA2, TA3 TA2 and TA3 are 16-bit timers and counters (Timer_A type) with two capture/compare registers each and with internal connections only. Each can support multiple captures or compares, PWM outputs, and interval timing. Each has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-13. TA2 Signal Connections DEVICE INPUT SIGNAL MODULE INPUT NAME COUT (internal) TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK From Capacitive Touch IO 0 (internal) INCLK TA3 CCR0 output (internal) CCI0A ACLK (internal) CCI0B DVSS GND DVCC VCC From Capacitive Touch IO 0 (internal) CCI1A COUT (internal) CCI1B DVSS GND DVCC VCC (1) MODULE BLOCK MODULE OUTPUT SIGNAL Timer N/A DEVICE OUTPUT SIGNAL TA3 CCI0A input CCR0 TA0 ADC12(internal) (1) ADC12SHSx = {5} CCR1 TA1 Only on devices with ADC Table 6-14. TA3 Signal Connections DEVICE INPUT SIGNAL MODULE INPUT NAME COUT (internal) TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK From Capacitive Touch IO 1 (internal) INCLK TA2 CCR0 output (internal) CCI0A ACLK (internal) CCI0B DVSS GND DVCC VCC From Capacitive Touch IO 1 (internal) CCI1A COUT (internal) CCI1B DVSS GND DVCC VCC (1) Only on devices with ADC 64 Detailed Description MODULE BLOCK MODULE OUTPUT SIGNAL Timer N/A DEVICE OUTPUT SIGNAL TA2 CCI0A input CCR0 TA0 ADC12(internal) (1) ADC12SHSx = {6} CCR1 TA1 Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 6.10.12 TB0 TB0 is a 16-bit timer and counter (Timer_B type) with seven capture/compare registers. It can support multiple captures or compares, PWM outputs, and interval timing. It has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 6-15. TB0 Signal Connections INPUT PORT PIN P2.0 DEVICE INPUT SIGNAL MODULE INPUT SIGNAL TB0CLK TBCLK ACLK (internal) ACLK SMCLK (internal) SMCLK P2.0 TB0CLK INCLK P2.1 TB0.0 CCI0A P2.5 TB0.0 CCI0B DVSS P1.4 P1.5 DVCC VCC TB0.1 CCI1A COUT (internal) CCI1B DVSS GND DVCC VCC TB0.2 CCI2A ACLK (internal) CCI2B DVSS GND DVCC VCC P3.4 TB0.3 CCI3A P1.6 TB0.3 CCI3B DVSS GND DVCC VCC P3.5 TB0.4 CCI4A P1.7 TB0.4 CCI4B DVSS GND P3.6 P4.4 P3.7 P2.0 (1) GND DVCC VCC TB0.5 CCI5A TB0.5 CCI5B DVSS GND DVCC VCC TB0.6 CCI6A TB0.6 CCI6B DVSS GND DVCC VCC MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer N/A N/A OUTPUT PORT PIN P2.1 P2.5 CCR0 TB0 TB0.0 ADC12 (internal) (1) ADC12SHSx = {2} P1.4 P2.6 CCR1 TB1 TB0.1 ADC12 (internal) (1) ADC12SHSx = {3} P1.5 CCR2 TB2 TB0.2 P2.2 P3.4 CCR3 TB3 TB0.3 P1.6 P3.5 CCR4 TB4 TB0.4 P1.7 P3.6 CCR5 TB5 TB0.5 P4.4 P3.7 CCR6 TB6 TB0.6 P2.0 Only on devices with ADC. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 65 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.10.13 ADC12_B The ADC12_B module supports fast 12-bit analog-to-digital conversions with differential and single-ended inputs. The module implements a 12-bit SAR core, sample select control, reference generator, and a conversion result buffer. A window comparator with a lower and upper limit allows CPU-independent result monitoring with three window comparator interrupt flags. The external trigger sources available are summarized in Table 6-16. The available multiplexing between internal and external analog inputs is listed in Table 6-17. Table 6-16. ADC12_B Trigger Signal Connections ADC12SHSx BINARY DECIMAL CONNECTED TRIGGER SOURCE 000 0 Software (ADC12SC) 001 1 TA0 CCR1 output 010 2 TB0 CCR0 output 011 3 TB0 CCR1 output 100 4 TA1 CCR1 output 101 5 TA2 CCR1 output 110 6 TA3 CCR1 output 111 7 Reserved (DVSS) Table 6-17. ADC12_B External and Internal Signal Mapping CONTROL BIT IN ADC12CTL3 REGISTER EXTERNAL ADC INPUT (CONTROL BIT = 0) ADC12BATMAP A31 Battery Monitor ADC12TCMAP A30 Temperature Sensor ADC12CH0MAP A29 N/A (1) ADC12CH1MAP A28 N/A (1) ADC12CH2MAP A27 N/A (1) ADC12CH3MAP A26 N/A (1) (1) INTERNAL ADC INPUT (CONTROL BIT = 1) N/A = No internal signal is available on this device. 6.10.14 Comparator_E The primary function of the Comparator_E module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals. 6.10.15 CRC16 The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard. 6.10.16 AES256 Accelerator The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit, 192-bit, or 256-bit keys according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware. 6.10.17 True Random Seed The Device Descriptor Information (TLV) section contains a 128-bit true random seed that can be used to implement a deterministic random number generator. 66 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 6.10.18 Shared Reference (REF) The REF module is responsible for generation of all critical reference voltages that can be used by the various analog peripherals in the device. 6.10.19 Embedded Emulation Embedded Emulation Module (EEM) The EEM supports real-time in-system debugging. The S version of the EEM that is implemented on all devices has the following features: • Three hardware triggers or breakpoints on memory access • One hardware trigger or breakpoint on CPU register write access • Up to four hardware triggers can be combined to form complex triggers or breakpoints • One cycle counter • Clock control on module level EnergyTrace++™ Technology The devices implement circuitry to support EnergyTrace++ technology. The EnergyTrace++ technology allows you to observe information about the internal states of the microcontroller. These states include the CPU Program Counter (PC), the ON or OFF status of the peripherals and the system clocks (regardless of the clock source), and the low-power mode currently in use. These states can always be read by a debug tool, even when the microcontroller sleeps in LPMx.5 modes. The activity of the following modules can be observed: • MPY is calculating. • WDT is counting. • RTC is counting. • ADC: a sequence, sample, or conversion is active. • REF: REFBG or REFGEN active and BG in static mode. • COMP is on. • AES is encrypting or decrypting. • eUSCI_A0 is transferring (receiving or transmitting) data. • eUSCI_A1 is transferring (receiving or transmitting) data. • eUSCI_B0 is transferring (receiving or transmitting) data. • TB0 is counting. • TA0 is counting. • TA1 is counting. • TA2 is counting. • TA3 is counting. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 67 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.10.20 Peripheral File Map For complete module register descriptions, see the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide (SLAU367). Table 6-18. Peripherals 68 MODULE NAME BASE ADDRESS OFFSET ADDRESS RANGE Special Functions (see Table 6-19) 0100h 000h-01Fh PMM (see Table 6-20) 0120h 000h-01Fh FRAM Control (see Table 6-21) 0140h 000h-00Fh CRC16 (see Table 6-22) 0150h 000h-007h Watchdog (see Table 6-23) 015Ch 000h-001h CS (see Table 6-24) 0160h 000h-00Fh SYS (see Table 6-25) 0180h 000h-01Fh Shared Reference (see Table 6-26) 01B0h 000h-001h Port P1, P2 (see Table 6-27) 0200h 000h-01Fh Port P3, P4 (see Table 6-28) 0220h 000h-01Fh Port PJ (see Table 6-29) 0320h 000h-01Fh TA0 (see Table 6-30) 0340h 000h-02Fh TA1 (see Table 6-31) 0380h 000h-02Fh TB0 (see Table 6-32) 03C0h 000h-02Fh TA2 (see Table 6-33) 0400h 000h-02Fh Capacitive Touch IO 0 (see Table 6-34) 0430h 000h-00Fh TA3 (see Table 6-35) 0440h 000h-02Fh Capacitive Touch IO 1 (see Table 6-36) 0470h 000h-00Fh Real-Time Clock (RTC_B) (see Table 6-37) 04A0h 000h-01Fh 32-Bit Hardware Multiplier (see Table 6-38) 04C0h 000h-02Fh DMA General Control (see Table 6-39) 0500h 000h-00Fh DMA Channel 0 (see Table 6-39) 0510h 000h-00Fh DMA Channel 1 (see Table 6-39) 0520h 000h-00Fh DMA Channel 2 (see Table 6-39) 0530h 000h-00Fh MPU Control (see Table 6-40) 05A0h 000h-00Fh eUSCI_A0 (see Table 6-41) 05C0h 000h-01Fh eUSCI_A1 (see Table 6-42) 05E0h 000h-01Fh eUSCI_B0 (see Table 6-43) 0640h 000h-02Fh ADC12_B (see Table 6-44) 0800h 000h-09Fh Comparator_E (see Table 6-45) 08C0h 000h-00Fh AES (see Table 6-46) 09C0h 000h-00Fh Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-19. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h Table 6-20. PMM Registers (Base Address: 0120h) REGISTER DESCRIPTION REGISTER OFFSET PMM Control 0 PMMCTL0 00h PMM interrupt flags PMMIFG 0Ah PM5 Control 0 PM5CTL0 10h Table 6-21. FRAM Control Registers (Base Address: 0140h) REGISTER DESCRIPTION REGISTER OFFSET FRAM control 0 FRCTL0 00h General control 0 GCCTL0 04h General control 1 GCCTL1 06h Table 6-22. CRC16 Registers (Base Address: 0150h) REGISTER DESCRIPTION REGISTER OFFSET CRC data input CRC16DI 00h CRC data input reverse byte CRCDIRB 02h CRC initialization and result CRCINIRES 04h CRC result reverse byte CRCRESR 06h Table 6-23. Watchdog Registers (Base Address: 015Ch) REGISTER DESCRIPTION Watchdog timer control REGISTER WDTCTL OFFSET 00h Table 6-24. CS Registers (Base Address: 0160h) REGISTER DESCRIPTION REGISTER OFFSET CS control 0 CSCTL0 00h CS control 1 CSCTL1 02h CS control 2 CSCTL2 04h CS control 3 CSCTL3 06h CS control 4 CSCTL4 08h CS control 5 CSCTL5 0Ah CS control 6 CSCTL6 0Ch Table 6-25. SYS Registers (Base Address: 0180h) REGISTER DESCRIPTION REGISTER OFFSET System control SYSCTL 00h JTAG mailbox control SYSJMBC 06h JTAG mailbox input 0 SYSJMBI0 08h JTAG mailbox input 1 SYSJMBI1 0Ah JTAG mailbox output 0 SYSJMBO0 0Ch JTAG mailbox output 1 SYSJMBO1 0Eh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 69 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 6-25. SYS Registers (Base Address: 0180h) (continued) REGISTER DESCRIPTION REGISTER OFFSET User NMI vector generator SYSUNIV 1Ah System NMI vector generator SYSSNIV 1Ch Reset vector generator SYSRSTIV 1Eh Table 6-26. Shared Reference Registers (Base Address: 01B0h) REGISTER DESCRIPTION Shared reference control REGISTER REFCTL OFFSET 00h Table 6-27. Port P1, P2 Registers (Base Address: 0200h) REGISTER DESCRIPTION REGISTER OFFSET Port P1 input P1IN 00h Port P1 output P1OUT 02h Port P1 direction P1DIR 04h Port P1 pullup/pulldown enable P1REN 06h Port P1 selection 0 P1SEL0 0Ah Port P1 selection 1 P1SEL1 0Ch Port P1 interrupt vector word P1IV 0Eh Port P1 complement selection P1SELC 16h Port P1 interrupt edge select P1IES 18h Port P1 interrupt enable P1IE 1Ah Port P1 interrupt flag P1IFG 1Ch Port P2 input P2IN 01h Port P2 output P2OUT 03h Port P2 direction P2DIR 05h Port P2 pullup/pulldown enable P2REN 07h Port P2 selection 0 P2SEL0 0Bh Port P2 selection 1 P2SEL1 0Dh Port P2 complement selection P2SELC 17h Port P2 interrupt vector word P2IV 1Eh Port P2 interrupt edge select P2IES 19h Port P2 interrupt enable P2IE 1Bh Port P2 interrupt flag P2IFG 1Dh Table 6-28. Port P3, P4 Registers (Base Address: 0220h) REGISTER DESCRIPTION REGISTER OFFSET Port P3 input P3IN 00h Port P3 output P3OUT 02h Port P3 direction P3DIR 04h Port P3 pullup/pulldown enable P3REN 06h Port P3 selection 0 P3SEL0 0Ah Port P3 selection 1 P3SEL1 0Ch Port P3 interrupt vector word P3IV 0Eh Port P3 complement selection P3SELC 16h Port P3 interrupt edge select P3IES 18h Port P3 interrupt enable P3IE 1Ah Port P3 interrupt flag P3IFG 1Ch 70 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-28. Port P3, P4 Registers (Base Address: 0220h) (continued) REGISTER DESCRIPTION REGISTER OFFSET Port P4 input P4IN 01h Port P4 output P4OUT 03h Port P4 direction P4DIR 05h Port P4 pullup/pulldown enable P4REN 07h Port P4 selection 0 P4SEL0 0Bh Port P4 selection 1 P4SEL1 0Dh Port P4 complement selection P4SELC 17h Port P4 interrupt vector word P4IV 1Eh Port P4 interrupt edge select P4IES 19h Port P4 interrupt enable P4IE 1Bh Port P4 interrupt flag P4IFG 1Dh Table 6-29. Port J Registers (Base Address: 0320h) REGISTER DESCRIPTION REGISTER OFFSET Port PJ input PJIN 00h Port PJ output PJOUT 02h Port PJ direction PJDIR 04h Port PJ pullup/pulldown enable PJREN 06h Port PJ selection 0 PJSEL0 0Ah Port PJ selection 1 PJSEL1 0Ch Port PJ complement selection PJSELC 16h Table 6-30. TA0 Registers (Base Address: 0340h) REGISTER DESCRIPTION REGISTER OFFSET TA0 control TA0CTL 00h Capture/compare control 0 TA0CCTL0 02h Capture/compare control 1 TA0CCTL1 04h Capture/compare control 2 TA0CCTL2 06h Capture/compare control 3 TA0CCTL3 08h Capture/compare control 4 TA0CCTL4 0Ah TA0 counter register TA0R 10h Capture/compare register 0 TA0CCR0 12h Capture/compare register 1 TA0CCR1 14h Capture/compare register 2 TA0CCR2 16h Capture/compare register 3 TA0CCR3 18h Capture/compare register 4 TA0CCR4 1Ah TA0 expansion register 0 TA0EX0 20h TA0 interrupt vector TA0IV 2Eh Table 6-31. TA1 Registers (Base Address: 0380h) REGISTER DESCRIPTION REGISTER OFFSET TA1 control TA1CTL 00h Capture/compare control 0 TA1CCTL0 02h Capture/compare control 1 TA1CCTL1 04h Capture/compare control 2 TA1CCTL2 06h TA1 counter register TA1R 10h Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 71 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 6-31. TA1 Registers (Base Address: 0380h) (continued) REGISTER DESCRIPTION REGISTER OFFSET Capture/compare register 0 TA1CCR0 12h Capture/compare register 1 TA1CCR1 14h Capture/compare register 2 TA1CCR2 16h TA1 expansion register 0 TA1EX0 20h TA1 interrupt vector TA1IV 2Eh Table 6-32. TB0 Registers (Base Address: 03C0h) REGISTER DESCRIPTION REGISTER OFFSET TB0 control TB0CTL 00h Capture/compare control 0 TB0CCTL0 02h Capture/compare control 1 TB0CCTL1 04h Capture/compare control 2 TB0CCTL2 06h Capture/compare control 3 TB0CCTL3 08h Capture/compare control 4 TB0CCTL4 0Ah Capture/compare control 5 TB0CCTL5 0Ch Capture/compare control 6 TB0CCTL6 0Eh TB0 register TB0R 10h Capture/compare register 0 TB0CCR0 12h Capture/compare register 1 TB0CCR1 14h Capture/compare register 2 TB0CCR2 16h Capture/compare register 3 TB0CCR3 18h Capture/compare register 4 TB0CCR4 1Ah Capture/compare register 5 TB0CCR5 1Ch Capture/compare register 6 TB0CCR6 1Eh TB0 expansion register 0 TB0EX0 20h TB0 interrupt vector TB0IV 2Eh Table 6-33. TA2 Registers (Base Address: 0400h) REGISTER DESCRIPTION REGISTER OFFSET TA2 control TA2CTL 00h Capture/compare control 0 TA2CCTL0 02h Capture/compare control 1 TA2CCTL1 04h TA2 register TA2R 10h Capture/compare register 0 TA2CCR0 12h Capture/compare register 1 TA2CCR1 14h TA2 expansion register 0 TA2EX0 20h TA2 interrupt vector TA2IV 2Eh Table 6-34. Capacitive Touch IO 0 Registers (Base Address: 0430h) REGISTER DESCRIPTION Capacitive Touch IO 0 control REGISTER CAPTIO0CTL OFFSET 0Eh Table 6-35. TA3 Registers (Base Address: 0440h) REGISTER DESCRIPTION REGISTER OFFSET TA3 control TA3CTL 00h Capture/compare control 0 TA3CCTL0 02h 72 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-35. TA3 Registers (Base Address: 0440h) (continued) REGISTER DESCRIPTION REGISTER OFFSET Capture/compare control 1 TA3CCTL1 04h TA3 register TA3R 10h Capture/compare register 0 TA3CCR0 12h Capture/compare register 1 TA3CCR1 14h TA3 expansion register 0 TA3EX0 20h TA3 interrupt vector TA3IV 2Eh Table 6-36. Capacitive Touch IO 1 Registers (Base Address: 0470h) REGISTER DESCRIPTION Capacitive Touch IO 1 control REGISTER CAPTIO1CTL OFFSET 0Eh Table 6-37. RTC_B Real-Time Clock Registers (Base Address: 04A0h) REGISTER DESCRIPTION REGISTER OFFSET RTC control 0 RTCCTL0 00h RTC control 1 RTCCTL1 01h RTC control 2 RTCCTL2 02h RTC control 3 RTCCTL3 03h RTC prescaler 0 control RTCPS0CTL 08h RTC prescaler 1 control RTCPS1CTL 0Ah RTC prescaler 0 RTCPS0 0Ch RTC prescaler 1 RTCPS1 0Dh RTC interrupt vector word RTCIV 0Eh RTC seconds RTCSEC/RTCNT1 10h RTC minutes RTCMIN/RTCNT2 11h RTC hours RTCHOUR/RTCNT3 12h RTC day of week RTCDOW/RTCNT4 13h RTC days RTCDAY 14h RTC month RTCMON 15h RTC year low RTCYEARL 16h RTC year high RTCYEARH 17h RTC alarm minutes RTCAMIN 18h RTC alarm hours RTCAHOUR 19h RTC alarm day of week RTCADOW 1Ah RTC alarm days RTCADAY 1Bh Binary-to-BCD conversion register BIN2BCD 1Ch BCD-to-binary conversion register BCD2BIN 1Eh Table 6-38. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h) REGISTER DESCRIPTION REGISTER OFFSET 16-bit operand 1 – multiply MPY 00h 16-bit operand 1 – signed multiply MPYS 02h 16-bit operand 1 – multiply accumulate MAC 04h 16-bit operand 1 – signed multiply accumulate MACS 06h 16-bit operand 2 OP2 08h 16 × 16 result low word RESLO 0Ah 16 × 16 result high word RESHI 0Ch Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 73 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 6-38. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h) (continued) REGISTER DESCRIPTION REGISTER OFFSET 16 × 16 sum extension register SUMEXT 0Eh 32-bit operand 1 – multiply low word MPY32L 10h 32-bit operand 1 – multiply high word MPY32H 12h 32-bit operand 1 – signed multiply low word MPYS32L 14h 32-bit operand 1 – signed multiply high word MPYS32H 16h 32-bit operand 1 – multiply accumulate low word MAC32L 18h 32-bit operand 1 – multiply accumulate high word MAC32H 1Ah 32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch 32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh 32-bit operand 2 – low word OP2L 20h 32-bit operand 2 – high word OP2H 22h 32 × 32 result 0 – least significant word RES0 24h 32 × 32 result 1 RES1 26h 32 × 32 result 2 RES2 28h 32 × 32 result 3 – most significant word RES3 2Ah MPY32 control register 0 MPY32CTL0 2Ch Table 6-39. DMA Registers (Base Address DMA General Control: 0500h, DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h) REGISTER DESCRIPTION REGISTER OFFSET DMA channel 0 control DMA0CTL 00h DMA channel 0 source address low DMA0SAL 02h DMA channel 0 source address high DMA0SAH 04h DMA channel 0 destination address low DMA0DAL 06h DMA channel 0 destination address high DMA0DAH 08h DMA channel 0 transfer size DMA0SZ 0Ah DMA channel 1 control DMA1CTL 00h DMA channel 1 source address low DMA1SAL 02h DMA channel 1 source address high DMA1SAH 04h DMA channel 1 destination address low DMA1DAL 06h DMA channel 1 destination address high DMA1DAH 08h DMA channel 1 transfer size DMA1SZ 0Ah DMA channel 2 control DMA2CTL 00h DMA channel 2 source address low DMA2SAL 02h DMA channel 2 source address high DMA2SAH 04h DMA channel 2 destination address low DMA2DAL 06h DMA channel 2 destination address high DMA2DAH 08h DMA channel 2 transfer size DMA2SZ 0Ah DMA module control 0 DMACTL0 00h DMA module control 1 DMACTL1 02h DMA module control 2 DMACTL2 04h DMA module control 3 DMACTL3 06h DMA module control 4 DMACTL4 08h DMA interrupt vector DMAIV 0Eh 74 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-40. MPU Control Registers (Base Address: 05A0h) REGISTER DESCRIPTION REGISTER OFFSET MPU control 0 MPUCTL0 00h MPU control 1 MPUCTL1 02h MPU Segmentation Boarder 2 MPUSEGB2 04h MPU Segmentation Boarder 1 MPUSEGB1 06h MPU access management MPUSAM 08h MPU IP control 0 MPUIPC0 0Ah MPU IP Encapsulation Segment Boarder 2 MPUIPSEGB2 0Ch MPU IP Encapsulation Segment Boarder 1 MPUIPSEGB1 0Eh Table 6-41. eUSCI_A0 Registers (Base Address: 05C0h) REGISTER DESCRIPTION REGISTER OFFSET eUSCI_A control word 0 UCA0CTLW0 00h eUSCI _A control word 1 UCA0CTLW1 02h eUSCI_A baud rate 0 UCA0BR0 06h eUSCI_A baud rate 1 UCA0BR1 07h eUSCI_A modulation control UCA0MCTLW 08h eUSCI_A status word UCA0STATW 0Ah eUSCI_A receive buffer UCA0RXBUF 0Ch eUSCI_A transmit buffer UCA0TXBUF 0Eh eUSCI_A LIN control UCA0ABCTL 10h eUSCI_A IrDA transmit control UCA0IRTCTL 12h eUSCI_A IrDA receive control UCA0IRRCTL 13h eUSCI_A interrupt enable UCA0IE 1Ah eUSCI_A interrupt flags UCA0IFG 1Ch eUSCI_A interrupt vector word UCA0IV 1Eh Table 6-42. eUSCI_A1 Registers (Base Address:05E0h) REGISTER DESCRIPTION REGISTER OFFSET eUSCI_A control word 0 UCA1CTLW0 00h eUSCI _A control word 1 UCA1CTLW1 02h eUSCI_A baud rate 0 UCA1BR0 06h eUSCI_A baud rate 1 UCA1BR1 07h eUSCI_A modulation control UCA1MCTLW 08h eUSCI_A status word UCA1STATW 0Ah eUSCI_A receive buffer UCA1RXBUF 0Ch eUSCI_A transmit buffer UCA1TXBUF 0Eh eUSCI_A LIN control UCA1ABCTL 10h eUSCI_A IrDA transmit control UCA1IRTCTL 12h eUSCI_A IrDA receive control UCA1IRRCTL 13h eUSCI_A interrupt enable UCA1IE 1Ah eUSCI_A interrupt flags UCA1IFG 1Ch eUSCI_A interrupt vector word UCA1IV 1Eh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 75 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 6-43. eUSCI_B0 Registers (Base Address: 0640h) REGISTER DESCRIPTION REGISTER OFFSET eUSCI_B control word 0 UCB0CTLW0 00h eUSCI_B control word 1 UCB0CTLW1 02h eUSCI_B bit rate 0 UCB0BR0 06h eUSCI_B bit rate 1 UCB0BR1 07h eUSCI_B status word UCB0STATW 08h eUSCI_B byte counter threshold UCB0TBCNT 0Ah eUSCI_B receive buffer UCB0RXBUF 0Ch eUSCI_B transmit buffer UCB0TXBUF 0Eh eUSCI_B I2C own address 0 UCB0I2COA0 14h eUSCI_B I2C own address 1 UCB0I2COA1 16h eUSCI_B I2C own address 2 UCB0I2COA2 18h eUSCI_B I2C own address 3 UCB0I2COA3 1Ah eUSCI_B received address UCB0ADDRX 1Ch eUSCI_B address mask UCB0ADDMASK 1Eh eUSCI I2C slave address UCB0I2CSA 20h eUSCI interrupt enable UCB0IE 2Ah eUSCI interrupt flags UCB0IFG 2Ch eUSCI interrupt vector word UCB0IV 2Eh Table 6-44. ADC12_B Registers (Base Address: 0800h) REGISTER DESCRIPTION REGISTER OFFSET ADC12_B Control 0 ADC12CTL0 00h ADC12_B Control 1 ADC12CTL1 02h ADC12_B Control 2 ADC12CTL2 04h ADC12_B Control 3 ADC12CTL3 06h ADC12_B Window Comparator Low Threshold Register ADC12LO 08h ADC12_B Window Comparator High Threshold Register ADC12HI 0Ah ADC12_B Interrupt Flag Register 0 ADC12IFGR0 0Ch ADC12_B Interrupt Flag Register 1 ADC12IFGR1 0Eh ADC12_B Interrupt Flag Register 2 ADC12IFGR2 10h ADC12_B Interrupt Enable Register 0 ADC12IER0 12h ADC12_B Interrupt Enable Register 1 ADC12IER1 14h ADC12_B Interrupt Enable Register 2 ADC12IER2 16h ADC12_B Interrupt Vector ADC12IV 18h ADC12_B Memory Control 0 ADC12MCTL0 20h ADC12_B Memory Control 1 ADC12MCTL1 22h ADC12_B Memory Control 2 ADC12MCTL2 24h ADC12_B Memory Control 3 ADC12MCTL3 26h ADC12_B Memory Control 4 ADC12MCTL4 28h ADC12_B Memory Control 5 ADC12MCTL5 2Ah ADC12_B Memory Control 6 ADC12MCTL6 2Ch ADC12_B Memory Control 7 ADC12MCTL7 2Eh ADC12_B Memory Control 8 ADC12MCTL8 30h ADC12_B Memory Control 9 ADC12MCTL9 32h ADC12_B Memory Control 10 ADC12MCTL10 34h ADC12_B Memory Control 11 ADC12MCTL11 36h 76 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-44. ADC12_B Registers (Base Address: 0800h) (continued) REGISTER DESCRIPTION REGISTER OFFSET ADC12_B Memory Control 12 ADC12MCTL12 38h ADC12_B Memory Control 13 ADC12MCTL13 3Ah ADC12_B Memory Control 14 ADC12MCTL14 3Ch ADC12_B Memory Control 15 ADC12MCTL15 3Eh ADC12_B Memory Control 16 ADC12MCTL16 40h ADC12_B Memory Control 17 ADC12MCTL17 42h ADC12_B Memory Control 18 ADC12MCTL18 44h ADC12_B Memory Control 19 ADC12MCTL19 46h ADC12_B Memory Control 20 ADC12MCTL20 48h ADC12_B Memory Control 21 ADC12MCTL21 4Ah ADC12_B Memory Control 22 ADC12MCTL22 4Ch ADC12_B Memory Control 23 ADC12MCTL23 4Eh ADC12_B Memory Control 24 ADC12MCTL24 50h ADC12_B Memory Control 25 ADC12MCTL25 52h ADC12_B Memory Control 26 ADC12MCTL26 54h ADC12_B Memory Control 27 ADC12MCTL27 56h ADC12_B Memory Control 28 ADC12MCTL28 58h ADC12_B Memory Control 29 ADC12MCTL29 5Ah ADC12_B Memory Control 30 ADC12MCTL30 5Ch ADC12_B Memory Control 31 ADC12MCTL31 5Eh ADC12_B Memory 0 ADC12MEM0 60h ADC12_B Memory 1 ADC12MEM1 62h ADC12_B Memory 2 ADC12MEM2 64h ADC12_B Memory 3 ADC12MEM3 66h ADC12_B Memory 4 ADC12MEM4 68h ADC12_B Memory 5 ADC12MEM5 6Ah ADC12_B Memory 6 ADC12MEM6 6Ch ADC12_B Memory 7 ADC12MEM7 6Eh ADC12_B Memory 8 ADC12MEM8 70h ADC12_B Memory 9 ADC12MEM9 72h ADC12_B Memory 10 ADC12MEM10 74h ADC12_B Memory 11 ADC12MEM11 76h ADC12_B Memory 12 ADC12MEM12 78h ADC12_B Memory 13 ADC12MEM13 7Ah ADC12_B Memory 14 ADC12MEM14 7Ch ADC12_B Memory 15 ADC12MEM15 7Eh ADC12_B Memory 16 ADC12MEM16 80h ADC12_B Memory 17 ADC12MEM17 82h ADC12_B Memory 18 ADC12MEM18 84h ADC12_B Memory 19 ADC12MEM19 86h ADC12_B Memory 20 ADC12MEM20 88h ADC12_B Memory 21 ADC12MEM21 8Ah ADC12_B Memory 22 ADC12MEM22 8Ch ADC12_B Memory 23 ADC12MEM23 8Eh ADC12_B Memory 24 ADC12MEM24 90h ADC12_B Memory 25 ADC12MEM25 92h ADC12_B Memory 26 ADC12MEM26 94h Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 77 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 6-44. ADC12_B Registers (Base Address: 0800h) (continued) REGISTER DESCRIPTION REGISTER OFFSET ADC12_B Memory 27 ADC12MEM27 96h ADC12_B Memory 28 ADC12MEM28 98h ADC12_B Memory 29 ADC12MEM29 9Ah ADC12_B Memory 30 ADC12MEM30 9Ch ADC12_B Memory 31 ADC12MEM31 9Eh Table 6-45. Comparator_E Registers (Base Address: 08C0h) REGISTER DESCRIPTION REGISTER OFFSET Comparator_E control register 0 CECTL0 00h Comparator_E control register 1 CECTL1 02h Comparator_E control register 2 CECTL2 04h Comparator_E control register 3 CECTL3 06h Comparator_E interrupt register CEINT 0Ch Comparator_E interrupt vector word CEIV 0Eh Table 6-46. AES Accelerator Registers (Base Address: 09C0h) REGISTER DESCRIPTION AES accelerator control register 0 REGISTER AESACTL0 Reserved OFFSET 00h 02h AES accelerator status register AESASTAT 04h AES accelerator key register AESAKEY 06h AES accelerator data in register AESADIN 008h AES accelerator data out register AESADOUT 00Ah AES accelerator XORed data in register AESAXDIN 00Ch AES accelerator XORed data in register (no trigger) AESAXIN 00Eh 78 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 6.11 Input/Output Schematics 6.11.1 Capacitive Touch Functionality Ports P1, P2, P3, P4, and PJ All port pins provide the Capacitive Touch functionality as shown in the following figure. The Capacitive Touch functionality is controlled using the Capacitive Touch IO control registers CAPTIO0CTL and CAPTIO1CTL as described in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide (SLAU367). The Capacitive Touch functionality is not shown in the individual pin schematics in the following sections. Analog Enable PxREN.y Capacitive Touch Enable 0 Capacitive Touch Enable 1 DVSS 0 DVCC 1 1 Direction Control PxOUT.y 0 1 Output Signal Px.y Input Signal Q D EN Capacitive Touch Signal 0 Capacitive Touch Signal 1 NOTE: Functional representation only. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 79 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.11.2 Port P1, P1.0 to P1.2, Input/Output With Schmitt Trigger Pad Logic (ADC) Reference (P1.0, P1.1) To ADC From ADC To Comparator From Comparator CBPD.x P1REN.x P1DIR.x 00 01 10 Direction 0: Input 1: Output 11 P1OUT.x DVSS 0 DVCC 1 1 00 From module 1 01 From module 2 10 DVSS 11 P1.0/TA0.1/DMAE0/RTCCLK/ A0/C0/VREF-/VeREFP1.1/TA0.2/TA1CLK/COUT/ A1/C1VREF+/VeREF+ P1.2/TA1.1/TA0CLK/COUT/A2/C2 P1SEL0.x P1SEL1.x P1IN.x EN To modules Bus Keeper D NOTE: Functional representation only. 80 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-47. Port P1 (P1.0 to P1.2) Pin Functions PIN NAME (P1.x) P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/ VREF-/VeREF- x 0 FUNCTION P1.0 (I/O) P1.2/TA1.1/TA0CLK/COUT/A2/C2 (1) (2) (3) (4) 1 2 P1DIR.x P1SEL1.x P1SEL0.x I: 0; O: 1 0 0 0 1 1 0 X 1 1 I: 0; O: 1 0 0 0 1 1 0 TA0.CCI1A 0 TA0.1 1 DMAE0 0 RTCCLK (2) 1 A0, C0, VREF-, VeREF- (3) (4) P1.1/TA0.2/TA1CLK/COUT/A1/C1/ VREF+/VeREF+ CONTROL BITS AND SIGNALS (1) P1.1 (I/O) TA0.CCI2A 0 TA0.2 1 TA1CLK 0 COUT 1 A1, C1, VREF+, VeREF+ (3) (4) X 1 1 I: 0; O: 1 0 0 0 1 1 0 1 1 P1.2 (I/O) TA1.CCI1A 0 TA1.1 1 TA0CLK 0 COUT 1 A2, C2 (3) (4) X X = Don't care Not available on MSP430FR5x5x devices Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 81 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.11.3 Port P1, P1.3 to P1.5, Input/Output With Schmitt Trigger Pad Logic To ADC From ADC To Comparator From Comparator CBPD.x P1REN.x P1DIR.x 00 From module 2 10 01 Direction 0: Input 1: Output 11 P1OUT.x DVSS 0 DVCC 1 1 00 From module 1 01 From module 2 10 DVSS 11 P1.3/TA1.2/UCB0STE/A3/C3 P1.4/TB0.1/UCA0STE/A4/C4 P1.5/TB0.2/UCA0CLK/A5/C5 P1SEL0.x P1SEL1.x P1IN.x EN To modules Bus Keeper D NOTE: Functional representation only. 82 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-48. Port P1 (P1.3 to P1.5) Pin Functions PIN NAME (P1.x) P1.3/TA1.2/UCB0STE/A3/C3 P1.4/TB0.1/UCA0STE/A4/C4 x 3 4 FUNCTION P1.3 (I/O) (1) (2) (3) (4) (5) P1SEL1.x P1SEL0.x 0 0 0 1 0 TA1.2 1 UCB0STE X (2) 1 0 A3, C3 (3) (4) X 1 1 I: 0; O: 1 0 0 0 1 X (5) 1 0 X 1 1 I: 0; O: 1 0 0 0 1 P1.4 (I/O) TB0.CCI1A 0 TB0.1 1 A4, C4 5 P1DIR.x I: 0; O: 1 TA1.CCI2A UCA0STE P1.5/TB0.2/UCA0CLK/A5/C5 CONTROL BITS AND SIGNALS (1) (3) (4) P1.5(I/O) TB0.CCI2A 0 TB0.2 1 UCA0CLK X (5) 1 0 A5, C5 (3) (4) X 1 1 X = Don't care Direction controlled by eUSCI_B0 module. Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit. Direction controlled by eUSCI_A0 module. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 83 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.11.4 Port P1, P1.6 to P1.7, Input/Output With Schmitt Trigger Pad Logic P1REN.x P1DIR.x 00 From module 2 10 01 Direction 0: Input 1: Output 11 P1OUT.x 00 From module 1 01 From module 2 10 From module 3 11 DVSS 0 DVCC 1 1 P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0 P1SEL0.x P1SEL1.x P1IN.x EN D To modules NOTE: Functional representation only. Table 6-49. Port P1 (P1.6 to P1.7) Pin Functions PIN NAME (P1.x) x P1.6/TB0.3/UCB0SIMO/UCB0SDA/ TA0.0 6 FUNCTION P1.6 (I/O) 7 84 P1SEL1.x P1SEL0.x 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 TB0.3 1 X (2) TA0.CCI0A 0 TA0.0 1 P1.7 (I/O) I: 0; O: 1 TB0.CCI4B 0 TB0.4 1 UCB0SOMI/UCB0SCL (1) (2) (3) P1DIR.x I: 0; O: 1 TB0.CCI3B UCB0SIMO/UCB0SDA P1.7/TB0.4/UCB0SOMI/UCB0SCL/ TA1.0 CONTROL BITS AND SIGNALS (1) X (3) TA1.CCI0A 0 TA1.0 1 X = Don't care Direction controlled by eUSCI_B0 module. Direction controlled by eUSCI_A0 module. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 6.11.5 Port P2, P2.0 to P2.2, Input/Output With Schmitt Trigger Pad Logic P2REN.x P2DIR.x 00 From module 2 10 01 Direction 0: Input 1: Output 11 P2OUT.x DVSS 0 DVCC 1 1 00 From module 1 01 From module 2 10 From module 3 11 P2.0/TB0.6/UCA0TXD/UCA0SIMO/ TB0CLK/ACLK P2.1/TB0.0/UCA0RXD/UCA0SOMI/ TB0.0 P2.2/TB0.2/UCB0CLK P2SEL0.x P2SEL1.x P2IN.x EN D To modules NOTE: Functional representation only. Table 6-50. Port P2 (P2.0 to P2.2) Pin Functions PIN NAME (P2.x) P2.0/TB0.6/UCA0TXD/UCA0SIMO/ TB0CLK/ACLK x 0 FUNCTION P2.0 (I/O) 1 2 P2SEL0.x 0 0 0 1 1 0 1 1 0 0 X 1 X (2) 1 0 I: 0; O: 1 0 0 0 1 1 0 1 1 TB0.6 1 X (2) TB0CLK 0 ACLK 1 P2.1 (I/O) I: 0; O: 1 TB0.CCI0A 0 TB0.0 1 P2.2 (I/O) N/A 0 TB0.2 1 UCB0CLK (1) (2) (3) P2SEL1.x 0 UCA0RXD/UCA0SOMI P2.2/TB0.2/UCB0CLK P2DIR.x I: 0; O: 1 TB0.CCI6B UCA0TXD/UCA0SIMO P2.1/TB0.0/UCA0RXD/UCA0SOMI/ TB0.0 CONTROL BITS AND SIGNALS (1) X (3) N/A 0 Internally tied to DVSS 1 X = Don't care Direction controlled by eUSCI_A0 module. Direction controlled by eUSCI_B0 module. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 85 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.11.6 Port P2, P2.3 to P2.4, Input/Output With Schmitt Trigger Pad Logic To ADC From ADC To Comparator From Comparator CBPD.x P2REN.x P2DIR.x 00 01 From module 2 10 Direction 0: Input 1: Output 11 P2OUT.x 00 From module 1 01 From module 2 10 DVSS 11 DVSS 0 DVCC 1 1 P2.3/TA0.0/UCA1STE/A6/C10 P2.4/TA1.0/UCA1CLK/A7/C11 P2SEL0.x P2SEL1.x P2IN.x EN To modules Bus Keeper D NOTE: Functional representation only. 86 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-51. Port P2 (P2.3 to P2.4) Pin Functions PIN NAME (P2.x) x P2.3/TA0.0/UCA1STE/A6/C10 3 FUNCTION P2.3 (I/O) 0 0 1 1 P2.4 (I/O) X (2) 1 0 X 1 1 I: 0; O: 1 0 0 0 1 1 0 1 1 TA1.CCI0B 0 TA1.0 1 A7, C11 (4) P2SEL0.x 0 TA0.0 UCA1CLK (1) (2) (3) P2SEL1.x 0 A6, C10 (3) (4) 4 P2DIR.x I: 0; O: 1 TA0.CCI0B UCA1STE P2.4/TA1.0/UCA1CLK/A7/C11 CONTROL BITS AND SIGNALS (1) (3) (4) X (2) X X = Don't care Direction controlled by eUSCI_A1 module. Setting P2SEL1.x and P2SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 87 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.11.7 Port P2, P2.5 to P2.6, Input/Output With Schmitt Trigger Pad Logic P2REN.x P2DIR.x 00 From module 2 10 01 Direction 0: Input 1: Output 11 P2OUT.x DVSS 0 DVCC 1 1 00 From module 1 01 From module 2 10 DVSS 11 P2.5/TB0.0/UCA1TXD/UCA1SIMO P2.6/TB0.1/UCA1RXD/UCA1SOMI P2SEL0.x P2SEL1.x P2IN.x EN D To modules NOTE: Functional representation only. Table 6-52. Port P2 (P2.5 to P2.6) Pin Functions PIN NAME (P2.x) P2.5/TB0.0/UCA1TXD/UCA1SIMO x 5 FUNCTION P2.5(I/O) 6 88 P2SEL1.x P2SEL0.x I: 0; O: 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 TB0.0 1 X (2) N/A 0 Internally tied to DVSS 1 P2.6(I/O) I: 0; O: 1 N/A 0 TB0.1 1 UCA1RXD/UCA1SOMI (1) (2) P2DIR.x TB0.CCI0B UCA1TXD/UCA1SIMO P2.6/TB0.1/UCA1RXD/UCA1SOMI CONTROL BITS AND SIGNALS (1) X (2) N/A 0 Internally tied to DVSS 1 X = Don't care Direction controlled by eUSCI_A1 module. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 6.11.8 Port P2, P2.7, Input/Output With Schmitt Trigger Pad Logic P2REN.x P2DIR.x 00 01 10 Direction 0: Input 1: Output 11 P2OUT.x 00 DVSS 01 DVSS 10 DVSS 11 DVSS 0 DVCC 1 1 P2.7 P2SEL0.x P2SEL1.x P2IN.x Bus Keeper EN To modules D NOTE: Functional representation only. Table 6-53. Port P2 (P2.7) Pin Functions PIN NAME (P2.x) P2.7 (1) x 7 FUNCTION P2.7(I/O) CONTROL BITS AND SIGNALS (1) P2DIR.x P2SEL1.x P2SEL0.x I: 0; O: 1 0 0 0 1 1 X N/A 0 Internally tied to DVSS 1 N/A 0 Internally tied to DVSS 1 X = Don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 89 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.11.9 Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger Pad Logic To ADC From ADC To Comparator From Comparator CBPD.x P3REN.x P3DIR.x 00 01 10 Direction 0: Input 1: Output 11 P3OUT.x DVSS 0 DVCC 1 1 00 DVSS 01 DVSS 10 DVSS 11 P3.0/A12/C12 P3.1/A13/C13 P3.2/A14/C14 P3.3/A15/C15 P3SEL0.x P3SEL1.x P3IN.x EN To modules Bus Keeper D NOTE: Functional representation only. 90 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-54. Port P3 (P3.0 to P3.3) Pin Functions PIN NAME (P3.x) P3.0/A12/C12 x 0 FUNCTION P3.0 (I/O) P3.2/A14/C14 P3.3/A15/C15 (1) (2) (3) 1 2 3 P3DIR.x P3SEL1.x P3SEL0.x I: 0; O: 1 0 0 0 1 1 0 X 1 1 I: 0; O: 1 0 0 0 1 1 0 N/A 0 Internally tied to DVSS 1 N/A 0 Internally tied to DVSS 1 A12/C12 (2) (3) P3.1/A13/C13 CONTROL BITS AND SIGNALS (1) P3.1 (I/O) N/A 0 Internally tied to DVSS 1 N/A 0 Internally tied to DVSS 1 A13/C13 (2) (3) X 1 1 I: 0; O: 1 0 0 0 1 1 0 P3.2 (I/O) N/A 0 Internally tied to DVSS 1 N/A 0 Internally tied to DVSS 1 A14/C14 (2) (3) X 1 1 I: 0; O: 1 0 0 0 1 1 0 1 1 P3.3 (I/O) N/A 0 Internally tied to DVSS 1 N/A 0 Internally tied to DVSS 1 A15/C15 (2) (3) X X = Don't care Setting P3SEL1.x and P3SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 91 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.11.10 Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger Pad Logic P3REN.x P3DIR.x 00 01 Direction 0: Input 1: Output 10 11 P3OUT.x DVSS 0 DVCC 1 1 00 From module 1 01 From module 2 10 From module 3 11 P3.4/TB0.3/SMCLK P3.5/TB0.4/CBOUT P3.6/TB0.5 P3.7/TB0.6 P3SEL0.x P3SEL1.x P3IN.x EN To modules D NOTE: Functional representation only. 92 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-55. Port P3 (P3.4 to P3.7) Pin Functions PIN NAME (P3.x) P3.4/TB0.3/SMCLK P3.5/TB0.4/COUT P3.6/TB0.5 4 5 6 P3.7/TB0.6 (1) x 7 FUNCTION P3.4 (I/O) CONTROL BITS AND SIGNALS (1) P3DIR.x P3SEL1.x P3SEL0.x I: 0; O: 1 0 0 0 1 1 X 0 0 0 1 1 X 0 0 0 1 1 X 0 0 0 1 1 X TB0.CCI3A 0 TB0.3 1 N/A 0 SMCLK 1 P3.5 (I/O) I: 0; O: 1 TB0.CCI4A 0 TB0.4 1 N/A 0 COUT 1 P3.6 (I/O) I: 0; O: 1 TB0.CCI5A 0 TB0.5 1 N/A 0 Internally tied to DVSS 1 P3.7 (I/O) I: 0; O: 1 TB0.CCI6A 0 TB0.6 1 N/A 0 Internally tied to DVSS 1 X = Don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 93 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.11.11 Port P4, P4.0 to P4.3, Input/Output With Schmitt Trigger Pad Logic To ADC From ADC P4REN.x P4DIR.x 00 01 10 Direction 0: Input 1: Output 11 P4OUT.x DVSS 0 DVCC 1 1 00 DVSS 01 DVSS 10 DVSS 11 P4.0/A8 P4.1/A9 P4.2/A10 P4.3/A11 P4SEL0.x P4SEL1.x P4IN.x EN To modules Bus Keeper D NOTE: Functional representation only. 94 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-56. Port P4 (P4.0 to P4.3) Pin Functions PIN NAME (P4.x) P4.0/A8 x 0 FUNCTION P4.0 (I/O) P4.2/A10 P4.3/A11 (1) (2) 1 2 3 P4DIR.x P4SEL1.x P4SEL0.x I: 0; O: 1 0 0 0 1 1 0 X 1 1 I: 0; O: 1 0 0 0 1 1 0 N/A 0 Internally tied to DVSS 1 N/A 0 Internally tied to DVSS 1 A8 (2) P4.1/A9 CONTROL BITS AND SIGNALS (1) P4.1 (I/O) N/A 0 Internally tied to DVSS 1 N/A 0 Internally tied to DVSS 1 A9 (2) X 1 1 I: 0; O: 1 0 0 0 1 1 0 P4.2 (I/O) N/A 0 Internally tied to DVSS 1 N/A 0 Internally tied to DVSS 1 A10 (2) X 1 1 I: 0; O: 1 0 0 0 1 1 0 1 1 P4.3 (I/O) N/A 0 Internally tied to DVSS 1 N/A 0 Internally tied to DVSS 1 A11 (2) X X = Don't care Setting P4SEL1.x and P4SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 95 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.11.12 Port P4, P4.4 to P4.7, Input/Output With Schmitt Trigger Pad Logic P4REN.x P4DIR.x 00 01 Direction 0: Input 1: Output 10 11 P4OUT.x DVSS 0 DVCC 1 1 00 From module 1 01 DVSS 10 DVSS 11 P4.4/TB0.5 P4.5 P4.6 P4.7 P4SEL0.x P4SEL1.x P4IN.x EN To modules D NOTE: Functional representation only. 96 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-57. Port P4 (P4.4 to P4.7) Pin Functions PIN NAME (P4.x) P4.4/TB0.5 4 P4.5 5 P4.6 6 P4.7 (1) x 7 FUNCTION P4.4 (I/O) CONTROL BITS AND SIGNALS (1) P4DIR.x P4SEL1.x P4SEL0.x I: 0; O: 1 0 0 0 1 1 X 0 0 0 1 1 X 0 0 0 1 1 X 0 0 0 1 1 X TB0.CCI5B 0 TB0.5 1 N/A 0 Internally tied to DVSS 1 P4.5 (I/O) I: 0; O: 1 N/A 0 Internally tied to DVSS 1 N/A 0 Internally tied to DVSS 1 P4.6 (I/O) I: 0; O: 1 N/A 0 Internally tied to DVSS 1 N/A 0 Internally tied to DVSS 1 P4.7 (I/O) I: 0; O: 1 N/A 0 Internally tied to DVSS 1 N/A 0 Internally tied to DVSS 1 X = Don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 97 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.11.13 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger Pad Logic To LFXT XIN PJREN.4 PJDIR.4 00 01 10 Direction 0: Input 1: Output 11 PJOUT.4 00 DVSS 01 DVSS 10 DVSS 11 DVSS 0 DVCC 1 1 PJ.4/LFXIN PJSEL0.4 PJSEL1.4 PJIN.4 EN To modules Bus Keeper D NOTE: Functional representation only. 98 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Pad Logic To LFXT XOUT PJSEL0.4 PJSEL1.4 LFXTBYPASS PJREN.5 PJDIR.5 00 01 10 Direction 0: Input 1: Output 11 PJOUT.5 DVSS 0 DVCC 1 1 00 DVSS 01 DVSS 10 DVSS 11 PJ.5/LFXOUT PJSEL0.5 PJSEL1.5 PJIN.5 EN To modules Bus Keeper D NOTE: Functional representation only. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 99 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 6-58. Port PJ (PJ.4 and PJ.5) Pin Functions CONTROL BITS AND SIGNALS (1) PIN NAME (PJ.x) PJ.4/LFXIN x 4 FUNCTION PJ.4 (I/O) PJSEL0.4 LFXT BYPASS I: 0; O: 1 X X 0 0 X X X 1 X X 1 LFXIN crystal mode (2) X X X 0 1 0 X X X 0 1 1 0 0 1 X X X (2) 5 Internally tied to DVSS LFXOUT crystal mode (2) 100 PJSEL1.4 0 N/A (3) (4) PJSEL0.5 Internally tied to DVSS PJ.5 (I/O) (1) (2) PJSEL1.5 N/A LFXIN bypass mode PJ.5/LFXOUT PJDIR.x I: 0; O: 1 0 1 X 0 see (4) see (4) X 0 see (4) see (4) X 0 0 1 X X X 0 1 (3) 0 1 (3) 0 0 1 X X X 1 (3) 0 1 0 0 X = Don't care If PJSEL1.4 = 0 and PJSEL0.4 = 1, the general-purpose I/O is disabled. When LFXTBYPASS = 0, PJ.4 and PJ.5 are configured for crystal operation and PJSEL1.5 and PJSEL0.5 are don't care. When LFXTBYPASS = 1, PJ.4 is configured for bypass operation and PJ.5 is configured as general-purpose I/O. When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O. If PJSEL0.5 = 1 or PJSEL1.5 = 1, the general-purpose I/O functionality is disabled. No input function is available. Configured as output, the pin is actively pulled to zero. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 6.11.14 Port PJ, PJ.6 and PJ.7 Input/Output With Schmitt Trigger Pad Logic To HFXT XIN PJREN.6 PJDIR.6 00 01 10 Direction 0: Input 1: Output 11 PJOUT.6 00 DVSS 01 DVSS 10 DVSS 11 DVSS 0 DVCC 1 1 PJ.6/HFXIN PJSEL0.6 PJSEL1.6 PJIN.6 EN To modules Bus Keeper D NOTE: Functional representation only. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 101 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Pad Logic To HFXT XOUT PJSEL0.6 PJSEL1.6 HFXTBYPASS PJREN.7 PJDIR.7 00 01 10 Direction 0: Input 1: Output 11 PJOUT.7 DVSS 0 DVCC 1 1 00 DVSS 01 DVSS 10 DVSS 11 PJ.7/HFXOUT PJSEL0.7 PJSEL1.7 PJIN.7 EN To modules Bus Keeper D NOTE: Functional representation only. 102 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-59. Port PJ (PJ.6 and PJ.7) Pin Functions CONTROL BITS AND SIGNALS (1) PIN NAME (PJ.x) PJ.6/HFXIN x 6 FUNCTION PJ.6 (I/O) PJSEL0.6 HFXT BYPASS I: 0; O: 1 X X 0 0 X X X 1 X X 1 HFXIN crystal mode (2) X X X 0 1 0 X X X 0 1 1 0 0 1 X X X (2) 5 Internally tied to DVSS HFXOUT crystal mode (2) (4) PJSEL1.6 0 N/A (3) PJSEL0.7 Internally tied to DVSS PJ.7 (I/O) (3) (1) (2) PJSEL1.7 N/A HFXIN bypass mode PJ.7/HFXOUT PJDIR.x I: 0; O: 1 0 1 X 0 see see X 0 (3) (3) see see X (3) (3) 0 0 1 X X X 0 1 (4) 0 1 (4) 0 0 1 X X X 1 (4) 0 1 0 0 X = Don't care Setting PJSEL1.6 = 0 and PJSEL0.6 = 1 causes the general-purpose I/O to be disabled. When HFXTBYPASS = 0, PJ.6 and PJ.7 are configured for crystal operation and PJSEL1.6 and PJSEL0.7 are do not care. When HFXTBYPASS = 1, PJ.6 is configured for bypass operation and PJ.7 is configured as general-purpose I/O. With PJSEL0.7 = 1 or PJSEL1.7 =1 the general-purpose I/O functionality is disabled. No input function is available. Configured as output the pin is actively pulled to zero. When PJ.6 is configured in bypass mode, PJ.7 is configured as general-purpose I/O. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 103 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.11.15 Port J, J.0 to J.3 JTAG pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger To Comparator From Comparator Pad Logic CBPD.x JTAG enable From JTAG From JTAG PJREN.x PJDIR.x 00 1 01 10 Direction 0: Input 1: Output 11 PJOUT.x DVSS 0 DVCC 1 0 1 00 From module 1 01 1 From Status Register (SR) 10 0 DVSS 11 PJSEL0.x PJSEL1.x PJIN.x EN To modules and JTAG Bus Keeper PJ.0/TDO/TB0OUTH/SMCLK/ SRSCG1/C6 PJ.1/TDI/TCLK/MCLK/ SRSCG0/C7 PJ.2/TMS/ACLK/ SROSCOFF/C8 PJ.3/TCK/ SRCPUOFF/C9 D NOTE: Functional representation only. 104 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-60. Port PJ (PJ.0 to PJ.3) Pin Functions PIN NAME (PJ.x) PJ.0/TDO/TB0OUTH/ SMCLK/SRSCG1/C6 x 0 FUNCTION PJDIR.x PJSEL1.x PJSEL0.x CEPD.x (Cx) I: 0; O: 1 0 0 0 TDO (3) X X X 0 TB0OUTH 0 SMCLK 1 0 1 0 N/A 0 CPU Status Register Bit SCG1 1 1 0 0 N/A 0 Internally tied to DVSS 1 1 1 0 PJ.0 (I/O) (2) C6 (4) PJ.1/TDI/TCLK/MCLK/ SRSCG0/C7 PJ.2/TMS/ACLK/ SROSCOFF/C8 1 PJ.1 (I/O) (2) TDI/TCLK (3) 2 (5) (4) (5) X 1 0 0 0 X X X 0 0 1 0 1 0 0 1 1 0 X X 1 MCLK 1 N/A 0 CPU Status Register Bit SCG0 1 N/A 0 Internally tied to DVSS 1 C7 (4) X PJ.2 (I/O) (2) (5) I: 0; O: 1 0 0 0 X X X 0 0 1 0 1 0 0 1 1 0 N/A 0 ACLK 1 N/A 0 CPU Status Register Bit OSCOFF 1 N/A 0 Internally tied to DVSS 1 PJ.3 (I/O) (2) TCK (1) (2) (3) X 0 TMS (3) 3 X I: 0; O: 1 N/A C8 (4) PJ.3/TCK/SRCPUOFF/C9 CONTROL BITS/ SIGNALS (1) (3) (5) X X X 1 I: 0; O: 1 0 0 0 X X X 0 0 1 0 1 0 0 1 1 0 X X 1 N/A 0 Internally tied to DVSS 1 N/A 0 CPU Status Register Bit CPUOFF 1 N/A 0 Internally tied to DVSS 1 C9 (4) X X = Don't care Default condition The pin direction is controlled by the JTAG module. JTAG mode selection is made via the SYS module or by the Spy-Bi-Wire four-wire entry sequence. Neither PJSEL1.x and PJSEL0.x nor CEPD.x bits have an effect in these cases. Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit. In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 105 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 6.12 Device Descriptors (TLV) Table 6-62 lists the contents of the device descriptor tag-length-value (TLV) structure for MSP430FR59xx(1) devices including AES. Table 6-61 summarizes the Device IDs of the corresponding MSP430FR59xx(1) devices. Table 6-61. Device IDs Device ID Device 01A05h 01A04h MSP430FR5969(1) 081h 069h MSP430FR5968 081h 068h MSP430FR5967 081h 067h MSP430FR5949 081h 061h MSP430FR5948 081h 060h MSP430FR5947(1) 081h 05Fh MSP430FR5959 081h 065h MSP430FR5958 081h 064h MSP430FR5957 081h 063h Table 6-62. Device Descriptor Table MSP430FR59xx(1) (1) Description Info Block Address Value Info length 01A00h 06h 01A00h 06h CRC length 01A01h 06h 01A01h 06h 01A02h per unit 01A02h per unit 01A03h per unit 01A03h per unit see Table 6-61 01A04h see Table 6-61 Device ID 01A06h per unit 01A06h per unit 01A07h per unit 01A07h per unit Die Record Tag 01A08h 08h 01A08h 08h Die Record length 01A09h 0Ah 01A09h 0Ah 01A0Ah per unit 01A0Ah per unit 01A0Bh per unit 01A0Bh per unit 01A0Ch per unit 01A0Ch per unit 01A0Dh per unit 01A0Dh per unit 01A0Eh per unit 01A0Eh per unit 01A0Fh per unit 01A0Fh per unit 01A10h per unit 01A10h per unit 01A11h per unit 01A11h per unit 01A12h per unit 01A12h per unit 01A13h per unit 01A13h per unit ADC12 Calibration Tag 01A14h 11h 01A14h 11h ADC12 Calibration length 01A15h 10h 01A15h 10h 01A16h per unit 01A16h per unit 01A17h per unit 01A17h per unit Die Y position Test results ADC Gain Factor (2) 106 01A05h Firmware revision Die X position (1) (2) 01A04h Hardware revision Lot/Wafer ID ADC12 Calibration MSP430FR59xx1 (I2C BSL) Value CRC value Die Record MSP430FR59xx (UART BSL) Address NA = Not applicable, per unit = content can differ from device to device ADC Gain: the gain correction factor is measured at room temperature using a 2.5V external voltage reference without internal buffer (ADC12VRSEL=0x2, 0x4, or 0xE). Other settings (for example, using internal reference) can result in different correction factors. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Table 6-62. Device Descriptor Table MSP430FR59xx(1)(1) (continued) Description Address Value 01A18h per unit 01A18h per unit 01A19h per unit 01A19h per unit ADC 1.2-V Reference Temp. Sensor 30°C 01A1Ah per unit 01A1Ah per unit 01A1Bh per unit 01A1Bh per unit ADC 1.2-V Reference Temp. Sensor 85°C 01A1Ch per unit 01A1Ch per unit 01A1Dh per unit 01A1Dh per unit ADC 2.0-V Reference Temp. Sensor 30°C 01A1Eh per unit 01A1Eh per unit 01A1Fh per unit 01A1Fh per unit ADC 2.0-V Reference Temp. Sensor 85°C 01A20h per unit 01A20h per unit 01A21h per unit 01A21h per unit ADC 2.5-V Reference Temp. Sensor 30°C 01A22h per unit 01A22h per unit 01A23h per unit 01A23h per unit ADC 2.5-V Reference Temp. Sensor 85°C 01A24h per unit 01A24h per unit 01A25h per unit 01A25h per unit REF Calibration Tag 01A26h 12h 01A26h 12h REF Calibration length 01A27h 06h 01A27h 06h 01A28h per unit 01A28h per unit 01A29h per unit 01A29h per unit 01A2Ah per unit 01A2Ah per unit 01A2Bh per unit 01A2Bh per unit 01A2Ch per unit 01A2Ch per unit 01A2Dh per unit 01A2Dh per unit 128-bit Random Number Tag 01A2Eh 15h 01A2Eh 15h Random Number Length 01A2Fh 10h 01A2Fh 10h 01A30h per unit 01A30h per unit 01A31h per unit 01A31h per unit 01A32h per unit 01A32h per unit 01A33h per unit 01A33h per unit 01A34h per unit 01A34h per unit 01A35h per unit 01A35h per unit 01A36h per unit 01A36h per unit 01A37h per unit 01A37h per unit 01A38h per unit 01A38h per unit REF 1.2-V Reference REF 2.0-V Reference REF 2.5-V Reference Random Number 128-bit Random Number (4) BSL Configuration (3) (4) MSP430FR59xx1 (I2C BSL) Value ADC Offset (3) REF Calibration MSP430FR59xx (UART BSL) Address 01A39h per unit 01A39h per unit 01A3Ah per unit 01A3Ah per unit 01A3Bh per unit 01A3Bh per unit 01A3Ch per unit 01A3Ch per unit 01A3Dh per unit 01A3Dh per unit 01A3Eh per unit 01A3Eh per unit 01A3Fh per unit 01A3Fh per unit BSL Tag 01A40h 1Ch 01A40h 1Ch BSL length 01A41h 02h 01A41h 02h BSL Interface 01A42h 00h 01A42h 01h ADC Offset: the offset correction factor is measured at room temperature using ADC12VRSEL= 0x2 or 0x4, an external reference, VR+ = external 2.5V, VR- = AVSS. 128-bit Random Number: The random number is generated during production test. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 107 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Table 6-62. Device Descriptor Table MSP430FR59xx(1)(1) (continued) Description BSL Interface Configuration MSP430FR59xx (UART BSL) MSP430FR59xx1 (I2C BSL) Address Value Address Value 01A43h 00h 01A43h 48h 6.13 Identification 6.13.1 Revision Identification The device revision information is shown as part of the top-side marking on the device package. The device-specific erratasheet describes these markings. For links to all of the erratasheets for the devices in this data sheet, see Section 8.2. The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For details on this value, see the "Hardware Revision" entries in Section 6.12. 6.13.2 Device Identification The device type can be identified from the top-side marking on the device package. The device-specific erratasheet describes these markings. For links to all of the erratasheets for the devices in this data sheet, see Section 8.2. A device identification value is also stored in the Device Descriptor structure in the Info Block section. For details on this value, see the "Device ID" entries in Section 6.12. 6.13.3 JTAG Identification Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in detail in the MSP430 Programming Via the JTAG Interface User's Guide (SLAU320). 108 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 7 Applications, Implementation, and Layout 7.1 Device Connection and Layout Fundamentals This section discusses the recommended guidelines when designing with the MSP430. These guidelines are to make sure that the device has proper connections for powering, programming, debugging, and optimum analog performance. 7.1.1 Power Supply Decoupling and Bulk Capacitors It is recommended to connect a combination of a 1-µF plus a 100-nF low-ESR ceramic decoupling capacitor to each AVCC and DVCC pin. Higher-value capacitors may be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few millimeters). Additionally, separated grounds with a single-point connection are recommend for better noise isolation from digital to analog circuits on the board and are especially recommended to achieve high analog accuracy. DVCC Digital Power Supply Decoupling + 1 µF 100 nF DVSS AVCC Analog Power Supply Decoupling + 1 µF 100 nF AVSS Figure 7-1. Power Supply Decoupling 7.1.2 External Oscillator Depending on the device variant (see Section 3), the device can support a low-frequency crystal (32 kHz) on the LFXT pins, a high-frequency crystal on the HFXT pins, or both. External bypass capacitors for the crystal oscillator pins are required. It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes. If they are left unused, they must be terminated according to Section 4.8. Figure 7-2 shows a typical connection diagram. LFXIN or HFXIN CL1 LFXOUT or HFXOUT CL2 Figure 7-2. Typical Crystal Connection See the application report MSP430 32-kHz Crystal Oscillators (SLAA322) for more information on selecting, testing, and designing a crystal oscillator with the MSP430 devices. Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 109 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 7.1.3 www.ti.com JTAG With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the connections also support the MSP-GANG production programmers, thus providing an easy way to program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG connector and the target device required to support in-system programming and debugging for 4-wire JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire). The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSPFET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the target board (that is, a battery or other local power supply) and adjusts the output signals accordingly. Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the target board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the jumper block. Pins 2 and 4 must not be connected at the same time. For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s Guide (SLAU278). VCC Important to connect MSP430FRxxx J1 (see Note A) AVCC/DVCC J2 (see Note A) R1 47 kW JTAG VCC TOOL VCC TARGET 2 1 4 3 6 TEST RST/NMI/SBWTDIO 5 8 7 10 9 12 11 14 13 TDO/TDI TDO/TDI TDI TDI TMS TCK TMS TCK GND RST TEST/SBWTCK C1 2.2 nF (see Note B) A. B. AVSS/DVSS If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used, make connection J2. The upper limit for C1 is 2.2 nF when using current TI tools. Figure 7-3. Signal Connections for 4-Wire JTAG Communication 110 Applications, Implementation, and Layout Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 VCC Important to connect MSP430FRxxx J1 (see Note A) AVCC/DVCC J2 (see Note A) R1 47 kΩ See Note B JTAG VCC TOOL VCC TARGET 2 1 4 3 6 5 8 7 10 9 12 11 14 13 TDO/TDI RST/NMI/SBWTDIO TCK GND TEST/SBWTCK C1 2.2 nF See Note B A. B. AVSS/DVSS Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the debug or programming adapter. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with the device. The upper limit for C1 is 2.2 nF when using current TI tools. Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire) 7.1.4 Reset The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function Register (SFR), SFRRPCR. In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing specifications generates a BOR-type device reset. Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the external NMI. When an external NMI event occurs, the NMIIFG is set. The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not. If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an external 47-kΩ pullup resistor to the RST/NMI pin with a 2.2-nF pulldown capacitor. The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers. See the device family user’s guide (SLAU367) for more information on the referenced control registers and bits. 7.1.5 Unused Pins For details on the connection of unused pins, see Section 4.8. Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 111 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 7.1.6 www.ti.com General Layout Recommendations • • • • 7.1.7 Proper grounding and short traces for external crystal to reduce parasitic capacitance. See the application report MSP430 32-kHz Crystal Oscillators (SLAA322) for recommended layout guidelines. Proper bypass capacitors on DVCC, AVCC, and reference pins if used. Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital switching signals such as PWM or JTAG signals away from the oscillator circuit. Proper ESD level protection should be considered to protect the device from unintended high-voltage electrostatic discharge. See the application report MSP430 System-Level ESD Considerations (SLAA530) for guidelines. Do's and Don'ts It is recommended to power AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits specified in the Absolute Maximum Ratings section. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM. 7.2 Peripheral- and Interface-Specific Design Information 7.2.1 ADC12_B Peripheral 7.2.1.1 Partial Schematic AVSS Using an External Positive Reference Using an External Negative Reference VREF+/VEREF+ + 10 µF 4.7 µF VEREF+ 10 µF 4.7 µF Figure 7-5. ADC12_B Grounding and Noise Considerations 7.2.1.2 Design Requirements As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise. Ground loops are formed when return current from the ADC flows through paths that are common with other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the ADC. The general guidelines in Section 7.1.1 combined with the connections shown in Section 7.2.1.1 prevent this. In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital switching or switching power supplies can corrupt the conversion result. A noise-free design using separate analog and digital ground planes with a single-point connection is recommend to achieve high accuracy. Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The internal reference module has a maximum drive current as specified in the Reference module's IO(VREF+) specification. 112 Applications, Implementation, and Layout Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage enters the device. In this case, the 10-µF capacitor is used to buffer the reference pin and filter any lowfrequency ripple. A bypass capacitor of 4.7 µF is used to filter out any high frequency noise. 7.2.1.3 Detailed Design Procedure For additional design information, see the application report Designing With the MSP430FR58xx, FR59xx, FR68xx, and FR69xx ADC (SLAA624). 7.2.1.4 Layout Guidelines Component that are shown in the partial schematic (see Figure 7-5) should be placed as close as possible to the respective device pins. Avoid long traces, because they add additional parasitic capacitance, inductance, and resistance on the signal. Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM), because the high-frequency switching can be coupled into the analog signal. If differential mode is used for the ADC12_B, the analog differential input signals must be routed closely together to minimize the effect of noise on the resulting signal. Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 113 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com 8 Device and Documentation Support 8.1 Device Support 8.1.1 Development Tools Support All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools. 8.1.1.1 Hardware Features See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features. See the application reports Advanced Debugging Using the Enhanced Emulation Module (EEM) With Code Composer Studio Version 6 (SLAA393) and MSP430™ Advanced Power Optimizations: ULP Advisor™ and EnergyTrace™ Technology (SLAA603) for further usage information. MSP430 Architecture 4-Wire JTAG 2-Wire JTAG Breakpoints (N) Range Breakpoints Clock Control State Sequencer Trace Buffer LPMx.5 Debugging Support Energy Trace++ MSP430Xv2 Yes Yes 3 Yes Yes No No Yes Yes EnergyTrace technology is supported with Code Composer Studio version 6.0 and newer. It requires specialized debugger circuitry, which is supported with the second-generation on-board eZ-FET flash emulation tool and second-generation standalone MSP-FET JTAG emulator. See the MSP430™ Advanced Power Optimizations: ULP Advisor™ and EnergyTrace™ Technology (SLAA603) application report, the Code Composer Studio for MSP430 User's Guide (SLAU157), and the MSP430 Hardware Tools User's Guide (SLAU278) for more detailed information. 8.1.1.2 Recommended Hardware Options 8.1.1.2.1 Target Socket Boards The target socket boards allow easy programming and debugging of the device using JTAG. They also feature header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the JTAG programmer and debugger included. The following table shows the compatible target boards and the supported packages. See the MSP430 Hardware Tools User's Guide (SLAU278) for board design information. Package Target Board and Programmer Bundle Target Board Only 48-pin QFN (RGZ) MSP-FET430U48C MSP-TS430RGZ48C 8.1.1.2.2 Experimenter Boards Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature additional hardware components and connectivity for full system evaluation and prototyping. See www.ti.com/msp430tools for details. This device is supported on the MSP430FR5969 LaunchPad Evaluation Kit (MSP-EXP430FR5969). 8.1.1.2.2.1 MSP430FR5969 LaunchPad Evaluation Kit With Sharp® Memory LCD BoosterPack Bundle The MSP-BNDL-FR5969LCD (MSP-EXP430FR5969 LaunchPad Evaluation Kit with 430BOOSTSHARP96 LCD Display BoosterPack) kit is an easy-to-use Evaluation Module for the MSP430FR5969 microcontroller. It contains everything needed to start developing on a MSP430 FRAM Technology platform, including on-board emulation for programming and debugging. The board features on-board buttons and LEDs for quick integration of a simple user interface as well as a SuperCap allowing standalone RTC operation without an external power supply. 114 Device and Documentation Support Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 8.1.1.2.3 Debugging and Programming Tools Hardware programming and debugging tools are available from TI and from its third-party suppliers. See the full list of available tools at www.ti.com/msp430tools. Part Number PC Port Features Provider MSP-FET USB Fast download and debugging. Supports EnergyTrace++ Technology. Compatible with 4-wire JTAG and 2-wire Spy-Bi-Wire (SBW) JTAG modes. Small form factor. Texas Instruments MSP-FET430UIF USB Legacy interface – superseded by MSP-FET. Compatible with 4-wire JTAG and 2-wire Spy-Bi-Wire (SBW) JTAG modes. Texas Instruments 8.1.1.2.4 Production Programmers The production programmers expedite loading firmware to devices by programming several devices simultaneously. Part Number PC Port MSP-GANG Serial and USB 8.1.1.3 Features Program up to eight devices at a time. Works with PC or standalone. Provider Texas Instruments Recommended Software Options 8.1.1.3.1 Integrated Development Environments Software development tools are available from TI or from third parties. Open-source solutions are also available. See the full list of available tools at www.ti.com/msp430tools. This device is supported by the Code Composer Studio™ IDE (CCS). See the MSP Debug Stack (MSPDS) landing page (www.ti.com/mspds) for useful information about debugging tools. 8.1.1.3.2 MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and other design resources for all MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing MSP430 design resources, MSP430Ware software also includes a high-level API called MSP430 Driver Library. This library makes it easy to program MSP430 hardware. MSP430Ware software is available as a component of CCS or as a standalone package. 8.1.1.3.3 Command-Line Programmer MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher can be used to download binary files (.txt or .hex) files directly to the MSP430 microcontroller without the need for an IDE. 8.1.2 Device and Development Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of three prefixes: MSP, PMS, or XMS (for example, MSP430FR59691). Texas Instruments recommends two of three possible prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully qualified production devices and tools (with MSP for devices and MSP for tools). Device development evolutionary flow: XMS – Experimental device that is not necessarily representative of the final device's electrical specifications MSP – Fully qualified production device Device and Documentation Support Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 115 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 www.ti.com Support tool development evolutionary flow: MSPX – Development-support product that has not yet completed Texas Instruments internal qualification testing. MSP – Fully-qualified development-support product XMS devices and MSPX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." MSP devices and MSP development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PZP) and temperature range (for example, T). Figure 8-1 provides a legend for reading the complete device name for any family member. MSP 430 FR 5 9691 I RGZ T Feature Set Processor Family 430 MCU Platform Optional: Distribution Format Device Type Packaging Series AES Oscilators, ADC Ch, I/O Processor Family MSP = Mixed Signal Processor XMS = Experimental Silicon 430 MCU Platform TI’s 16-bit Low-Power Microcontroller Platform Device Type Memory Type FR = FRAM Series FRAM 5 Series = Up to 16 MHz Feature Set First Digit - AES 9 = AES 8 = No AES Optional: Temperature Range S = 0°C to 50°C I = -40°C to 85°C T = -40°C to 105°C Optional: Temperature Range Optional: BSL FRAM Second Digit - Oscilators, ADC Channels, I/O 6 = DCO/HFXT/LFXT, 16, 40 5 = DCO/LFXT, 14/12, 33/31 4 = DCO/HFXT, 14/12, 33/31 Packaging www.ti.com/packaging Optional: Distribution Format T = Small Reel (7 inch) R = Large Reel (11 inch) No Markings = Tube or Tray Optional: Additional Features -Q1 = Automotive Qualified -EP = Enhanced Product (-40°C to 105°C) -HT = Extreme Temperature Parts (-55°C to 150°C) Third Digit - FRAM (KB) 9 = 64 8 = 48 7 = 32 Optional Fourth Digit - BSL 2 1=IC No value = UART Figure 8-1. Device Nomenclature 116 Device and Documentation Support Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com 8.2 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 Documentation Support The following documents describe the MSP430FR59xx MCUs. Copies of these documents are available on the Internet at www.ti.com. 8.2.1 SLAU367 MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide. Detailed description of all modules and peripherals available in this device family. SLAZ473 MSP430FR5969 Device Erratasheet. Describes the known exceptions to the functional specifications for each silicon revision of this device. SLAZ601 MSP430FR59691 Device Erratasheet. Describes the known exceptions to the functional specifications for each silicon revision of this device. SLAZ472 MSP430FR5968 Device Erratasheet. Describes the known exceptions to the functional specifications for each silicon revision of this device. SLAZ471 MSP430FR5967 Device Erratasheet. Describes the known exceptions to the functional specifications for each silicon revision of this device. SLAZ469 MSP430FR5959 Device Erratasheet. Describes the known exceptions to the functional specifications for each silicon revision of this device. SLAZ468 MSP430FR5958 Device Erratasheet. Describes the known exceptions to the functional specifications for each silicon revision of this device. SLAZ467 MSP430FR5957 Device Erratasheet. Describes the known exceptions to the functional specifications for each silicon revision of this device. SLAZ465 MSP430FR5949 Device Erratasheet. Describes the known exceptions to the functional specifications for each silicon revision of this device. SLAZ464 MSP430FR5948 Device Erratasheet. Describes the known exceptions to the functional specifications for each silicon revision of this device. SLAZ463 MSP430FR5947 Device Erratasheet. Describes the known exceptions to the functional specifications for each silicon revision of this device. SLAZ602 MSP430FR59471 Device Erratasheet. Describes the known exceptions to the functional specifications for each silicon revision of this device. Related Links Table 8-1 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 8-1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY MSP430FR5969 Click here Click here Click here Click here Click here MSP430FR59691 Click here Click here Click here Click here Click here MSP430FR5968 Click here Click here Click here Click here Click here MSP430FR5967 Click here Click here Click here Click here Click here MSP430FR5959 Click here Click here Click here Click here Click here MSP430FR5958 Click here Click here Click here Click here Click here MSP430FR5957 Click here Click here Click here Click here Click here MSP430FR5949 Click here Click here Click here Click here Click here MSP430FR5948 Click here Click here Click here Click here Click here MSP430FR5947 Click here Click here Click here Click here Click here MSP430FR59471 Click here Click here Click here Click here Click here Device and Documentation Support Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Copyright © 2012–2014, Texas Instruments Incorporated 117 MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 8.2.2 www.ti.com Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 8.3 Trademarks EnergyTrace++, MSP430, Code Composer Studio, MSP430Ware are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 8.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.5 Export Control Notice Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from Disclosing party under this Agreement, or any direct product of such technology, to any destination to which such export or reexport is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws. 8.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 9 Mechanical Packaging and Orderable Information 9.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 118 Mechanical Packaging and Orderable Information Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 PACKAGE OPTION ADDENDUM www.ti.com 11-Jul-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) MSP430FR59471IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR59471 MSP430FR59471IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR59471 MSP430FR5947IDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5947 MSP430FR5947IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5947 MSP430FR5947IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5947 MSP430FR5947IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5947 MSP430FR5948IDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5948 MSP430FR5948IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5948 MSP430FR5948IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5948 MSP430FR5948IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5948 MSP430FR5949IDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5949 MSP430FR5949IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5949 MSP430FR5949IRHAR ACTIVE VQFN RHA 40 1 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5949 MSP430FR5949IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5949 MSP430FR5957IDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5957 MSP430FR5957IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5957 MSP430FR5957IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5957 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Jul-2014 Status (1) (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) MSP430FR5957IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5957 MSP430FR5958IDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5958 MSP430FR5958IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5958 MSP430FR5958IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5958 MSP430FR5958IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5958 MSP430FR5959IDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5959 MSP430FR5959IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5959 MSP430FR5959IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5959 MSP430FR5959IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5959 MSP430FR5967IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5967 MSP430FR5967IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5967 MSP430FR5968IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5968 MSP430FR5968IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5968 MSP430FR59691IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR59691 MSP430FR59691IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR59691 MSP430FR5969IRGZR ACTIVE VQFN RGZ 48 1 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5969 MSP430FR5969IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5969 The marketing status values are defined as follows: Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Jul-2014 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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