ETC OCX160 Ocx160 crosspoint switch Datasheet

OCX160 Crosspoint Switch
Preliminary Data Sheet
Features
•
•
•
•
667 Mb/s port data bandwidth, >50Gb/s aggregate bandwidth
Low power CMOS, 2.5V and 3.3V power supply
SRAM-based, in-system programmable
160 configurable I/O ports
– 80 dedicated differential input ports
– 80 dedicated differential output ports
– Supports LVDS and LVPECL I/O
– LVTTL control interface
– Output Enable control for all outputs
• Non-blocking switch matrix
– Patented ActiveArray™ matrix for superior performance
– Double-buffered configuration RAM cells for simultaneous
global updates
– ImpliedDisconnect™ function for single cycle disconnect/
connect
• Full Broadcast and multicast capability
– One-to-One and One-to-Many connections
– Special broadcast mode routes one input to
all outputs at maximum data rate
• Registered and flow-through data modes
– 333 MHz synchronous mode
– 667 Mb/s asynchronous mode
– Low jitter and signal skew
– Low duty cycle distortion
• RapidConfigure™ parallel interface for
configuration and readback
• JTAG serial interface for configuration and
Boundary Scan testing
• 420 BGA package with 1.27mm ball spacing
Description
The OCX™ family of SRAM-based devices are non-blocking n X n digital crosspoint switches capable of data
rates of 667 Megabits per second per port. The I/O ports are fixed as either input or output ports. The input ports
support flow-through mode only. The output ports are individually programmable to operate in either flowthrough (asynchronous) or registered (synchronous) mode. Each output register may be clocked by a global
clock or a next neighbor clock source.
The patented ActiveArray provides greater density, superior performance, and greater flexibility compared to a
traditional n:1 multiplexer architecture. The OCX devices support various operating modes covering one input to
one output at a time as well as one input to many outputs, plus a special broadcast mode to program one input to
all outputs while maintaining maximum data rates. In all modes data integrity and connections are maintained on
all unchanged data paths.
The RapidConfigure parallel interface allows fast configuration of both the Output Buffers and the switch
matrix. Readback is supported for device test and verification purposes. The OCX160 also supports the industry
standard JTAG (IEEE 1149.1) interface for boundary scan testing. The JTAG interface can also be used to
download configuration data to the device and readback data. A functional block diagram of the OCX160 is
shown in Figure 1.
Applications
• SONET/SDH and DWDM
• Digital Cross-Connects
• System Backplanes and Interconnects
• High Speed Test Equipment
160
160
OUT[79:0]
IN[79:0]
Input
Buffers
RapidConfigure
Signals
RCA[6:0] 7
RCB[6:0] 7
RCI[3:0] 4
RCO[4:0] 5
RC_CLK#
RC_EN#
• ATM Switch Cores
• Video Switching
80 x 80
Crosspoint
Switch Matrix
Output
Buffers
Configuration and
Programming Logic
2 CLK
OE#
TCK
TMS
TDI
TRST#
TDO
JTAG
Signals
HW_RST#
UPDATE#
Figure 1 OCX160 Functional Block Diagram
I-Cube, Inc.
[Rev. 1.6] 2/20/01
1
OCX160 Crosspoint Switch—Preliminary Data Sheet
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[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
Contents
1.
Introduction ........................................................................................................................... 7
1.1
Input and Output Buffers...................................................................................................... 8
1.1.1
Input and Output Port Function Mode ........................................................................... 8
1.1.2
Broadcast Mode ............................................................................................................. 9
1.2
Output Buffer Configuration ................................................................................................ 9
1.2.1
Output Control Signals................................................................................................... 9
1.2.2
Neighboring Output Port as a Clock Source .................................................................. 9
1.3
RapidConfigure Interface ....................................................................................................11
1.3.1
RapidConfigure Programming Instructions.................................................................. 11
1.3.2
ImpliedDisconnect ....................................................................................................... 13
1.4
JTAG Configuration Controller.......................................................................................... 14
1.4.1
JTAG Interface............................................................................................................. 14
1.4.2
Output Port Configuration ........................................................................................... 14
1.4.3
Switch Matrix Configuration ....................................................................................... 14
1.4.4
Mode Control Register Configuration.......................................................................... 14
1.4.5
JTAG Architecture and Shift Registers ........................................................................ 15
1.4.6
JTAG State Machine .................................................................................................... 16
1.4.7
JTAG Input Format ...................................................................................................... 16
1.4.8
JTAG Instructions ........................................................................................................ 17
1.5
Device Reset Options ......................................................................................................... 20
2.
Pin Description .....................................................................................................................21
3.
Differential I/O Standards ...................................................................................................22
3.1
LVDS ................................................................................................................................. 22
3.2
LVPECL ............................................................................................................................. 23
3.3
Termination Resistor Packs ................................................................................................ 24
3.4
Mixed I/O Systems............................................................................................................. 24
4.
Electrical Specifications .......................................................................................................25
4.1
Absolute Maximum Ratings .............................................................................................. 25
4.2
Recommended Operating Conditions ................................................................................ 25
I-Cube, Inc.
[Rev. 1.6] 2/20/01
3
OCX160 Crosspoint Switch—Preliminary Data Sheet
4.3
Pin Capacitance ................................................................................................................. 25
4.4
DC Electrical Specifications............................................................................................... 26
4.5
AC Electrical Specifications............................................................................................... 27
4.6
Timing Diagrams................................................................................................................ 28
5.
Package and Pinout ............................................................................................................. 32
5.1
Package Pinout ................................................................................................................... 32
5.2
Pinout by Ball Sequence..................................................................................................... 33
5.3
Pinout by Ball Name .......................................................................................................... 36
5.4
Package Dimensions........................................................................................................... 38
5.5
Package Thermal Characteristics........................................................................................ 39
6.
4
Power Consumption ............................................................................................................ 40
6.1
Power for LVDS I/O .......................................................................................................... 40
6.2
Power for LVPECL I/O ..................................................................................................... 41
7.
Component Availability and Ordering Information ......................................................... 42
8.
Glossary ................................................................................................................................ 42
9.
Product Status Definition .................................................................................................... 44
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
Figures
Figure 1
OCX160 Functional Block Diagram .................................................................................................... 1
Figure 2
OCX160 Switch Matrix ........................................................................................................................ 7
Figure 3
Input and Output Buffer Configuration ................................................................................................ 8
Figure 4
Next Neighbor Clock Block Diagram ................................................................................................ 10
Figure 5
OCX160 JTAG Architecture .............................................................................................................. 15
Figure 6
OCX160 JTAG State Machine ........................................................................................................... 16
Figure 7
Transmitting LVDS Signal Circuit ..................................................................................................... 22
Figure 8
Receiving LVDS Signal Circuit ......................................................................................................... 22
Figure 9
Transmitting LVPECL Signal Circuit ................................................................................................ 23
Figure 10
Receiving LVPECL Signal Circuit..................................................................................................... 23
Figure 11
Registered Output Mode Timing ........................................................................................................ 28
Figure 12
Flow-Through Mode Timing .............................................................................................................. 28
Figure 13
Output Enable Timing ........................................................................................................................ 28
Figure 14
Duty Cycle Distortion ......................................................................................................................... 29
Figure 15
RapidConfigure Write Cycle .............................................................................................................. 29
Figure 16
RapidConfigure Read Cycle ............................................................................................................... 30
Figure 17
JTAG Timing ...................................................................................................................................... 30
Figure 18
Typical Performance LVDS mode ..................................................................................................... 31
Figure 19
Typical Performance LVPECL mode................................................................................................. 31
Figure 20
OCX160 Package Pinout .................................................................................................................... 32
Figure 21
OCX160 Package—Bottom, Top and Side Views ............................................................................. 38
Figure 22
Power Consumption Diagram for the OCX160 using LVDS............................................................. 40
Figure 23
Power Consumption Diagram for the OCX160 using LVPECL........................................................ 41
I-Cube, Inc.
[Rev. 1.6] 2/20/01
5
OCX160 Crosspoint Switch—Preliminary Data Sheet
Tables
6
Table 1
Summary for Programmable I/O Attributes for OCX160 ................................................................. 8
Table 2
Next Neighbor Outputs.................................................................................................................... 10
Table 3
RapidConfigure Programming Instructions .................................................................................... 11
Table 4
RCO[4:0] Readback Pin Assignment.............................................................................................. 13
Table 5
Programming an Output Buffer using RapidConfigure .................................................................. 13
Table 6
Mode Control Register .................................................................................................................... 14
Table 7
JTAG Input Format ......................................................................................................................... 16
Table 8
JTAG Instructions ........................................................................................................................... 17
Table 9
Programming an Output using JTAG.............................................................................................. 19
Table 10
Number of JTAG Cycles and Configuration Time ......................................................................... 19
Table 11
Device Reset Options ...................................................................................................................... 20
Table 12
OCX160 Pin Description................................................................................................................. 21
Table 13
Termination Resistor Packs............................................................................................................. 24
Table 14
Supply Voltages and Terminating Resistors ................................................................................... 24
Table 15
Absolute Maximum Ratings............................................................................................................ 25
Table 16
Recommended Operating Conditions.............................................................................................. 25
Table 17
Pin Capacitance ............................................................................................................................... 25
Table 18
LVTTL DC Electrical Specifications.............................................................................................. 26
Table 19
LVDS DC Electrical Specifications ................................................................................................ 26
Table 20
LVPECL DC Electrical Specifications ........................................................................................... 26
Table 21
AC Electrical Specifications............................................................................................................ 27
Table 22
OCX160 Pinout By Ball Sequence.................................................................................................. 33
Table 23
OCX160 Pinout By Ball Name ....................................................................................................... 36
Table 24
Package Thermal Coefficients......................................................................................................... 39
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
1. Introduction
The OCX160 is a differential crosspoint-switching device. The main functional block of the device is a Switch
Matrix as shown in Figure 1. The Switch Matrix is a x-y structure supporting an input-to-output data flow.
Figure 2 shows a conceptual view of the switch matrix with inputs connected to the horizontal trace and outputs
to the vertical trace. Connections between vertical and horizontal lines are implemented with a proprietary highperformance buffering circuit. Signal path delays through the Switch Matrix are very well balanced, resulting in
predictable and uniform pin-to-pin delays.
Note – For the purpose of clarity, the logic diagrams within this data sheet are conceptual
representations only and do not show actual circuit implementation.
Data
Loading
SRAM
Cell
Active
SRAM
Cell
UPDATE#
Proprietary High-performance
Buffering Circuit
Figure 2
OCX160 Switch Matrix
The Active SRAM cells are responsible for establishing connections in the switch matrix by turning on the
interconnect circuit, while the Loading SRAM cell can be used to store a second configuration that can be
transferred to the Active SRAM cell at a later time. The two SRAM cells are arranged so that a double buffered
scheme can be employed. Through the use of an internal signal (generated automatically during a programming
cycle) it is possible to store a second configuration map in the Loading SRAM while the Active SRAM
maintains its present connection status. When the UPDATE# signal is asserted low, the contents of the Loading
SRAM cell are transferred to the Active SRAM cell and the switch matrix connection is either made or broken.
The UPDATE# signal can be used to control when the switch matrix is reconfigured. For instance, as long as the
UPDATE# signal is asserted high, the Loading SRAM cells for the entire switch matrix could be changed
without affecting the current configuration of the switch. When the UPDATE# signal is asserted low, the entire
switch matrix would be reconfigured simultaneously. If the UPDATE# signal is asserted continuously, all
crosspoint programming commands (generated by RapidConfigure or JTAG programming cycles) will take
effect immediately, since the Loading SRAM cell’s contents will be transferred directly to the Active SRAM
cell.
I-Cube, Inc.
[Rev. 1.6] 2/20/01
7
OCX160 Crosspoint Switch—Preliminary Data Sheet
1.1 Input and Output Buffers
All of the input buffers are differential inputs with flow-through mode. The output buffers are
programmable for either flow-through or registered mode. Figure 3 shows the basic block diagram of the
input and output blocks with the sources for the output control signals (OE# and CLK). The control signals
are explained in more details in the following sections.
Output Mode
Select
Input
Switch
Matrix
Output
D
Q
OE#
CLK
Next
Neighbor
Clock
Select
Figure 3
Input and Output Buffer Configuration
1.1.1 Input and Output Port Function Mode
The following legend describes the various modes of the Input and Output Ports and the
specification used by the OCXPro™ Software.
Legend:
Ax–Switch Matrix Signal
Px–Port Signal
OE#–Output Enable (# means “Active Low”)
CLK–Clock
Table 1
Summary for Programmable I/O Attributes for OCX160
Symbol
Px
Ax
Px
Ax
I/O Port Function
Mnemonic
Input – The external signal is buffered from the Input Port pin
to the corresponding Switch Matrix line.
IN
Output – The internal signal is buffered from the
corresponding Switch Matrix line to the Output Port pin. In
this mode an optional output enable (OE#) can be selected.
The default state is logic high with enable set to ON.
OP
Registered Output – The internal signal on the Switch Matrix
line is registered by an edge-triggered register within the
Output Port. A clock source is required in this mode. An
output enable (OE#) is available but not required.
RO
No Connect – In this mode, the output Port pin is isolated
from the Switch Matrix.
NC
OE#
Ax
D
Px
Q
CLK
OE#
Ax
8
Px
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
1.1.2
Broadcast Mode
The OCX160 has a special Broadcast Mode which connects any input to all outputs without
performance degradation. The input is selected using RapidConfigure or JTAG and disconnects
all other inputs. The Global Update pin (UPDATE#) must be held high during Broadcast Mode.
Asserting the UPDATE# pin returns the array to the previous program condition.
1.2 Output Buffer Configuration
Every output port of the OCX160 can be configured as either a flow-through or registered output. In
registered mode there are two clock sources that are available:
•
•
Global Clock
Next Neighbor
Additionally, there are output control signals.
1.2.1
Output Control Signals
Every output port of the OCX has a global Output Enable signal (OE#). All output buffers have
output enables that have programmable polarity and are individually configurable.
Additionally each output can be permanently enabled (always ON) or disabled (always OFF)
which is useful for applications which need to tri-state outputs (for example when using multiple
chips in expansion mode) or for power saving in designs that do not need to use all the outputs
available.
Two control bits are used to control the function of the output enable function as described in
Table 5.
1.2.2
Neighboring Output Port as a Clock Source
A physically adjacent port can be used as a clock source for an output port configured in
registered mode. These outputs are grouped in pairs such that the signal being switched through
OUT0 can be used to clock the signal being switched through OUT1, and vice versa. Any single
clock or data input signal can be used to clock any other input signal provided they are switched
to an appropriate output pair (see Table 2). Figure 4 shows the implementation of next neighbor
output port clocking in the OCX160 switch.
For example, INx is used for data input while INy is used for the corresponding clock. INx is
connected to OUT0 via the crosspoint array while INy is connected to OUT1 via the crosspoint
array. OUT0 is configured in registered output (RO) mode with OUT1 as its next neighbor clock
selection. OUT1 will output the clock signal as well as clock the data in OUT0. Adjacent port
selection is required for next neighbor clocking in the registered output mode.
This feature is useful in many applications where different types of data switching through the
crosspoint array have various associated clocks. To match the delays in the data and
corresponding clocks, it is common practice to pass the clocks through the switch along with the
data.
I-Cube, Inc.
[Rev. 1.6] 2/20/01
9
OCX160 Crosspoint Switch—Preliminary Data Sheet
Crosspoint
Array
Output Mode
Select
Any Input
Port
(INx)
OUT0
D
Q
CLK
Next
Neighbor
OE#
Clock
Select
Output Mode
Select
Any Input
Port
(INy)
OUT1
D
Q
CLK
Next
Neighbor
OE#
Clock
Select
Figure 4
Next Neighbor Clock Block Diagram
The advantages of next neighbor clocking are:
1. Using next neighbor clocking in the registered output (RO) mode helps reduce the
skew in outgoing data.
2. For a design with a large number of outputs switching simultaneously, next neighbor
clocking mode is useful to stagger outputs for reduced board noise caused by
simultaneous switching outputs.
Note – Selecting the next neighbor clock for both outputs at the same time is not recommended.
Only one output in the pair at a time can be clocked by its next neighbor.
Table 2
Next Neighbor Outputs
Pairing Sequence for Neighboring Outputs
Output Next Neighbor Pairs
0,1
2,3
4,5
6,7
8,9
◗ ◗ ◗ ◗ 76,77
78,79
Only OUT1 can neighbor with OUT0, OUT3 with OUT2, etc. OUT2 cannot neighbor with OUT1,
or OUT4 with OUT3, etc.
10
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
1.3 RapidConfigure Interface
RapidConfigure (RC) is a 25 signal parallel interface that is used to program the OCX160 device. The 25
pins are allocated as follows:
RCA[6:0] = RapidConfigure Address A. RCA are input pins.
RCB[6:0] = RapidConfigure Address B. RCB are input pins.
RCI[3:0] = RapidConfigure Instruction Bits
RCO[4:0] = RapidConfigure Readback. RCO are output pins.
RC_CLK# = RapidConfigure Clock (negative edge clock)
RC_EN# = RapidConfigure Cycle Enable (active low)
1.3.1
RapidConfigure Programming Instructions
The RC interface supports both write and read types of operations:
1. Write Operations (reset crosspoint and Input or Output Buffer (IOB), configure an
Output Buffer, connect/disconnect crosspoint)
2. Read Operations (Output Buffer and crosspoint configuration read).
Table 3
RCI[3:0]
RCA[6:0]
RapidConfigure Programming Instructions
RCB[6:0]
RCO[4:0]
Instruction
0000
Reserved
0001
Reserved
Description
0010
X
X
Reset Crosspoint
Array
Reset the entire crosspoint array to no
connect. All Output Buffers remain
unchanged by this operation.
0011
X
Input Port
Address
Set Array to Broadcast
mode
Connects the input selected by RCB[6:0]
to all output ports and disconnects all
other inputs. The Global Update
(UPDATE#) pin must be held high
during Broadcast mode. Activating the
Global Update pin returns the array to
the previous program condition.
0100
Output Port
Address
Data
Configure an Output
Buffer
Program an Output Buffer specified by
RCA[6:0].
See Table 5 for RCB[6:0] bit assignment
and buffer functionality.
0101
Cycle 1
I-Cube, Inc.
Readback Crosspoint,
Output Buffer status
Output Port
Address
Intput Port
Address
X
[Rev. 1.6] 2/20/01
This is a two-cycle instruction.
Specify the crosspoint connect status at
input location specified by RCA[6:0] to
the output location specified by
RCB[6:0].
11
OCX160 Crosspoint Switch—Preliminary Data Sheet
Table 3
RapidConfigure Programming Instructions (Continued)
RCI[3:0]
RCA[6:0]
RCB[6:0]
RCO[4:0]
Cycle 2
X
X
Output Data
Instruction
Description
Readback (using RCO[4:0]) the status of
the input buffer specified in Cycle 1 by
RCA[6:0], the output buffer specified in
Cycle 1 by RCO[4:0] and the crosspoint
connect status.
See Table 4 for RCO[4:0] readback pin
assignment.
0110
X
X
Update
Program the Global Update function
without the use of the UPDATE# pin.
0111
X
Input Port
Address
Disconnect Input
Disconnect the crosspoint cells of the
input row location specified by
RCA[6:0].
1000
Output Port
Address
Input Port
Address
Disconnect Input and
Output
Disconnect the crosspoint cell at the
input location specified by RCA[6:0] to
the output location specified by
RCB[6:0].
All other connections from the source
input address or to the same output
address remain the same as before.
1001
Output Port
Address
Input Port
Address
Connect, with
ImpliedDisconnect
Connect the crosspoint cell at the input
location specified by RCA[6:0] to the
output location specified by RCB[6:0].
All other connections from the same
input address or to the same output
address are set to no connect (NC).
1010
Output Port
Address
Input Port
Address
Connect, without
ImpliedDisconnect
Connect the crosspoint cell at the input
location specified by RCA[6:0] to the
output location specified by RCB[6:0].
All other connections from the same
input address remain the same as before.
1011
Reserved
1100
Reserved
1101
X
X
Reset All
1110
Reserved
1111
Reserved
Reset the switch matrix to no connects
(NC). Output Buffers default to flowthrough mode (OP) with output enable
set to always enabled (ON). Output
Buffer defaults to select Global Clock
(CLK) source even though mode is OP.
Note – X = Don’t care.
12
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
Table 4
RCO[4:0] Readback Pin Assignment
RCO[4:0]
Readback Location
O4
Crosspoint
O3
Output Buffer
Clock Select:
0 = Global Clock — (default state at reset)
1 = Next Neighbor
O2
Output Buffer
Output Mode:
0 = Flow-through (OP) — (default state at reset)
1 = Registered (RO)
O1, O0
0,0
0,1
1,0
1,1
Output Buffer
Output Enable:
Output enabled (ON) – this is the default state at reset
Output disabled (OFF)
Output controlled by OE (active high)
Output controlled by OE# (active low)
Table 5
Signal/Function
Connection Status:
0 = No connection (NC) — (default state at reset)
1 = Connected
Programming an Output Buffer using RapidConfigure
RCB[6:0]
B6, B5, B4
B3
Clock Select:
0 = Global Clock
1 = Next Neighbor
B2
Output Mode:
0 = Flow-through (OP)
1 = Registered (RO)
B1, B0
0,0
0,1
1,0
1,1
1.3.2
Signal/Function
Don’t care
Output Enable:
Output enabled (ON) – this is the default state at reset
Output disabled (OFF)
Output controlled by OE (active high)
Output controlled by OE# (active low)
ImpliedDisconnect
ImpliedDisconnect is a feature that provides the ability to make fast switch connection changes.
When using the RC instruction “Connect, with ImpliedDisconnect” to establish a new connection,
any existing connection to that output port is automatically broken. Thus, a connection change,
i.e. breaking an existing connection and then making a new one, can be accomplished in one
RapidConfigure cycle.
I-Cube, Inc.
[Rev. 1.6] 2/20/01
13
OCX160 Crosspoint Switch—Preliminary Data Sheet
1.4 JTAG Configuration Controller
The Output port attributes and the Switch Matrix connections can be programmed using the JTAG serial
bus. The RapidConfigure Interface can be enabled or disabled using the JTAG serial bus.
The JTAG–based serial mode is always available for configuration regardless of whether the
RapidConfigure mode is enabled or disabled. However, proper care must be taken when switching between
JTAG and RapidConfigure for configuring the devices. Before attempting to change Switch Matrix
connections or output port configuration through JTAG, the user must first ensure that the RapidConfigure
mode is disabled by using JTAG serial mode to set the RCE bit to zero in the Mode Control Register.
1.4.1
JTAG Interface
The dedicated JTAG TAP interface is designed in compliance with the IEEE-1149.1. The standard
interface has five pins: Test Data Out (TDO), Test Mode Select (TMS), Test Data In (TDI), Test
Reset (TRST#), and Test Clock (TCK), which allow Boundary Scan Testing as well as device
configuration and verification. The I-Cube supplied software will automatically generate the
necessary bitstream from a higher-level textual description of the required configuration. Data on
the TDI and TMS pins are clocked into the device on the rising edge of the TCK signal, while the
valid data appears on the TDO pin after the falling edge of TCK. For more detailed information
on JTAG programming, refer to the OCX160 Register Programming Manual.
1.4.2
Output Port Configuration
Output port configuration is accomplished by loading the appropriate bitstream into the
programming registers present at each Output port. The JTAG serial bus is used to load
configuration data into the Output port programming registers, one Output port at a time.
1.4.3
Switch Matrix Configuration
The contents of the SRAM cells controlling Switch Matrix connection can be modified using the
JTAG. This is accomplished by loading the configuration data, one word at a time, into the SRAM
cells in the Switch Matrix.
1.4.4
Mode Control Register Configuration
The OCX160 contains a single bit Mode Control Register used to store user flags for
RapidConfigure Enable (RCE). These are required for proper functioning of the device. The
contents of this register can be changed using the JTAG interface and a special JTAG instruction.
Table 6
Mode Control Register
RCE
14
Mode
0
RapidConfigure interface disabled (OFF)
1
RapidConfigure interface enabled (ON)
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
1.4.5
JTAG Architecture and Shift Registers
Boundary Scan Register
(189 x 2 = 378 Bits)
JTAG Data Register - 1 Bit
Device Identification Register - 32 Bits
MUX
BUF
TDO
TDI
Mode Control Register - 1 Bits
JTAG Address Register - 7 Bits
Bypass Register - 1 Bit
Instruction Register - 16 Bits
TAP
Controller
TMS
TCK
Figure 5
I-Cube, Inc.
TRST#
OCX160 JTAG Architecture
[Rev. 1.6] 2/20/01
15
OCX160 Crosspoint Switch—Preliminary Data Sheet
1.4.6
JTAG State Machine
1
Test Logic
Reset
0
1
0
Run Test/ 1
Idle
Select DR
Scan
1
Select IR
Scan
0
0
Capture
DR
1
0
0
0
1
Capture
IR
Shift DR
Shift IR
0
1
1
Exit 1 DR
Exit 1 IR
1
1
0
0
0
Pause DR
Pause IR
0
1
1
0
0
Exit 2 DR
Exit 2 IR
1
1
Update DR
1
Figure 6
1.4.7
1
0
0
OCX160 JTAG State Machine
JTAG Input Format
Table 7
JTAG Input Format
Instruction
16
Update IR
Data
Bit Number
15
14
13
12
11
10
Bit Name
I3
I2
I1
I0
BB BA
Address A
9
8
7
6
5
4
3
2
1
0
B9
B8
B7
A6
A5
A4
A3
A2
A1
A0
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
1.4.8
JTAG Instructions
Table 8
JTAG Instructions
I [3:0]
BB
BA
B9
B8
B7
A6-A0
0 0 0 0
X
X
X
X
X
X
Sample/EXTEST
Places the device in scan mode.
0 0 0 1
X
X
X
X
X
X
Sample/EXTEST
Places the device in scan mode.
0 0 1 0
X
X
X
X
X
X
Reset the Crosspoint Resets the entire Crosspoint Array to no-connect. All
Array
other Output Buffer configurations are unchanged by
this operation.
0 0 1 1
X
X
X
X
X
X
Set Array for
Broadcast mode
Use the JTAG Address Register as the Input address to
be the broadcast input Connects the selected Input to
all Output cells and disconnects all other Inputs.
Activating the Global Update JTAG instruction returns
the Crosspoint array from the Broadcast mode to the
previous programed state.
0 1 0 0
X
OE
OE
Output Buffer
Address
Program a Buffer
Programs the Output Buffer address specified in the
JTAG instruction (A6-A0). The configuration data is
also specified in the JTAG instruction bits BA-B7. See
Table 9 for bit assignment of the Buffer functionality.
0 1 0 1
X
X
X
Clock Data
Select Mode
X
X
Instruction
Output Address/ Configuration
Buffer
readback
Description
Readback the connectivity of the Crosspoint cell with
the Input location specified in the JTAG Address
Register and the Output location specified JTAG
instruction (A0-A6). It also returns the configuration of
the Output Buffer addressed in the JTAG instruction
(A0-A6).
The readback data is shifted out of TDO in the
following sequence:
1. Crosspoint Connect (1=connected, 0=no
connection)
2. Output Enable—B7 (see Table 9)
3. Output Enable—B8 (see Table 9)
4. Output Data Source—B9 (0=Flow-through,
1=registered)
5. Output Clock Select—BA (0=Global Clock,
1=Next Neighbor)
6. State of Broadcast bit
7. State of the RCE bit
NOTE: This instruction does not increment the JTAG
Address Register. This instruction also requires two
DR cycles
0 1 1 0
X
X
X
X
X
X
Update the
Crosspoint Array
Update the programmed connection from the Loading
SRAM to the Active SRAM.
0 1 1 1
X
X
X
X
X
X
Disconnect Input
cell
Disconnect the Crosspoint connections from the Input
address specified in the JTAG Address Register.
I-Cube, Inc.
[Rev. 1.6] 2/20/01
17
OCX160 Crosspoint Switch—Preliminary Data Sheet
Table 8
JTAG Instructions (Continued)
I [3:0]
BB
BA
B9
B8
B7
1 0 0 0
X
X
X
X
X
Output Address Disconnect Input
and Output
Disconnect the Crosspoint cell at the Input location
specified at the JTAG Address Register and the Output
location specified in the Disconnect JTAG instruction
(A6-A0).
All other connections from the same input address or
to the same output address remain the same.
1 0 0 1
X
X
X
X
X
Output Address Connect with
ImpliedDisconnect
Connects the Crosspoint cell at the Input location
specified on the JTAG Address Register and the output
location specified in the Connect JTAG instruction
(A6-A0).
All other connections from the same Input address or
the same Output address are set to no-connects.
NOTE: This instruction increments the JTAG Address
Register (Input address).
1 0 1 0
X
X
X
X
X
Output Address Connect—no
ImpliedDisconnect
Connects the Crosspoint cell at the Input address
specified in the JTAG Address Register and the Output
address specified in the Connect JTAG instruction
(A6-A0).
All other connections from the same input remain the
same as before.
1 0 1 1
X
X
X
X
X
Input Address
1 1 0 0
X
X
X
X
X
1 1 0 1
X
X
X
X
1 1 1 0
X
X
X
1 1 1 1
X
X
X
18
A6-A0
Instruction
Description
Set the JTAG
Address Register
Sets the 7-bit JTAG Address Register with the 7-bit
address (A6-A0) of the JTAG Instruction Register. The
7-bit address of the JTAG Address Register becomes
the Input port address for Crosspoint Access.
X
Device ID out
Serialize the device ID and revision history out to
TDO. ID for the OCX160 is 0x0000B89F
X
X
Reset Output Buffer Resets the Crosspoint Array to no-connects. Sets the
and Crosspoint
Output buffer to Flow-through mode with Output
Array
Enabled. The device ID is serialized to TDO.
X
X
X
Set RCE Bit
Sets the RCE bit of the Mode Control Register with the
JTAG instruction bit A0.
To turn ON the RCE bit, encode bit A0 to 1.
To turn OFF the RCE bit, encode bit A0 to 0.
X
X
X
Bypass
Places device in a mode to pass TDI data to TDO with
one clock delay. Used for programming and testing
devices through serial connected JTAG controls.
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
Table 9
Programming an Output using JTAG
BA, B9, B8, B7
Signal/Function
BA
Clock Select:
0 = Global Clock
1 = Next Neighbor
B9
Output Mode:
0 = Flow-through (OP)
1 = Registered (RO)
B8, B7
0,0
0,1
1,0
1,1
Table 10
Output Enable:
Output enabled (ON) – this is the default state at reset
Output disabled (OFF)
Output controlled by OE (active high)
Output controlled by OE# (active low)
Number of JTAG Cycles and Configuration Time
OCX160
Operation
I-Cube, Inc.
JTAG
Cycles
JTAG Reset Sequence (TMS = “11111”)
7
Enable or Disable RapidConfigure
28
Change attributes of ONE Output Port
28
Change attributes of ALL Output Ports
2,240
Reset JTAG Controller + Reset ALL Output Ports + Clear ALL SRAM cells
35
Connect or disconnect two Ports
56
Configure Entire Switch Matrix
181,440
Completely Configure the Device (All Output Ports and All Switch Matrix Connections)
183,680
[Rev. 1.6] 2/20/01
19
OCX160 Crosspoint Switch—Preliminary Data Sheet
1.5 Device Reset Options
The power-on reset, RapidConfigure reset, hardware reset, and JTAG reset functions will program the
output buffers to flow-through mode (with Global Clock selected), and Output Enabled (ON). JTAG can
be reset via the TRST# pin or by clocking five consecutive one to the TMS pin. The hardware reset pin
can be done accomplished through the HW_RST# pin (active low). RC reset can be accomplished by
applying the RC instruction 1101 to the RCI[3:0] pins.
Table 11
Programming
Interface
Hardware Reset
JTAG Reset
Output
Ports
Switch
Matrix
RCE Mode
Control
Power-on Reset
OP
NC
1
(RC Enabled)
TLR1
HW_RST# (low pulse)
OP
NC
1
(RC Enabled)
TLR
1. Low Pulse on TRST#
Unchanged
Unchanged
Unchanged
TLR
2. TMS high for 5
TCLK cycles
Unchanged
Unchanged
Unchanged
TLR
3. Device Reset
(instruction 1101)
OP
NC
1
(RC Enabled)
TLR
Unchanged
NC
Unchanged
Unchanged
OP
NC
1
(RC Enabled)
Unchanged
Unchanged
NC
Unchanged
Unchanged
Reset Method
4. Reset Crosspoint
Array (instruction 0010)
RapidConfigure
Reset
Device Reset Options
1. Device reset
(instruction 1101)
2. Reset Crosspoint
Array (instruction 0010)
JTAG TAP
1. TLR = Test Logic Reset state.
20
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
2. Pin Description
Table 12
Pin Name
OCX160 Pin Description
# of Pins
Type
Description
INP[79:0]
80
Input
Non-inverting differential input signals
INN[79:0]
80
Input
Inverting differential input signals
OUTP[79:0]
80
Output
Non-inverting differential input signals
OUTN[79:0]
80
Output
Inverting differential input signals
CLKP
1
Input
Non-inverting differential Global Clock
CLKN
1
Input
Inverting differential Global Clock
OE#
1
Input
Global Output Enable
HW_RST#
1
Input
Hardware Reset
UPDATE#
1
Input
Global Update
RC Pins
RCA[6:0]
7
Input
RapidConfigure Address A
RCB[6:0]
7
Input
RapidConfigure Address B
RCO[4:0]
5
Output
RapidConfigure Readback
RCI[3:0]
4
Input
RapidConfigure Instruction Bits
RC_CLK#
1
Input
RapidConfigure Clock
RC_EN#
1
Input
RapidConfigure Cycle Enable
JTAG Pins
TCK
1
Input
JTAG Test Clock
TMS
1
Input
JTAG Test Mode Select
TDI
1
Input
JTAG Test Data In
JTAG Test Reset
TRST#
1
Input
TDO
1
Output
JTAG Test Data Out
Power and Ground Pins
VDD.CORE
VDD.PAD
VDD.IN
(2, 3)
(1, 4)
VSS
12
8
2.5V Power
Core Voltage
2.5V or 3.3V Power Differential Output Buffer Voltage
8
3.3V Power
36
Ground
LVTTL Control pins Voltage and Differential Input
Buffer Voltage
Ground
NOTES:
1. Dedicated differential input buffers can receive both LVDS and LVPECL voltage levels using
3.3V supply.
2. VDD.PAD is 2.5V for LVDS outputs or 3.3V for LVPECL outputs.
3. Dedicated differential output buffers can be biased using different supplies for VDD.PAD and
external resistors to support both LVDS and LVPECL output voltage levels.
4. The LVTTL control, JTAG pins, and differential input ports are 3.3V—they are not 5V tolerant.
5. The differential output pins powered from 2.5V are 3.3V tolerant.
I-Cube, Inc.
[Rev. 1.6] 2/20/01
21
OCX160 Crosspoint Switch—Preliminary Data Sheet
3. Differential I/O Standards
The OCX160 support the two most popular differential signaling standards: Low Voltage Differential Signaling
(LVDS) and Low Voltage Positive Emitter Coupled Logic (LVPECL).
LVDS is typically used in communication systems as high speed, low noise point-to-point links. The OCX160
conforms to the ANSI/TIA/EIA-644 standard covering electrical specifications for output drivers and receiver
inputs.
LVPECL is commonly used in video switching applications or those designs requiring transmission of highspeed clock signals.
3.1 LVDS
LVDS is a differential signaling standard. It requires that one data bit is carried through two signal lines.
As with all differential signaling standards, LVDS has an inherent noise immunity over single-ended
standards. The voltage swing between two signal lines is approximately 350mV. The use of a reference
voltage or a board termination voltage is not required. LVDS requires the use of two pins per input or
output. LVDS requires external resistor termination.
Transmitting and receiving circuits for LVDS are shown in Figures 7 and 8.
OCX
Device
OUTP
2.5V
Z0=50Ω
RS
to LVDS Receiver
165
RDIV
140
Data
Transmit
Z0=50Ω
RS
VDD.PAD=2.5V
LVDS Output
to LVDS Receiver
OUTN 165
Figure 7
Transmitting LVDS Signal Circuit
Z0=50Ω
INP
RT
100
from LVDS
Driver
OCX
Device
+
–
Data
Recieve
Z0=50Ω
INN
Figure 8
22
Receiving LVDS Signal Circuit
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
3.2 LVPECL
LVPECL is another differential signaling standard that specifies two pins per input or output. The voltage
swing between these two signal lines is approximately 850 mV. The use of a reference voltage or a board
termination voltage is not required. The LVPECL standard requires external resistor termination.
Transmitting and receiving circuits for LVPECL are shown in Figures 9 and 10.
OCX
Device
OUTP
3.3V
Z0=50Ω
RS
to LVPECL
Receiver
100
RDIV
187
Data
Transmit
Z0=50Ω
RS
VDD.PAD=3.3V
LVPECL Output
Figure 9
Transmitting LVPECL Signal Circuit
Z0=50Ω
from
LVPECL
Driver
to LVPECL
Receiver
OUTN 100
INP
RT
100
OCX
Device
+
–
Data
Recieve
Z0=50Ω
INN
Figure 10 Receiving LVPECL Signal Circuit
I-Cube, Inc.
[Rev. 1.6] 2/20/01
23
OCX160 Crosspoint Switch—Preliminary Data Sheet
3.3 Termination Resistor Packs
Resistor packs are available with the values and the configuration required for LVDS and LVPECL
termination from Bourns, Inc. The part numbers are listed in Table 13. For pricing and availability
questions, please contact them directly at www.bourns.com.
Table 13
Termination Resistor Packs
Bournes Part Number
Differential I/O Standard
Termination
for:
Pairs per
Pack
No. of Pins
CAT16-LV2F6
LVDS
Driver
2
8
CAT16-LV4F12
LVDS
Driver
4
16
CAT16-PC2F6
LVPECL
Driver
2
8
CAT16-PC4F12
LVPECL
Driver
4
16
CAT16-PT2F2
LVDS/LVPECL
Receiver
2
8
CAT16-PT4F4
LVDS/LVPECL
Receiver
4
16
3.4 Mixed I/O Systems
The use of different supply voltages and terminating resistors allows the OCX160 to support LVDS /
LVPECL translation as well as switching as outlined in Table 14.
Table 14
Supply Voltages and Terminating Resistors
Input
Output
VDD.PAD
RT
RS
RDIV
LVDS
LVDS
2.5V
100Ω
165Ω
140Ω
LVPECL
LVDS
2.5V
100Ω
165Ω
140Ω
LVDS
LVPECL
3.3V
100Ω
100Ω
187Ω
LVPECL
LVPECL
3.3V
100Ω
100Ω
187Ω
NOTES:
1. VDD.IN = 3.3V ±10%, VDD.CORE = 2.5V ±5%
2. It is not possible to mix LVDS and LVPECL outputs on a device
24
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
4. Electrical Specifications
4.1 Absolute Maximum Ratings
Table 15
Symbol
Absolute Maximum Ratings1
Parameter
VDD.CORE
VDD.IN
VDD.PAD
VIN2
Limits
Units
Supply Voltage (core)
-0.3 to +3.0
V
Supply Voltage (inputs)
-0.3 to +3.6
V
Supply Voltage (differential outputs)
-0.3 to +3.6
V
Input Voltage
-0.3 to +3.63
V
TJ
Junction Temperature
+150
°C
TSTG
Storage Temperature
-65 to +150
°C
PMAX
Maximum Power Dissipation
6
W
ESD6
Electrostatic Discharge
2000
V
4.2 Recommended Operating Conditions
Table 16
Symbol
Recommended Operating Conditions
Parameter
VDD.CORE
Supply Voltage (core)
VDD.PAD4
Supply Voltage (differential output buffers)
VDD.IN
Supply Voltage (inputs)
Units
+2.375 to +2.625
V
3.3V ±10% to 2.5V ±5%
V
+3.0 to +3.6
V
0 to +70
-40 to +85
°C
Operating Temperature: Commercial
Operating Temperature: Industrial
TA
Limits
4.3 Pin Capacitance
Table 17
Symbol
CPIN
Pin Capacitance5
Parameter
Signal Pin Capacitance
Max
Units
10
pF
1.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2.
A maximum undershoot of 2V for a maximum duration of 20 ns is acceptable. Overshoot to 3.6V is acceptable.
3.
All inputs are 3.3V tolerant with the VDD pin at 2.5V or 3.3V.
4.
Note that min and max values for VDD for differential outputs are I/O Standard dependent.
5.
Capacitance measured at 25°C. Sample tested only.
6.
Measured using Human Body Model.
I-Cube, Inc.
[Rev. 1.6] 2/20/01
25
OCX160 Crosspoint Switch—Preliminary Data Sheet
4.4 DC Electrical Specifications
(TA = -40°C to 85°C, VDD.IN = 3.3V ±10%, VDD.CORE = 2.5V ±5%)
Table 18
Symbol
LVTTL DC Electrical Specifications
Parameter
Conditions
Min
Max
Units
VIH
High-level Input
Ports are 3.3V tolerant
2.0
3.6
V
VIL
Low-level Input
Ports are 3.3V tolerant
-0.3
0.8
V
VOH
High-level Output
VDD.PAD = Min
IOH = -4mA
2.4
VDD.PAD+ 0.3
V
VOL
Low-level Output
VDD.PAD = Min
IOL = 8mA
0.4
V
Input Pin Leakage Current
VDD.IN= Max
0.0 < In < VDD.PAD
+5
-50
µΑ
Tristate Leakage Output OFF State
VDD.PAD = Max
0.0 < In < VDD.PAD
+5
-5
µΑ
Quiescent Power
All VDD = Max
0.5
W
ILIH, ILIL (1)
ILOZ
Power
PDDQ (2)
Table 19
LVDS DC Electrical Specifications
DC Parameter
Min
Output High Voltage for OUTP and OUTN
Output Low Voltage for OUTP and OUTN
Differential Output Voltage
Typ
(3)
(5)
350
100
350
0.25
1.25
All LVTTL input pins have pull-up resistors.
See section 6 for dynamic power consumption calcualtion.
3.
Refer to Figures 7 and 8 for termination resistor.
4.
Refer to Figures 9 and 10 for termination resistor.
5.
Maximum capacitive load is 12 pF.
Table 20
V
450
1.125 1.25 1.375
Input Common-Mode Voltage
2.
1.6
V
Differential Input Voltage
1.
Units
0.90
250
Output Common-Mode Voltage
Max
V
mV
2.25
V
LVPECL DC Electrical Specifications
DC Parameters
(4)
Min
Max
VDD.PAD - 1.165
VDD.PAD - 0.880
VIL
VDD.PAD - 1.810
VDD.PAD - 1.475
VOH
1.80
2.40
VOL
0.95
1.55
VIH
mV
These values in Table 20 are valid at the output of the source termination pack, as shown in sections 3.2
and 3.3, with a 100Ω differential load only. The VOH levels are 200mV below LVPECL levels and are
compatible with devices tolerant of lower common-mode ranges. The above table summarizes the DC
output specifications of LVPECL.
26
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
4.5 AC Electrical Specifications
(VDD.IN = 3.3V ±10%, VDD.CORE = 2.5V ±5%)
Table 21
AC Electrical Specifications
0°C to 70°C
Symbol
Parameter
NRZ Data Rate
RDATA
Registered Output Clock Frequency
FRO
Min
(1)
(1)
tW_RO
Registered Clock Pulse Width, High or Low
(1)
Max
-40°C to +85°C
Max
Units
667
667
Mb/s
333
333
MHz
2
Min
2
ns
tS_RO
Registered Output Setup Time to Clock
4
4
ns
tH_RO
Registered Output Clock to Hold Data
0
0
ns
tCO_RO
Registered Output Clock to Data Out Valid
2.5
2.5
ns
One Way Signal Propagation Delay, Fanout = 1
5.5
6.5
ns
tPHL, tPLH
tW+
Input Flow-through Positive Pulse Width
1.5
1.5
ns
tW-
Input Flow-through Negative Pulse Width
1.5
1.5
ns
tDCD+, tDCD-
Duty Cycle Distortion
0.5
Output Jitter
tJITTER
TBD
(1)
TBD
TBD
0.6
ns
TBD
ps
tSK
Skew between Output Ports
0.5
0.6
ns
tPHZ_OT,
tPLZ_OT
Output Enable to Valid Data
3
3
ns
tPZH_OT,
tPZL_OT
Output Enable to High Z State
3
3
ns
tRC
RapidConfigure Clock Period
12
12
ns
RapidConfigure Clock Pulse Width
5
5
ns
tS_RC
RapidConfigure Address Setup to RC_CLK#
3
4
ns
tH_RC
RapidConfigure Address and Enable Hold Time to RC_CLK#
3
tP_UD
Update of Crosspoint to Data Out
10
10
ns
fJTAG
JTAG Clock Frequency (TCK)
20
20
MHz
30
ns
tW+_RC
tW-_RC
tW_JTAG
JTAG Clock Pulse Width (TCK) @ 20MHz cycle
20
4
30
20
ns
tS_JTAG
JTAG Setup Time
4
4
ns
tH_JTAG
JTAG Hold Time
0
0
ns
tP_JTAG
JTAG Clock to Output Data Valid (TDO)
20
20
ns
NOTES:
1.
I-Cube, Inc.
These parameters are guaranteed but not tested in production.
[Rev. 1.6] 2/20/01
27
OCX160 Crosspoint Switch—Preliminary Data Sheet
4.6 Timing Diagrams
Note – For the purpose of clarity, the timing diagrams within this data sheet are conceptual
representations only and do not show actual circuit implementation.
tW_RO
tW_RO
CLK
tS_RO tH_RO
IN
RO
Switch
Matrix
InPort
D
InPort
Dn
Dn+1
OutPort
Q
OutPort
CLK
Dn-1
Dn
Dn+1
tCO_RO
Figure 11 Registered Output Mode Timing
InPort 1
InPort 2
IN
OP
InPort 1
tW+
tPLH
tPHL
tSK
tSK
OutPort 1
OutPort 1
Switch
Matrix
InPort 2
OutPort 2
OutPort 2
Figure 12 Flow-Through Mode Timing
OE#
tPZH_OT
InPort
IN
InPort
Switch
Matrix
OP
tPZL_OT
OutPort
tPHZ_OT
tPLZ_OT
OutPort
OE#
Figure 13 Output Enable Timing
28
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
IN
InPort
Switch
Matrix
InPort
OP
tIN+
tIN-
tOUT+
tOUT-
OutPort
OutPort
tDCD+ = tIN+ - tOUT+
tDCD- =
tIN- - tOUT-
Figure 14 Duty Cycle Distortion
tRC
tW+_RC
tRC
tW-_RC
RC_CLK#
tS_RC
tH_RC
RCA/RCB Address,
Instruction
tS_RC tH_RC
RC_EN#
Figure 15 RapidConfigure Write Cycle
I-Cube, Inc.
[Rev. 1.6] 2/20/01
29
OCX160 Crosspoint Switch—Preliminary Data Sheet
tRC
tW+_RC
tRC
tW-_RC
RC_CLK#
tS_RC
tH_RC
RCA/RCB Address,
Instruction
tS_RC tH_RC
RC_EN#
Data Valid
RCO
High Impedance
Figure 16 RapidConfigure Read Cycle
tW_JTAG
tW_JTAG
TCK
tS_JTAG tH_JTAG
TDI, TMS
tP_JTAG
TDO
Figure 17 JTAG Timing
30
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
Typical Performance at 667 Mb/s with PRBS Data
(Currently not available for this document)
Figure 18 Typical Performance LVDS mode
Typical Performance at 667 Mb/s with PRBS Data
(Currently not available for this document)
Figure 19 Typical Performance LVPECL mode
I-Cube, Inc.
[Rev. 1.6] 2/20/01
31
OCX160 Crosspoint Switch—Preliminary Data Sheet
5. Package and Pinout
5.1
Package Pinout
1 2
A
B
C
D
E
F
G
H
J
K
L
VSS
IN40N
IN40P
RC_CLK#
OUT78P
VSS
OUT79N
OUT75P
OUT75N
OUT74N
R
T
OUT71N
VDD.CORE
OUT69N
OUT70N
OUT68N
OUT63P
OUT68P
VDD.PAD
OUT62N
OUT62P
OUT60P
OUT63N
OUT61P
OUT60N
OUT59N
OUT64N
OUT61N
VSS
VSS
OUT54N
OUT11N
OUT03P
OUT02N
OUT11P
OUT05P
OUT16N
OUT04P
OUT16P
OUT05N
VDD.PAD
OUT17N
OUT04N
OCX160
in 420 BGA package
40-79
Outputs
OUT17P
OUT06N
VDD.CORE
OUT18P
OUT06P
OUT18N
OUT10P
VDD.CORE
OUT13P
OUT08P
OUT08N
0-39
Outputs
Top View
OUT13N
OUT10N
OUT15N
OUT12N
VDD.PAD
OUT19P
OUT14P
OUT21P
OUT14N
VSS
OUT21N
VSS
OUT19N
OUT24N
OUT23N
OUT45N
OUT45P
VDD.PAD
OUT30P
OUT27N
VDD.CORE
OUT31N
OUT32P
OUT44N
OUT43P
OUT41P
OUT20N
OUT41N
VSS
RCB2
OUT40P
RCA2
IN39P
IN39N
IN38N
IN36P
IN34P
IN28N
IN29P
IN30P
IN33N
IN37N
IN34N
VSS
IN28P
3 4 5 6 7
IN27P
IN26P
IN15N
IN22P
IN12N
IN15P
IN22N
IN19N
IN10P
IN17P
IN17N
IN11N
IN01N
IN02P
IN04N
IN09N
IN07N
RCO3
RCA1
RCA0
IN07P
IN11P
IN16P
RCO2
VSS
VSS
CLKP
IN00P
IN01P
IN02N
OUT33P
VSS
OE#
IN04P
IN09P
OUT33N
RCO1
VSS
IN03P
IN06P
IN10N
IN16N
IN18N
IN03N
OUT35P
OUT38P
VSS
VDD.IN
IN00N
VSS
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
[Rev. 1.6] 2/20/01
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
CLKN
Figure 20 OCX160 Package Pinout
32
J
OUT36P
OUT38N
RCO0
IN05N
IN08P
IN13N
IN19P
VDD.CORE
IN06N
IN13P
IN18P
IN24N
IN24P
IN08N
IN14N
IN20N
IN25N
IN12P
IN05P
G
H
OUT34N
OUT36N
OUT39N
VDD.CORE
IN14P
IN20P
IN25P
IN26N
IN32P
IN32N
IN21P
OUT30N
OUT32N
OUT37P
OUT34P
VDD.PAD
OUT39P
OUT35N
VSS
VSS
IN23N
IN27N
IN33P
IN38P
IN23P
OUT26N
OUT27P
OUT37N
VDD.IN
VSS
IN21N
VSS
IN29N
IN30N
IN31P
IN37P
RCA4
IN36N
VDD.IN
IN35P
VSS
VDD.IN
VDD.CORE
IN31N
RCA3
VSS
RCB1
IN35N
E
F
OUT25P
OUT29P
OUT31P
0-39
Inputs
OUT24P
OUT22N
OUT29N
RCB3
OUT40N
OUT28P
OUT22P
OUT43N
OUT42P
VSS
D
OUT15P
OUT12P
OUT47P
VDD.CORE
OUT42N
1 2
OUT09P
OUT03N
TMS
OUT47N
OUT50N
RCA5
40-79
Inputs
OUT07P
UPDATE#
OUT09N
OUT02P
OUT28N
OUT25N
VDD.PAD
OUT23P
OUT26P
OUT50P
VSS
VSS
OUT49P
VDD.CORE
OUT44P
RCA6
IN72N
OUT01N
A
B
C
OUT07N
TRST#
OUT52N
OUT56P
RCB0
TDO
TCK
NC
OUT00N
OUT01P
OUT20P
OUT46P
OUT48N
VSS
OUT53N
OUT49N
OUT52P
OUT51P
VDD.CORE
VDD.IN
VSS
IN79N
IN72P
VDD.IN
HW_RST#
OUT00P
OUT58P
OUT58N
OUT46N
VSS
IN77N
TDI
IN75N
VSS
VSS
OUT54P
VDD.PAD
OUT55N
OUT57P
VSS
VSS
IN71N
IN69N
IN62N
IN76N
IN75P
IN74P
IN69P
RCO4
IN77P
IN79P
IN73P
IN71P
IN68N
IN63N
VSS
VSS
VDD.IN
IN67P
IN62P
IN78N
IN74N
IN70N
IN68P
IN63P
IN61P
IN55N
VDD.CORE
IN65P
IN61N
IN60P
IN54P
IN66N
IN76P
IN78P
IN73N
OUT53P
OUT59P
OUT55P
OUT48P
AE
AF
OUT69P
OUT65P
OUT51N
AD
OUT76P
OUT71P
OUT66P
OUT65N
OUT56N
AB
AC
OUT70P
OUT67P
OUT66N
IN52N
VDD.CORE
IN46P
RCI0
OUT77N
VDD.PAD
OUT72P
OUT67N
IN46N
VDD.IN
IN55P
IN70P
IN67N
IN59N
IN60N
IN54N
IN66P
IN65N
IN64P
IN57P
IN50N
IN52P
IN59P
IN64N
IN58N
IN53N
RCB6
OUT76N
OUT73P
OUT72N
W
Y
AA
RCB5
OUT74P
OUT57N
U
V
VSS
OUT77P
OUT73N
IN43N
VSS
IN50P
IN47P
IN58P
IN57N
IN53P
IN47N
IN45P
RCI1
RCB4
IN49P
IN45N
IN43P
RCI2
RC_EN#
IN56N
IN51P
IN48P
RCI3
IN56P
IN51N
IN49N
IN44P
IN41P
OUT78N
OUT79P
IN44N
IN42P
VSS
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
IN48N
IN42N
IN41N
VSS
OUT64P
M
N
P
3 4 5 6 7
I-Cube, Inc.
AF
OCX160 Crosspoint Switch—Preliminary Data Sheet
5.2 Pinout by Ball Sequence
Table 22
Ball # Ball Name
Ball # Ball Name
OCX160 Pinout By Ball Sequence
Ball # Ball Name
Ball # Ball Name
Ball # Ball Name
A1
VSS
B1
RC_CLK#
C1
OUT78P
D1
OUT79P
E1
OUT75P
A2
VSS
B2
VSS
C2
OUT78N
D2
OUT79N
E2
OUT75N
A3
IN40N
B3
IN40P
C3
VSS
D3
RC_EN#
E3
RCB4
RCB5
A4
IN41N
B4
IN41P
C4
RCI2
D4
VSS
E4
A5
IN42N
B5
IN42P
C5
RCI3
D5
RCI1
E5
VSS
A6
IN44N
B6
IN44P
C6
IN43P
D6
IN43N
E6
RCI0
A7
IN48N
B7
IN48P
C7
IN45N
D7
IN45P
E7
VDD.IN
A8
IN49N
B8
IN49P
C8
IN47P
D8
IN46N
E8
IN46P
A9
IN51N
B9
IN51P
C9
IN47N
D9
IN52P
E9
VDD.CORE
A10
IN56N
B10
IN50P
C10
IN50N
D10
IN52N
E10
VDD.CORE
A11
IN56P
B11
IN53P
C11
IN53N
D11
IN54N
E11
IN54P
A12
IN57N
B12
IN57P
C12
IN55P
D12
IN55N
E12
VDD.IN
A13
IN58P
B13
IN58N
C13
IN60N
D13
IN60P
E13
VSS
A14
IN64N
B14
IN64P
C14
IN61P
D14
VSS
E14
VSS
A15
IN59P
B15
IN59N
C15
IN61N
D15
IN62P
E15
IN62N
A16
IN65N
B16
IN65P
C16
IN63P
D16
IN63N
E16
VDD.IN
A17
IN66P
B17
IN66N
C17
IN68P
D17
IN68N
E17
VSS
A18
IN67N
B18
IN67P
C18
IN69P
D18
IN69N
E18
VDD.CORE
A19
IN70P
B19
IN70N
C19
IN71P
D19
IN71N
E19
VDD.IN
A20
IN73N
B20
IN73P
C20
IN74P
D20
IN72P
E20
IN72N
A21
IN78P
B21
IN74N
C21
IN75P
D21
IN75N
E21
NC
A22
IN78N
B22
IN79P
C22
IN79N
D22
TCK
E22
VSS
A23
IN76P
B23
IN76N
C23
TDI
D23
VSS
E23
TRST#
A24
IN77P
B24
IN77N
C24
VSS
D24
TDO
E24
UPDATE#
A25
RCO4
B25
VSS
C25
OUT00P
D25
OUT01P
E25
OUT07N
A26
VSS
B26
HW_RST#
C26
OUT00N
D26
OUT01N
E26
OUT07P
I-Cube, Inc.
[Rev. 1.6] 2/20/01
33
OCX160 Crosspoint Switch—Preliminary Data Sheet
Table 22
Ball # Ball Name
Ball # Ball Name
OCX160 Pinout By Ball Sequence (Continued)
Ball # Ball Name
Ball # Ball Name
Ball # Ball Name
F1
OUT74N
G1
OUT73N
H1
OUT72N
J1
OUT67N
K1
OUT66N
F2
OUT74P
G2
OUT73P
H2
OUT72P
J2
OUT67P
K2
OUT66P
F3
OUT77P
G3
OUT76N
H3
OUT70P
J3
OUT69P
K3
OUT69N
F4
OUT77N
G4
OUT76P
H4
OUT71N
J4
OUT70N
K4
OUT68P
F5
RCB6
G5
VDD.PAD
H5
OUT71P
J5
VDD.CORE
K5
OUT68N
VDD.CORE
F22
TMS
G22
OUT02N
H22
VDD.PAD
J22
VDD.CORE
K22
F23
OUT02P
G23
OUT03P
H23
OUT04P
J23
OUT04N
K23
OUT06P
F24
OUT03N
G24
OUT05P
H24
OUT05N
J24
OUT06N
K24
OUT10P
F25
OUT09N
G25
OUT11N
H25
OUT16N
J25
OUT17N
K25
OUT18P
F26
OUT09P
G26
OUT11P
H26
OUT16P
J26
OUT17P
K26
OUT18N
L1
OUT65N
M1
OUT64P
N1
OUT61P
P1
OUT61N
R1
OUT55P
L2
OUT65P
M2
OUT63N
N2
OUT64N
P2
OUT59P
R2
OUT55N
L3
OUT63P
M3
OUT62N
N3
OUT59N
P3
OUT54N
R3
OUT53P
L4
OUT62P
M4
OUT60N
N4
VSS
P4
OUT54P
R4
OUT53N
VDD.PAD
L5
VDD.PAD
M5
OUT60P
N5
VSS
P5
VSS
R5
L22
OUT08N
M22
VDD.PAD
N22
VSS
P22
VSS
R22
OUT20P
L23
OUT08P
M23
OUT12P
N23
OUT14P
P23
VSS
R23
OUT20N
L24
OUT10N
M24
OUT12N
N24
OUT14N
P24
OUT19N
R24
OUT22N
L25
OUT13P
M25
OUT15P
N25
OUT19P
P25
OUT21N
R25
OUT28P
L26
OUT13N
M26
OUT15N
N26
OUT21P
P26
OUT24N
R26
OUT24P
T1
OUT57P
U1
OUT57N
V1
OUT46N
W1
OUT56N
Y1
OUT51N
T2
OUT58N
U2
OUT52P
V2
OUT46P
W2
OUT56P
Y2
OUT44P
T3
OUT58P
U3
OUT52N
V3
OUT47N
W3
OUT45N
Y3
OUT44N
T4
OUT49P
U4
OUT47P
V4
OUT45P
W4
OUT43P
Y4
OUT43N
T5
OUT49N
U5
VDD.CORE
V5
VDD.CORE
W5
VDD.PAD
Y5
OUT41P
T22
VDD.PAD
U22
OUT23N
V22
VDD.CORE
W22
OUT31P
Y22
VDD.PAD
T23
OUT22P
U23
OUT23P
V23
OUT29N
W23
OUT31N
Y23
OUT37N
T24
OUT28N
U24
OUT29P
V24
OUT27N
W24
OUT32N
Y24
OUT37P
T25
OUT25P
U25
OUT26P
V25
OUT27P
W25
OUT32P
Y25
OUT34N
T26
OUT25N
U26
OUT26N
V26
OUT30P
W26
OUT30N
Y26
OUT34P
AA1
OUT51P
AA2
OUT50N
AA3
OUT50P
AA4
OUT41N
AA5
RCB3
AA22
OUT39N
AA23
OUT39P
AA24
OUT36N
AA25
OUT35N
AA26
OUT35P
34
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
Table 22
Ball # Ball Name
Ball # Ball Name
OCX160 Pinout By Ball Sequence (Continued)
Ball # Ball Name
Ball # Ball Name
Ball # Ball Name
AB1
OUT48P
AC1
OUT48N
AD1
RCB0
AE1
RCA6
AF1
VSS
AB2
OUT42P
AC2
OUT40P
AD2
RCB1
AE2
VSS
AF2
RCA5
AB3
OUT42N
AC3
OUT40N
AD3
VSS
AE3
IN36N
AF3
IN36P
AB4
RCB2
AC4
VSS
AD4
RCA4
AE4
IN34N
AF4
IN34P
IN38N
AB5
VSS
AC5
RCA3
AD5
IN39P
AE5
IN39N
AF5
AB6
RCA2
AC6
IN35P
AD6
IN37P
AE6
IN37N
AF6
IN38P
AB7
IN35N
AC7
IN31N
AD7
IN31P
AE7
IN33N
AF7
IN33P
AB8
VDD.IN
AC8
IN30N
AD8
IN30P
AE8
IN32P
AF8
IN32N
AB9
VDD.CORE
AC9
IN29N
AD9
IN29P
AE9
IN27N
AF9
IN27P
AB10
VSS
AC10
IN28N
AD10
IN28P
AE10
IN26N
AF10
IN26P
IN25N
AB11
VDD.IN
AC11
IN23P
AD11
IN23N
AE11
IN25P
AF11
AB12
IN21N
AC12
IN21P
AD12
IN22P
AE12
IN22N
AF12
IN24P
AB13
VSS
AC13
VSS
AD13
IN20P
AE13
IN20N
AF13
IN24N
AB14
VSS
AC14
IN15N
AD14
IN15P
AE14
IN19P
AF14
IN19N
AB15
VDD.IN
AC15
IN14P
AD15
IN14N
AE15
IN18P
AF15
IN18N
AB16
IN12P
AC16
IN12N
AD16
IN13N
AE16
IN17P
AF16
IN17N
AB17
VDD.CORE
AC17
IN08N
AD17
IN13P
AE17
IN16N
AF17
IN16P
AB18
VDD.CORE
AC18
IN08P
AD18
IN10N
AE18
IN11P
AF18
IN11N
AB19
IN05P
AC19
IN06N
AD19
IN10P
AE19
IN09P
AF19
IN09N
AB20
VDD.IN
AC20
IN05N
AD20
IN06P
AE20
IN07P
AF20
IN07N
AB21
RCO0
AC21
IN03N
AD21
IN03P
AE21
IN04P
AF21
IN04N
AB22
VSS
AC22
OE#
AD22
RCA0
AE22
IN02P
AF22
IN02N
AB23
OUT38N
AC23
VSS
AD23
RCA1
AE23
IN01N
AF23
IN01P
AB24
OUT38P
AC24
VSS
AD24
VSS
AE24
IN00P
AF24
IN00N
AB25
OUT36P
AC25
RCO1
AD25
RCO3
AE25
VSS
AF25
CLKN
AB26
OUT33N
AC26
OUT33P
AD26
RCO2
AE26
CLKP
AF26
VSS
I-Cube, Inc.
[Rev. 1.6] 2/20/01
35
OCX160 Crosspoint Switch—Preliminary Data Sheet
5.3 Pinout by Ball Name
Table 23
Ball Name
36
Ball # Ball Name
OCX160 Pinout By Ball Name
Ball # Ball Name
Ball # Ball Name
Ball # Ball Name
Ball #
CLKN
AF25
IN20N
AE13
IN42N
A5
IN64N
A14
OUT05P
G24
CLKP
AE26
IN20P
AD13
IN42P
B5
IN64P
B14
OUT06N
J24
OE#
AC22
IN21N
AB12
IN43N
D6
IN65N
A16
OUT06P
K23
HW_RST#
B26
IN21P
AC12
IN43P
C6
IN65P
B16
OUT07N
E25
IN00N
AF24
IN22N
AE12
IN44N
A6
IN66N
B17
OUT07P
E26
IN00P
AE24
IN22P
AD12
IN44P
B6
IN66P
A17
OUT08N
L22
IN01N
AE23
IN23N
AD11
IN45N
C7
IN67N
A18
OUT08P
L23
IN01P
AF23
IN23P
AC11
IN45P
D7
IN67P
B18
OUT09N
F25
IN02N
AF22
IN24N
AF13
IN46N
D8
IN68N
D17
OUT09P
F26
IN02P
AE22
IN24P
AF12
IN46P
E8
IN68P
C17
OUT10N
L24
IN03N
AC21
IN25N
AF11
IN47N
C9
IN69N
D18
OUT10P
K24
G25
IN03P
AD21
IN25P
AE11
IN47P
C8
IN69P
C18
OUT11N
IN04N
AF21
IN26N
AE10
IN48N
A7
IN70N
B19
OUT11P
G26
IN04P
AE21
IN26P
AF10
IN48P
B7
IN70P
A19
OUT12N
M24
IN05N
AC20
IN27N
AE9
IN49N
A8
IN71N
D19
OUT12P
M23
IN05P
AB19
IN27P
AF9
IN49P
B8
IN71P
C19
OUT13N
L26
IN06N
AC19
IN28N
AC10
IN50N
C10
IN72N
E20
OUT13P
L25
IN06P
AD20
IN28P
AD10
IN50P
B10
IN72P
D20
OUT14N
N24
IN07N
AF20
IN29N
AC9
IN51N
A9
IN73N
A20
OUT14P
N23
IN07P
AE20
IN29P
AD9
IN51P
B9
IN73P
B20
OUT15N
M26
IN08N
AC17
IN30N
AC8
IN52N
D10
IN74N
B21
OUT15P
M25
IN08P
AC18
IN30P
AD8
IN52P
D9
IN74P
C20
OUT16N
H25
IN09N
AF19
IN31N
AC7
IN53N
C11
IN75N
D21
OUT16P
H26
J25
IN09P
AE19
IN31P
AD7
IN53P
B11
IN75P
C21
OUT17N
IN10N
AD18
IN32N
AF8
IN54N
D11
IN76N
B23
OUT17P
J26
IN10P
AD19
IN32P
AE8
IN54P
E11
IN76P
A23
OUT18N
K26
IN11N
AF18
IN33N
AE7
IN55N
D12
IN77N
B24
OUT18P
K25
IN11P
AE18
IN33P
AF7
IN55P
C12
IN77P
A24
OUT19N
P24
IN12N
AC16
IN34N
AE4
IN56N
A10
IN78N
A22
OUT19P
N25
IN12P
AB16
IN34P
AF4
IN56P
A11
IN78P
A21
OUT20N
R23
IN13N
AD16
IN35N
AB7
IN57N
A12
IN79N
C22
OUT20P
R22
IN13P
AD17
IN35P
AC6
IN57P
B12
IN79P
B22
OUT21N
P25
IN14N
AD15
IN36N
AE3
IN58N
B13
NC
E21
OUT21P
N26
IN14P
AC15
IN36P
AF3
IN58P
A13
OUT00N
C26
OUT22N
R24
IN15N
AC14
IN37N
AE6
IN59N
B15
OUT00P
C25
OUT22P
T23
IN15P
AD14
IN37P
AD6
IN59P
A15
OUT01N
D26
OUT23N
U22
IN16N
AE17
IN38N
AF5
IN60N
C13
OUT01P
D25
OUT23P
U23
IN16P
AF17
IN38P
AF6
IN60P
D13
OUT02N
G22
OUT24N
P26
IN17N
AF16
IN39N
AE5
IN61N
C15
OUT02P
F23
OUT24P
R26
IN17P
AE16
IN39P
AD5
IN61P
C14
OUT03N
F24
OUT25N
T26
IN18N
AF15
IN40N
A3
IN62N
E15
OUT03P
G23
OUT25P
T25
IN18P
AE15
IN40P
B3
IN62P
D15
OUT04N
J23
OUT26N
U26
IN19N
AF14
IN41N
A4
IN63N
D16
OUT04P
H23
OUT26P
U25
IN19P
AE14
IN41P
B4
IN63P
C16
OUT05N
H24
OUT27N
V24
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
Table 23
Ball Name
OUT27P
Ball # Ball Name
V25
OCX160 Pinout By Ball Name (Continued)
Ball # Ball Name
Ball # Ball Name
Ball # Ball Name
Ball #
OUT51N
Y1
OUT74P
F2
VDD.CORE
K22
VSS
AB14
AB22
OUT28N
T24
OUT51P
AA1
OUT75N
E2
VDD.CORE
U5
VSS
OUT28P
R25
OUT52N
U3
OUT75P
E1
VDD.CORE
V5
VSS
AC4
OUT29N
V23
OUT52P
U2
OUT76N
G3
VDD.CORE
V22
VSS
AC13
OUT29P
U24
OUT53N
R4
OUT76P
G4
VDD.CORE
AB9
VSS
AC23
OUT30N
W26
OUT53P
R3
OUT77N
F4
VDD.CORE
AB17
VSS
AC24
OUT30P
V26
OUT54N
P3
OUT77P
F3
VDD.CORE
AB18
VSS
AD3
OUT31N
W23
OUT54P
P4
OUT78N
C2
VDD.IN
E7
VSS
AD24
OUT31P
W22
OUT55N
R2
OUT78P
C1
VDD.IN
E12
VSS
AE2
OUT32N
W24
OUT55P
R1
OUT79N
D2
VDD.IN
E16
VSS
AE25
OUT32P
W25
OUT56N
W1
OUT79P
D1
VDD.IN
E19
VSS
AF1
OUT33N
AB26
OUT56P
W2
RCI2
C4
VDD.IN
AB8
VSS
AF26
OUT33P
AC26
OUT57N
U1
RCI3
C5
VDD.IN
AB11
OUT34N
Y25
OUT57P
T1
RCA0
AD22
VDD.IN
AB15
AB20
OUT34P
Y26
OUT58N
T2
RCA1
AD23
VDD.IN
OUT35N
AA25
OUT58P
T3
RCA2
AB6
VDD.PAD
G5
OUT35P
AA26
OUT59N
N3
RCA3
AC5
VDD.PAD
H22
OUT36N
AA24
OUT59P
P2
RCA4
AD4
VDD.PAD
L5
M22
OUT36P
AB25
OUT60N
M4
RCA5
AF2
VDD.PAD
OUT37N
Y23
OUT60P
M5
RCA6
AE1
VDD.PAD
R5
OUT37P
Y24
OUT61N
P1
RCB0
AD1
VDD.PAD
T22
OUT38N
AB23
OUT61P
N1
RCB1
AD2
VDD.PAD
W5
OUT38P
AB24
OUT62N
M3
RCB2
AB4
VDD.PAD
Y22
OUT39N
AA22
OUT62P
L4
RCB3
AA5
VSS
A1
OUT39P
AA23
OUT63N
M2
RCB4
E3
VSS
A2
OUT40N
AC3
OUT63P
L3
RCB5
E4
VSS
A26
OUT40P
AC2
OUT64N
N2
RCB6
F5
VSS
B2
OUT41N
AA4
OUT64P
M1
RC_CLK#
B1
VSS
B25
OUT41P
Y5
OUT65N
L1
RC_EN#
D3
VSS
C3
OUT42N
AB3
OUT65P
L2
RCI0
E6
VSS
C24
OUT42P
AB2
OUT66N
K1
RCI1
D5
VSS
D4
OUT43N
Y4
OUT66P
K2
RCO4
A25
VSS
D14
OUT43P
W4
OUT67N
J1
RCO0
AB21
VSS
D23
OUT44N
Y3
OUT67P
J2
RCO1
AC25
VSS
E5
OUT44P
Y2
OUT68N
K5
RCO2
AD26
VSS
E13
OUT45N
W3
OUT68P
K4
RCO3
AD25
VSS
E14
OUT45P
V4
OUT69N
K3
TCK
D22
VSS
E17
OUT46N
V1
OUT69P
J3
TDI
C23
VSS
E22
OUT46P
V2
OUT70N
J4
TDO
D24
VSS
N4
OUT47N
V3
OUT70P
H3
TMS
F22
VSS
N5
OUT47P
U4
OUT71N
H4
TRST#
E23
VSS
N22
OUT48N
AC1
OUT71P
H5
UPDATE#
E24
VSS
P5
OUT48P
AB1
OUT72N
H1
VDD.CORE
E9
VSS
P22
OUT49N
T5
OUT72P
H2
VDD.CORE
E10
VSS
P23
OUT49P
T4
OUT73N
G1
VDD.CORE
E18
VSS
AB5
OUT50N
AA2
OUT73P
G2
VDD.CORE
J5
VSS
AB10
OUT50P
AA3
OUT74N
F1
VDD.CORE
J22
VSS
AB13
I-Cube, Inc.
[Rev. 1.6] 2/20/01
37
OCX160 Crosspoint Switch—Preliminary Data Sheet
5.4 Package Dimensions
(BOTTOM VIEW)
(TOP VIEW)
(SIDE VIEW)
Figure 21 OCX160 Package—Bottom, Top and Side Views
38
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
5.5 Package Thermal Characteristics
Table 24
Package Thermal Coefficients
Package
Pin Count
ΘJC(C/W)
ΘJA(°C/W)
Still Air
PBGA
420
1.7°C/W
12°C/W
NOTE:
1.
I-Cube, Inc.
Thermal performance values are based on simulation data.
[Rev. 1.6] 2/20/01
39
OCX160 Crosspoint Switch—Preliminary Data Sheet
6. Power Consumption
There are two main factors to consider when calculating power consumption for the OCX160:
• Power consumed by the chip
• Power dissipated by the terminating resistors at the switch differential outputs
The first component, chip power, consists of three integral elements (refer to Figure 22):
1. Input Power—This element is fixed (always ON) due to the DC current for differential outputs.
2. Core Power—This element is the same for LVDS or LVPECL outputs. Core power is a function of
data rate (Mb/s) and the number of connection paths through the switch matrix.
3. Ouput Power—This element is a fixed amount for each differential output. The value is zero if the
Output Enable (OE#) is disabled or set to OFF.
The second component, termination power, is the power dissipated by the terminating resistors at the
switch differential outputs. The value is zero if the Output Enable (OE#) is disabled or set to OFF.
The following diagram shows the chip power elements (as described above), the formulas used for
determining chip power, and the total power consumption as determined by the formula [Chip Power +
Termination Power].
6.1 Power for LVDS I/O
Chip Power
Core
Power
Input
Power
+
Termination Power
Output
Power
Termination
Power
(always ON)
RS
Switch
Matrix
Output
Buffer
RDIV
RS
CLK
4mW/Input
+
0.015mW/Mbs/Connection
+
Chip Power
+
800mW
16mW/Output (Load)
Termination Power
Example: Worst Case = (4mW x 80) + (0.015 mW x 667 x 80) + (4mW x 80)
320mW
+
4mW/Output
+
(16mW x 80)
+
320mW
+
1280mW
=
1440mW
+
1280mW
= 2.72 watts (total power consumption)
Figure 22 Power Consumption Diagram for the OCX160 using LVDS
40
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
6.2 Power for LVPECL I/O
Chip Power
Core
Power
Input
Power
+
Termination Power
Output
Power
Termination
Power
(always ON)
RS
Switch
Matrix
Output
Buffer
RDIV
RS
CLK
4mW/Input
+
0.015mW /Mbs/Connection
+
Chip Power
+
800mW
28mW/Output (Load)
Termination Power
Example: Worst Case = (4mW x 80) + (0.015 mW x 667 x 80) + (4mW x 80)
320mW
+
4mW/Output
+
(28mW x 80)
+
320mW
+
2240mW
=
1440mW
+
2240mW
= 3.68 watts (total power consumption)
Figure 23 Power Consumption Diagram for the OCX160 using LVPECL
I-Cube, Inc.
[Rev. 1.6] 2/20/01
41
OCX160 Crosspoint Switch—Preliminary Data Sheet
7. Component Availability and Ordering Information
OCXxxx - PPT
Family
# I/O Ports
Package Code
PB = Ball Grid Array
Temperature Range
Blank - Commercial (0°C to 70°C)
I - Industrial (-40°C to +85°C)
8. Glossary
CLOCK: A single differential input used to gate data into registers in the Output Buffer. The input serves all
outputs of the OCX. The neighbor input can also be used as a register clock.
CROSSPOINT: A single cell controlled by two RAM bits. The RAM bits are connected in a master-slave
configuration to provide an update for programming and changing program information all at once.
CROSSPOINT ARRAY: An array of Crosspoint cells used to connect any input port to any output port.
INPUT OR OUTPUT PATH: The signal flow from pin to array and array to pin. Each path has a register with
selectable clocks, drivers for the loaded outputs with selectable enables, and sense circuits to detect changes on
either side of the IO Buffer.
NEXT NEIGHBOR: A physically adjacent port can be used as a clock source for an output configured in
registered mode. These outputs are grouped in pairs such that the signal being switched through Output 0 can be
used to clock the signal being switched through Output 1, or vice-versa. Any single clock or data input signal
can be used to clock any other input signal provided they are switched to an appropriate output pair.
PORT: A name followed by a number to identify a pin on the device.
RAPIDCONFIGURE: A parallel programming method for the OCX devices. The RC mode uses 25 dedicated
pins to program the Crosspoint Array and the IO Buffers. The 25 pins consist of an enable, a clock, four
instruction bits, two seven-bit address fields, and a five-bit data field.
42
[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch—Preliminary Data Sheet
Revision History
Date/
Version No.
6/16/2000
Revision 1.0
Initial release of “Advanced” data sheet
9/25/00
Revision 1.1
Additions include RCO output pin information, pinout drawing, pinout tables,
package dimensions and illustration, duty-cycle diagram, thermal characteristics
table, device reset options table, a section on configuring multiple devices,
bitstream generation and downloading, JTAG information, and Power Consumption
information/illustrations.
10/20/00
Revision 1.2
Corrections to RC Programming table. Additions/corrections to multiple tables and
timing diagrams.
11/16/00
Revision 1.3
Updated RapidConfigure Read Cycle timing diagram so that RCO is relative to
RC_CLK#; RCO was previously relative to RC_EN#. Replaced “+” on signal
names to “P” and “-” to “N”. Corrected RCO[4:0] pin locations. Changed product
status definition from Advanced to Preliminary.
11/21/00
Revision 1.4
Corrected Pinout drawing and Pinout tables to reflect that “P” and “N” are reversed
on OUT40 to OUT79.
12/14/00
Revision 1.5
Corrections to Table 22 “Pinout By Ball Sequence” to match Pinout
drawing—changed ball name on T4 and T5 from OUT49N and OUT49P to
OUT49P and OUT49N resepctively; ball # for IN07P corrected from AD20 to
AE20.
Corrections to Table 23 “Pinout By Ball Name” to match Pinout
drawing—corrected IN07P ball # from AD20 to AE20; corrected OUT49P (T5)
and OUT49N (T4) to be OUT49N (T5) and OUT49P (T4); corrected OUT50P
(AA2) and OUT50N (AA3) to be OUT50N (AA2) and OUT50P (AA3).
1/20/2001
Revision 1.6
Changed the VIH, VIL, VOH, and VOL minimum and maximum values for LVPECL
DC specifications in Table 20; added a note below table explaining the current
values; changed Pass Transistor to proprietary high-performance buffering circuit.
I-Cube, Inc.
Description
[Rev. 1.6] 2/20/01
43
OCX160 Crosspoint Switch—Preliminary Data Sheet
9. Product Status Definition
Data Sheet Identification
Advanced
Product Status
Definition
Formative or In Design
This data sheet contains the design specifications for
product development. Specification may change in any
manner without notice.
Preproduction Product
This data sheet contains the preliminary data, and
supplementary data will be published at a later date. I-Cube
reserves the right to make changes at any time without
notice in order to improve design and supply the best
possible product.
Preliminary
No Identification
Full Production
Obsolete
No longer in Production
This data sheet contains final specifications. I-Cube
reserves the right to make changes at any time without
notice in order to improve design and supply the best
possible product.
This data sheet contains specifications for a product that
has been discontinued by I-Cube. The data sheet is
provided for reference information only.
I-Cube® is a registered trademark and RapidConnect, RapidConfigure, ActiveArray, ImpliedDisconnect, IQ, IQX,
MSX, MSXPro, OCX, OCXPro, and PSX are trademarks of I-Cube, Inc. All other trademarks or registered trademarks
are the property of their respective holders. I-Cube, Inc., does not assume any liability arising out of the applications
or use of the product described herein; nor does it convey any license under its patents, copyright rights or any rights
of others.
The information contained in this document is believed to be current and accurate as of the publication date. I-Cube
reserves the right to make changes, at any time, in order to improve reliability, function, performance or design in order
to supply the best product possible.
I-Cube assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction
if such be made.
This product is protected under the U.S. patents: 5202593, 5282271, 5426738, 5428750, 5428800, 5465056, 5530814,
5559971, 5625780, 5710550, 5717871, 5734334, 5781717, 5790048. Additional patents pending.
OCX160 Crosspoint Switch Data Sheet— Rev 1.6, February 2001
Copyright © 1992-2001 I-Cube, Inc. All rights reserved. Unpublished—rights reserved under the copyright laws of
the United States. Use of copyright notices is precautionary and does not imply publication or disclosure.
I-Cube®, Inc.
2605 S. Winchester Blvd.
Campbell, CA 95008 USA
Phone:
Fax:
Email:
Internet:
44
+(408) 341-1888
+(408) 341-1899
[email protected]
http://www.icube.com
OCX160 Crosspoint Switch Data Sheet
Revision 1.6, February 2001
Document#: MKT-OCX-DS_Rev+1+dot+6
[Rev. 1.6] 2/20/01
I-Cube, Inc.