ETC2 AD7091R-8BRUZ-RL7 2-/4-/8-channel, 1 msps, ultralow power, 12-bit adc in 16-/20-/24-lead tssop Datasheet

FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fast throughput rate: 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Ultralow power: 467 µA typical at 3 V and 1 MSPS
On-chip accurate 2.5 V reference, 5 ppm/°C typical drift
2, 4, and 8 single-ended analog input channels
Programmable channel sequencer
ALERT function available in 4- and 8-channel versions
BUSY indication available in 4- and 8-channel versions
GPOx pins available in 4- and 8-channel versions
Wide input bandwidth
70 dB signal-to-noise ratio (SNR) typical at input
frequency of 10 kHz
Flexible power/throughput rate management
No pipeline delays
High speed serial interface
SPI/QSPI™/MICROWIRE™/DSP compatible
Daisy-chain mode
Power-down mode
550 nA typical at VDD = 5.25 V
435 nA typical at VDD = 3 V
16-lead, 20-lead, and 24-lead TSSOP packages
Temperature range: −40°C to +125°C
MUXOUT
ADCIN
VDD
REFIN/
REFOUT
2.5V
VREF
VIN0
VIN1
T/H
VIN2
REGCAP
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
VDRIVE
VIN3
VIN4
I/P
MUX
RESET
VIN5
CONVST
ON-CHIP
OSC
VIN6
VIN7
SDO
CONTROL LOGIC
AND REGISTERS
SDI
SCLK
CS
CHANNEL
SEQUENCER
AD7091R-8
ALERT/
BUSY/
GPO0
GND
GPO1
GND
10891-001
Data Sheet
2-/4-/8-Channel, 1 MSPS, Ultralow Power,
12-Bit ADC in 16-/20-/24-Lead TSSOP
AD7091R-2/AD7091R-4/AD7091R-8
Figure 1.
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
Optical sensors
Diagnostic/monitoring functions
The AD7091R-2/AD7091R-4/AD7091R-8 family offers up to eight
single-ended analog input channels with a channel sequencer
that allows a preprogrammed selection of channels to be converted
sequentially.
GENERAL DESCRIPTION
The AD7091R-2/AD7091R-4/AD7091R-8 family is a multichannel
12-bit, ultralow power, successive approximation analog-toconverter (ADC) that is available in two, four, or eight analog
input channel options. The AD7091R-2/AD7091R-4/AD7091R-8
operate from a single 2.7 V to 5.25 V power supply and is capable
of achieving a sampling rate of 1 MSPS. The AD7091R-2/
AD7091R-4/AD7091R-8 contain a wide bandwidth track-andhold amplifier that can operate at input frequencies in excess of
1.5 MHz. The AD7091R-2/AD7091R-4/AD7091R-8 also feature
an on-chip conversion clock, an on-chip accurate 2.5 V reference,
and a high speed serial interface.
Rev. 0
The AD7091R-2/AD7091R-4/AD7091R-8 have a serial port
interface (SPI) that allows data to be read after the conversion
while achieving a 1 MSPS throughput rate. The conversion process
and data acquisition are controlled using the CONVST pin.
The AD7091R-2/AD7091R-4/AD7091R-8 use advanced design
techniques to achieve ultralow power dissipation at high
throughput rates. They also feature flexible power management
options. An on-chip configuration register allows the user to set up
different operating conditions. These include power management,
alert functionality, busy indication, channel sequencing, and
general-purpose output pins. The MUXOUT and ADCIN pins allow
signal conditioning of the multiplexer output prior to
acquisition by the ADC.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Powered by TCPDF (www.tcpdf.org)
IMPORTANT LINKS for the AD7091R-2_7091R-4_7091R-8*
Last content update 02/19/2014 10:48 am
SIMILAR PRODUCTS & PARAMETRIC SELECTION TABLES
DESIGN COLLABORATION COMMUNITY
Find Similar Products By Operating Parameters
Collaborate Online with the ADI support team and other designers
about select ADI products.
DOCUMENTATION
UG-633: Evaluating the AD7091R-2/AD7091R-4/AD7091R-8 12-Bit
Monitor and Control System
Follow us on Twitter: www.twitter.com/ADI_News
Like us on Facebook: www.facebook.com/AnalogDevicesInc
SUGGESTED COMPANION PRODUCTS
DESIGN SUPPORT
Submit your support request here:
Recommended Driver Amplifiers for the AD7091R-2/ AD7091R-4/
AD7091R-8
For low frequency and low bias current, we recommend the
ADA4627-1, ADA4637-1 or the AD8610.
For precision, low power, rail-to-rail output, we recommend
the ADA4841-1, ADA4896-2 or the AD8031.
For high frequency, low noise, low distortion, we recommend
the ADA4899-1, ADA4897-1 or the AD8021.
For additional driver amplifier selections, we recommend
selecting the product category and filtering on our parametric
search tables.
Recommended External References for the AD7091R-2/
AD7091R-4/ AD7091R-8
For a 3V, low power, low noise, we recommend the ADR4530
or the REF193.
For a 5V, low power, low noise, we recommend the ADR4550
or the REF195.
For additional voltage reference selections, we recommend
filtering on our parametric search tables.
Recommended Power Solutions for the AD7091R-2/ AD7091R-4/
AD7091R-8
For selecting voltage regulator products, use ADIsimPower.
For selecting supervisor products, use the Supervisor
Parametric Search.
Linear and Data Converters
Embedded Processing and DSP
Telephone our Customer Interaction Centers toll free:
Americas:
Europe:
China:
India:
Russia:
1-800-262-5643
00800-266-822-82
4006-100-006
1800-419-0108
8-800-555-45-90
Quality and Reliability
Lead(Pb)-Free Data
Package Information
SAMPLE & BUY
AD7091R-2
AD7091R-4
AD7091R-8
View Price & Packaging
Request Evaluation Board
Request Samples
Check Inventory & Purchase
Find Local Distributors
EVALUATION KITS & SYMBOLS & FOOTPRINTS
View the Evaluation Boards and Kits page for documentation and
purchasing
Symbols and Footprints for the AD7091R-2
Symbols and Footprints for the AD7091R-4
Symbols and Footprints for the AD7091R-8
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.
Note: Dynamic changes to the content on this page (labeled 'Important Links') does not
constitute a change to the revision number of the product data sheet.
This content may be frequently modified.
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Conversion Result Register ....................................................... 22
Applications ....................................................................................... 1
Channel Register ........................................................................ 23
General Description ......................................................................... 1
Configuration Register .............................................................. 24
Functional Block Diagram .............................................................. 1
Alert Indication Register ........................................................... 26
Revision History ............................................................................... 2
Channel x Low Limit Register .................................................. 28
Specifications..................................................................................... 3
Channel x High Limit Register ................................................. 28
Timing Specifications .................................................................. 5
Channel x Hysteresis Register .................................................. 28
Absolute Maximum Ratings ............................................................ 7
Serial Interface ................................................................................ 29
Thermal Resistance ...................................................................... 7
Reading Conversion Result ....................................................... 29
ESD Caution .................................................................................. 7
Writing Data to the Registers ................................................... 29
Pin Configurations and Function Descriptions ........................... 8
Reading Data from the Registers.............................................. 29
Typical Performance Characteristics ........................................... 12
Modes of Operation ....................................................................... 31
Terminology .................................................................................... 17
Normal Mode .............................................................................. 31
Theory of Operation ...................................................................... 18
Power-Down Mode .................................................................... 31
Circuit Information .................................................................... 18
ALERT (AD7091R-4 and AD7091R-8 Only) .......................... 32
Converter Operation .................................................................. 18
BUSY (AD7091R-4 and AD7091R-8 Only) ............................. 32
ADC Transfer Function ............................................................. 18
Channel Sequencer .................................................................... 33
Reference ..................................................................................... 18
Daisy Chain ................................................................................. 34
Typical Connection Diagram.................................................... 19
Outline Dimensions ....................................................................... 36
Analog Input ............................................................................... 19
Ordering Guide .......................................................................... 37
Registers ........................................................................................... 21
Addressing Registers .................................................................. 21
REVISION HISTORY
12/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE = 1.8 V to 5.25 V, VREF = 2.5 V internal reference, fSAMPLE = 1 MSPS, fSCLK = 50 MHz, TA = TMIN to TMAX, unless
otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
Signal-to-Noise + Distortion (SINAD)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Channel-to-Channel Isolation
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
Offset Error Matching
Offset Error Drift
Gain Error
Gain Error Matching
Gain Error Drift
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance 1
VOLTAGE REFERENCE INPUT/OUTPUT
REFOUT 2
REFIN2
Drift
Power-On Time
LOGIC INPUTS
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IIN)
LOGIC OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
Floating State Leakage Current
Output Coding
CONVERSION RATE
Conversion Time
Transient Response
Throughput Rate
Test Conditions/Comments
fIN = 10 kHz sine wave
Min
Typ
66.5
65.5
70
69
−80
−81
−95
5
40
1.5
1.2
fIN = 1 kHz sine wave
At −3 dB
At −0.1 dB
VDD ≥ 3.0 V
VDD ≥ 2.7 V
Guaranteed no missing codes to 12 bits
TA = 25°C
TA = 25°C
12
−1
−1.25
−0.9
−1.5
−1.5
TA = 25°C
TA = 25°C
−0.1
−0.1
±0.7
±0.8
±0.3
0.2
0.2
2
0.0
0.0
2
0
−1
During acquisition phase
Outside acquisition phase
Internal reference output, TA = 25°C
External reference input
Max
dB
dB
dB
dB
dB
ns
ps
MHz
MHz
+1
+1.25
+0.9
+1.5
+1.5
+0.1
+0.1
2.5
V
µA
pF
pF
2.51
VDD
V
V
ppm/°C
ms
5
50
CREF = 2.2 µF
0.7 × VDRIVE
0.3 × VDRIVE
+1
Typically 10 nA, VIN = 0 V or VDRIVE
−1
ISOURCE = 200 µA
ISINK = 200 µA
VDRIVE − 0.2
−1
Full-scale step input
Rev. 0 | Page 3 of 40
Bits
LSB
LSB
LSB
mV
mV
ppm/°C
% FS
% FS
ppm/°C
VREF
+1
10
1.5
2.49
1.0
Unit
0.4
+1
Straight (natural) binary
600
400
1
V
V
µA
V
V
µA
ns
ns
MSPS
AD7091R-2/AD7091R-4/AD7091R-8
Parameter
POWER REQUIREMENTS
VDD
VDRIVE
VDRIVE Range 3
IDD
Normal Mode—Static 4
Normal Mode—Operational
Power-Down Mode
IDRIVE
Normal Mode—Static 5
Normal Mode—Operational
Power-Down Mode
Total Power Dissipation 6
Normal Mode—Static
Normal Mode—Operational
Power-Down Mode
Data Sheet
Test Conditions/Comments
Specified performance
Functional
VIN = 0 V
VDD = 5.25 V
VDD = 3 V
VDD = 5.25 V, fSAMPLE = 1 MSPS
VDD = 3 V, fSAMPLE = 1 MSPS
VDD = 5.25 V
VDD = 5.25 V, TA = −40°C to +85°C
VDD = 3 V
VIN = 0 V
VDRIVE = 5.25 V
VDRIVE = 3 V
VDRIVE = 5.25 V, fSAMPLE = 1 MSPS
VDRIVE = 3 V, fSAMPLE = 1 MSPS
VDRIVE = 5.25 V
VDRIVE = 3 V
VIN = 0 V
VDD = VDRIVE = 5.25 V
VDD = VDRIVE = 3 V
VDD = VDRIVE = 5.25 V, fSAMPLE = 1 MSPS
VDD = VDRIVE = 3 V, fSAMPLE = 1 MSPS
VDD = 5.25 V
VDD = 5.25 V, TA = −40°C to +85°C
VDD = VDRIVE = 3 V
Min
Typ
Max
Unit
5.25
5.25
5.25
V
V
V
22
21.6
500
450
0.550
0.550
0.435
50
46
570
530
17
6
15
µA
µA
µA
µA
µA
µA
µA
2
1
30
17
4
3.5
70
15
1
1
µA
µA
µA
µA
µA
µA
0.130
0.070
2.8
1.4
3
3
1.4
0.290
0.149
3.4
1.7
95
33
50
mW
mW
mW
mW
µW
µW
µW
2.7
2.7
1.8
Sample tested during initial release to ensure compliance.
When referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configurations and Function Descriptions section.
3
Device is functional and meets dynamic performance/dc accuracy specifications with VDRIVE down to 1.8 V, but the device is not capable of achieving a throughput of
1 MSPS.
4
SCLK operates in burst mode, and CS idles high. With a free running SCLK and CS pulled low, the IDD static current is increased by 30 µA typical at VDD = 5.25 V.
5
SCLK operates in burst mode, and CS is idles high. With a free running SCLK and CS pulled low, the IDRIVE static current is increased by 32 µA typical at VDRIVE = 5.25 V.
6
Total power dissipation includes contributions from VDD, VDRIVE, and REFIN (see Note 2).
1
2
Rev. 0 | Page 4 of 40
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE = 1.8 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
500µA
Symbol
tCONVERT
tACQ
tCYC
tCNVPW
tSCLK
12
13
14
20
tEOCCSL
tEN
tDIS
tSSDISCLK
tHSDISCLK
tQUIET
5
5
5
5
2
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDELAY
VIH2
VIL2
10891-138
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Y% VDRIVE
tDELAY
IOH
500
20
25
6
6
5
tSCLKL
tSCLKH
tHSDO
tDSDO
1.4V
500µA
Max
600
tSCLK
X% VDRIVE
CL
20pF
400
1000
10
Typ
16
22
IOL
TO SDO
Min
VIH2
VIL2
NOTES
1FOR V
DRIVE ≤ 3.0V, X = 90 AND Y = 10; FOR VDRIVE > 3.0V, X = 70 AND Y = 30.
2MINIMUM V AND MAXIMUM V USED. SEE SPECIFICATIONS FOR DIGITAL
IL
IH
INPUTS PARAMETER IN TABLE 2.
Figure 3. Voltage Levels for Timing
Figure 2. Load Circuit for Digital Interface Timing
Rev. 0 | Page 5 of 40
10891-139
Parameter
Conversion Time: CONVST Falling Edge to Data Available
Acquisition Time
Time Between Conversions (Normal Mode)
CONVST Pulse Width
SCLK Period (Normal Mode)
VDRIVE Above 2.7 V
VDRIVE Above 1.8 V
SCLK Period (Chain Mode)
VDRIVE Above 2.7 V
VDRIVE Above 1.8 V
SCLK Low Time
SCLK High Time
SCLK Falling Edge to Data Remains Valid
SCLK Falling Edge to Data Valid Delay
VDRIVE Above 4.5 V
VDRIVE Above 3.3 V
VDRIVE Above 2.7 V
VDRIVE Above 1.8 V
End of Conversion to CS Falling Edge
CS Low to SDO Enabled
CS High or Last SCLK Falling Edge to SDO High Impedance
SDI Data Setup Time Prior to SCLK Rising Edge
SDI Data Hold Time After SCLK Rising Edge
Last SCLK Falling Edge to Next CONVST Falling Edge
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
Timing Diagram
tCYC
EOC
tACQ
tCNVPW
CONVST
tQUIET
tCONVERT
tEOCCSL
CS
1
SCLK
tSCLK
2
6
7
15
DB10
DB9
DB1
5
tSCLKL
CH_ID2
CH_ID1
CH_ID0
ADD4
ADD3
ADD2
ALERT
DB11
16
tDIS
TRISTATE
tSSDISCLK
SDI
tSCLKH
4
tDSDO
tEN
SDO
3
tHSDISCLK
ADD1
ADD0
RW
DB9
Figure 4. Serial Port Timing
Rev. 0 | Page 6 of 40
DB1
TRISTATE
DB0
DB0
10891-002
tHSDO
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 3.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
VDD to GND
VDRIVE to GND
Analog Input Voltage to GND
Digital Input1 Voltage to GND
Digital Output2 Voltage to GND
Input Current to Any Pin Except Supplies3
Operating Temperature Range
Storage Temperature Range
Junction Temperature
ESD
Human Body Model (HBM)
Field Induced Charged Device Model
(FICDM)
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VREF + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
±10 mA
−40°C to +125°C
−65°C to +150°C
150°C
Table 4. Thermal Resistance
Package Type
24-Lead TSSOP
20-Lead TSSOP
16-Lead TSSOP
ESD CAUTION
1.5 kV
500 V
The digital input pins include the following: RESET, CONVST, SDI, SCLK, and CS.
The digital output pins include the following: SDO, GPO1, and ALERT/BUSY/GPO0.
3
Transient currents of up to 100 mA do not cause SCR latch-up.
1
2
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 7 of 40
θJA
73.54
84.29
106.03
θJC
14.94
18.43
28.31
Unit
°C/W
°C/W
°C/W
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
CS 1
RESET
15 CONVST
VDD
3
14 SCLK
REGCAP 4
REFIN/REFOUT 5
AD7091R-2
13 SDO
TOP VIEW
(Not to Scale)
12 SDI
GND
6
11 GND
MUXOUT
7
10 ADC IN
VIN0 8
9
VIN1
10891-007
16 VDRIVE
2
Figure 5. 2-Channel Pin Configuration
Table 5. 2-Channel Pin Function Descriptions
Pin No.
1
2
3
4
Mnemonic
CS
RESET
VDD
REGCAP
5
REFIN/REFOUT
6, 11
7
GND
MUXOUT
8
9
10
VIN0
VIN1
ADCIN
12
SDI
13
SDO
14
15
SCLK
CONVST
16
VDRIVE
Description
Chip Select Input. When CS is held low, the serial bus enables and CS frames the output data on the SPI.
Reset. Logic input.
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND.
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this output pin separately to
GND using a 2.2 µF capacitor.
Voltage Reference Output, 2.5 V. Decouple this pin to GND. The typical recommended decoupling capacitor
value is 2.2 µF. The user can either access the internal 2.5 V reference or overdrive the internal reference with
the voltage applied to this pin. The reference voltage range for an externally applied reference is 1.0 V to VDD.
Chip Ground. These pins are the ground reference point for all circuitry on the AD7091R-2.
Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or buffering is
required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the conditioning network to the
ADCIN pin.
Analog Input 0. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 1. Single-ended analog input. The analog input range is 0 V to VREF.
ADC Input. This pin allows access to the on-chip track-and-hold. If no external filtering or buffering is required,
tie this pin directly to the MUXOUT pin; otherwise tie the input of the conditioning network to the MUXOUT pin.
Serial Data Input Bus. This input provides the data written to the on-chip control registers. Data clocks into the
registers on the falling edge of the SCLK input. Provide data most significant bits (MSB) first.
Serial Data Output Bus. The conversion output data is supplied to this pin as a serial data stream. The bits are
clocked out on the falling edge of the SCLK input, and 13 SCLK cycles are required to access the data. The data is
provided MSB first.
Serial Clock. This pin acts as the serial clock input.
Convert Start Input Signal. Edge triggered logic input. The falling edge of CONVST places the track-and-hold
mode into hold mode and initiates a conversion.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
Connect decoupling capacitors between VDRIVE and GND. The typical recommended values are 10 µF and
0.1 µF. The voltage range on this pin is 1.8 V to 5.25 V and may be different from the voltage range at VDD but
must never exceed it by more than 0.3 V.
Rev. 0 | Page 8 of 40
AD7091R-2/AD7091R-4/AD7091R-8
CS
1
20
VDRIVE
RESET
2
19
CONVST
VDD
3
18
SCLK
REGCAP
4
17
SDO
REFIN/REFOUT
5
AD7091R-4
16
SDI
GND
6
TOP VIEW
(Not to Scale)
15
GND
MUXOUT
7
14
ADCIN
VIN0
8
13
VIN1
VIN2
9
12
VIN3
ALERT/BUSY/GPO0 10
11
GPO1
10891-005
Data Sheet
Figure 6. 4-Channel Pin Configuration
Table 6. 4-Channel Pin Function Descriptions
Pin No.
1
2
3
4
Mnemonic
CS
RESET
VDD
REGCAP
5
REFIN/REFOUT
6, 15
7
GND
MUXOUT
8
9
10
VIN0
VIN2
ALERT/BUSY/GPO0
11
12
13
14
GPO1
VIN3
VIN1
ADCIN
16
SDI
17
SDO
18
19
SCLK
CONVST
20
VDRIVE
Description
Chip Select Input. When CS is held low, the serial bus enables and CS frames the output data on the SPI.
Reset. Logic input.
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND.
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this output pin
separately to GND using a 2.2 µF capacitor.
Voltage Reference Output, 2.5 V. Decouple this pin to GND. The typical recommended decoupling
capacitor value is 2.2 µF. The user can either access the internal 2.5 V reference or overdrive the internal
reference with the voltage applied to this pin. The reference voltage range for an externally applied
reference is 1.0 V to VDD.
Chip Ground. These pins are the ground reference point for all circuitry on the AD7091R-4.
Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or buffering
is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the conditioning network to
the ADCIN pin.
Analog Input 0. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 2. Single-ended analog input. The analog input range is 0 V to VREF.
Alert Output (ALERT). This is a multifunction pin determined by the configuration register. When
functioning as ALERT, this pin is a logic output indicating that a conversion result has fallen outside the
limit of the register settings.
BUSY Output (BUSY). When the ALERT/BUSY/GPO0 pin is configured as a BUSY output, use this pin to
indicate when a conversion is taking place.
General-Purpose Digital Output (GPO0). The pin can also function as a general-purpose digital output.
General-Purpose Digital Output.
Analog Input 3. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 1. Single-ended analog input. The analog input range is 0 V to VREF.
ADC Input. This pin allows access to the on-chip track-and-hold. If no external filtering or buffering is
required, tie this pin directly to the MUXOUT pin; otherwise, tie the input of the conditioning network to
the MUXOUT pin.
Serial Data Input Bus. This input provides data written to the on-chip control registers. Data clocks into the
registers on the falling edge of the SCLK input. Provide data MSB first.
Serial Data Output Bus. The conversion output data is supplied to this pin as a serial data stream. The bits are
clocked out on the falling edge of the SCLK input, and 13 SCLK cycles are required to access the data. The
data is provided MSB first.
Serial Clock. This pin acts as the serial clock input.
Convert Start Input Signal. Edge triggered logic input. The falling edge of CONVST places the track-andhold mode into hold mode and initiates a conversion.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. Connect decoupling capacitors between VDRIVE and GND. The typical recommended values are
10 µF and 0.1 µF. The voltage range on this pin is 1.8 V to 5.25 V and may be different from the voltage
range at VDD but must never exceed it by more than 0.3 V.
Rev. 0 | Page 9 of 40
Data Sheet
CS
1
24
VDRIVE
RESET
2
23
CONVST
VDD
3
22
SCLK
REGCAP
4
21
SDO
REFIN/REFOUT
5
20
SDI
GND
6
AD7091R-8
19
GND
MUXOUT
7
TOP VIEW
(Not to Scale)
18
ADCIN
VIN0
8
17
VIN1
VIN2
9
16
VIN3
ALERT/BUSY/GPO0 10
15
GPO1
VIN4 11
14
VIN5
VIN6 12
13
VIN7
10891-003
AD7091R-2/AD7091R-4/AD7091R-8
Figure 7. 8-Channel Pin Configuration
Table 7. 8-Channel Pin Function Descriptions
Pin No.
1
2
3
4
Mnemonic
CS
RESET
VDD
REGCAP
5
REFIN/REFOUT
6, 19
7
GND
MUXOUT
8
9
10
VIN0
VIN2
ALERT/BUSY/GPO0
11
12
13
14
15
16
17
18
VIN4
VIN6
VIN7
VIN5
GPO1
VIN3
VIN1
ADCIN
20
SDI
21
SDO
22
23
SCLK
CONVST
Description
Chip Select Input. When CS is held low, the serial bus enables and CS frames the output data on the SPI.
Reset. Logic input.
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND.
Decoupling Capacitor Pin For Voltage Output from Internal Regulator. Decouple this output pin
separately to GND using a 2.2 μF capacitor.
Voltage Reference Output, 2.5 V. Decouple this pin to GND. The typical recommended decoupling
capacitor value is 2.2 µF. The user can either access the internal 2.5 V reference or overdrive the internal
reference with the voltage applied to this pin. The reference voltage range for an externally applied
reference is 1.0 V to VDD.
Chip Ground. These pins are the ground reference point for all circuitry on the AD7091R-8.
Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or buffering
is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the conditioning network to
the ADCIN pin.
Analog Input 0. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 2. Single-ended analog input. The analog input range is 0 V to VREF.
Alert Output (ALERT). This is a multifunction pin determined by the configuration register. When
functioning as ALERT, this pin is a logic output indicating that a conversion result has fallen outside the
limit of the register settings.
BUSY Output (BUSY). When the ALERT/BUSY/GPO0 pin is configured as a BUSY output, use this pin to
indicate when a conversion is taking place.
General-Purpose Digital Output (GPO0). The pin can also function as a general-purpose digital output.
Analog Input 4. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 6. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 7. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 5. Single-ended analog input. The analog input range is 0 V to VREF.
General-Purpose Digital Output.
Analog Input 3. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 1. Single-ended analog input. The analog input range is 0 V to VREF.
ADC Input. This pin allows access to the on-chip track-and-hold. If no external filtering or buffering is
required, tie this pin directly to the MUXOUT pin; otherwise, tie the input of the conditioning network to
the MUXOUT pin.
Serial Data Input Bus. Data to be written to the on-chip control registers is provided on this input. Data is
clocked into the registers on the falling edge of the SCLK input. Provide data MSB first.
Serial Data Output Bus. The conversion output data is supplied to this pin as a serial data stream. The bits are
clocked out on the falling edge of the SCLK input, and 13 SCLK cycles are required to access the data. The
data is provided MSB first.
Serial Clock. This pin acts as the serial clock input.
Convert Start Input Signal. Edge triggered logic input. The falling edge of CONVST places the track-andhold mode into hold mode and initiates a conversion.
Rev. 0 | Page 10 of 40
Data Sheet
Pin No.
24
Mnemonic
VDRIVE
AD7091R-2/AD7091R-4/AD7091R-8
Description
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. Connect decoupling capacitors between VDRIVE and GND. The typical recommended values are
10 µF and 0.1 µF. The voltage range on this pin is 1.8 V to 5.25 V and may be different from the voltage
range at VDD but must never exceed it by more than 0.3 V.
Rev. 0 | Page 11 of 40
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
–0.2
VDD = 3.0V
VREF = 2.5V
TA = 25°C
fSAMPLE = 1MSPS
POSITIVE INL = +0.74LSB
NEGATIVE INL = –0.37LSB
–0.4
–0.6
–0.8
–1.0
0
500
1000
1500
2000
0
–0.2
–0.4
VDD = 3.0V
VREF = 2.5V
TA = 25°C
fSAMPLE = 1MSPS
POSITIVE DNL = +0.48LSB
NEGATIVE DNL = –0.50LSB
–0.6
2500
3000
3500
4000
–0.8
–1.0
4500
0
500
1000
1500
2000
CODE
3500
4000
4500
Figure 11. Differential Nonlinearity vs. Code
60000
40000
VDD = VDRIVE = 3.0V
65k SAMPLES
TA = 25°C
35000
NUMBER OF OCCURRENCES
NUMBER OF OCCURRENCES
3000
2500
CODE
Figure 8. Integral Nonlinearity vs. Code
50000
10891-116
DNL (LSB)
1.0
10891-115
INL (LSB)
TYPICAL PERFORMANCE CHARACTERISTICS
40000
30000
20000
VDD = VDRIVE = 3.0V
65k SAMPLES
TA = 25°C
30000
25000
20000
15000
10000
10000
0
2048
2047
10891-120
10891-119
5000
0
2049
2045
2044
Figure 9. Histogram of a DC Input at Code Center
2047
Figure 12. Histogram of a DC Input at Code Transition
0
0
VDD = 3.0V
VREF = 2.5V EXTERNAL
TA = 25°C
fIN = 10kHz
fSAMPLE = 1MSPS
SNR = 69.52dB
SINAD = 69.21dB
THD = –84.25dB
SFDR = –85.79dB
–60
–80
–40
–60
–80
–100
–120
–120
–140
–140
10891-117
–100
–160
0
50
100
150
200
250
300
350
400
450
10891-118
–40
VDD = 3.0V
VREF = 2.5V INTERNAL
TA = 25°C
fIN = 10kHz
fSAMPLE = 1MSPS
SNR = 69.44dB
SINAD = 69.19dB
THD = –84.21dB
SFDR = –85.82dB
–20
SNR (dB)
–20
SNR (dB)
2046
CODE
CODE
–160
0
500
50
100
150
200
250
300
350
400
450
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 10. 10 kHz FFT, VDD = 3.0 V, VREF = 2.5 V External
Figure 13. 10 kHz FFT, VDD = 3.0 V, VREF = 2.5 V Internal
Rev. 0 | Page 12 of 40
500
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
0
72
TA = 25°C
fSAMPLE = 1MSPS
VREF = 2.5V
–10
70
–20
2.7V
3.0V
5.0V
–30
–40
THD (dB)
66
–50
2.7V
3.0V
5.0V
–60
64
–70
TA = 25°C
fSAMPLE = 1MSPS
VREF = 2.5V
62
–80
–90
1
10
–100
10891-108
60
100
INPUT FREQUENCY (kHz)
1
10
10891-109
SNR (dB)
68
100
INPUT FREQUENCY (kHz)
Figure 14. SNR vs. Analog Input Frequency for Various Supply Voltages
Figure 17. THD vs. Analog Input Frequency for Various Supply Voltages
69.6
72
69.5
70
SNR (dB)
66
64
69.3
69.2
69.1
TA = 25°C
fSAMPLE = 1MSPS
VREF = 2.5V
62
69.0
10
68.9
–10
10891-111
60
1
VDD = 5.0V
TA = 25°C
fSAMPLE = 1MSPS
fIN = 10kHz
100
INPUT FREQUENCY (kHz)
10891-123
SINAD (dB)
69.4
2.7V
3.0V
5.0V
68
–9
71.0
–6
–5
–4
–1
–2
–3
0
Figure 18. SNR vs. Input Level
–78
12.00
SNR
SINAD
ENOB
–7
INPUT LEVEL (dB)
Figure 15. SINAD vs. Analog Input Frequency for Various Supply Voltages
72.0
–8
THD
SFDR
11.80
–80
11.60
11.00
67.0
10.80
VDD = 5.0V
TA = 25°C
fSAMPLE = 1MSPS
fIN = 10kHz
66.0
65.0
64.0
1.0
2.0
2.5
3.0
3.5
4.0
4.5
–84
–86
10.60
10.40
10.20
1.5
–82
–88
–90
1.0
5.0
REFERENCE VOLTAGE (V)
VDD = 5.0V
TA = 25°C
fSAMPLE = 1MSPS
fIN = 10kHz
10891-128
68.0
ENOB (Bits)
11.20
THD, SFDR (dB)
11.40
69.0
10891-121
SNR, SINAD (dB)
70.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
REFERENCE VOLTAGE (V)
Figure 16. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 19. THD and SFDR vs. Reference Voltage
Rev. 0 | Page 13 of 40
5.0
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
–80
600
–81
550
–82
500
CURRENT (µA)
THD (dB)
–83
–84
–85
–86
–87
VDD = 5.0V
fSAMPLE = 1MSPS
fIN = 10kHz
450
400
5.25V
5.0V
3.3V
2.7V
350
fSAMPLE = 1MSPS
300
–88
–35
–15
5
25
45
65
85
105
10891-125
–90
–55
250
10891-129
–89
200
25
–40
125
TEMPERATURE (°C)
70
70.8
70.6
60
VDD = 3.0V
VREF = 2.5V
fIN = 10kHz
fSAMPLE = 1MSPS
5.25V
5.0V
3.3V
2.7V
50
CURRENT (µA)
SNR (dB)
70.2
125
Figure 23. Operational IDD Supply Current vs. Temperature
for Various VDD Supply Voltages
Figure 20. THD vs. Temperature
70.4
85
TEMPERATURE (°C)
70.0
69.8
40
30
69.6
20
69.4
–35
–15
5
25
45
65
85
105
10891-126
69.0
–55
10
10891-122
69.2
0
25
–40
125
125
Figure 24. Operational IDRIVE Supply Current vs. Temperature for
Various VDRIVE Supply Voltages
Figure 21. SNR vs. Temperature
500
8
450
IDD (µA) AT VDD = VDRIVE = 3.00V
IDRIVE (µA) AT VDD = VDRIVE = 3.00V
IDD (µA) AT VDD = VDRIVE = 5.00V
IDRIVE (µA) AT VDD = VDRIVE = 5.00V
7
5.25V
5.0V
3.3V
2.7V
6
TOTAL CURRENT (µA)
400
350
300
250
200
150
5
4
3
2
100
200
300
400
500
600
700
800
900
0
1000
–40
THROUGHPUT (kSPS)
Figure 22. Operating Current vs. Throughput
10891-127
50
0
100
1
10891-137
CURRENT (µA)
85
TEMPERATURE (°C)
TEMPERATURE (°C)
25
85
125
TEMPERATURE (°C)
Figure 25. Total Power-Down Current vs. Temperature for Various Supplies
Rev. 0 | Page 14 of 40
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
12
100
VDRIVE = 1.8V, +25°C
VDRIVE = 1.8V, +125°C
95
90
8
VDRIVE = 1.8V, –40°C
PSRR (dB)
VDRIVE = 3V, +125°C
6
85
TA = 25°C
fSAMPLE = 1MSPS
80
4
VREF = 2.5V EXTERNAL
VDRIVE = 3V, +25°C
VDD = VDRIVE = 5.00V
VDD = VDRIVE = 3.00V
VDRIVE = 3V, –40°C
75
2
20
30
40
50
70
SDO CAPACITANCE LOAD (pF)
10
1
Figure 29. PSRR vs. Ripple Frequency
1.5
0.10
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
0.5
0.08
0.06
GAIN ERROR (%FS)
1.0
OFFSET ERROR (mV)
1000
100
RIPPLE FREQUENCY (kHz)
Figure 26. tDSDO Delay vs. SDO Capacitance Load and Supply
0
–0.5
0.04
0.02
0
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
–0.02
–0.04
–0.06
10891-130
–1.0
–1.5
–55
10891-136
10
10891-113
0
–35
–15
25
5
45
65
85
105
–0.08
–0.10
–55
125
–35
–15
TEMPERATURE (°C)
5
25
45
65
85
10891-133
tDSDO DELAY (ns)
10
105
125
105
125
TEMPERATURE (°C)
Figure 30. Gain Error vs. Temperature
Figure 27. Offset Error vs. Temperature
1.5
0.10
0.08
GAIN ERROR MATCH (%FS)
0.5
0
–0.5
0.04
0.02
0
–0.02
–0.04
–35
–15
5
25
45
65
85
105
10891-134
–1.5
–55
0.06
–0.06
–1.0
10891-131
OFFSET ERROR MATCH (mV)
1.0
–0.08
–0.10
–55
125
TEMPERATURE (°C)
–35
–15
5
25
45
65
85
TEMPERATURE (°C)
Figure 31. Gain Error Match vs. Temperature
Figure 28. Offset Error Match vs. Temperature
Rev. 0 | Page 15 of 40
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
–50
VDD = 5.0V
TA = 25°C
fSAMPLE = 1MSPS
–70
TA = 25°C
VDD = 3V
–55
fIN = 10kHz
fSAMPLE = 1MSPS
–60
THD (dB)
–80
–90
–65
–70
–100
–75
–110
–80
10891-124
1
–85
100
10
Figure 35. THD vs. Source Impedance
2.510
INTERNAL REFERENCE VOLTAGE (V)
–87
–89
–91
–93
–95
–97
VDD = 5.0V
fSAMPLE = 1MSPS
fIN = 10kHz
10891-132
CHANNEL-TO-CHANNEL ISOLATION (dB)
–85
–101
–103
–105
–55
–35
–15
5
25
45
65
85
105
VDD = VDRIVE = 3V
2.500
2.498
2.494
2.492
2.490
+25°C
–40°C
+85°C
+125°C
2.486
2.484
60
80
100
CURRENT LOAD (µA)
10891-114
VREF (V)
2.496
40
2.495
–35
–15
5
25
45
65
85
Figure 36. Internal Reference vs. Temperature
2.502
20
2.500
TEMPERATURE (°C)
Figure 33. Channel-to-Channel Isolation vs. Temperature
0
2.505
2.490
–55
125
TEMPERATURE (°C)
2.488
10k
1k
SOURCE IMPEDANCE (Ω)
Figure 32. Channel-to-Channel Isolation vs. Input Frequency
–99
100
10
INPUT FREQUENCY (kHz)
10891-110
–120
10891-135
CHANNEL-TO-CHANNEL ISOLATION (dB)
–60
Figure 34. Reference Voltage Output (VREF) vs. Current Load
for Various Temperatures
Rev. 0 | Page 16 of 40
105
125
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. For the
AD7091R-2/AD7091R-4/AD7091R-8, the endpoints of the
transfer function are zero scale, a point ½ LSB below the first
code transition, and full scale, a point ½ LSB above the last code
transition.
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal 1
LSB change between any two adjacent codes in the ADC.
Offset Error
The offset error is the deviation of the first code transition
(00 … 000 to 00 … 001) from the ideal (such as GND + 0.5 LSB).
Offset Error Match
This is the difference in offset error between any two input
channels.
Gain Error
For the AD7091R-2/AD7091R-4/AD7091R-8, the gain error is
the deviation of the last code transition (111 … 110 to 111 …
111) from the ideal (such as VREF − 1.5 LSB) after the offset
error has been adjusted out.
Gain Error Match
Gain error match is the difference in gain error between any two
input channels.
Transient Response Time
The track-and-hold amplifier returns to track mode after the
end of conversion. The track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within ±0.5 LSB, after the end of conversion.
See the Serial Interface section for more details.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between the selected channel and all of the other
channels. It is measured by applying a full-scale, 10 kHz sine
wave signal to all unselected input channels and determining
the degree to which the signal attenuates in the selected channel
that has a dc signal applied to it. Figure 32 shows the worst case
across all channels for the AD7091R-2/AD7091R-4/AD7091R-8.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental.
For the AD7091R-2/AD7091R-4/AD7091R-8, it is defined as
THD (dB ) = 20 log
V22 + V32 + V4 2 + V52 + V62
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum; however,
for ADCs where the harmonics are buried in the noise floor, it
is a noise peak.
Signal-to-(Noise + Distortion) (SINAD) Ratio
SINAD is the measured ratio of signal-to-(noise + distortion) at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Thus, for a 12-bit converter, the SINAD ratio is 74 dB.
Rev. 0 | Page 17 of 40
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
THEORY OF OPERATION
The AD7091R-2/AD7091R-4/AD7091R-8 are a 12-bit, fast
(1 MSPS), ultralow power, single-supply ADCs. The devices
operate from a 2.7 V to 5.25 V supply. The AD7091R-2/
AD7091R-4/AD7091R-8 are capable of throughput rates of
1 MSPS.
The AD7091R-2/AD7091R-4/AD7091R-8 provide an on-chip,
track-and-hold ADC and a serial interface housed in a 16-lead,
20-lead, or 24-lead TSSOP package, which offers considerable
space-saving advantages over alternative solutions. The serial
clock input accesses data from the device. The clock for the
successive approximation ADC is generated internally. The
reference voltage for the AD7091R-2/AD7091R-4/AD7091R-8 is
provided externally, or it is generated internally by an accurate
on-chip reference source. The analog input range for the
AD7091R-2/AD7091R-4/AD7091R-8 is 0 V to VREF.
When the ADC starts a conversion, SW2 opens and SW1 moves
to Position B, causing the comparator to become unbalanced (see
Figure 38). Using the control logic, the charge redistribution DAC
adds and subtracts fixed amounts of charge from the sampling
capacitor to bring the comparator back into a balanced condition.
When the SAR decisions are made, the comparator inputs are
rebalanced. From these SAR decisions, the control logic
generates the ADC output code.
ADC TRANSFER FUNCTION
The output coding of the AD7091R-2/AD7091R-4/AD7091R-8 is
straight binary. The designed code transitions occur midway
between successive integer LSB values, such as ½ LSB, 1½ LSB, and
so on. The LSB size for the AD7091R-2/AD7091R-4/AD7091R-8
is VREF/4096. The ideal transfer characteristic for the AD7091R-2/
AD7091R-4/AD7091R-8 is shown in Figure 39.
The AD7091R-2/AD7091R-4/AD7091R-8 also feature a powerdown option to save power between conversions. The power-down
feature is implemented across the standard serial interface as
described in the Modes of Operation section.
ADC CODE
111...111
111...110
CONVERTER OPERATION
The AD7091R-2/AD7091R-4/AD7091R-8 are successive
approximation ADCs based on a charge redistribution digitalto-analog converter (DAC). Figure 37 and Figure 38 show
simplified schematics of the ADC. Figure 37 shows the ADC
during its acquisition phase. When SW2 is closed and SW1 is in
Position A, the comparator is held in a balanced condition, and
the sampling capacitor acquires the signal on VIN.
CHARGE
REDISTRIBUTION
DAC
SAMPLING
CAPACITOR
VIN
SW1
B
ACQUISITION
PHASE
CONTROL
LOGIC
SW2
COMPARATOR
AGND
10891-015
A
VDD/2
CHARGE
REDISTRIBUTION
DAC
SAMPLING
CAPACITOR
VIN
CONVERSION
PHASE
CONTROL
LOGIC
SW2
COMPARATOR
AGND
VDD/2
10891-016
SW1
B
1LSB = VREF /4096
011...111
000...010
000...001
000...000
0V 1LSB
ANALOG INPUT
+VREF – 1LSB
Figure 39. AD7091R-2/AD7091R-4/AD7091R-8 Transfer Characteristic
REFERENCE
The AD7091R-2/AD7091R-4/AD7091R-8 can operate with
either the internal 2.5 V on-chip reference or an externally
applied reference. The logic state of the P_DOWN LSB bit in
the configuration register determines whether the internal
reference is used. The internal reference is selected for the
ADCs when the P_DOWN LSB bit are set to 1.
When the P_DOWN LSB bit is set to 0, supply an external
reference in the range of 2.5 V to VDD through the REFIN/REFOUT
pin. At power-up, the internal reference disables by default.
The internal reference circuitry consists of a 2.5 V band gap
reference and a reference buffer. When operating the AD7091R-2/
AD7091R-4/AD7091R-8 in internal reference mode, the 2.5 V
internal reference is available at the REFIN/REFOUT pin, which is
typically decoupled to GND using a 2.2 µF capacitor. It is
recommended to buffer the internal reference before applying
it elsewhere in the system.
Figure 37. ADC Acquisition Phase
A
111...000
10891-017
CIRCUIT INFORMATION
The reference buffer requires 50 ms to power up and charge the
2.2 µF decoupling capacitor during the power-up time.
Figure 38. ADC Conversion Phase
Rev. 0 | Page 18 of 40
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
TYPICAL CONNECTION DIAGRAM
VDD VREF
Connect a positive power supply in the 2.7 V to 5.25 V range to
the VDD pin. Typical values for these decoupling capacitors are
100 nF and 10 µF. Place these capacitors near the device pins.
Take care to decouple the REFIN/REFOUT pin to achieve specified
performance. The typical value for the REFIN/REFOUT capacitor
is 2.2 µF, which provides an analog input range of 0 V to VREF.
The typical value for the regulator bypass (REGCAP) decoupling
capacitor is 1 µF. The voltage applied to the VDRIVE input
controls the voltage of the serial interface; therefore, connect
this pin to the supply voltage of the microprocessor. Set VDRIVE
in the 1.8 V to 5.25 V range. Typical values for the VDRIVE
decoupling capacitors are 100 nF and 10 µF. The conversion
result is output in a 16-bit word with the most significant bits
(MSBs) first.
When an externally applied reference is required, disable the
internal reference using the configuration register. Choose the
externally applied reference voltage in the 1.0 V to 5.25 V VDD
range and connect it to the REFIN/REFOUT pin.
For applications where power consumption is a concern, use the
power-down mode of the ADC to improve power performance.
See the Modes of Operation section for additional details.
ANALOG INPUT
Figure 40 shows an equivalent circuit of the analog input structure
of the AD7091R-2/AD7091R-4/AD7091R-8. The two diodes, D1
and D2, provide ESD protection for the analog input. Take care
to ensure that the analog input signal never exceeds the supply
rails by more than 300 mV because this causes these diodes to
become forward-biased and start conducting current into the
substrate. These diodes can conduct a maximum of 10 mA
without causing irreversible damage to the device.
D1
D3
R1
VIN
C1
400fF
C2
3.6pF
D2
CONVERSION PHASE–SWITCH OPEN
TRACK PHASE–SWITCH CLOSED
10891-019
Figure 41 shows a typical connection diagram for the AD7091R-2/
AD7091R-4/AD7091R-8.
Figure 40. Equivalent Analog Input Circuit
The C1 capacitor in Figure 40 is typically about 400 fF and can
primarily be attributed to pin capacitance. The R1 resistor is a
lumped component composed of the on resistance of a switch.
This resistor is typically about 500 Ω. The C2 capacitor is the
ADC sampling capacitor and typically has a capacitance of
3.6 pF
In applications where harmonic distortion and signal-to-noise
ratio are critical, drive the analog inputs from low impedance
sources. Large source impedances significantly affect the ac
performance of the ADC that can necessitate using input buffer
amplifiers, as shown in Figure 41. The choice of the op amp is a
function of the particular application.
When no amplifiers are used to drive the analog input, limit the
source impedance to low values. The maximum source impedance
depends on the amount of THD that can be tolerated. The THD
increases as the source impedance increases and performance
degrades.
Use an external filter on the analog input signal paths to the
AD7091R-2/AD7091R-4/AD7091R-8 VINx pins to achieve the
specified performance. This filter can be a one-pole low-pass
RC filter, or similar.
Connect the MUXOUT pin directly to the ADCIN pin. Insert a
buffer amplifier in the path, if desired. When sequencing
channels, do not place a filter between MUXOUT and the input to
any buffering because doing so leads to crosstalk. If buffering is
not employed, do not place a filter between MUXOUT and ADCIN
when sequencing channels because doing so leads to crosstalk.
Rev. 0 | Page 19 of 40
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
WITH BUSY
INDICATION
VDRIVE
47kΩ
10µF
100nF
10µF
VDD
100nF
VDRIVE
MICROCONTROLLER/
MICROPROCESSOR/
DSP
SDO
REGCAP
SCLK
1µF
CS
CONVST
ANALOG
INPUT
VIN0
SDI
ALERT1
AD7091R-2/
AD7091R-4/
AD7091R-8
ANALOG
INPUT
ADCIN
VINX
REFIN/
REFOUT
GND
MUXOUT
2.2µF
NOTES
1THIS PIN IS FOR THE AD7091R-4/AD7091R-8.
OPTIONAL
BUFFER
10891-018
33Ω
560pF
Figure 41. Typical Connection Diagram with Optional Buffer
WITH BUSY
INDICATION
VDRIVE
47kΩ
10µF
100nF
10µF
VDD
100nF
VDRIVE
SDO
REGCAP
SCLK
MICROCONTROLLER/
MICROPROCESSOR/
DSP
1µF
CS
33Ω
ANALOG
INPUT
CONVST
VIN0
SDI
560pF
ALERT1
AD7091R-2/
AD7091R-4/
AD7091R-8
ANALOG
INPUT
560pF
ADCIN
VINX
GND
REFIN/
REFOUT
MUXOUT
2.2µF
NOTES
1THIS PIN IS FOR THE AD7091R-4/AD7091R-8.
Figure 42. Typical Connection Diagram Without Optional Buffer
Rev. 0 | Page 20 of 40
10891-140
33Ω
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
REGISTERS
ADDRESSING REGISTERS
The AD7091R-2/AD7091R-4/AD7091R-8 have user
programmable registers. Table 8 contains the complete list
of registers.
The registers are either read/write (R/W) or read only (R). Data
is written to or read back from the read/write registers. Read
only registers is only read. Any write to a read only register or
unimplemented register address is considered no operation
(NOP). A NOP command is an SPI command that is ignored by
the AD7091R-2/AD7091R-4/AD7091R-8. After a write to a read
only register, the output on the subsequent SPI frame is all zeros
if there was no conversion before the next SPI frame. Similarly,
any read of an unimplemented register outputs zeros.
A serial transfer on the AD7091R-2/AD7091R-4/AD7091R-8
consists of 16 SCLK cycles. The six MSBs on the SDI line during
the 16 SCLK transfer are decoded to determine which register is
addressed. The six MSBs consist of the register address (ADDx),
Bits[4:0] and the read/write bit. The register address bits
determine which of the on-chip registers are selected. The
read/write bit determines if the data on the SDI line following the
read/write bit loads into the addressed register. If the read/write
bit is 1, the bits load into the register addressed by the register
select bits. Data loads into the register on the rising edge of CS.
If the read/write bit is 0, the command is seen as a read request.
The requested register data is available on the subsequent message
on the SDO line.
Table 8. Register Description
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
…
0x1F
Register Name
Conversion result
Channel
Configuration
Alert indication
Channel 0 low limit
Channel 0 high limit
Channel 0 hysteresis
Channel 1 low limit
Channel 1 high limit
Channel 1 hysteresis
Channel 2 low limit
Channel 2 high limit
Channel 2 hysteresis
Channel 3 low limit
Channel 3 high limit
Channel 3 hysteresis
Channel 4 low limit
Channel 4 high limit
Channel 4 hysteresis
Channel 5 low limit
Channel 5 high limit
Channel 5 hysteresis
Channel 6 low limit
Channel 6 high limit
Channel 6 hysteresis
Channel 7 low limit
Channel 7 high limit
Channel 7 hysteresis
Reserved
…
Reserved
Default
0x0000
0x0000
0x00C0
0x0000
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
…
0x0000
Rev. 0 | Page 21 of 40
AD7091R-8
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NOP
…
NOP
Access
AD7091R-4
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
…
NOP
AD7091R-2
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
…
NOP
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
CONVERSION RESULT REGISTER
The conversion result register is a 16-bit read only register that stores the results from the most recent ADC conversion in straight binary
format. The channel ID of the converted channel and the alert status are also included in the register.
Figure 43. Conversion Result Register
Table 9. Conversion Result Register Map
MSB
B15
B14
CH_ID
B13
B12
ALERT
B11
B10
B9
B8
B7
B6
B5
CONV_RESULT
B4
B3
B2
LSB
B0
B1
Table 10. Bit Descriptions for the Conversion Result Register
Bit(s)
[15:13]
Name
CH_ID
12
ALERT
[11:0]
CONV_RESULT
1
2
Description
3-bit channel ID of channel converted
B15 1, 2
B142
B13
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
ALERT flag
0: No ALERT occurred
1: ALERT occurred
12-bit conversion result
Reset
0x0
Access
R
0
R
0x000
R
Analog Input Channel
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
Always zero on the AD7091R-4.
Always zero on the AD7091R-2.
Rev. 0 | Page 22 of 40
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
CHANNEL REGISTER
The channel register on the AD7091R-2/AD7091R-4/AD7091R-8 is an 8-bit, read/write register. Each of the eight analog input channels has
one corresponding bit in the channel register. To select a channel for inclusion in the channel conversion sequence, set the corresponding
channel bit to 1 in the channel register. There is a latency of one conversion before the channel conversion sequence is updated. If the channel
register is programmed with a new value, the conversion sequence is reset to the lowest numbered channel in the new value.
Figure 44. Channel Registers
Table 11. Channel Register Map
MSB
B15
B14
B13
B12
B11
Reserved
B10
B9
B8
B7
CH7
B6
CH6
B5
CH5
B4
CH4
B3
CH3
B2
CH2
B1
CH1
Table 12. Bit Descriptions for the Channel Register
Bit(s)
[15:8]
7
Name
Reserved
CH7
6
CH6
5
CH5
4
CH4
3
CH3
2
CH2
1
CH1
Description
Reserved
Convert on Channel 7
0: Disable Channel 7
1: Enable Channel 7
Convert on Channel 6
0: Disable Channel 6
1: Enable Channel 6
Convert on Channel 5
0: Disable Channel 5
1: Enable Channel 5
Convert on Channel 4
0: Disable Channel 4
1: Enable Channel 4
Convert on Channel 3
0: Disable Channel 3
1: Enable Channel 3
Convert on Channel 2
0: Disable Channel 2
1: Enable Channel 2
Convert on Channel 1
0: Disable Channel 1
1: Enable Channel 1
Rev. 0 | Page 23 of 40
Reset
0x00
0x0
Access
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
LSB
B0
CH0
AD7091R-2/AD7091R-4/AD7091R-8
Bit(s)
0
Name
CH0
Data Sheet
Description
Convert on Channel 0
0: Disable Channel 0
1: Enable Channel 0
Reset
0x0
Access
R/W
CONFIGURATION REGISTER
The configuration register is a 16-bit, read/write register that is used to set the operating modes of the AD7091R-2/AD7091R-4/AD7091R-8.
Figure 45. Configuration Register
Table 13. Configuration Register Map
MSB
B15
B14
B13 B12
Reserved
B11
B10
B9
SRST
B8
Reserved
B7
ALERT_
STICKY
B6
ALERT_
DRIVE_TYPE
B5
BUSY
B4
ALERT_EN_
OR_GPO0
B3
ALERT_POL_
OR_GPO0
LSB
B0
B2
B1
GPO1
P_DOWN
Table 14. Bit Descriptions for the Configuration Register
Bit(s)
[15:10]
9
Name
Reserved
SRST
8
7
RESERVED
ALERT_STICKY
Description
Software reset bit. Setting this bit resets the internal digital control logic and
the result and alert registers, but it does not reset the other memory map
registers. This bit automatically clears in the next clock cycle. Note that it
loads random access memory (RAM) from fuses.
0: Soft reset not active.
1: Activate soft reset.
ALERT_STICKY bit is sticky. It is not cleared on a valid hysteresis condition.
0: Clear ALERT 1 if the result falls beyond hysteresis.
1: Clear ALERT1 only on a read or soft reset.
Rev. 0 | Page 24 of 40
Reset
0x00
0x0
Access
R
RWAC
0x0
0x1
R
R/W
Data Sheet
Bit(s)
6
Name
ALERT_DRIVE_TYPE
5
BUSY
4
ALERT_EN_OR_GPO0
3
ALERT_POL_OR_GPO0
2
GPO1
[1:0]
P_DOWN
1
AD7091R-2/AD7091R-4/AD7091R-8
Description
Drive type of ALERT1 pin.
0: ALERT1 pin is of open-drain drive type.
1: ALERT1 pin is of CMOS drive type.
ALERT1 pin indicates if the part is busy converting.
0: ALERT1 pin is not used for BUSY status.
1: ALERT1 pin is used for BUSY status, provided ALERT_EN_OR_GPO0) is 1.
Else, this bit is always read back as 0.
Enable ALERT pin or GPO01.
0: ALERT1 pin used as GPO01.
1: ALERT1 pin is used for ALERT1/BUSY1 status.
Polarity of ALERT1 pin (if ALERT_EN_OR_GPO0 is 1) or value at GPO01.
0: Active low ALERT1 polarity (if ALERT_EN_OR_GPO0 = 1) or GPO01 = 0.
1: Active high ALERT1 polarity (if ALERT_EN_OR_GPO0 = 1) or GPO01 = 1.
Value at GPO11.
0: Drive 0 on GPO11 pin.
1: Drive 1 on GPO11 pin.
Power-down mode.
Setting Mode
Sleep Mode/Bias Generator Internal Reference
00
Mode 0 Off
Off
01
Mode 1 Off
On
10
Mode 2 On
Off
11
Mode 2 On
On
Reset
0x1
Access
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
When referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configurations and Function Descriptions section.
Rev. 0 | Page 25 of 40
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
ALERT INDICATION REGISTER
The 16-bit alert indication register is a read only register that
provides information on an alert event. If a conversion result
activates the ALERT function of the ALERT/BUSY/GPO0 pin,
as described in the Channel x Low Limit Register section and
the Channel x High Limit Register section, the alert register can
be read to determine the source of the alert. The register contains
two status bits per channel, one corresponding to the high limit,
and the other to the low limit. The bit with a status equal to 1
shows where the violation occurred, that is, on which channel,
and whether the violation occurred on the upper or lower limit.
If a second alert event occurs on another channel between
receiving the first alert and interrogating the alert register, the
corresponding bit for that alert event is also set.
The contents of the alert indication register are reset by reading
it. The alert indication register is reset on the second SCLK
cycle of the SPI frame where the ALERT data is read out. If a
conversion happens in the meantime, the conversion result is
sent instead of the alert indication register contents. The alert
indication register is not reset in this case.
The alert bits for any unimplemented channels on the two and
four channel devices always return zeros.
Figure 46. Alert Indication Register (Figure Shows Default Register Value of 0, Indicating No Alert Has Occurred)
Table 15. Alert Indication Register Register Map
MSB
B15
LO_7
B14
HI_7
B13
LO_6
B12
HI_6
B11
LO_5
B10
HI_5
B9
LO_4
B8
HI_4
B7
LO_3
B6
HI_3
B5
LO_2
B4
HI_2
B3
LO_1
B2
HI_1
B1
LO_0
Table 16. Bit Descriptions for the Alert Indication Register
Bit(s)
15
Bit Name
LO_7
14
HI_7
Description
Channel 7 low alert status
0: No alert on Channel 7
1: Low alert occurred on Channel 7
Channel 7 high alert status
0: No alert on Channel 7
1: High alert occurred on Channel 7
Rev. 0 | Page 26 of 40
Reset
0x0
Access
R
0x0
R
LSB
B0
HI_0
Data Sheet
Bit(s)
13
Bit Name
LO_6
12
HI_6
11
LO_5
10
HI_5
9
LO_4
8
HI_4
7
LO_3
6
HI_3
5
LO_2
4
HI_2
3
LO_1
2
HI_1
1
LO_0
0
HI_0
AD7091R-2/AD7091R-4/AD7091R-8
Description
Channel 6 low alert status
0: No alert on Channel 6
1: Low alert occurred on Channel 6
Channel 6 high alert status
0: No alert on Channel 6
1: High alert occurred on Channel 6
Channel 5 low alert status
0: No alert on Channel 5
1: Low alert occurred on Channel 5
Channel 5 high alert status
0: No alert on Channel 5
1: High alert occurred on Channel 5
Channel 4 low alert status
0: No alert on Channel 4
1: Low alert occurred on Channel 4
Channel 4 high alert status
0: No alert on Channel 4
1: High alert occurred on Channel 4
Channel 3 low alert status
0: No alert on Channel 3
1: Low alert occurred on Channel 3
Channel 3 high alert status
0: No alert on Channel 3
1: High alert occurred on Channel 3
Channel 2 low alert status
0: No alert on Channel 2
1: Low alert occurred on Channel 2
Channel 2 high alert status
0: No alert on Channel 2
1: High alert occurred on Channel 2
Channel 1 low alert status
0: No alert on Channel 1
1: Low alert occurred on Channel 1
Channel 1 high alert status
0: No alert on Channel 1
1: High alert occurred on Channel 1
Channel 0 low alert status
0: No alert on Channel 0
1: Low alert occurred on Channel 0
Channel 0 high alert status
0: No alert on Channel 0
1: High alert occurred on Channel 0
Rev. 0 | Page 27 of 40
Reset
0x0
Access
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
CHANNEL x LOW LIMIT REGISTER
Of the 16 bits, only the nine LSBs are used, DB8 to DB0. DB15 to
DB9 are not used. These nine bits, which are programmed by the
user, are used as the most significant bits of the internal 12-bit
register. The three LSBs in the internal 12-bit registers are set to 111.
Each analog input channel of the AD7091R-2/AD7091R-4/
AD7091R-8 has its own low limit register. The low limit registers
are 16-bit read/write registers. See Table 8 for the register addresses.
The low limit registers store the lower limit of the conversion
value that activates the ALERT output.
CHANNEL x HYSTERESIS REGISTER
Each analog input channel of the AD7091R-2/AD7091R-4/
AD7091R-8 has its own hysteresis register, which are 16-bit
read/write registers. See Table 8 for the register addresses. The
hysteresis register stores the hysteresis value (N) when using the
limit registers. The hysteresis value determines the reset point
for the ALERT/BUSY/GPO0 pin if a violation of the limits has
occurred.
Of the 16 bits, only the nine least significant bits (LSBs) are
used, DB8 to DB0. DB15 to Bit DB9 are not used. These nine
bits, which are programmed by the user, are used as the MSBs
of the internal 12-bit register. The three LSBs in the internal
12-bit registers are set to 000.
CHANNEL x HIGH LIMIT REGISTER
Of the 16 bits, only the nine LSBs are used, DB8 to DB0. DB15
to DB9 are not used in the register and are set to zeros. These
nine bits, which are programmed by the user, are used as the LSBs
of the internal 12-bit register. The three MSBs are set to 000.
Each analog input channel of the AD7091R-2/AD7091R-4/
AD7091R-8 has its own high limit register. The high limit registers
are 16-bit read/write registers. See Table 8 for the register addresses.
The high limit registers store the upper limit of the conversion
value that activates the ALERT output.
Table 17. Channel x Low Limit Register Register Map
MSB
B15
B14
B13
B12
B11
Reserved
B10
B9
B8
B7
B6
B5
B4
B3
CHx LOW LIMIT
B2
B1
LSB
B0
Table 18. Bit Descriptions for the Channel x Low Limit Register
Bit(s)
[15:9]
[8:0]
Bit Name
Reserved
CHx LOW LIMIT
Description
Reserved
Low limit value for Channel x
Reset
0x00
0x000
Access
R
R/W
Table 19. Channel x High Limit Register Map
MSB
B15
B14
B13
B12
B11
Reserved
B10
B9
B8
B7
B6
B5
B4
B3
CHx HIGH LIMIT
B2
B1
LSB
B0
Table 20. Bit Descriptions for the Channel x High Limit Register
Bits
[15:9]
[8:0]
Bit Name
Reserved
CHx HIGH LIMIT
Description
Reset
0x00
0x1FF
High limit value for Channel x
Access
R
R/W
Table 21. Channel x Hysteresis Register Map
MSB
B15
B14
B13
B12
B11
Reserved
B10
B9
B8
B7
B6
B5
B4
B3
CHx HYSTERESIS
B2
B1
LSB
B0
Table 22. Bit Descriptions for the Channel x Hysteresis Register
Bit(s)
[15:9]
[8:0]
Bit Name
Reserved
CHx HYSTERESIS
Description
Hysteresis value for Channel x
Rev. 0 | Page 28 of 40
Reset
0x00
0x1FF
Access
R
R/W
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
SERIAL INTERFACE
on the previous (15th) falling edge. After the 16th falling edge,
take CS high again to return the SDO to a high impedance state.
If another conversion is required, take the CONVST pin low
again (after at least 1 µs), and repeat the read cycle. The timing
diagram for this operation is shown in Figure 48.
The SPI is a 4-wire interface (three inputs and one output) for
serial data communication. It has a chip-select (CS) line, a serial
clock (SCLK), a serial data input (SDI), and a serial data output
(SDO). Data transfers on SDI and SDO take place with respect
to SCLK. CS is used to frame the data and is active low.
When CS is high, SDO is kept in high impedance. The falling
edge of CS takes the SDO line out of the high impedance state.
A rising edge on CS returns the SDO to a high impedance state.
WRITING DATA TO THE REGISTERS
All the read/write registers in the device can be written to over
the SPI. A register write command is performed by a single 16-bit
SPI access. The format for a write command is shown in Table 23.
Bits[B15:B11] contain the register address. See Table 8 for the
complete list of register addresses. Setting Bit B10 to 1 selects a
write command. The subsequent 10 bits (Bits[B9:B0]) contain
the data to be written to the selected register.
The SPI implemented on the AD7091R-2/AD7091R-4/AD7091R-8
can support both of the following: CPHA and CPOL = 0, and
CPHA and CPOL = 1. This support ensures that the device can
interface to micro-controllers and DSPs that keep either SCLK
high or SCLK low when CS is not asserted. The device ignores
SCLK toggling when CS is not asserted.
READING DATA FROM THE REGISTERS
READING CONVERSION RESULT
All the registers in the device can be read over the SPI. A register
read is performed by issuing a register read command followed
by an additional SPI command that can be either a valid command
or NOP. The format for a read command is shown in Table 24.
Bits[B15:B11] contain the register address. See Table 8 for the
complete list of register addresses. Setting Bit B10 to 0 selects
a read command. The device ignores the subsequent bits
(Bits[B9:B0]).
The CONVST signal is used to initiate the conversion process.
A high-to-low transition on the CONVST signal puts the trackand-hold into hold mode and samples the analog input at this
point. A conversion is initiated and requires 600 ns to complete.
Before the end of the conversion, take the CONVST signal high
again. When the conversion process is finished, the track-andhold mode goes back into track mode. Then, take the CS pin
low and the conversion result clocks out on the SDO pin. The
data is shifted out of the device as a 16-bit word under the
control of the serial clock (SCLK) input. The data is shifted out
on falling edge of SCLK, and the data bits are valid on both the
rising edge and the falling edge. The MSB is shifted out on the
falling edge of CS. The final bit in the data transfer is valid on
the 16th rising edge and 16th falling edge, having clocked out
Any conversion event is treated as a special case and overrides
a previous read command. The AD7091R-2/AD7091R-4/
AD7091R-8 always drive out the conversion result register
on SDO after a conversion even though a register read was
initiated in the previous SPI frame.
Table 23. Write Command Message Configuration
B14
B13
B12
Register Address[4:0]
B11
B10
1
B9
B8
B7
B6
B5
B4
Data[9:0]
B3
B2
LSB
B0
B1
CONVST
CS
SDI
WRITE REG 1
WRITE REG 2
WRITE REG 3
SDO
CONV RESULT
INVALID DATA
INVALID DATA
Figure 47. Serial Interface Register Write
Rev. 0 | Page 29 of 40
10891-024
MSB
B15
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
Table 24. Read Command Message Configuration
B14
B13
B12
Register Address[4:0]
B11
B10
0
B9
B8
B7
B6
B5
B4
Don’t Care
B3
B2
LSB
B0
B1
CONVST
CS
SDI
READ REG 1
READ REG 2
READ REG 3
SDO
CONV RES
REG 1 DATA
REG 2 DATA
Figure 48. Serial Interface Register Read
Rev. 0 | Page 30 of 40
10891-025
MSB
B15
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
MODES OF OPERATION
NORMAL MODE
The user controls whether the device remains in normal mode or
enters power-down mode. These modes of operation provide
flexible power management options allowing optimization of the
power dissipation and throughput rate ratio for different
application requirements.
To achieve the fastest throughput rate performance, use normal
mode. Power-up times are not an issue for the AD7091R-2/
AD7091R-4/AD7091R-8 because they remain fully powered at all
times. Figure 49 shows the general diagram of the AD7091R-2/
AD7091R-4/AD7091R-8 in normal mode. The conversion
initiates on the falling edge of CONVST, as described in the
Serial Interface section. To ensure that the device remains fully
powered up at all times, return CONVST high before tCONVERT
and keep it high until the conversion has finished. The end of
conversion (EOC) point shown in Figure 49 indicates the end of
EOC and the moment when the logic level of CONVST is tested.
To read back data stored in the conversion result register, wait
until the conversion is completed. Then, take CS low, and the
conversion data clocks out on the SDO pin. The output shift
register is 16 bits wide. Data is shifted out of the device as a 16-bit
word under the control of the serial clock (SCLK) input. The
full timing diagram for this operation is shown in Figure 4.
When the conversion read is completed, pull CONVST low
again to start another conversion.
POWER-DOWN MODE
When slower throughput rates and lower power consumption
are required, use power-down mode by either powering down
the ADC between each conversion or by performing a series of
conversions at a high throughput rate and then powering down
the ADC for a relatively long duration between these burst
conversions. When the AD7091R-2/AD7091R-4/AD7091R-8 are
in power-down mode, all analog circuitry power down; however,
the serial interface is active.
To enter power-down, write to the power-down configuration
bits in the configuration register, as seen in Table 13. To enter
full power-down mode, set the sleep mode/bias generator bit to 1,
and set the internal reference bit to 0, which ensures that all analog
circuitry and the internal reference powers down. When the
internal reference is enabled, it consumes power anytime Bit 0 of
the configuration register is set to 1.
The serial interface of the AD7091R-2/AD7091R-4/AD7091R-8
is functional in power-down; therefore, user can read back
results of the conversion after the device enters power-down mode.
To exit this mode of operation and power up the AD7091R-2/
AD7091R-4/AD7091R-8 again, write to the power-down
configuration bits in the configuration register (see Table 13). On
the rising edge of CONVST, the device begins to power up. The
power-up time of the AD7091R-2/AD7091R-4/AD7091R-8 is
typically 1 µs. After power-up is complete, the ADC is fully
powered up, and the input signal is properly acquired. To start
the next conversion, operate the interface as described in the
Normal Mode section. When using the internal reference, and
the device is in full power-down mode, the user must wait to
perform conversions until the internal reference has had time to
power up and settle. The reference buffer requires 50 ms to
power up and charge the 2.2 µF decoupling capacitor during the
power-up time.
By using the power-down mode on the AD7091R-2/AD7091R-4/
AD7091R-8 when this device is not converting, the average power
consumption of the ADC decreases at lower throughput rates.
Use power-down mode with lower throughput rates. When
there is not a significant time interval between bursts of
conversions, use normal mode (see the Normal Mode section).
EOC
tCNVPW
CONVST
tCONVERT
tEOCCSL
CS
tEN
CONVERSION DATA
SDO
10891-026
NOTES
1.
tDIS
DON’T CARE
Figure 49. Serial Interface Read Timing in Normal Mode
Rev. 0 | Page 31 of 40
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
ALERT (AD7091R-4 AND AD7091R-8 ONLY)
The alert functionality is used as an out-of-range indicator. An
alert event is triggered when the value in the conversion result
register exceeds the CHx HIGH LIMIT value in the channel high
limit register or falls below the CHx LOW LIMIT value in the
channel low limit register for a selected channel.
The ALERT/BUSY/GPO0 pin has an open-drain configuration
that allows the alert outputs of several AD7091R-4/AD7091R-8
devices to be wired together when the ALERT function of the
ALERT/BUSY/GPO0 pin is active low. The ALERT_DRIVE_TYPE
bit (Bit 6) of the configuration register controls the ALERT/
BUSY/GPO0 pin configuration.
Detailed alert information is accessible in the alert register. The
register contains two status bits per channel, one corresponding
to the high limit, and the other to the low limit. A logical OR of
alert signals for all channels creates a common alert value. This
value can be accessed by the alert bit in the conversion result
register and configured to drive out on the ALERT function of
the ALERT/BUSY/GPO0 pin. The ALERT/BUSY/GPO0 pin is
configured as ALERT by configuring the following bits in the
configuration register:
When using the ALERT function of the ALERT/BUSY/GPO0
pin and the open-drain configuration, an external pull-up
resistor is required. Connect the external pull-up resistor to
VDRIVE. The resistor value is application dependent; however, it
must be large enough to avoid excessive sink currents when the
ALERT function of the ALERT/BUSY/GPO0 pin is triggered.
•
•
•
Set the ALERT_EN_OR_GPO0 bit, Bit 4, to 1.
Set the BUSY bit, Bit 5, to 0.
Set the ALERT_POL_OR_GPO0 bit, Bit 3, to 0 for the the
ALERT function of the ALERT/BUSY/GPO0 pin to be
active low and set it to 1 for the the ALERT function of the
ALERT/BUSY/GPO0 pin to be active high.
The alert register, alert bit, and the ALERT function of the
ALERT/BUSY/GPO0 pin are cleared by reading the alert register
contents. Additionally, if the conversion result goes beyond the
hysteresis value for a selected channel, the alert bit
corresponding to that channel is reset automatically. The
automatic clearing of the alert status can be disabled by setting
the ALERT_STICKY bit in the configuration register to 1. If the
ALERT_STICKY bit is set when an alert occurs, it can only be
reset by a read of the alert register. Issuing a software reset also
clears the alert status.
Use the ALERT_POL_OR_GPO0 bit (Bit 3) of the configuration
register to set the active polarity of the alert output. The power-up
default is active low.
BUSY (AD7091R-4 AND AD7091R-8 ONLY)
When configuring the ALERT/BUSY/GPO0 pin as a BUSY output,
use the pin to indicate when a conversion is taking place. To
configure the ALERT/BUSY/GPO0 pin as BUSY, use the
following bits in the configuration register:
•
•
•
Set the ALERT_EN_OR_GPO0 bit, Bit 4, to 1.
Set the BUSY bit, Bit 5, to 1.
Set the ALERT_POL_OR_GPO0 bit, Bit 3, to 0 for the
BUSY pin to be active low, and set it to 1 for the BUSY pin
to be active high.
When using the BUSY function of the ALERT/BUSY/GPO0 pin
pin, an external pull-up resistor is required because the output
is an open-drain configuration. Connect the external pull-up
resistor to VDRIVE. The resistor value is application dependent;
however, it must be large enough to avoid excessive sink currents
at the BUSY function of the the ALERT function of the
ALERT/BUSY/GPO0 pin.
Rev. 0 | Page 32 of 40
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
CHANNEL SEQUENCER
The AD7091R-2/AD7091R-4/AD7091R-8 include a channel
sequencer that is useful for scanning channels in a repeated
fashion. Channels included in the sequence are configured in
the channel register. If all the bits in the channel register are 0,
Channel 0 is selected by default, and all conversions happen on
this channel. If the channel register is nonzero, the conversion
sequence starts from the lowest numbered channel enabled in
the channel register. The sequence cycles through all the
enabled channels in ascending order. After all the channels in
the sequence are converted, the sequence starts again.
There is a latency of one conversion before the channel conversion
sequence is updated. If the channel register is programmed with
a new value, the conversion sequence is reset to the lowest
numbered channel in the new value.
CONVST
SDI
WRITE 0x00F0
CHANNEL REG
NOP
NOP
NOP
SDO
RESULT
CHANNEL 0
RESULT
CHANNEL 0
RESULT
CHANNEL 4
RESULT
CHANNEL 5
10891-028
CS
Figure 50. Channel Sequencer
CONVST
SDI
WRITE 0x001
CHANNEL REG
WRITE 0x002
CHANNEL REG
WRITE 0x004
CHANNEL REG
WRITE 0x008
CHANNEL REG
WRITE 0x0010
CHANNEL REG
SDO
RESULT
CHANNEL 0
RESULT
CHANNEL 0
RESULT
CHANNEL 0
RESULT
CHANNEL 1
RESULT
CHANNEL 2
Figure 51. Channel Sequencer Multiple Channel Write
Rev. 0 | Page 33 of 40
10891-029
CS
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
DAISY CHAIN
Each AD7091R-2/AD7091R-4/AD7091R-8 slave in the chain
requires a 16-bit SPI command. If there are N slaves, each SPI
frame must have N × 16 bits of data. In the AD7091R-2/
AD7091R-4/AD7091R-8, when the bit counter crosses 16 bits,
all of the received bits are sent out over the SDO. The output
from the first slave is the input of the second slave. Effectively,
each slave ignores all the incoming 16-bit SPI commands,
except the last one. The SPI command received just before
the CS rising edge is the only valid SPI command for a given
device in the daisy chain. The output on the next SPI frame is
determined by the valid SPI command or any conversion event.
This mode is intended for applications where multiple
AD7091R-2/AD7091R-4/AD7091R-8 devices are used. This
feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
All ADC slaves are addressed by the same CS, CONVST, and
SCLK signals. The SDI of the first AD7091R-2/AD7091R-4/
AD7091R-8 slave in the chain is driven directly by the MOSI
pin of the SPI master. The SDO of the first slave is connected
to the SDI of the second slave. All the subsequent slaves are
connected in this fashion, and the SDO of the last slave drives
the master input, slave output (MISO) pin of the master. A
connection diagram example using two AD7091R-2/AD7091R4/AD7091R-8 devices is shown in Figure 52.
The methods for reading a conversion result to configuring the
slave registers are outlined in Figure 53 to Figure 57 for a twoslave example. Additional slave devices can be added to the
chain by following the same principles defined for the twodevice configuration.
MOSI
SS
CS
CS
AD7091R-x
AD7091R-x
SDO
SDI
SLAVE A
CONVST
MISO
SDO
SLAVE B
CONVST
SCLK
SCLK
SCLK
CONVERT
10891-030
SDI
DIGITAL HOST
SPI MASTER
Figure 52. Daisy-Chain Configuration
CONVST
CS
1
16 17
32
1
16 17
32
NOP
NOP
NOP
NOP
SDO A/
SDI B
CONV_RESULT A
NOP
CONV_RESULT A
NOP
SDO B
CONV_RESULT B
CONV_RESULT A
CONV_RESULT B
CONV_RESULT A
SDI A
Figure 53. Conversion in a Two-Slave Daisy-Chain Mode Configuration
Rev. 0 | Page 34 of 40
10891-031
SCLK
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
CONVST
CS
1
16 17
32
SDI A
WRITE REG1 B
WRITE REG2 A
SDO A/
SDI B
INVALID DATA
WRITE REG1 B
SDO B
INVALID DATA
INVALID DATA
10891-032
SCLK
Figure 54. Single Register Write in a Two-Slave Daisy-Chain Mode Configuration
CONVST
CS
1
16 17
1
32
16 17
32
READ REG1 B
READ REG2 A
NOP
NOP
SDO A/
SDI B
CONV_RESULT A
READ REG1 B
DATA REG2 A
NOP
SDO B
CONV_RESULT B
CONV_RESULT A
DATA REG1 B
DATA REG2 A
SDI A
10891-033
SCLK
Figure 55. Single Register Read in a Two-Slave Daisy-Chain Mode Configuration
CONVST
CS
1
16 17
32
1
16 17
32
1
16 17
32
READ REG1 B
READ REG2 A
READ REG3 B
READ REG4 A
NOP
NOP
SDO A/
SDI B
CONV_RESULT A
READ REG1 B
DATA REG2 A
READ REG3 B
DATA REG4 A
NOP
SDO B
CONV_RESULT B
CONV_RESULT A
DATA REG1 B
DATA REG2 A
DATA REG3 B
DATA REG4 A
SDI A
10891-034
SCLK
Figure 56. Multiple Register Read in a Two-Slave Daisy-Chain Mode Configuration
CONVST
CS
1
16 17
32
1
16 17
32
1
16 17
32
WRITE REG1 B
WRITE REG2 A
WRITE REG3 B
WRITE REG4 A
NOP
NOP
SDO A/
SDI B
CONV_RESULT A
WRITE REG1 B
INVALID DATA
WRITE REG3 B
INVALID DATA
NOP
SDO B
CONV_RESULT B
CONV_RESULT A
INVALID DATA
INVALID DATA
INVALID DATA
INVALID DATA
SDI A
Figure 57. Multiple Register Write in a Two-Slave Daisy-Chain Mode Configuration
Rev. 0 | Page 35 of 40
10891-035
SCLK
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 58. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
1
10
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 59. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
Rev. 0 | Page 36 of 40
0.75
0.60
0.45
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
7.90
7.80
7.70
24
13
4.50
4.40
4.30
6.40 BSC
1
12
PIN 1
0.65
BSC
0.15
0.05
0.30
0.19
1.20
MAX
SEATING
PLANE
0.20
0.09
8°
0°
0.75
0.60
0.45
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 60. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD7091R-2BRUZ
AD7091R-2BRUZ-RL7
EVAL-AD7091R-2SDZ
AD7091R-4BRUZ
AD7091R-4BRUZ-RL7
EVAL-AD7091R-4SDZ
AD7091R-8BRUZ
AD7091R-8BRUZ-RL7
EVAL-AD7091R-8SDZ
EVAL-SDP-CB1Z
1
Channels
2
2
Temperature Range
−40°C to +125°C
−40°C to +125°C
4
4
−40°C to +125°C
−40°C to +125°C
8
8
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
Evaluation Board
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
Evaluation Board
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
Evaluation Board
Evaluation Controller Board
Z = RoHS Compliant Part.
Rev. 0 | Page 37 of 40
Package Option
RU-16
RU-16
RU-20
RU-20
RU-24
RU-24
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
NOTES
Rev. 0 | Page 38 of 40
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
NOTES
Rev. 0 | Page 39 of 40
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
NOTES
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10891-0-12/13(0)
Rev. 0 | Page 40 of 40