STMicroelectronics L4969URD-E System voltage regulator with fault tolerant low speed can transceiver Datasheet

L4969UR-E
L4969URD-E
System voltage regulator with fault tolerant
low speed CAN transceiver
Features
■
Operating supply voltage 6 V to 28 V, transient
up to 40 V
■
Low quiescent current consumption, less than
40 µA in sleep mode
■
Two very low drop voltage regulators
5 V/200 mA
■
Separate voltage regulator for CAN transceiver
supply with low power sleep mode
■
Efficient microcontroller supervision and reset
logic
Description
■
24 bit serial interface
■
An unpowered or insufficiently supplied node
does not disturb the bus lines
The L4969UR-E and L4969URD-E are integrated
circuits containing 3 independent voltage
regulators and a standard fault tolerant low speed
CAN line interface in multipower BCD3S process.
■
VS voltage sense comparator
■
Supports transmission with groundshift: single
wire 1.5 V - differential: 3 V
Table 1.
SO-20
PowerSO-20
They integrate all main local functions for
automotive body electronic applications
connected to a CAN bus.
Device summary
Order codes
Package
Tube
Tape and reel
SO-20
L4969URD-E
L4969URDTR-E
PowerSO-20
L4969UR-E
L4969URTR-E
September 2013
Doc ID 022587 Rev 2
1/46
www.st.com
1
Contents
L4969UR-E, L4969URD-E
Contents
1
Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
2/46
General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.1
V1 output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.2
V2 output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.3
V3 output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.4
Internal supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2
Power-up, initialization and sleep mode transitions . . . . . . . . . . . . . . . . . 17
3.3
CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.1
Negligible errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.2
Problematic errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.3
Severe errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.4
Wakeup via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6.1
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6.2
Undervoltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6.3
Reset signalling during sleepmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7
Identifier filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8
Ground shift detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10
Serial Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10.1
General dataframe format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.2
Address/command field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.3
Datafield #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.10.4
Datafield #2/CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID 022587 Rev 2
L4969UR-E, L4969URD-E
3.11
4
Contents
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1
ADR 0: VRCR voltage regulator control register . . . . . . . . . . . . . . . . . . . 28
4.2
ADR 1: CTCR CAN - transceiver control register . . . . . . . . . . . . . . . . . . . 29
4.3
ADR 2: GPTR global parameter and test register . . . . . . . . . . . . . . . . . . 30
4.4
ADR 3: RCADJ RC-oscillator adjust register . . . . . . . . . . . . . . . . . . . . . . 30
4.5
ADR4: WDC watchdog control register . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.5.1
Watchdog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.5.2
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.5.3
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.5.4
Wakeup watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.6
ADR5: GIEN global interrupt enable register . . . . . . . . . . . . . . . . . . . . . . 35
4.7
ADR6: IFR interrupt flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.8
ADR7: CTSR CAN transceiver status register . . . . . . . . . . . . . . . . . . . . . 36
4.9
ADR 8 and 9: ID01, ID23 identifier filter sequence select register . . . . . . 37
4.10
ADR 10: BTL identifier filter bittimelogic control register . . . . . . . . . . . . . 38
4.11
ADR 15: SYS system status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5
Interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6
Remarks for application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8
7.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2
SO-20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.3
PowerSO-20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Doc ID 022587 Rev 2
3/46
List of tables
L4969UR-E, L4969URD-E
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 11.
Table 10.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
4/46
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data of PowerSO-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Voltage regulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Voltage regulator 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset and watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CAN Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CAN error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Detectable physical busline failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
L4969UR memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating modes of the CAN line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SO-20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
PowerSO-20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Doc ID 022587 Rev 2
L4969UR-E, L4969URD-E
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
State diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Wakeup signalling via RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
NRES pin internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
NRES timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Internal circuitry and suggested CEXT for NRES generation during sleep mode . . . . . . . . 23
General dataframe format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Address / command field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Datafield #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Datafield #2 / CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ADR 0: VRCR voltage regulator control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ADR 1: CTCR CAN - transceiver control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ADR 2: GPTR global parameter and test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
State transition during oscillator calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
State transition during oscillator calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
ADR4: WDC watchdog control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Watchdog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Window watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Wakeup watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Valid timing windows for WDC register rewrite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ADR5: GIEN global interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ADR6: IFR interrupt flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
ADR7: CTSR CAN transceiver status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
ADR 8 and 9: ID01, ID23 identifier filter sequence select register . . . . . . . . . . . . . . . . . . . 37
ADR 10: BTL identifier filter bittimelogic control register. . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ADR 15: SYS system status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
General circuit connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SO-20 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PowerSO-20 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Doc ID 022587 Rev 2
5/46
Block diagram and pins description
1
L4969UR-E, L4969URD-E
Block diagram and pins description
Figure 1.
Block diagram
VS
VREG 1
V1
V2
VREG 2
V3
VREG 3
Watchdog and
adjustable RC-Oscillator
NRESET
Identifier Filter
WAKE
Control and Status Memory
RX
NINT
TX
CANH
Fault tolerant
low speed
CAN-transceiver
RTH
CANL
SCLK
SIN
24 Bit SPI
RTL
SOUT
Table 2.
Pins description
Pin Number
Pin name
6/46
Function
PowerSO-20
SO-20
1, 10, 11, 20
5, 6, 15, 16
GND
2
7
V1
Microcontroller supply voltage
3
8
V2
Peripheral supply voltage
4
9
V3
Internal CAN supply
5
10
VS
Power supply
6
11
CANH
7
12
RTL
8
13
CANL
9
14
RTH
CANH termination source
12
17
RXD
Act. Low CAN receive dominant data output
13
18
TXD
Act. Low CAN transmit dominant data input
14
19
SOUT
Power ground
CANH line driver output
CANL termination source
CANL line driver output
Serial data output
Doc ID 022587 Rev 2
L4969UR-E, L4969URD-E
Table 2.
Block diagram and pins description
Pins description (continued)
Pin Number
Pin name
Function
PowerSO-20
SO-20
15
20
SIN
16
1
SCLK
Serial clock
17
2
NRES
Act. low reset output
18
3
NINT
Act. low interrupt request
19
4
WAKE
Dual edge triggerable wakeup input
Figure 2.
Serial data input
Pins configuration
WAKE
SCLK
NRES
SIN
V1
V2
NINT
NINT
TX
NRES
WAKE
SCLK
GND
SIN
GND
GND
V3
VS
CANH
GND
L4969UR-E
PowerSO-20
SOUT
L4969URD-E
SO-20
RX
GND
GND
SOUT
V1
CANL
TXD
V2
CANL
RTH
RXD
V3
RTL
GND
GND
VS
CANH
RTL
Doc ID 022587 Rev 2
RTH
7/46
Electrical specifications
L4969UR-E, L4969URD-E
2
Electrical specifications
2.1
Absolute maximum ratings
Applying stress which exceeds the ratings listed in the Table 3: Absolute maximum ratings
may cause permanent damage to the device. These are stress ratings only and operation of
the device at these or any other conditions above those indicated in the Operating sections
of this specification is not implied. Exposure to the conditions in this section for extended
periods may affect device reliability.
Table 3.
Absolute maximum ratings(1)
Symbol
Parameter
Value
Unit
VVSDC
DC operating supply voltage
-0.3 to 28
V
VVSTR
Transient operating supply voltage (T < 400 ms)
-0.3 to 40
V
IVOUT1...3 Output currents
TSTG
TJ
Internally limited
Storage temperature
-65 to 150
°C
Operating junction temperature
-40 to 150
°C
VOUT1(2)
Externally forced output voltage OUT1
-0.3 to VS + 0.3, max + 6.3
V
VOUT2(2)
Externally forced output voltage OUT2
-0.3 to VS + 0.3
V
VOUT3(2)
Externally forced output voltage OUT3
-0.3 to VS + 0.3, max + 6.3
V
-0.3 to 7
V
-0.3 to VS + 0.3
V
-28 to 40
V
-28 to 40
V
Vinli
VinliW
Input voltage logic inputs: SIN, SCLK, NRES
Input voltage WAKE
line(3)
Vcanh
Voltage CANH
Vcanl
Voltage CANL line
1. All pins of the IC are protected against ESD. The verification is performed according to MIL 883C, human
body model with R = 1.5 k, C = 100 pF and discharge voltage 2000 V, corresponding to a maximum
discharge energy of 0.2 mJ.
2. Voltage forced means voltage limited to the specified values while the current is not limited.
3. ESD pulses on CAN-pins up to 4 KV HBM vs GND with all other pins grounded.
2.2
Thermal data
Table 4.
Symbol
Thermal data of PowerSO-20
Parameter
Rthj-a
Thermal resistance junction-ambient
Rthj-c
Thermal resistance junction-case
1. Typical value soldered on a PC board with 8
8/46
cm2
copper ground plane (35µm thick).
Doc ID 022587 Rev 2
Value
Unit
40(1)
°C/W
3
°C/W
L4969UR-E, L4969URD-E
2.3
Electrical specifications
Electrical characteristics
VS = 14 V, Tj = -40°C to 150°C, unless otherwise specified
Table 5.
Symbol
ISSL
ISSLWK
ISSB
IS
ISCP
Table 6.
Symbol
V01
VDP1
VOL01
ILIM1
Supply current
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Timer off (sleep #1)
20
40
60
µA
Timer on (sleep #2)
50
90
135
µA
RX only
2
4
6
mA
Timer off (standby #1)
100
150
250
µA
Timer on (standby #2)
150
200
300
µA
Default (standby #3)
350
440
600
µA
IOUT1 = -100 mA;
IOUT2 = -10 mA; no CAN
load
110
120
150
mA
55
80
100
µA
10
30
50
µA
Min.
Typ.
Max.
Unit
6 V < VS < 28 V;
IO > -100 mA(1)
4.9
5
5.1
V
6 V < VS < 28 V;
IO > -150 mA(2)
4.9
5
5.1
V
IOUT1 = -10 mA
0.0
0.025
0.06
V
0.0
0.25
0.6
V
All regulators off (CANH
Standby
V1 off, V2 off, V3 on (CAN RX
only)
V1 only (CAN Standby)
All regulators on, (CAN active,
TX high)
Additional oscillator and charge VS = 6 V; Timer off
pump current at low VS
VS = 6 V; Timer on
Voltage regulator 1
Parameter
Test conditions
V1 output voltage
Dropout voltage 1@
VS = 4.8 V
Load regulation 1
Current limit 1
IOUT1 = -100
mA(1)
IOUT1 = -150
mA(2)
0.0
0.4
0.9
V
IO = -1 mA to -100
mA(1)
0
10
40
mV
IO = -1 mA to -150
mA(2)
0
10
40
mV
0.8 V < VO1 < 4.5 V;
VS = 6 V(1)
-180
-400
-800
mA
0.8 V < VO1 < 4.5 V;
VS = 14 V(2)
-180
-400
-800
mA
0
5
30
mV
VOLI1
Line regulation 1
6 V < VS < 28 V; IO1 = -1 mA
TOVT1
Overtemp flag 1
6 V < VS < 28 V
130
140
150
°C
TOTKL1
Thermal shutdown 1
6 V < VS < 28 V
175
185
205
°C
Min V1 reset threshold
voltage
RTC0 = 0
4.15
4.5
4.7
V
RTC0 = 1
3.7
4.0
4.2
V
Vres
1. Valid for SO-20 package
2. Valid for PowerSO-20 package
Doc ID 022587 Rev 2
9/46
Electrical specifications
Table 7.
Symbol
L4969UR-E, L4969URD-E
Voltage regulator 2 and 3
Parameter
VO
Output voltage
VDP
Dropout voltage
VOLO
Test conditions
Min.
Typ.
Max.
Unit
(1)
6 V < VS < 28 V; IO > -100 mA
4.8
5
5.2
V
6 V < VS < 28 V; IO > -150 mA(2)
4.8
5
5.2
V
VS = 4.8 V; IOUT = 100 mA(1)
0.0
0.25
0.6
V
0.0
0.4
0.9
V
0
10
40
mV
0
10
40
mV
-180
-400
-800
mA
-180
-400
-800
mA
0
5
30
mV
(2)
IOUT = 150 mA
IO = -1 mA to -100 mA
Load regulation
(1)
(2)
IO = -1 mA to -150 mA
(1)
0.8 V < VO1 < 4.5 V; VS = 6 V
ILIM
Current limit
VOLI
Line regulation
6 V < VS < 28 V; IOUT = - 5 mA
TOVT
Overtemp flag
6 V < VS < 28 V
130
140
150
°C
TOTKL
Thermal shutdown
6 V < VS < 28 V
150
165
180
°C
V2 tracking offset
6 V < VS < 28 V; IO2 = 0
-90
0
+90
mV
Vtrc
(2)
0.8 V < VO1 < 4.5 V
1. Valid for SO-20 package
2. Valid for PowerSO-20 package
Table 8.
Symbol
tOSC
tOSCslow
tWDC
Parameter
Test conditions
OnChip RC-timebase
RC-Adjustment = 0
Watchdog timebase (2.5 ms)
Min.
Typ.
Max.
Unit
Normal, RXonly,
standby3 (“1MHz”)
0.95
1.1
1.35
µs
Sleep2, standby2
(“250KHz”)
4.0
5.4
6.8
µs
Normal, RXonly,
standby3 (“1MHz”)
2498
tOSC
Sleep2, standby2
(“250KHz”)
624
tOSCslow
tRDnom
Reset pulse duration (1 ms)
1024
tOSC
tWDstart
Reset pulse pause (320 ms)
(startup watchdog)
128
tWDC
SWT = 0 (2.5 ms)
1
tWDC
SWT = 1 (5 ms)
Watchdog window start
(Software window watchdog) SWT = 2 (10 ms)
2
tWDC
4
tWDC
SWT = 3 (20 ms)
8
tWDC
SWT = 0 (5 ms)
2
tWDC
SWT = 1 (10 ms)
Watchdog window end
(Software window watchdog) SWT = 2 (20 ms)
4
tWDC
8
tWDC
SWT = 3 (40 ms)
16
tWDC
tWDswS
tWDswE
10/46
Reset and watchdog
Doc ID 022587 Rev 2
L4969UR-E, L4969URD-E
Table 8.
Symbol
tWD1C
tWD2C
Electrical specifications
Reset and watchdog (continued)
Parameter
Test conditions
System watchdog 1
System watchdog 2
Min.
RPURES
Table 9.
Symbol
Reset output LOW voltage
Max.
Unit
WDT = 0 (80 ms)
32
tWDC
WDT = 1 (160 ms)
64
tWDC
WDT = 2 (320 ms)
128
tWDC
WDT = 3 (640 ms)
256
tWDC
WDT = 4 (800 ms)
320
tWDC
WDT = 8 (1 s)
400
tWDC
WDT = 9 (2 s)
784
tWDC
WDT = 10 (4 s)
1600
tWDC
WDT = 11 (8 s)
3200
tWDC
1081344
tWDC
WDT = 12 (45 min)
VRESL
Typ.
IRES = 500 µA;
V1 = 2.5 V
0
0.3
0.4
V
IRES = 500 µA;
V1 = 1.5 V
0
0.85
1.4
V
80
120
280
K
Internal reset Pull-Up
Resistance
CAN Line Interface
Parameter
Test conditions
Min.
Typ.
Max.
Unit
tdrd
Propagation delay (rec to
dom state)
Cload = 3.3 nF
0.4
1.0
1.5
µs
tddr
Propagation delay (dom to
rez state)
Cload = 3.3 nF;
RTERM = 100 
0.4
1.0
2.0
µs
SRD
Bus output slew rate (r  d)
10% ... 90%;
CLoad = 3.3 nF
4
5
8
V/µs
RRTH,
RRTL
External termination
resistance (application limit)
0.5
16
K
VCCFS
Force Standby mode (fail
safe)
2.20
4.0
V
VHRXD
High level output voltage on
RXD
V1 - 0.9
V1
V
VLRXD
Low level output voltage on
RXD
0
0.9
V
Vd_r
Differential receiver dom to
rec threshold VCANH VCANL
No bus failures
-3.85
-2.50
V
Vr_d
Differential receiver rez to
dom threshold VCANH VCANL
No bus failures
-3.50
-2.20
V
CANH recessive output
voltage
TXD = V1; RRTH < 4 K
0.35
V
VCANHr
Min VS to turn off CANIF and V3
Doc ID 022587 Rev 2
11/46
Electrical specifications
Table 9.
Symbol
12/46
L4969UR-E, L4969URD-E
CAN Line Interface (continued)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VCANHd
CANH dominant output
voltage
TXD = 0;
ICANH = 40 mA
V3 - 1.4 V
V
VCANLr
CANL recessive output
voltage
TXD = V1; RRTL < 4 K
V3 - 0.2 V
V
VCANLd
CANL dominant output
voltage
TXD = 0;
ICANL = -40 mA
ICANH
CANH dominant output
current
TXD = 0; VCANH = 0 V
70
ICANL
CANL dominant output
current
TXD = 0; VCANL = 14 V
ILCANH
Sleep mode.
CANH Sleep mode leakage
Tj = 150°C;
current
VCANH = 0 V
ILCANL
CANL Sleep mode leakage
current
VWakeH
1.4
V
100
160
mA
-70
-100
-160
mA
-10
0
-10
µA
Sleep mode.
Tj = 150°C;
VCANL = 0 V; VS = 12 V
-10
0
-10
µA
CANH wakeup voltage
Sleep/ standby mode
1.2
1.9
2.7
V
VWakeL
CANL wakeup voltage
Sleep/ standby mode
2.4
3.1
3.8
V
Vcanhs
CANH single ended
receiver threshold
Normal mode.
-5 V < CANL < VS
1.5
1.82
2.15
V
Vcanls
CANL single ended receiver Normal mode.
threshold
-5 V < CANH < VS
2.7
3.1
3.4
V
VOVH
CANH overvoltage
detection threshold
Normal mode.
-5 V < CANL < VS
6.5
7.2
8.0
V
VOVL
CANL overvoltage detection Normal mode.
threshold
-5 V < CANH < VS
6.5
7.2
8.0
V
RTRTH
Internal RTH to GND
termination resistance
Normal mode, no failures.
VRTH = 1 V
25
45
80

ITRTHF
Internal RTH to GND
termination current Normal
mode, failure EIII
VRTH = V3 - 1 V
55
75
100
µA
RTRTL
Internal RTL to VCC
termination resistance
Normal mode, no failures.
VRTL = V3 - 1 V
25
45
85

ITRTLF
Internal RTL to VCC
termination current Normal
mode. (failure EIV, EVI,
EVII)
VRTL = V3 - 1 V
-6
-40
-70
µA
RTRTLS
Internal RTL to VS
termination resistance. No
failures.
Standby/sleep mode.
VRTL = 1 V, 4 V
7
13
26
k
Doc ID 022587 Rev 2
L4969UR-E, L4969URD-E
Table 10.
Symbol
Electrical specifications
Digital I/O
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VSINL
Low level input voltage
0
0.9
V
VSINH
High level input voltage
V1 - 0.9
V1
V
VSCLKL
Low level input voltage
0
0.9
V
VSCLKH
High level input voltage
V1 - 0.9
V1
V
VTXL
Low level input voltage
0
0.9
V
VTXH
High level input voltage
V1 - 0.9
V1
V
VWakeL
Low level input voltage
0
0.9
V
VWakeH
High level input voltage
4.1
5.0
V
VSoutH
High level output voltage
V1 - 0.9
V1
V
VSoutL
Low level output voltage
0
0.9
V
VRXDH
High level output voltage
V1 - 0.9
V1
V
VRXDL
Low level output voltage
0
0.9
V
IohRXD
High level output current
RXD = 0
-2.5
-1.8
-0.9
mA
IolRXD
Low level output current
RXD = 5 V
0.9
1.6
2.5
mA
IohSOUT
High level output current
SOUT = 0
-18.0
-14.0
-7.0
mA
IolSOUT
Low level output current
SOUT = 5 V
15
24
35
mA
IohINT
High level output current
INT = 0
-20
-15
-8
mA
IolINT
Low level output current
INT = 5 V
15
24
35
mA
IohReset
High level output current
RESET = 0
-25.0
-15,0
-6.0
µA
IolReset
Low level output current
RESET = 5 V
5.0
7.5
10.0
mA
IohWake
High level output current
VWake = 5 V
-1.5
0
1.5
µA
IolWake
Low level output current
VWake = 0 V
-4.5
-3.4
-2.0
µA
Table 11.
Symbol
Serial data interface
Parameter
Test conditions
Min.
Typ.
Max.
Unit
tStart
SIN low to SCLK low setup time
(frame start)
100
ns
tSetup
SIN to SCLK setup time (write)
100
ns
tHold
SIN to SCLK hold time (write)
100
ns
tD
SCLK to SOUT delay time (read)
SCLK maximum cycle time
(timeout)
1
tGAP
Interframe gap
5
fSCLK
SCLK frequency range
tCKmax
Doc ID 022587 Rev 2
0.25
1.5
500
ns
3.0
ms
µs
0.5
1
MHz
13/46
Electrical specifications
Table 12.
Diagnostic functions
Symbol
Parameter
VSmin
GSCANH
Table 13.
Symbol
14/46
L4969UR-E, L4969URD-E
Test conditions
Min.
Typ.
Max.
Unit
Sense comparator detection
threshold
6.0
7.2
8,0
V
CANH groundshift detection
threshold
-1.5
-1
-0.6
V
Typ.
Max.
Unit
CAN error detection
Parameter
Test conditions
Min.
NEdgeH
Nr of dom to rec edges on
CANL to detect permanent
rez CANH
Operating mode (EI_V)
3
Edges
NEdgeHR
Nr of dom to rec edges to
detect recovery of CANH
Operating mode (EI_V)
3
Edges
NEdgeL
Nr of dom to rec edges on
CANH to detect permanent
rez CANL
Operating mode (EII_IX)
3
Edges
NEdgeLR
Nr of dom to rec edges to
detect recovery of CANL
Operating mode (EII_IX)
3
Edges
tEIII
CANH to VS short circuit
detection time
Operating mode (EIII)
1.6
2
3.6
ms
Sleep/ standby mode (EIII)
1.6
2
3.6
ms
tEIIIR
CANH to VS short circuit
recovery time
Operating mode (EIII)
0.4
0.9
1.6
ms
Sleep/ standby mode (EIII)
0.4
0.9
1.6
ms
tEIV
CANL to GND short circuit
detection time
Operating mode (EIV)
0.4
0.9
1.6
ms
Sleep/ standby mode (EIV)
0.4
0.9
1.6
ms
tEIVR
CANL to GND short circuit
recovery time
Operating mode (EIV)
10
30
50
µs
Sleep/ standby mode (EIV)
0.4
0.9
1.6
ms
tEVI
CANL to VS short circuit
detection time
Operating mode (EVI)
0.4
0.9
1.6
ms
tEVIR
CANL to VS short circuit
recovery time
Operating mode (EVI)
200
500
750
µs
tEVII
CANL to CANH short circuit
Operating mode (EVII)
detection time
0.4
0.9
1.6
ms
tEVIIR
CANL to CANH short circuit
Operating mode (EVII)
recovery time
10
30
50
µs
Operating mode (EVIII)
1.6
1.8
3.6
ms
tEVIII
CANH to VDD short circuit
detection time
Sleep/ standby mode
(EVIII)
1.6
1.8
3.6
ms
CANH to VDD short circuit
recovery time
Operating mode (EVIII)
0.4
0.9
1.6
ms
tEVIIIR
Sleep/ standby mode
(EVIII)
0.4
0.9
1.6
ms
Doc ID 022587 Rev 2
L4969UR-E, L4969URD-E
Table 13.
Symbol
Electrical specifications
CAN error detection (continued)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
tFailTX
TX permanent dominant
detection time (Fail safe)
Operating mode (EX)
0.4
0.9
1.6
ms
tFailTXR
TX permanent dominant
recovery time (Fail safe)
Operating mode (EX)
1
4
8
µs
Min.
Typ.
Max.
Unit
Table 14.
Symbol
Wakeup
Parameter
Test conditions
twuCAN
Minimum dominant time for
wake-up via CANH or CANL
Sleep/standby
8
22
38
µs
twuWK
Minimum pulse time for wakeSleep/standby
up via WAKE
8
22
38
µs
Doc ID 022587 Rev 2
15/46
Functional description
L4969UR-E, L4969URD-E
3
Functional description
3.1
General features
The L4969UR is a monolithic integrated circuit which provides all main functions for an
automotive body CAN network.
It features two independent regulated voltage supplies V1 and V2, an interrupt and reset
logic with internal clock generator, Serial Interface and a low speed CAN-bus transceiver
which is supplied by a separate third voltage regulator (V3).
The device guarantees a clearly defined behavior in case of failure, to avoid permanent CAN
bus errors.
The device operates in four basic modes, with additional programming for V1 Standby
modes in CTCR:
Table 15.
Operating mode description
LP1, LP0
Mode
V1 V2 V3
Timer/WDC
CAN-IF
Ityp
Sleep #1
Off Off Off
Off
Standby
40µ
x,x
No Timer based wakeup
Sleep #2
Off Off Off On (250Khz) Standby
80µ
x,x
Timer active based on tOSCslow
Standby 170µ
1,1
No Watchdog or Timer
Standby #2(1) On Off Off On (250KHz) Standby 210µ
1,0
Watchdog or timer active based on
tOSCslow
Standby
1.
#1(1)
On Off Off
Off
(CTCR)
Remarks
Standby #3
On Off Off
On (1MHz)
Standby 440µ
0,0
Watchdog or timer activ, POR default
RXOnly
Off Off On
On (1MHz)
RX-Only 4mA
x,x
Active during Busactivity to filter ID,
auto- matic fall back to Sleep when Bus
idle
Normal
On On On
On (1MHz)
Normal
x,x
No Currents from CAN or Regulators
5mA
Note, that in order to enter either Standby #1 or Standby #2 the Startup-Watchdog has to be acknowledged, in Standby #1, the Window
Watchdog has to be disabled as described in Chapter 2.5, to allow the decativation of the internal oscillator.
3.1.1
V1 output voltage
The V1 regulator uses a DMOS transistor as an output stage. With this structure very low
dropout voltage is obtained. The dropout operation of the standby regulator is maintained
down to 4 V input supply voltage. The output voltage is regulated up to the transient input
supply voltage of 40 V. With this feature no functional interruption due to overvoltage pulses
is generated. The output 1 regulator is switched off in sleep mode.
3.1.2
V2 output voltage
The V2 regulator uses the same output structure as the output 1 regulator except to being
short circuit proof to VS. The V2 output can be switched on and off through a dedicated
enable bit in the control register. In addition a tracking option can be enabled to allow V2
follow V1 with constant offset. This feature allows consistent A/D conversion inside the
microcontroller (supplied by V1) when the converted signals are referenced to V2. The
maximum voltage that can be applied to V2 is VS + 0.3 V up to a max VS of 40 V.
16/46
Doc ID 022587 Rev 2
L4969UR-E, L4969URD-E
3.1.3
Functional description
V3 output voltage
The third voltage regulator of the device generates the supply voltage for the internal logic
and the CAN-transceiver. In operating mode it is capable of supplying up to 200 mA in order
to guarantee the required short circuit current for the CAN_H driver. The sleep and
operating modes are switched through a dedicated enable bit.
3.1.4
Internal supply voltage
A low power sleep mode regulator supplies the internal logic in sleep mode.
3.2
Power-up, initialization and sleep mode transitions
The following state-diagram illustrates the possible mode transitions inside the device.
As a prerequisite, an SPI-connection to the microcontroller with the correct CRC-algorythms
is required.
During the debug phase the NRES line can be forced high externally (connect to V1) to
deactivate the startup failure mechanism and keeping V1 alive.
Doc ID 022587 Rev 2
17/46
Functional description
L4969UR-E, L4969URD-E
Figure 3.
State diagram
The forced sleep mode is left upon wake-up through either CAN or edge on
WAKE. Applying a permanent wake-up (i.e. both CAN-lines dominant) prevents V1 from being turned off (can be used during System debugging)
After POR, V1 up or externally forced reset
through low NRES, the STARTUP STATE is
entered
WAKEUP
V1 Low
Forcing NRES high externally, fail will not be incremented (Emulation)
NRES Low
WAKEUP
STARTUP
V1 active
V2, V3, CAN off
t=320ms
t=1ms
STARTUP
FAILURE
RESET low
WDC-FAIL
Depending on the value from the last
WDC-ACK, another one has to be
written within the specified time frame
(SWDC[1:0]). A failure will activate
the STARTUP STATE
Writing to the WDCregister
(WDC-ACK)
the NORMAL STATE is
entered.
NORMAL MODE WDC-ACK
WINDOW WDC t=tWIN2
WDC-OK
ACTIVE
V1 off
No Reset
(fail ++)
A missing ACK within 320ms will
initiate a STARTUP FAILURE
phase (RESET low).
WDC-ACK
FORCED SLEEP
fail = 7
WDC-ACK
&
WDEN SET
WINDOW
WATCHDOG
REFRESH
If no WDC-ACK is received within
seven retrials the voltage regulator
V1 will be turned off by entering the
FORCED SLEEP state.
The Window supervision can temporarily be deactivated for the time programmed during the
last WDC-ACK (WDT[3:0]). Upon rewriting
(WDC-ACK) or expiry of the timer, the NORMAL
STATE is reentered.
TIMER
ACTIVE
(restart by double
WDC-ACK & WDEN)
WDEN SET
TIMEOUT | (WDC-ACK & NOT TIMEOUT(1))
WND SET
(1)
Rewriting of the WDC register when the timer just expires can
lead to an unwanted window watchdog failure resulting in a low
pulse on RESET (see note on section 4.5.4)
DISAR
SET
If during the last WDC-ACK WND has been set (after releasing
write lock, see description of Watchdog Control Register) the Window watchdog is deactivated, and no uC supervision is active.
WDEN SET
NORMAL MODE
WINDOW WDC
TIMEOUT | WDC-ACK
DISABLED
WAKEUP
WAKEUP
&V1_UV
Here the timer can be used to
generate time events (i.e.
wake-up uC from stop)
TIMER
ACTIVE
(restart by double
WDC-ACK & WDEN)
DISAR
SET
Programmed
SLEEP
V1 OFF
No Reset
Setting DISAR (see Voltage Regulator Control Register) Voltage regulator V1 is
turned off, and the output voltage is decreasing depending on the external load
and blocking capacitor.
Note, that during this transition no Reset will be generated (due to Debug mode).
Upon wake-up howewer NRES will be pulled low, if V1was below the programmable reset threshold (V1_UV).
WAKEUP&V1_UV
3.3
CAN transceiver
–
–
–
–
–
Supports double wire unshielded busses
Baud rate up to 125 KBaud
Short circuit protection (battery, ground, wires shorted)
Single wire operation possible (automatic switching to single wire upon bus failures)
Bus not loaded in case of unpowered transceiver
The CAN transceiver stage is able to transfer serial data on two independent communication
wires either deferentially (normal operation) or in case of a single wire fault on the remaining
line. The physical bitcoding is done using dominant (transmitter active) and overwritable
18/46
Doc ID 022587 Rev 2
L4969UR-E, L4969URD-E
Functional description
recessive states. Too long dominant phases are detected internally and further transmission
is automatically disabled (malfunction of protocol unit does not affect communication on the
bus, "fail-safe" - mechanism). For low current consumption during bus inactivity a sleep
mode is available. The operating mode can be entered from the sleep mode either by local
wake up (microcontroller) or upon detection of a dominant bit on the CAN-bus (external
wake up).
Ten different errors on the physical buslines can be distinguished:
Table 16.
Detectable physical busline failures
N
Type of errors
Conditions
Errors caused by damage of the datalines or isolation
I
CANH wire interrupted (tied to Ground or termination)
Edgecount difference > 3
II
CANL wire interrupted (floating or tied terminationk)
Edgecount difference > 3
III
CANH short circuit to VBAT (overvoltage condition)
V(CANH) > 7.2 V after 3.6 ms
IV
CANL short circuit to GND (permanently dominant)
V(CANL) < 3.1 V &
V(CANH)-V(CANL) > -3.25 V
after 1.6 ms
V
CANH short circuit to GND (permanently recessive)
Edgecount difference > 3
VI
CANL short circuit to VBAT (overvoltage condition)
V(CANL) > 7.2 V after 1.6 ms
V(CANH) - V(CANL) < -3.25 V
after 1.6 ms
VII CANL shorted to CANH
Errors caused by misbehavior of transceiver stage
VIII CANH short circuit to VDD (permanently dominant)
IX
CANL short circuit to VDD (permanently recessive)
V(CANH) > 1.8 V &
V(CANH) - V(CANL) > -3.25 V
after 3.2 ms
Edgecount difference > 3
Errors caused by defective protocol unit
X
CANH, CANL driven dominant for more than 1.6 ms
Note:
Not all of the 10 different errors lead to a breakdown of the whole communication. So the
errors can be categorized into 'negligible', 'problematic' and 'severe':
3.3.1
Negligible errors
●
Transmitter
–
Error I and II (CANH or CANL interrupted but still tied to termination)
–
Error IV and VIII (CANH or CANL permanently dominant by short circuit)
In all cases above data can still be transmitted in differential mode.
●
Receiver
–
Error I and II (CANH or CANL interrupted but still tied to termination).
–
Error V and IX (CANH or CANL permanently recessive by short circuit).
In all cases above data can still be received in differential mode.
Doc ID 022587 Rev 2
19/46
Functional description
3.3.2
L4969UR-E, L4969URD-E
Problematic errors
●
Transmitter
–
Error III and VI (CANH or CANL show overvoltage condition by short circuit).
Data is transmitted using the remaining dataline (single wire).
●
Receiver
–
Error III and VI (CANH or CANL show overvoltage condition by short circuit).
Data is received using the remaining dataline (single wire).
3.3.3
Severe errors
●
Transmitter
–
Error V and IX (CANH or CANL permanently recessive by short circuit).
Data is transmitted on the remaining dataline after short circuit detection.
–
Error VII (CANH is shorted to CANL).
Data is transmitted on CANH or CANL after overcurrent was detected.
–
Error X (attempt to transmit more than 10 successive dominant bits (at lowest
bitrate specified).
Transmission is terminated (fail safe).
●
Receiver
–
Error VII (CANH is shorted to CANL).
Data is received on CANH or CANL after detection of permanent dominant state.
–
Error IV and VIII (CANH or CANL permanently dominant by short circuit).
Data is received on CANH or CANL after short circuit was detected.
–
Error X (reception of a sequence of dominant bits, violating the protocol rules).
Data is received normally, error is detected by protocol-unit.
The error conditions is signaled issuing an error flag inside a dedicated register which
is readable by the microcontroller through the serial interface. The information of the
error type (I through X) is also stored into this register.
3.3.4
Wakeup via CAN
When the CAN transceiver is in standby mode special low power comparators detect activity
on CANH and / or CANL. This information is filtered and can be defined as a wakeup
condition for the voltage regulator and the application via the ‘WKC’ flag in the IFR register
as a maskable interrupt through NINT or via RX.
The wakeup signalling via RX is described in the following diagram:
Figure 4.
Wakeup signalling via RX
dominant
CANx
RX
recessive
twuCAN
< twuCAN
twuREP
20/46
tOSC
Doc ID 022587 Rev 2
L4969UR-E, L4969URD-E
Functional description
After detecting a dominant level on either CANH or CANL for longer than the wakeup filter
time (twuCAN), RX goes low for one tOSC cycle. This is repeated cyclically every twuREP until
CANx returns to a recessive state or CANx is considered as shorted to a dominant value.
Note, that the duration of the extended cycle twuREP equals twuCAN when the oscillator is in
1 MHz mode (Standby3, RXOnly and Normal mode, see Table 15).
If the device uses the low power oscillator (250 KHz) in either Sleep2 or Standby2
twuREP = 4.2 x twuCAN.
3.4
Oscillator
A low power oscillator provides an internal clock, that can be calibrated in a range from
-16% to +16% via the RCADJ register using the µC-XTAL as a reference.
In the operating modes Sleep2 and Standby2 (Watchdog / timer active) the output frequency
is ~250 kHz (1/ tOSCslow), if the Watchdog function is not requested, the internal Oscillator is
switched off.
In the operating modes Normal, RXonly and Standby3 the oscillator is running at ~1 MHz
(1/ tOSC).
3.5
Watchdog
A triple function programmable watchdog is integrated to perform the following tasks:
●
Wakeup watchdog:
When in sleep or standby mode the watchdog can generate a wakeup condition after a
programmable period of time ranging from 80 ms up to 45 minutes
●
Startup watchdog:
Upon V1 power-up or microcontroller failure during SPI supervision a reset pulse is
generated periodically every 320 ms for 2.5 ms until activity of the microcontroller is
detected (SPI sequence) or no acknowledge is received within 7 cycles (2.2 sec). In
this condition the device is forced into Sleep mode until a Wakeup is detected and a
startup cycle is reinitialized.
●
Window watchdog:
After passing the startup sequence, this watchdog request an acknowledge by the
microcontroller via the SPI within a programmable timing frame, ranging from 2.5 ...
5 ms up to 20 ... 40 ms. Upon a missing or misplaced acknowledge the Startup
Watchdog is initialized.
3.6
Reset
3.6.1
Power-on reset
Upon Power-on (VS > 3.5 V), the internal reset forces the device into a predefined power-On
state (see Section 3.1: General features):
Standby #3: V1 on V2 off V3 off,CAN-Standby mode, ID-Filter disabled, startup watchdog
active.
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Functional description
L4969UR-E, L4969URD-E
With VS below 5 V the regulator V1 will follow VS with minimum drop. The microcontroller
retrieves a reset if V1 is dropping below a programmable voltage level of either 4.5V (default)
or 4.0 V. The programmed state of the L4969UR remains unchanged. The act. low Reset
pulse duration is fixed internally by an open-drain output stage to 1 ms. However, this time
can be externally extended by an additional capacitance connect between NRESET and
GROUND which is then charged by the internal pull-up of typical 120 K. Depending on the
Reset-Input-Threshold of the microcontroller (UTR), the required Capacitance for a typical tD
can be calculated as follows:
CEXT = -tD / (120E3 ln(1-UTR/V1)).
To obtain a reset-pulse duration of tD = 50 ms with UTR/V1 = 0.5, a capacitance of
CEXT= -50E-3 / (120E3 ln 0.5) = 600 nF is required
Figure 5.
NRES pin internal structure
V1
120K
to Reset Input of uC
NRES
CEXT
3.6.2
Undervoltage reset
Upon detection of a V1 voltage level below a programmable voltage level of either 4.5 V
(default) or 4.0 V, the NRES-pin is pulled low. Since this undervoltage detection is
additionally sampled periodically every ms, the NRES low time will be extended by up to
1 ms if V1 was low (V1UV) at the sampling point (see Figure 6).
Figure 6.
NRES timings
1ms sampling
V1UV
NRES
3.6.3
Reset signalling during sleepmode
When entering the sleep mode by writing 1 to DISAR in the VRCR register, the Voltage
regulators and their references will be deactivated to allow minimum current consumption.
By removing the V1 reference, the output voltage is no longer supervised and thus NO reset
will be generated.
Now two scenarios are possible (see Figure 3: State diagram):
1) Wakeup with V1 still above reset threshold: V1 will be reactivated and Normal mode is
resumed
2) Wakeup with V1 below reset threshold: V1 will be activated, NRES will go low and remain
low until V1 is above reset threshold and startup mode is entered.
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Doc ID 022587 Rev 2
L4969UR-E, L4969URD-E
Functional description
The scenario 2 is the most critical when used with microcontroller that do not have their own
POR circuitry.
In this case V1 will ramp down with an unknown application state.
To guarantee a proper shut off of a microcontroller without an internal POR circuitry the
following mechanism can be utilized: the L4969UR uses a bidirectional reset to detect a
possible watchdog failure of the microcontroller. If this failure condition is detected, NRES
will be forced low for 1 ms (with activated timer) or until a wakeup condition occurs (WDEN
bit in WDC register reset, thus RC-oscillator will be switched off during sleep).
Two methods can be used to allow a proper sleep transition:
●
With Timer (WDEN = 1): immediately after setting DISAR the microcontroller has to
program its WDC to generate a failure causing the L4969UR to detect a low level on
NRES followed by an automatic 1 ms pulse extension. If V1 is ramping down slow, Cext
has to be defined in a way, that NRES will stay below the input threshold of the
microcontroller until V1 is in a safe level.
●
Without timer (WDEN = 0): same procedure as above, but microcontroller has to
generate a Reset within 1 ms after WDEN has been cleared. NRES will then stay low,
until a wakeup condition occurs.
Figure 7.
DISAR
Internal circuitry and suggested CEXT for NRES generation during sleep
mode
V1
REF REG
R2
R1
NRES
WDC
1ms
CEXT
µC
RC-Osc
L4969UR
3.7
Identifier filter
A 12-Bit CAN-ID-filter is implemented allowing wakeup via specific CAN-messages thus
aiding the implementation of low power partial communication networks like standby
diagnostics without the need to power-up the whole network.
To guarantee the detection of the programmed Identifiers, the local RC-oscillator can be
calibrated to allow the programmable Bittime logic to extract the incoming stream with a
maximum of tolerance over temperature deviation.
3.8
Ground shift detection
In case of single wire communication via CANH the signal to noise ratio is low. Detecting the
local ground shift can be used as an additional indicator on the current signal quality. The
Doc ID 022587 Rev 2
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Functional description
L4969UR-E, L4969URD-E
information of the integrated ground shift detector will be refreshed upon every falling edge
on TX and can be read from the CAN Transceiver Status Register (CTSR).
It will be set, if V(CANH) < -1 V, reset if V(CANH > -1 V) at the falling edge of TX.
3.9
Thermal protection
The device features three independent thermal warning circuits which monitor the
temperature of the V1 output, the V2 output and the CAN_H and CAN_L drivers together
with voltage regulator V3. Each circuit sets a separate overtemperature flag in a register
which is read and writable by the serial interface. The overtemperature flags cause an
interrupt to the microcontroller. The microcontroller is able to switch V1, V2 and CAN drivers
on and off through dedicated enable registers. To enhance system security the following
strategy is chosen for thermal warning and shutdown:
●
3 independent warning flags are set at 140°C for V1, V2 and V3 /CAN-Transceiver
●
at 170°C V2 and V3 switched off
●
at 200°C V1 is switched off
●
V2 and V3 can be switched on again through the microcontroller
●
V1 can be switched on again at wake-up (watchdog wake-up, CAN wake-up, external
wake-up)
Note, that if no wakeup source is set for V1 the external WAKE pin and the CAN interface will
be activated to allow a proper retry cycle.
3.10
Serial Interface (SPI)
A standard serial peripheral interface (SPI) is implemented to allow access to the internal
registers of the L4969UR.
A total of 12 registers with different datalengths can be directly read from or written to,
providing the requested address at the beginning of a dataframe. Upon every access to this
interface, the content of the register currently accessed is shifted out via SOUT. All
operations are performed on the rising edge of SCLK.
If a frame is not completed, the interface is automatically reset after 1.5 ms of SCLK idle
time (auto timeout detection). If a message is corrupted (additional or missing SCLK
pulses), the application software can detect this by evaluating the returned value of the CRC
and force a communication gap of min 1.5 ms to allow communication recovery. A
corruption can be caused during startup of the microcontroller and SPI initialization. The
application should then wait at least 1.5 ms after SPI init prior to starting the communication.
The dataframe format used is described on Section 3.10.1: General dataframe format.
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Doc ID 022587 Rev 2
L4969UR-E, L4969URD-E
3.10.1
Functional description
General dataframe format
Figure 8.
General dataframe format
Data is sampled on the rising edge of the clock and SOUT will change upon SCLK falling.
SOUT will show a copy of SIN for the Address/Command field for initial data path checks.
Independently of the command state, SOUT will show the content of the register addressed.
SIN contains either data to be written or arbitrary data for all other operations. The
transaction will be terminated with four bit of data followed by a 4-Bit wide CRC (Cyclic
Redundancy Check) as a result of either SIN related data or calculated automatically on
data returned via SOUT. Here the microcontroller has to provide the correct sequence in
order to get the write command activated inside. A CRC-failure is signalled via NINT. For
returned data the CRC can also be used to verify a successful transfer.
Note:
The information in data field 1 is copied from the adressed register into the SPI shift register
at the last rising SCLK edge of the address/command field. A clear or write operation on the
addressed register takes place after the last (24th) rising SCLK edge of the telegram if the
CRC check passes.
As a consequence any Read/Clear or Write SPI command can remove the information from
the addressed register that was set after the register content has been copied into the shift
register for reading.
This has to be considered especially in interrupt service routines processing Wakeup
Watchdog restarts that need to be synchronized with the ‘WKW’ flag inside the IFR register.
3.10.2
Address/command field
Figure 9.
Address / command field
7
0
0
1
ADR3
Frame start sequence
always has to be
transmitted as 0 1
ADR2
ADR1
ADR0
Address field specifying
the Control/Status word
to be accessed
Doc ID 022587 Rev 2
C1
C0
SPI command:
00: Read register
01: Clear IFR
10: illegal command
11: Write register
25/46
Functional description
L4969UR-E, L4969URD-E
The Address/command field starts with a 2-Bit start sequence consisting of ‘01’. Any other
sequence will lead to a protocol error signalled via the NINT. The address field is specifying
the register to be accessed. The SPI command flags allow in addition to the normal
read/write operation to clear the Interrupt flag register after read.
3.10.3
Datafield #1
Figure 10. Datafield #1
Datafield #1 contains either the lower 8 bits of a 12-bit frame or the complete byte of an 8-bit
transfer.
Note, that SOUT is always showing the content of the register currently accessed and not a
copy of SIN as during the address/command field.
3.10.4
Datafield #2/CRC
Figure 11. Datafield #2 / CRC
Datafield #2 contains either the upper four bits of a 12-bit frame or zeros in case of an 8-bit
transfer. This field is followed by a four bit CRC sequence that is calculated based upon the
polynom 0x11h (17 decimal). This sequence is simply the remainder of a polynomial
division performed on the data previously transferred. If the CRC appended to the SIN
sequence fails, any writing will be disabled and an error is signalled via NINT. Another
remainder is calculated on the SOUT stream and appended accordingly to allow the
application software to validate the correctness of incoming data. To aid evaluation, the CRC
checking can be turned off by writing arbitrary data with a valid CRC to address 15. CRCchecking will be reenabled upon another operation of this kind (Toggled information).
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Doc ID 022587 Rev 2
L4969UR-E, L4969URD-E
3.11
Functional description
Memory map
Table 17.
ADR
Group
0
L4969UR memory map
MSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VRCR
EUV3
EUV2
RTC0
TRC
RES
ENV3
ENV2
DISAR
1
CTCR
ACT
TXEN
RES
RES
OVR
LP2
LP1
LP0
2
GPTR
RES
RES
RES
RES
TM1
TM0
TMUX
TEN
3
RCADJ
CG1
CG0
PGEN
SIGN
ADJ3
ADJ2
ADJ1
ADJ0
4
WDC
WDEN
WND
SWT1
SWT0
WDT3
WDT2
WDT1
WDT0
5
GIEN
ISET
IRES
EUV
EOVT
EEW
ECW
EWW
EIFW
6
IFR
ESPI
ISET
IRES
UV23
UVVS
OVT3
OVT2
OVT1
WKE
WKC
WKW
WKIF
7
CTSR
RES
RES
RES
GSH
EX
EVIII
EVII
EVI
EIV
EIII
EII
EI
8
ID01
A11
A10
A01
A00
B11
B10
B01
B00
C11
C10
C01
C00
9
ID23
D11
D10
D01
D00
E11
E10
E01
E00
F11
F10
F01
F00
10
BTL
PS23
PS22
PS21
PS20
PS13
PS12
PS11
PS10
TD3
TD2
TD1
TD0
11
NAV
12
NAV
13
NAV
14
TEST
15
SYS
Undefined
Register Memory
Undefined
Register Memory
T11
T10
T09
T08
Undefined Register Memory
T07
T06
T05
T04
T03
T02
T01
T00
NCRC
STAT
WNDF
STF
OTF
UCF
WAKE
NPOR
The memory space is divided up into 16 different registers each being directly accessible
using the SPI.
Each register contains specific information of a functional group.
In general all reserved bitpositions (‘RES’) have to be written with ‘0’.
Undefined bits are read as ‘0’ and cannot be overwritten.
In addition there is one register (CTSR) being read only, thus any write attempt will leave the
register content unchanged.
Certain interlock mechanisms exist to prevent unwanted overwriting of important functions
i.e. voltage regulators or oscillator adjustments. These mechanisms are described with the
functions of these registers.
Doc ID 022587 Rev 2
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Control and status registers
4
L4969UR-E, L4969URD-E
Control and status registers
The functionality of the device can be observed and controlled through a set of registers
which are read and writable by the serial interface.
4.1
ADR 0: VRCR voltage regulator control register
Figure 12. ADR 0: VRCR voltage regulator control register
D7
EUV3
D0
EUV2
RTC0
TRC
RES
ENV3
Has to be
written as ‘0’.
Enable undervoltage
detection on
Regulator #2 and #3
(see note below)
Enable Regulator #2 tracking option
to have V2 following V1 with constant offset
Default value is ‘0’ (disabled)
Enable Regulator #3.
V3 will be activated by either setting ENV3 or
upon enabling of the CAN Lineinterface
Default value is ‘0’ (disabled)
This bit will be automatically reset upon
Overtemperature from CANIF or Regulator #3
V1
DISAR
Disable all regulators (Go to Sleep)
Note, that at least one Wake-up Source
without a pending wake-up is required
to enable access.
This bit will be automatically set upon
the system failures Overtemperature V1
or watchdog startup failure.
Set reset threshold value to 4.0V
Default value is ‘0’ (4.5V)
DISAR
ENV2
Note, that no reset will be generated
from low V1 during Sleep mode transition
The Reset line has to be forced low
externally, or through a window failure
DISAR will be cleared upon a valid
wake-up signal which is either defined
in GIEN or is forced to WAKE or CAN
after a system failure
Enable Regulator #2.
Default value is ‘0’ (disabled)
This bit will be automatically reset upon
Overtemperature at Regulator #2.
Note, that due to the large initial charging current of the output capacitors,
the activation of V2 AND V3 within the same command is not recommended
also leaving ENV2 or ENV3 set when setting DISAR can therefore not be
recommended (after wake-up V1 AND V2 or V3 would be turned on)
TRC
DISAR & ENV2
(DISAR & ENV3 |
ACT) & TSDV3
REF
V2
V3
V3 will be activated upon VRCR.ENV3 or
CCTR.ACT without pending thermal shutdown
Note, that when using the Undervoltage-detection, EUV2 and EUV3 have to be activated
after V2 or V3 have been turned on and settled (t > 1 ms). Otherwise unwanted undervoltage
can be detectected during turn on of the corresponding voltage regulator.
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Doc ID 022587 Rev 2
L4969UR-E, L4969URD-E
4.2
Control and status registers
ADR 1: CTCR CAN - transceiver control register
Figure 13. ADR 1: CTCR CAN - transceiver control register
D7
ACT
D0
TXEN
RES
RES
LP2
OVR
LP1
LP0
Standby-mode control (V1 only, see 1.1)
enable Auto-Osc-Off
reduce Osc-frequency to 250KHz
CAN-Transceiver application control
0X: Standby / Sleep
10: Receive only mode A (Readback TX, if not EX)
11: Normal Operation
CANL Over Voltage Retry Threshold
default value is ‘0’, threshold is 7.2V
set to ‘1’, threshold is 3.2V
Note: If CANL OV is detected, the
programmed threshold is used to validate
if transmission on CANL is valid and can
be continued.
Note, that TXEN is automatically reset upon
occurrence of EX (TX permanent dominant)
and has to be reprogrammed after problem
correction to enter normal mode.
Reserved bits (‘RES’) have to be written as ‘0’.
Three basic operating modes are available using different logic combinations on ACT and
TXEN. Each of these modes in conjunction with other inputs has its unique combination of
parameters inside the specification:
Table 18.
Operating modes of the CAN line interface
Input signals
ACT TXEN TX
Output signals
CANH
CANL
V3
Mode
RTL
RTH
CANH CANL
RX
0
X
X
RTH
RTL
ON
Standby
VBAT
GND
OFF
OFF
1
1
0
1/0
RTH
RTL
ON
RXonly
VDD
GND
OFF
OFF
TX
1
0
1
RTL
ON
RXonly
VDD
GND
OFF
OFF
1
0
1
RTH
ON
RXonly
VDD
GND
OFF
OFF
1
1
1
RTH
RTL
ON
Normal
VDD
GND
ON
ON
1
1
1
0
RTH
RTL
ON
Normal
VDD
GND
VDD
GND
0
1
1
1
RTL
ON
Normal
VDD
GND
ON
ON
1
1
1
RTH
ON
Normal
VDD
GND
ON
ON
1
1
0*1
RTH
RTL
ON
Error X
VDD
GND
OFF
OFF
1
1
X
1
VDD*1
RTL
ON
Error VII,
VIII
VDD
ISRC
OFF
ON
CANL
1
X
1
VS*1
RTL
ON
Error EIII,
VII, VIII
VDD
ISRC
OFF
ON
CANL
1
X
1
GND
ON
Error EI_V
VDD
GND
ON
ON
1
X
1
x3
VDD
ON
Error EII_IX
VDD
GND
ON
ON
*1
ON
Error EVI
ISRC GND
ON
OFF
1
X
1
RTH
x3
VS
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CANH
29/46
Control and status registers
Table 18.
L4969UR-E, L4969URD-E
Operating modes of the CAN line interface (continued)
Input signals
ACT TXEN TX
4.3
1
X
1
1
X
1
Output signals
CANH
CANL
V3
Mode
RTH
GND*1
ON
Error EVII,
EIV
ISRC GND
ON
OFF
CANH
ON
Error EVII
ISRC GND
ON
OFF
CANH
CANL*1 CANH*1
RTL
RTH
CANH CANL
RX
ADR 2: GPTR global parameter and test register
Figure 14. ADR 2: GPTR global parameter and test register
D7
RES
D0
RES
RES
RES
TM1
TM0
TMUX
Note:
This register is to be used for test purpose only, all bits have to remain ‘zero’
4.4
ADR 3: RCADJ RC-oscillator adjust register
TEN
Figure 15. State transition during oscillator calibration
During normal operation the microcontroller can set CG1 and CG0 to ‘01’ to force a 200Hz
rectangular waveform on NINT with 50% duty cycle. Note, that all other pending interrupts
have to be cleared before.
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L4969UR-E, L4969URD-E
Control and status registers
After the XTAL driven timer of the microcontroller has calculated the relative cycle time and
the corresponding deviation, CG1 and CG0 have to be set to ‘10’ to disable the adjustment
cycle on NINT. From the deviation calculated by the microcontroller, the correction factor of
the RC-oscillator -15% to 16% can be reprogrammed with CG1 and CG0 set to ‘00’ or ‘11’.
(‘11’ can be used to indicate that calibration has already been performed).
Note, that overwriting this register is only valid, if the cycle measurement was started and
terminated properly. This can be tested by evaluating PGEN either prior to or during
correction (Read back via SOUT).
Note also, that any write to the WDC register will reset the timer and thus reset the phase of
the testcycle. Therefore a cyclic access to the window watchdog during the pulsewidth
measurement has to be avoided and the timer watchdog to be used instead (i.e. 1 sec)
Figure 16. State transition during oscillator calibration
“No Request”
CG=00
CG=01 “2.5ms cycle CG=10
“Finish
Cycle”
“Update ADJ”
on NINT”
CG=11
Watchdog and Interrupt
has to be disabled
4.5
Start time measurement
at rising edge
Calculate
Write offset
Offset Watchdog and Interrupt can be enabled
ADR4: WDC watchdog control register
Figure 17. ADR4: WDC watchdog control register
D7
WDEN
D0
WND
SWT1
Disable
Window Watchdog,
only allowed with
PGEN set, see
previous table
for Osc adjust
Enable Wakeup Watchdog,
Window Watchdog will be
automatically deactivated
until wakeup watchdog expires
SWT0
WDT3
WDT2
Software Window Watchdog
timing configuration
00: 2.5 - 5ms
01: 5 - 10ms
10: 10 - 20ms
11: 20 - 40ms
Reserved bits (‘RES’) have to be written as ‘0’.
WDT1
WDT0
Wake-up Watchdog
timing configuration
0000: 80ms
0001: 160ms
0010: 320ms
0011: 640ms
0100: 800ms
1000: 1sec
1001: 2sec
1010: 4sec
1011: 8sec
1100: 45min
The startup watchdog is not programmable and will always generate a 1.0 ms low cycle on
NRESET followed by a 320 ms high cycle until an Acknowledgment will occur. If no
Acknowldege is received after the 7th cycle, the device will automatically be forced into
Sleep mode.
Doc ID 022587 Rev 2
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Control and status registers
L4969UR-E, L4969URD-E
Acknowledgment and Reset of Startup and window watchdog is automatically performed by
overwriting (or rewriting) this register.
Note, that with WDEN set, a cyclic setting of IFR.WKW after the programmed Wakeup time
will occur.
4.5.1
Watchdog configuration
Figure 18. Watchdog configuration
POR
NRESET
forced low
externally
ExtWake
CAN-Wake
Startup missing Ack
Wd (after 350ms)
Wakeup
Prog
Sleep
Ack
Ack
Note:
1
Forced
Sleep
missing
Ack
Timeout
Window
WR & NOT Timeout
Wd WR(1) & WDEN
Wakeup
Timer
WR (1) : writing to WDC twice register will restart the timer. Rewriting the WDC register while
the Wakeup Timer just expires can lead to an unwanted window watchdog failure and
therefore a low pulse on Reset (see note on section 4.5.4).
After power-on-reset of VS and V1 or wakeup from Sleep or NRESET being forced low
externally, the Startup Watchdog is active, supervising the proper startup of the V1 supplied
microcontroller. Upon missing SPI write operation to the WDC register after 7 reset cycles
(1 ms active, 320 ms high) the Sleep mode is entered.
Leaving the forced Sleep mode will be automatically performed upon wakeup via CAN, an
edge on WAKE or upon device powerup.
After successful startup, the Window Watchdog supervision is activated, meaning, that the
microcontroller has to send an acknowledge within a predefined, programmable window.
Upon failure, a reset is generated and the Startup Watchdog is reactivated.
If the Timer function is requested, the window watchdog is deactivated until expiry of the
wakeup time, or rewriting of this register. Any write to this register will reset the timer.
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4.5.2
Control and status registers
Startup
Figure 19. Startup
V1
1ms
NRESET
Startup Acknowledgement via SPI within 320ms
NRESET
Startup Acknowledgement via SPI within 640ms
NRESET
No Startup Acknowledgement via SPI within 2.3s (Device will enter Sleep mode)
After powerup, the L4969UR is expecting the microcontroller to send an acknowledgement
within a predefined segmented timing frame of 7 x 320 ms. A missing acknowledgement
until after the 2.3s will force the device into sleep mode until either external or CAN wakeup
or POR cause a restart of the sequence above.
4.5.3
Window watchdog
Figure 20. Window watchdog
2,5 .. 20ms
50%
Early (late) Acknowledge supervision
5 .. 40ms
Early (late) Acknowledge supervision
Acknowledge is restarting Window
After successful acknowledgement of the Startup sequence, the Window watchdog is
automatically activated and controlling proper microcontroller activity by supervising an
incoming acknowledge to lie within a predefined programmable window. Upon every
acknowledge the watchdog is restarting the window.
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Control and status registers
4.5.4
L4969UR-E, L4969URD-E
Wakeup watchdog
Figure 21. Wakeup watchdog
Window Wd
Timer (80ms .. 45min)
Ack Window &
Start Timer
NINT
Window Wd
restart timer
safely before expiration
by writing WDC twice
Timeout and resume Window Wd
Interrupt active upon timeout (via GIEN)
If the Timer is activated during Normal mode by setting WDEN in WDC, an “acknowledgefree” sequence is started for a predefined programmable time. Window Watchdog activity is
resumed after expiry of the timer.
To be able to detect the timeout, the corresponding interrupt enable must be set in GIEN.
This mode can also be used to allow a bootstrap loader mode with longer execution times
than the maximum specified window. Correct startup of this loader is safely detected upon
missing response following the timeout.
Note:
Special considerations for the timer restart via WDC write:
Due to a restriction in the transition from Wake-up Watchdog to Window Watchdog an
unwanted low pulse on RESET (Window Watchdog failure) can be triggered when WDC
register is rewritten while the Wake-up Watchdog just expires.
Therefore the timer can only be restarted by rewriting WDEN twice in WDC when the
location of the timer expiration is considered.
This is the case, when the expiration of the timer is monitored through timer expiration
interrupt via NINT (configuration as in Figure 21). Here a safe rewrite to the WDC register is
possible directly after this event has been detected (the time for event processing plus the
duration of the corresponding SPI frame are far longer than the Wake-up Watchdog to
Window Watchdog state transition).
When the timer expiration cannot be known while updating the WDC register, two strategies
are possible to bypass this behaviour:
1.
Disable the Window Watchdog function as described in section 4.5, in the Watchdog
control register to avoid a false Window Watchdog failure. The potential impact on a
safe application supervision has to be considered.
2.
Access the internal state of the Wake-up Watchdog to identify a safe window for a WDC
rewrite (see Figure 22):
the internal state of the Wake-up Watchdog prescaler can be accessed via NINT after
setting the bit D6, ‘CG0’ of the RCADJ register.
To avoid that other active interrupt sources pull NINT low they have to be masked by
clearing the global interrupt mask register GIEN.
An expiration of the Wake-up Watchdog can only occur with the rising edge of the
rectangular waveform now visible on NINT, so that a safe rewrite of the WDC register can
take place at any time while NINT is high or directly after the falling edge. After WDC rewrite
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Control and status registers
the bit D6, ‘CG0’ in RCADJ can be cleared again and the original GIEN value has to be
restored.
Figure 22. Valid timing windows for WDC register rewrite.
2.5ms
2.5ms
NINT
(WDC prescaler
after setting CG0
and clearing GIEN)
critical window for
WDC rewrite (< 15us)
critical window for
WDC rewrite (< 15us)
valid WDC register rewrite
4.6
ADR5: GIEN global interrupt enable register
Figure 23. ADR5: GIEN global interrupt enable register
D7
ISET
D0
IRES
EUV
EOVT
EEW
ECW
EWW
EIFW
Enable Identifier
based wakeup / Interrupt
Enable Interrupt
upon CAN error
detection
Enable Wakeup,/ Interrupt
via Watchdog
Enable CAN
wakeup / Interrupt
Enable Interrupt
upon CAN error
recovery
Enable
Interrupt
upon VS / VREG
Undervoltage
Enable Wakeup / Interrupt
via edge on WAKE
Enable Interrupt
upon Overtemp.
Warning
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Control and status registers
4.7
L4969UR-E, L4969URD-E
ADR6: IFR interrupt flag register
Figure 24. ADR6: IFR interrupt flag register
D11
D0
ESPI
ISET
IRES
CAN Linefailure
detected (ISET)
removed (IRES)
UV23 UVVS OVT3 OVT2 OVT1
VS < 7.2V
detected
WKC
WKW
WKIF
Signal edge
on WAKE
detected
V2 or V3
Undervoltage
Overtemperature
Warning level reached
OVT1 : T(V1) > 140degC
OVT2 : T(V2) > 140degC
OVT3 : T(V3) > 140degC
CRC- / Format
Error or SCLKTimeout detected
by SPI (non maskable)
WKE
Wakeup condition
via CAN detected
Watchdog timeout
detected
Identifier passed
CAN ID-Filter
Reserved bit (‘RES’) has to be written as ‘0’.
Except ESPI all bits in this register are maskable in GIEN. Any masked bit will force NINT
low until the register content is reset (either explicitly or by SPI ‘clear register).
4.8
ADR7: CTSR CAN transceiver status register
Figure 25. ADR7: CTSR CAN transceiver status register
D11
RES
D0
RES
RES
GSH
EX
EVIII
CANH < -1V
at falling edge TX
TX permanent
dominant detected
(TXD = ‘0’, t > 1.3ms)
EVII
EVI
EIV
CANL short
circuit to VS
detected
(CANL > 7.2V,
t > 32us)
CANH permanent
dominant detected
(CANH > 1.8V, t > 1.3ms)
CANL permanent
dominant detected
(CANL < 3.1V,
t > 1.3ms)
Short circuit CANH to CANL detected
(CANH - CANL > -3.25V, t > 1.3ms)
EIII
EII_IX
EI_V
Single wire
communication
detected
(edge count
difference > 3)
EI_V: CANH off
EII_IX: CANL off
CANH short
circuit to VS
detected
(CANH > 7.2V,
t > 32us)
Reserved bits (‘RES’) are always read as ‘0’
Note, that this register, except bit EX, is read only and only provides the unlatched
information on current bus errors. Bit EX is read only and provides the latched Error Flag.
This bit is reset by forcing the device into Normal Operation Mode (programming ACT and
TXEN in CTCR).
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4.9
Control and status registers
ADR 8 and 9: ID01, ID23 identifier filter sequence select
register
Figure 26. ADR 8 and 9: ID01, ID23 identifier filter sequence select register
SEGA
ID10
ID9
SEGB
ID8
SEGC
ID7
ID6
ID5
SEGD
ID4
ID3
SEGE
ID2
ID1
SEGF
ID0
RTR
SOF
4/2
Demux
4/2
Demux
00
00
A00
F00
A01
F01
A10
F10
11
A11
11
F11
PASS
99AT0028
SEGE
SEGD SEGF
Examples:
10 01 00
Identifiers to pass: 10 01 01
00 01 01
01 01 01
01 11 01
10 00 10
SEGA SEGC
SEGB
Valid sequence
for each segment
SEGA: A10, A00
SEGB: B01
SEGC: C01, C00
SEGD: D10, D01
SEGE: E11, E01, E00
SEGF: F10, F01
ID bits to be set
0101
0010 ID01: 0011 0010 0101
0011
0110
1011 ID01: 0110 1011 0110
0011
Identifier of CAN Frame can be divided up into 6 segments numbered from ‘A’ to ‘F’.
For each segment a filter register is implemented, enabling different pass functions on every
two bit wide block.
Segments A through C (ID01) are located at ADR 8 with MSB ‘C11’
Segments D through F (ID23) are located at ADR 9 with MSB ‘F11’
Note, that clearing a complete segment disables the whole filter.
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Control and status registers
4.10
L4969UR-E, L4969URD-E
ADR 10: BTL identifier filter bittimelogic control register
Figure 27. ADR 10: BTL identifier filter bittimelogic control register
The total bitlength equals the sum of 1 + PSEG1 + PSEG2 in units of s.
The location of the sampling point is determined by the length of PSEG1.
At the start of frame (initial recessive to dominant edge) the bitlength counter is reset.
Upon every signal edge the counter will be lengthened or shortened according to location of
the transition within the programmed boundaries of PSEG1 or PSEG2. If the edge lies within
PSEG1 additional cycles are inserted in order to shift the sampling point to a safe location
after the settling of the input signal. If the signal transition is located within PSEG2, this
segment will be shortened accordingly with the goal of the next edge to lie at the beginning
of PSEG1.
The amount of cycles one segment is lengthened or shortened is determined by the type of
edge (rec  dom or dom  rec) and the programming of TD: The re synchronization jump
width will be either set to ‘1’ (dom  rec edge) or to 1 + TD (rec  dom edge).
Note, that the length of one time quanta depends on the offset of the on chip RC-oscillator
and therefore on the accuracy of calibration (see register RCADJ (ADR 3) for details on
frequency correction).
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4.11
Control and status registers
ADR 15: SYS system status register
Figure 28. ADR 15: SYS system status register
D7
NCRC
D0
STAT
WNDF
STF
OTF
UCF
WAKE
NPOR
Cold Start
after low VS
CRC-Checking
disabled
Reserved
status flag
(test only)
Warm start
after failure of
Window watchdog
Warm start
after V1
Overtemp failure
Warm start
after < 7 missing
Ack during Startup
Warm start
after leaving
prog. Sleep mode
Warm start
after 7 missing
Ack during Startup
The lower 6 bit of this register can be used to analyze the reason of startup (after NRESET
low). This information is valid until the first Watchdog-Acknowledge, and will then be
reinitialized to 000001.
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Interrupt management
5
L4969UR-E, L4969URD-E
Interrupt management
Figure 29. Interrupt management
IFR
D11
ESPI ISET
IRES
UV23
UVVS
ISET
OVT3
D0
OVT2 OVT1 WKE
WKC
WKW WKIF
EEW
ECW
EWW EIFW
IRES EUV
D7
EOVT
GIEN
D0
NINT
All Interrupt flags (in IFR) except ESPI can be masked in the global interrupt enable register
(GIEN).
An Interrupt will be signalled by NINT going low until either the corresponding mask or the
flag itself will be reset by the application software. An autoreset function is available for IFR,
allowing to remove all interrupt flags after reading their state (see SPI).
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6
Remarks for application
Remarks for application
Figure 30. General circuit connection diagram
CAN IF
Note:
C* ceramic C close to pin recommended for EMI
Doc ID 022587 Rev 2
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Package information
L4969UR-E, L4969URD-E
7
Package information
7.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.2
SO-20 package information
Figure 31. SO-20 package dimensions
("1($'5
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Table 19.
Package information
SO-20 mechanical data
Millimeters
Symbol
Min
Max
A
2.35
2.65
A1
0.10
0.30
B
0.33
0.51
C
0.23
0.32
D
12.60
13.00
E
7.40
7.60
e
1.27
H
10.0
10.65
h
0.25
0.75
L
0.40
1.27
k
0°
8°
ddd
7.3
Typ
0.10
PowerSO-20 package information
Figure 32. PowerSO-20 package dimensions
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Package information
L4969UR-E, L4969URD-E
Table 20.
PowerSO-20 mechanical data
Millimeters
Symbol
Min
Typ
A
a1
3.6
0.1
0.3
a2
3.3
a3
0
0.1
b
0.4
0.53
c
0.23
0.32
D
15.8
16
D1
9.4
9.8
E
13.9
14.5
e
1.27
e3
11.43
E1
10.9
11.1
E2
2.9
E3
5.8
6.2
G
0
0.1
H
15.5
15.9
h
L
1.1
0.8
N
1.1
8°
S
8°
T
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Max
10
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8
Revision history
Revision history
Table 21.
Document revision history
Date
Revision
Changes
16-Dec-2011
1
Initial release.
19-Sep-2013
2
Updated Disclaimer.
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L4969UR-E, L4969URD-E
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