AN2683 Application note Compact dual output point of load converter based on the PM6680 step-down controller Introduction This application note demonstrates the performance of the PM6680 dual step-down controller by implementing a two output point of load converter in a small printed circuit board footprint. Utilizing constant on-time architecture and featuring a no-audio skip mode of operation, a common bus voltage that ranges between 10 to 16 VDC is converted to 1.0 VDC at 10.5 amps and 1.8 VDC at 2.5 amps for a total output power level of 15 watts. The unique no-audio skip feature significantly improves efficiency at light load. Using surface mount components on both the top and bottom of the circuit board and featuring ceramic output capacitors, the area needed for the converter measures only 1.0 by 1.25 inches (25.4 by 37.75 mm). The method for component value dimensioning is described along with the schematic and construction details. Typical efficiencies and functional test data are also presented. Figure 1. April 2008 PM6680 - top and bottom view Rev 1 1/38 www.st.com Contents AN2683 Contents 1 Main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Output ripple voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 Output overload/short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 Functional testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1 Input/output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 Ripple/noise voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 Load transient overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4 Output current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 Output short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.6 Input under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2/38 AN2683 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. PM6680 - top and bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Circuit board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Components of virtual ESR network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Top layer component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Top layer copper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Inner layer 1 showing additional power traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power ground layer (inner layer 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Signal ground layer (inner layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Bottom layer components placement (mirrored). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bottom layer copper (mirrored) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Inner layer 4 (mirrored) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Efficiency vs. load current in PWM mode (1.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Efficiency vs. load current in NA-skip mode (1.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Efficiency vs. load current in PWM mode (1.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Efficiency vs. load current in NA-skip mode (1.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 VDC output - 100% to 50% load change (20µs/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 VDC output - 50% to 100% load change (20µs/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 VDC output - 20% to 80% step load change (50µs/div). . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 VDC output - 100% to 50% load change (20µs/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 VDC output - 50% to 100% load change (20µs/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 VDC output - 20% to 80% step load change (50µs/div). . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3/38 List of tables AN2683 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. 4/38 Input voltage range 10 - 16 VDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.0 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.8 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.0 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.8 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.0 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.8 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.0 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.8 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.0 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.8 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 AN2683 Main characteristics 1 Main characteristics 1.1 Input voltage range Table 1. Input voltage range 10 - 16 VDC Output Nominal voltage VDC Max. current amp Regulation %(1) 1 1.8 2.5 0.44 2 1.0 10.5 2.6 1. Regulation over entire line and load range 1.2 1.3 1.4 Output ripple voltage ● Output 1: 45 mV p-p at maximum output current ● Output 2: 30 mV p-p at maximum output current Switching frequency ● Output 1: 1 - 300 kHz ● Output 2: 2 - 400 kHz Output overload/short circuit ● Output 1: nominal trip level 3.37 A (135%) ● Output 2: nominal trip level 13.65 A (130%) Protection is latched. Power must be cycled to reset. 5/38 Circuit description 2 AN2683 Circuit description The PM6680 contains all the control circuitry needed to implement two independent stepdown synchronous buck regulators using the constant on-time method. The constant ontime method, an improved variant of hysteretic control, provides superior transient response to changes of input voltage and load levels. One of the big advantages of this control method is that it can provide this quick response without the use of an error amplifier which in turn eliminates the need for frequency compensation. As shown in the photographs (Figure 1) all the parts used are surface mount type including the inductors. The circuit board is a multiple layer type consisting of six layers. The top two layers are power routing, the middle two are ground layers split as power and signal, and the bottom two are signal routing layers. In this design, in order to have a low inductor value for the higher current 10.5 A output side, the PM6680 runs in its intermediate range with output one running at 300 kHz and output two running at 400 kHz. So as a consequence the 2.5 A output will run at 300 kHz. With the switching frequencies established the dimensions of the other components can be defined. 6/38 Vout2 10.0k R14 R13 1.10k QC P3 C20 QC P4 C15 - C9 1 - 16.0 VDC C19 - 1.0 VDC @ 10.5 A 1 2 1 2 L1 2 MLC1550 0.7uH 1.8nF R8 5.11k QC P2 1 D3 Open R7 26.1k 1 R11 1.91k 2 Q2 STS25NH3LL 2 330pF C11 2 7 1 3 6 8 4 1 5 8 2 3 7 4 6 C12 22pF C7 10 uF 5 STS12NH3LL Q1 C6 10 uF C22 4.7uF 1 750R R5 C21 1uF C5 4.7uF 2 1 2 27 7 16 2 8 1 14 12 13 11 10 C4 0.22uF Pgood2 FB2 SGnd2 Comp2 Out2 SGnd1 PGnd Csense2 Lgate2 Phase2 Hgate2 R2 C2 10R0 0.1uF C3 0.1uF R4 3R92 1/4W 1% 1 2 R3 47R5 1% U1 PM6680 C18 0.1uF 1 2 Vin 10.2 K A 1/8W K2 P1 6 nc 19 Vin 9 Boot2 Hgate1 Shdn FB1 Pgood1 Comp1 Out1 V5SW Csense1 Lgate1 Phase1 5 28 26 30 29 17 20 15 21 22 R1 10R0 D1 C17 100pF BAT54A 1 1 R6 750R C1 0.1uF R18 30.0k R17 110k 1 2 1 2 QC 24 Fsel 3 K1 Vcc A LD05 23 Boot1 31 Skip 2 4 2 1 C8 10 uF 7 8 3 18 Vref 32 Q3 C14 22pF 5 6 STS8DNF3LL K A 2 En2 4 En1 25 D2 Open 1 C13 330pF R9 57.6k 1 1.8nF C10 R10 3.74k 2.55k R12 MSS1038 2.5 uH L2 2 1 2 2 P6 QC C16 47uF 1 2 1 2 QC R16 10.0k R15 10.0k P5 Vout 1 - 1.8 VDC @ 2.5 A Figure 2. + AN2683 Circuit description Circuit board schematic 100uF 47uF 100uF 7/38 Circuit description AN2683 As a starting point for the value of the inductors we look at the full load current (Ifl) for each output and let the inductor ripple (Ir) current equal 20 to 30 percent of it. For this design a value of 30 percent is used. Ir = Ifl * 0.3 for ● Output 1: Ir = 0.75 A ● Output 2: Ir = 3.15 A Then the values of the inductors are calculated using the formula: Equation 1: V in – V out V out L = ------------------------- ⋅ ----------f sw ⋅ I r V in where Vin is the nominal input voltage, Vout the output voltage and fsw the switching frequency. So for input 1: Equation 2 12 – 1.8 1.8 L = ---------------------------------------- ⋅ -------- = 6.8µH 300kHz ⋅ 0.75 12 and for output 2: Equation 3 12 – 1 12 L = ---------------------------------------- ⋅ ------ = 0.7µH 400kHz ⋅ 3.15 1 The output filter capacitors are roughly approximated so that the change in output voltage (∆Vout) during a positive load transient (load is reduced) is minimized. For this design an output voltage change of two to three percent of the total output voltage is considered acceptable. The formula used is: Equation 4 L ⋅ ( I fl ) 2 C > ---------------------------------------------------------------2 ⋅ ( V in – V out ) ⋅ Λ V out 8/38 AN2683 Circuit description For output 1 a ∆Vout of 2.5% of 1.8 VDC or 45 mV is used, thus: Equation 5 6.8µH ⋅ ( 2.5 ) 2 46.2µF > ---------------------------------------------------------2 ⋅ ( 12 – 1.8 ) ⋅ 0.045 This is a nonstandard value so a 47 µF is used. For output 2 a ∆Vout of 2% of 1.0 VDC or 20 mV is used: Equation 6 0.7µH ⋅ ( 10.5 ) 2 175µF > ---------------------------------------------------------2 ⋅ ( 12 – 1.0 ) ⋅ 0.020 As the formula indicates the capacitor value should be greater than that calculated. Even though the board area is small, this section allows the use of ceramic capacitors that are comprised of two 100 µF and one 47 µF all in parallel and which still fit in the required footprint. With these values of capacitors the ripple voltage can be checked. This is dominated by the equivalent series resistance (ESR) of the capacitors. The ESR must be equal or less than the value calculated by: Equation 7: Vr ESR ≤----Ir where Vr is the output ripple voltage and Ir is the inductor ripple current. The ESR for the capacitors is given in their datasheets at the frequency they are used at as shown in the graphs. The value is basically the same at both 300 and 400 kHz. For the 47 µF the ESR is 2 mΩ and for the 100 µF it is 1.5 mΩ. With these values we can calculate the ripple voltage Vr by: Equation 8: V r = I r ⋅ ESR 9/38 Circuit description AN2683 for output 1: Equation 9 0.75A ⋅ 2mΩ= 1.5mV for output 2: Equation 10 3.15A ⋅ 545µΩ= 1.9mV These values conform to the specification. They are higher in a practical circuit because of parasitic inductance and loop resistance. Good circuit board layout techniques are essential. Additionally, because of the constant on-time control, the system regulates the output voltage by the valley value of the ripple voltage. A minimum amount of ripple voltage of 30 mV should be on the comp pin to accomplish this. Since the calculated ripple voltage is much lower than this, an additional circuit called the virtual ESR network is incorporated to provide the additional voltage. Before addressing this design, the current limit resistor values will be established. In this design the RDS(on) of the lower MOSFETS is used to implement the current limit. For output 1 with its relatively low output current the MOSFET chosen was the STS8DNF3LL with a nominal RDS(on) of 18 mΩ. This particular part is a dual, that is two MOSFETs are contained in the same SO-8 package realizing further circuit board space savings. The current limit is a valley type that operates during the conduction of the low side MOSFET. A 100 µA internal current generator connected to the Csense pin along with a resistor establishes a voltage to which the voltage generated by the RDS(on) is compared. If the RDS(on) voltage is greater, then the voltage at the Csense pin the generation of a new conduction cycle is inhibited. The value of Rcsense is determined by: Equation 11: R DS ( on ) ⋅ I valley Rc sense = ----------------------------------------100µA The 18 mΩ value for RDS(on) is a nominal 25 °C number. As current is switched through the device and the ambient is raised, the RDS(on) increases. An increase of approximately 140% is used. Targeting the maximum output current (Ioutmax) at 3.375 A and having a Ir of 0.750 A the valley current value is: 10/38 AN2683 Circuit description Equation 12 I I valley = I out ( max ) – ---r 2 then: Equation 13 0.750 3.375A – --------------- = 3.0A 2 Rcsense is then: Equation 14 25mΩ ⋅ 3.0A ------------------------------------ = 750Ω 100µA For output 2 the current levels are substantially higher than output 1 and two discrete MOSFETS must be used. With a nominal input voltage of 12 volts and a one volt output the low side MOSFET is conducting over 90 percent of the time. This means that the RDS(on) of the low side MOSFET must be as low as possible. For this design the STS25NH3LL MOSFET with a nominal 3.2 mΩ on resistance is used. Because of the high current and duty cycle an RDS(on) multiplier of 200% for the Rcsense calculation is used. Again targeting the output 2 maximum current at 13.65 A the valley current is: Equation 15 3.15A 13.65A – ---------------- = 12.075A 2 Rcsense for output 2 then is: Equation 16 6.4mΩ ⋅ 12.75A------------------------------------------= 773Ω 100µA 11/38 Circuit description AN2683 With the maximum output currents established attention can be redirected at designing the virtual ESR network. As mentioned earlier, the ripple voltage should be greater than 30 mV and range between 30 to 50 mV. To derive the necessary minimum value of the virtual ESR (VESR) to produce the ripple voltage the following formula is used: Equation 17 0.05V VESR ( min ) = ⎛ ----------------⎞ – ESR cout ⎝ Ir ⎠ for output 1: Equation 18 ⎛ 0.05V ----------------⎞ ⎝ 0.75A⎠ – 2mΩ= 64.6mΩ for output 2: Equation 19 ⎛ 0.05V ----------------⎞ ⎝ 3.15A⎠ – 0.545mΩ= 15.3mΩ The total ESR (ESRtot) is the sum of the virtual ESR (VESR) and the ESR (ESRcout) of the output capacitor. for output 1: Equation 20 64.6mΩ + 2mΩ= 66.6mΩ for output 2: Equation 21 15.3mΩ + 0.545mΩ= 15.8mΩ 12/38 AN2683 Circuit description The first component to be dimensioned in the virtual ESR network is Cint as shown in Figure 3 below. Before this can be done the corner frequency (fz) of the output capacitor must be determined by: Equation 22 1 f Z = -----------------------------------2πC out ESR tot Figure 3. Components of virtual ESR network for output 1: Equation 23 1 --------------------------------------------------= 50.56kHz 2π ⋅ 47µF ⋅ 67mΩ 13/38 Circuit description AN2683 for output 2: Equation 24 1 -------------------------------------------------------------- = 41.46kHz 2π ⋅ 247µF ⋅ 15.54mΩ With fz established the stability of the system needs to be verified. The system is stable if the switching frequency (fsw) is greater than 4 times the corner frequency (fz) of Cout; fsw > fz x 4. for output 1: Equation 25 50.56kHz ⋅ 4 = 202.2kHz Equation 26 202.2kHz < 300kHz OK for output 2: Equation 27 41.46kHz ⋅ 4 = 165.8kHz Equation 28 165.8kHz < 400kHz OK The value of Cint is actually computed three different ways. The maximum value that results from the computations is the value that should be used. In the formulas for calculating Cint the following constants are used: gm = 50 µs (the transconductance of the integrator amplifier); k = 4; Vr = 0.9 V (internal reference voltage). 14/38 AN2683 Circuit description Equation 29 Vr gm C int > -------------------------------- ⋅ ----------V out fsw 2π⎛⎝ --------- – f z⎞⎠ k or Vr gm - -------------------------⋅ 2π ⋅ f z V out or 6µA ⋅ C out -------------------------------I out ( max ) I r ---------------------- + --4 2 for output 1: Equation 30 50µs ------------------------------------------------------------------------ ⋅ 0.9V ------------ = 162.8pF 1.8V 300kHz ⎛ ⎞ 2π ⋅ --------------------- – 50.56kHz ⎝ ⎠ 4 or Equation 31 50µs --------------------------------------- ⋅ 0.9V ------------ = 78.7pF 2π ⋅ 50.56kHz 1.8V or Equation 32 6µA ⋅ 47µF - = 231.3pF ----------------------------------------3.375A ------------------- + 0.75A ---------------4 2 for output 2 Equation 33 50µs ------------------------------------------------------------------------- ⋅ 0.9V ------------ = 122.4pF 1.0V 400kHz ⎛ ⎞ 2π ⋅ --------------------- – 41.46kHz ⎝ ⎠ 4 or 15/38 Circuit description AN2683 Equation 34 50µs --------------------------------------- ⋅ 0.9V ------------ = 172.8pF 2π ⋅ 41.46kHz 1.0V or Equation 35 6µA ⋅ 247µF - = 297.1pF ----------------------------------------13.65A ------------------- + 3.15A ---------------4 2 Standard values must be used. In both cases a value rounded up to 330 pF will be used for Cint. The next part of the network to be calculated is the capacitor Cfilt. The formula for this part is straightforward which is: Equation 36 C int ⋅ ( 1 – q ) C filt = --------------------------------q Where q is an attenuation factor equal to 0.95. Since Cint is the same for both outputs Cfilt is the same for both outputs: Equation 37 330pF ⋅ ( 1 – 0.95 ) = 17.3pF -------------------------------------------------0.95 A standard value of 22 pF is used. Building on the previous calculations the value of Rint is the next part to be established. The formula for Rint is given below: Equation 38 1 R int = -----------------------------------------------------------------------C int ⋅ C filt 2π ⋅ 10 ⋅ fsw ⋅ -------------------------C int + C filt 16/38 AN2683 Circuit description for output 1: Equation 39 1 R int = ------------------------------------------------------------------------------------------------ = 2570Ω 330pF ⋅ 22pF 2π ⋅ 10 ⋅ 300kHz ⋅ --------------------------------------330pF + 22pF using standard value 2.55 kΩ for output 2: Equation 40 1 R int = ------------------------------------------------------------------------------------------------ = 1929Ω 330pF ⋅ 22pF 2π ⋅ 10 ⋅ 400kHz ⋅ --------------------------------------330pF + 22pF using standard value 1.91 kΩ Then, the value of the C of the virtual ESR network is calculated. It is simply: Equation 41 C = C int ⋅ 5 Since Cint is the same for both outputs: Equation 42 C = 330pF ⋅ 5 = 1650pF Use standard value 1.8 nF. Next, the R value of the network is established. This is determined by the formula: Equation 43 L R = ----------------------------ESR tot ⋅ C 17/38 Circuit description AN2683 for output 1: Equation 44 6.8µH -------------------------------------- = 58.12KΩ 65mΩ ⋅ 1.8nF for output 2: Equation 45 0.7µH -------------------------------------- = 25.92KΩ 15mΩ ⋅ 1.8nF The standard value of 57.6 KΩ can be used for output 1 and 26.1 KΩ for output 2. Finally the last component of the virtual ESR network R1 is computed with the formula: Equation 46 1 R ⋅ ⎛ ------------⎞ ⎝ Cπf z⎠ R1 = ----------------------------1 R – -----------Cπf z for output 1: Equation 47 1 57.6KΩ ⋅ ⎛ ----------------------------------------------⎞ ⎝ 1.8nFπ50.56kHz⎠ ------------------------------------------------------------------------------- = 3723Ω 1 57.6KΩ – --------------------------------------------1.8nFπ50.56kHz for output 2: Equation 48 1 26.1KΩ ⋅ ⎛ ----------------------------------------------⎞ ⎝ 1.8nFπ41.46kHz⎠ ------------------------------------------------------------------------------- = 5098Ω 1 26.1KΩ – --------------------------------------------1.8nFπ41.46kHz The standard value of 3.74 KΩ can be used for output 1 and 5.11 KΩ for output 2. With the design of the virtual ESR complete the only other output components to be determined are the resistor dividers that connect to the feedback pins FB1 and FB2. With an internal reference voltage (Vr) of 0.9 volts the determination of the values is straightforward by: 18/38 AN2683 Circuit description Equation 49 V out – V r R2 = --------------------Vr -------R1 where R1 is the resistor connecting the feedback pin to ground (resistors R14 and R16 in the schematic) and R2 is the resistor connecting the output to the feedback pin (resistors R13 and R15 in the schematic). The value for R1 is chosen as 10.0 KΩ for both outputs. The value for R2 is then: for output 1: Equation 50 1.8V – 0.9V R2 = ------------------------------- = 10KΩ 0.9V-------------10KΩ for output 2: Equation 51 1.0V – 0.9V R2 = ------------------------------- = 1.11KΩ 0.9V-------------10KΩ Use standard values 10.0 KΩ ohm for R15 and 1.10 KΩ ohm for R13. With the output component values determined it is important not to overlook the dimensioning of input components critical to proper operation. These are the input capacitors that provide the high frequency input currents needed by the converters. Locate these capacitors as close as possible to the drain of the upper MOSFET and also make sure to minimize the inductance to the other power components on the power ground plane. The ripple current (Ir) ratings should meet or exceed the value as computed below: Equation 52 Ir = 2 2 D 1 ⋅ I out1 ⋅ ( 1 – D 1 ) + D 2 ⋅ I out2 ⋅ ( 1 – D 2 ) where D is the duty cycle of the converter and is given by: 19/38 Circuit description AN2683 Equation 53 V out D = ---------V in and Iout is the maximum output current of the converter. For output 1 D1 is: Equation 54 1.8V ------------ = 0.15 12V For output 2 D2 is: Equation 55 1.0V ------------ = 0.083 12V So then we have: Equation 56 Ir = 20/38 2 2 0.15 ⋅ 3.375 ⋅ ( 1 – 0.15 ) + 0.083 ⋅ 13.65 ⋅ ( 1 – 0.083 ) = 3.95A AN2683 3 Construction Construction With the components dimensioned the construction of the circuit board can be considered. With this type of high frequency converter separate power and signal grounds are a must. Additionally, the small board area necessitated component placement on both sides and the use of additional layers for routing the signal interconnects and providing lower conductor resistance in the heavy current paths. In Figure 4. below the top layer component placement is shown. The top layer components are comprised of the power handling ones such as the MOSFETS and inductors. Along with the power component placement is Figure 5 that shows the top copper power traces. The first inner layer shown in Figure 6 is a layer that has redundant power traces to lower resistance in the high current paths. The power ground and signal ground layers are shown in Figure 7 and 8 respectively. Care must be taken that they connect at only one point close to pin 14 of the PM6680. The component placement for the bottom layer is shown in Figure 9, these are the parts that do the signal conditioning and connect to the PM6680 controller. Of special note on the bottom layer copper shown in Figure 10, is the square copper island under U1 (the PM6680). This island connects to the thermal sink contact that is on the bottom of the package. A requirement for proper operation is that this pad be connected to signal ground. As shown in Figure 11, which is the fourth inner layer used for additional signal routing, a matrix of nine vias are used to make the connection to the signal ground layer. The board uses 1-ounce copper on all layers. While not necessary for the signal traces, keeping the copper weight even on all the layers reduces the chances of the board warping during the manufacturing process. Figure 4. Top layer component placement 21/38 Construction 22/38 AN2683 Figure 5. Top layer copper Figure 6. Inner layer 1 showing additional power traces AN2683 Construction Figure 7. Power ground layer (inner layer 2) Figure 8. Signal ground layer (inner layer 3) 23/38 Construction Figure 9. AN2683 Bottom layer components placement (mirrored) Figure 10. Bottom layer copper (mirrored) 24/38 AN2683 Construction Figure 11. Inner layer 4 (mirrored) 25/38 Functional testing 4 AN2683 Functional testing Using the component values calculated the demonstration board's efficiency was evaluated. Each converter was tested individually with the idle converter disabled by grounding its enable pin so that the power consumed by the idle converter's MOSFET driver section would not be included in the input power calculation. The efficiency of each section was measured in two different modes of operation, normal PWM and no-audible skip mode. In all cases the input voltage was set to 12.0 VDC. Figure 12. Efficiency vs. load current in PWM mode (1.0 V) % Efficiency 1.0V Eff vs Load Current in PWM mode 100 90 80 70 60 50 40 30 20 10 0 Eff vs Load I 0 1 2 3 4 5 6 7 8 9 10 11 Load Current Figure 13. Efficiency vs. load current in NA-skip mode (1.0 V) % Efficiency 1.0V Eff vs Load Current in NA-Skip mode 100 90 80 70 60 50 40 30 20 10 0 Eff vs Load I 0 1 2 3 4 5 6 7 Load Current 26/38 8 9 10 11 AN2683 Functional testing As can be seen at significant load current the efficiency for the 1.0 V output averages in the lower eighty percent area. Additionally, the graph for no-audible skip mode shows the advantage of running in this mode. By using the current zero-crossing detector the condition of negative current that occurs at light load is sensed. The control circuit then keeps the average current equal to the load current by skipping cycles. The result is higher efficiency at light load. As the load is increased and the inductor current does not go to zero, normal PWM operation is resumed. Figure 14. Efficiency vs. load current in PWM mode (1.8 V) % Efficiency 1.8V Eff vs Load Current in PWM mode 100 90 80 70 60 50 40 30 20 10 0 Eff vs Load I 0 1 2 3 Load Current Figure 15. Efficiency vs. load current in NA-skip mode (1.8 V) % Efficiency 1.8V Eff vs Load Current in NA-Skip mode 100 90 80 70 60 50 40 30 20 10 0 Eff vs Load I 0 1 2 3 Load Current 27/38 Functional testing AN2683 The graphs in Figure 14 and 15 show that the 1.8 V output has better efficiency than the 1.0 V output, in the high eighties at high current levels. Along with the efficiency measurements further functional testing was conducted as outlined in the following sections. 4.1 Input/output voltage The input voltage was swept from 10.2 to 16 VDC at the load levels indicated. The output voltage was recorded at each level and did not vary more than 1 mV over the entire input range. Input/output voltage at different load levels. Table 2. Table 3. 4.2 1.0 VDC output Load current Output voltage 50 mA 0.998 VDC 7.5 A 1.019 VDC 10.5 A 1.027 VDC 1.8 VDC output Load current Output voltage 50 mA 1.792 VDC 1.8 A 1.794 VDC 2.5 A 1.794 VDC Ripple/noise voltage The maximum peak to peak ripple voltage was measured at the load level indicated. Table 4. Table 5. 4.3 1.0 VDC output Load current Ripple voltage p-p 10.5 A 25 mV 1.8 VDC output Load current Ripple voltage p-p 2.5 A 20 mV Load transient overshoot The output load levels were varied in a stepwise fashion at the percentage and load levels indicated. The maximum change in output voltage was recorded in the following oscilloscope photographs. 28/38 AN2683 Functional testing Table 6. 1.0 VDC output Percent load change Current level change (A) 100 to 50% 5.25 to 10.5 50 to 100% 5.25 to 10.5 20 to 80% 2.0 to 8.5 Figure 16. VDC output - 100% to 50% load change (20µs/div) where: ● Top trace - L1 current 2 A/division ● Bottom trace - output voltage 50 mV/division 29/38 Functional testing Figure 17. VDC output - 50% to 100% load change (20µs/div) where: ● Top trace - L1 current 2 A/division ● Bottom trace - output voltage 50 mV/division Figure 18. VDC output - 20% to 80% step load change (50µs/div) 30/38 AN2683 AN2683 Functional testing where: ● Top trace - L1 current 2 A/division ● Bottom trace - output voltage 50 mV/division Table 7. 1.8 VDC output Percent load change Current level change (A) 100 to 50% 2.5 to 1.25 50 to 100% 1.25 to 2.5 20 to 80% 0.5 to 2 Figure 19. VDC output - 100% to 50% load change (20µs/div) where: ● Top trace - L1 current 0.5 A/division ● Bottom trace - output voltage 50 mV/division 31/38 Functional testing Figure 20. VDC output - 50% to 100% load change (20µs/div) where: ● Top trace - L1 current 0.5 A/division ● Bottom trace - output voltage 50 mV/division Figure 21. VDC output - 20% to 80% step load change (50µs/div) 32/38 AN2683 AN2683 Functional testing where: 4.4 ● Top trace - L1 current 0.5 A/division ● Bottom trace - output voltage 50 mV/division Output current limit Each output was loaded to its maximum rated load level. The load was increased in 10% increments of the maximum rated load until the overcurrent limiting functioned. The level was recorded. Table 8. 1.0 VDC output Percent of maximum load (A) 130% (13.65) Table 9. 1.8 VDC output Percent of maximum load (A) 130% (3.25) After the overcurrent limit functioned, the load level was adjusted back the maximum rated level and the input power was shut off and reapplied. The outputs resumed to normal operation. 4.5 Output short circuit Each output in turn was loaded to its maximum rated load level. A short was then applied to the output at which time the overcurrent protection functioned. The opposite output remained running. The short was then removed and the output remained latched off. The input power was removed and then reapplied. The output resumed normal function. With input power removed, each output in turn was shorted. Then input power was applied. The shorted output's current limiting function operated while the non-shorted output ran normally. The short was then removed and the input power was recycled. The output resumed normal function. 4.6 Input under voltage lockout With each output loaded to its nominal load level the input voltage was slowly increased from 0 to 6 VDC and the output voltages were recorded. The input voltage was then slowly increased from 6 to 8 VDC and the output voltages were recorded. The voltage at which the device turns on is adjusted by the voltage divider consisting of R17 and R18 connected to the SHDN pin(5). The typical turn-on threshold is 1.35 VDC and the device typically shuts down with 0.85 VDC on the pin. 33/38 Functional testing Table 10. Table 11. 34/38 AN2683 1.0 VDC output Voltage at Vin 6 VDC Voltage at Vin 8 VDC 0.0 1.017 1.8 VDC output Voltage at Vin 6 VDC Voltage at Vin 8 VDC 0.0 1.795 AN2683 Bill of material 5 Bill of material Table 12. Part list Part reference Value / type PCB footprint Manufacturer C1 0.1 µF 50 V X5R SM_0805 Any C2 0.1 µF 50 V X5R SM_0805 Any C3 0.1 µF 50 V X5R SM_0805 Any C4 0.22 µF 25 V X5R SM_0805 Any C5 4.7 µF 25 V X5R SM_1210 Any C6 10 µF 25 V X5R SM_1206 Any C7 10 µF 25 V X5R SM_1206 Any C8 10 µF 25 V X5R SM_1206 Any C9 1.8 nF 50 V X5R SM_0805 Any C10 1.8 nF 50 V X5R SM_0805 Any C11 330 pF 50 V NPO SM_0603 Any C12 22 pF 50 V NPO SM_0603 Any C13 330 pF 50 V NPO SM_0603 Any C14 22 pF 50 V NPO SM_0603 Any C15 100 µF 6.3 V X5R SM_1210 TDK or equivalent C3225X5ROJ107K C16 47 µF 6.3 V X5R SM_1206 TDK or equivalent C3216X5ROJ476K C17 100 pF 50 V NPO SM_0603 Any C18 0.1 µF 50 V X5R SM_0805 Any C19 100 µF 6.3 V X5R SM_1210 TDK or equivalent C3225X5ROJ107K C20 47 µF 6.3 V X5R SM_1206 TDK or equivalent C3216X5ROJ476K C21 4.7 µF 25 V X5R SM_1210 Any C22 1 µF 16 V X5R SM_0603 Any SOT-23 STMicroelectronics BAT54A D1 BAT54A dual Schottky P/N D2 Open DO-214AC D3 Open DO-214AC L1 0.7 µH 17 A Custom Coilcraft MLC1265-701MLB L2 7.0 µH 4.35 A Custom Coilcraft MSS1038-702NLB Q1 STS12NH3LL MOSFET SO-8 STMicroelectronics STS12NH3LL Q2 STS25NH3LL MOSFET SO-8 STMicroelectronics STS25NH3LL 35/38 Bill of material Table 12. AN2683 Part list (continued) Part reference Value / type PCB footprint Manufacturer P/N Q3 STS8DNF3LL dual MOSFET SO-8 STMicroelectronics STS8DNF3LL R1 10R0 1% SM_0805 Any R2 10R0 1% SM_0805 Any R3 47R5 1% SM_0805 Any R4 3R92 1% SM_1206 Any R5 750R 1% SM_0805 Any R6 750R 1% SM_0805 Any R7 21.6k 1% SM_0805 Any R8 5.11k 1% SM_0805 Any R9 57.6k 1% SM_0805 Any R10 3.74k 1% SM_0805 Any R11 1.91k 1% SM_0805 Any R12 2.55k 1% SM_0805 Any R13 1.10k 1% SM_0603 Any R14 10.0k 1% SM_0603 Any R15 10.0k 1% SM_0603 Any R16 10.0k 1% SM_0603 Any R17 110k 1% SM_0603 Any R18 30.0k 1% SM_0603 Any U1 PM6680 Dual Dc-Dc Controller VFQFPN-32 5x5 STMicroelectronics 36/38 PM6680 AN2683 6 Revision history Revision history Table 13. Document revision history Date Revision 15-Apr-2008 1 Changes Initial release. 37/38 AN2683 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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