MOTOROLA MC54HCXXXJ Highâ performance siliconâ gate cmo Datasheet

SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC54/74HC160 and HC162 are identical in pinout to the LS160 and
LS162, respectively. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC160 and HC162 are programmable BCD counters with asynchronous and synchronous Reset inputs, respectively.
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
•
•
•
•
•
•
1
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 234 FETs or 58.5 Equivalent Gates
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
LOGIC DIAGRAM
ORDERING INFORMATION
P0
PRESENT
DATA
INPUTS
P1
P2
P3
CLOCK
3
14
4
13
5
12
6
11
2
15
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Q0
Q1
Q2
BCD OR
BINARY
OUTPUTS
Q3
PIN ASSIGNMENT
RESET
1
16
CLOCK
2
15
P0
3
14
VCC
RIPPLE
CARRY OUT
Q0
P1
4
13
Q1
P2
5
12
Q2
P3
6
11
Q3
ENABLE P
7
10
ENABLE T
GND
8
9
RIPPLE
CARRY
OUT
RESET
LOAD
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COUNT
ENABLES
ENABLE P
ENABLE T
Device
Count
Mode
PIN 16 = VCC
PIN 8 = GND
BCD
Asynchronous
HC162
BCD
Synchronous
LOAD
FUNCTION TABLE
Inputs
Reset Mode
HC160
Ceramic
Plastic
SOIC
Clock
Output
Reset*
Load
Enable P
Enable T
Q
L
H
H
H
H
X
L
H
H
H
X
X
H
L
X
X
X
H
X
L
Reset
Load Preset Data
Count
No Count
No Count
* HC162 only. HC160 is an Asynchronous Reset Device
H = high level
L = low level
X = don’t care
10/95
 Motorola, Inc. 1995
1
REV 6
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MC54/74HC160 MC54/74HC162
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
6.0
± 0.1
± 1.0
± 1.0
VOH
Vin = VIH or VIL |Iout|
|Iout|
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL |Iout|
|Iout|
Iin
Maximum Input Leakage Current
4.0 mA
5.2 mA
Vin = VCC or GND
4.0 mA
5.2 mA
V
µA
Vin = VCC or GND
6.0
8
80
160
µA
Iout = 0 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ICC
MOTOROLA
Maximum Quiescent Supply
Current (per Package)
2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC54/74HC160 MC54/74HC162
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)*
(Figures 1 and 7)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH
Maximum Propagation Delay, Clock to Q
(Figures 1 and 7)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
Symbol
Parameter
tPHL
tPHL
Maximum Propagation Delay, Reset to Q (HC160 Only)
(Figures 2 and 7)
2.0
4.5
6.0
210
42
36
265
53
45
315
63
54
ns
tPLH
Maximum Propagation Delay, Enable T to Ripple Carry Out
(Figures 3 and 7)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
2.0
4.5
6.0
195
39
33
245
49
42
295
59
50
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
2.0
4.5
6.0
215
43
37
270
54
46
325
65
55
tPHL
tPLH
Maximum Propagation Delay, Clock to Ripple Carry Out
(Figures 1 and 7)
tPHL
ns
tPHL
Maximum Propagation Delay, Reset to Ripple Carry Out
(HC160 Only)
(Figures 2 and 7)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 7)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Cin
* Applies to noncascaded/nonsynchronously clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out
propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine f max. However,
if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the f max in the table above is applicable.
See Applications Information in this data sheet.
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
60
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
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MC54/74HC160 MC54/74HC162
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
tsu
Minimum Setup Time, Preset Data Inputs to Clock
(Figure 5)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tsu
Minimum Setup Time, Load to Clock
(Figure 5)
2.0
4.5
6.0
135
27
23
170
34
29
205
41
35
ns
tsu
Minimum Setup Time, Reset to Clock (HC162 only)
(Figure 4)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
tsu
Minimum Setup Time, Enable T or Enable P to Clock
(Figure 6)
2.0
4.5
6.0
200
40
34
250
50
43
300
60
51
ns
th
Minimum Hold Time, Clock to Preset Data Inputs
(Figure 5)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
th
Minimum Hold Time, Clock to Load
(Figure 5)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
th
Minimum Hold Time, Clock to Reset (HC162 only)
(Figure 4)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
th
Minimum Hold Time, Clock to Enable T or Enable P
(Figure 6)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
trec
Minimum Recovery Time, Reset Inactive to Clock (HC160 only)
(Figure 2)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
trec
Minimum Recovery Time, Load Inactive to Clock
(Figure 5)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Reset (HC160 only)
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
Symbol
tr, tf
Parameter
Unit
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC160 MC54/74HC162
CONTROL FUNCTIONS
FUNCTION DESCRIPTION
Resetting
The HC160/162 are programmable 4–bit synchronous
counters that feature parallel Load, synchronous or asynchronous Reset, a Carry Output for cascading, and count–
enable controls.
The HC160 and HC162 are BCD counters with asynchronous Reset, and synchronous Reset, respectively.
A low level on the Reset pin (pin 1) resets the internal flip–
flops and sets the outputs (Q0 through Q3) to a low level.
The HC160 resets asynchronously and the HC162 resets
with the rising edge of the Clock input (synchronous reset).
Loading
With the rising edge of the Clock, a low level on Load (pin
9) loads the data from the Preset Data Input pins (P0, P1, P2,
P3) into the internal flip–flops and onto the output pins, Q0
through Q3. The count function is disabled as long as Load is
low.
Although the HC160 and HC162 are BCD counters, they
may be programmed to any state. If they are loaded with a
state disallowed in BCD code, they will return to their normal
count sequence within two clock pulses (see the Output
State Diagram).
INPUTS
Clock (Pin 2)
The internal flip–flops toggle and the output count advances with the rising edge of the Clock input. In addition,
control functions, such as resetting (HC162) and loading
occur with the rising edge of the Clock input.
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
These are the data inputs for programmable counting.
Data on these pins may be synchronously loaded into the internal flip–flops and appear at the counter outputs. P0 (pin 3)
is the least–significant bit and P3 (pin 6) is the most–significant bit.
Count Enable/Disable
These devices have two count–enable control pins: Enable P (pin 7) and Enable T (pin 10). The devices count when
these two pins and the Load pin are high. The logic equation
is:
Count Enable = Enable P Enable T Load
OUTPUTS
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
The count is either enabled or disabled by the control inputs according to Table 1. In general, Enable P is a count–
enable control; Enable T is both a count–enable and a
Ripple–Carry Output control.
These are the counter outputs (BCD or binary). Q0 (pin 14)
is the least–significant bit and Q3 (pin 11) is the most–significant bit.
Table 1. Count Enable/Disable
Ripple Carry Out (Pin 15)
Control Inputs
When the counter is in its maximum state (1001 for the
BCD counters or 1111 for the binary counters), this output
goes high, providing an external look–ahead carry pulse that
may be used to enable successive cascaded counters. Ripple Carry Out remains high only during the maximum count
state. The logic equation for this output is:
Ripple Carry Out = Enable T Q0 Q1 Q2 Q3
for BCD counters HC160 and
HC162
Result at Outputs
Load
Enable P
Enable T
Q0 – Q3
Ripple Carry Out
H
H
H
Count
High when Q0 – Q3
are maximum*
L
H
H
No Count
X
L
H
No Count
High when Q0 – Q3
are maximum*
X
X
L
No Count
L
* Q0 through Q3 are maximum for the HC160 and HC162 when
Q3 Q2 Q1 Q0 = 1001.
OUTPUT STATE DIAGRAMS
HC160 and HC162 BCD Counters
0
2
3
4
15
5
14
6
13
7
12
High–Speed CMOS Logic Data
DL129 — Rev 6
1
11
10
5
9
8
MOTOROLA
MC54/74HC160 MC54/74HC162
SWITCHING WAVEFORMS
tr
90%
50%
10%
CLOCK
tf
tw
VCC
GND
GND
tPHL
tw
1/fmax
tPLH
tPHL
ANY
OUTPUT
VCC
50%
RESET
50%
ANY
OUTPUT
90%
50%
10%
trec
VCC
tTLH
50%
CLOCK
tTHL
GND
Figure 1.
Figure 2.
tr
tf
VCC
90%
50%
10%
tPLH
90%
50%
10%
ENABLE T
RIPPLE
CARRY
OUT
50%
RESET
GND
th
tsu
tPHL
VCC
50%
CLOCK
tTLH
GND
tTHL
Figure 3.
Figure 4. HC162 Only
VALID
INPUTS
P0, P1,
P2, P3
VCC
50%
GND
tsu
th
VALID
VCC
LOAD
50%
ENABLE T
OR
ENABLE P
GND
tsu
CLOCK
th
trec
VCC
50%
GND
tsu
th
VCC
VCC
CLOCK
50%
50%
GND
GND
Figure 5.
Figure 6.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and jig capacitance
Figure 7.
MOTOROLA
6
High–Speed CMOS Logic Data
DL129 — Rev 6
High–Speed CMOS Logic Data
DL129 — Rev 6
3
7
LOAD
CLOCK
RESET
ENABLE T
ENABLE P
P3
P2
3
2
1
10
7
6
5
P1 4
P0
LOAD
LOAD
C
C
R
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
VCC = PIN 16
GND = PIN 8
Q3
Q2
Q1
Q0
15 RIPPLE
CARRY
OUT
11
12
13
14
The flip–flops shown in the circuit diagrams are Toggle–Enable flip–flops. A Toggle–
Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data from
Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flip–flop. The logic level at the Pn input is then clocked to the Q output of the flip–flop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
output of the flip–flop low.
T3
R
C
C
LOAD
LOAD
P3
T2
R
C
C
LOAD
LOAD
P2
T1
R
C
C
LOAD
LOAD
P1
T0
R
C
C
LOAD
LOAD
P0
MC54HC160 • MC74HC160
BCD Counter with Asynchronous Reset
MC54/74HC160 MC54/74HC162
MOTOROLA
MC54/74HC160 MC54/74HC162
HC160, HC162 TIMING DIAGRAM
Sequence illustrated in waveforms:
1. Reset outputs to zero.
2. Preset to BCD seven.
3. Count to eight, nine, zero, one, two, and three.
4. Inhibit.
RESET (HC160)
(ASYNCHRONOUS)
RESET (HC162)
(SYNCHRONOUS)
LOAD
P0
PRESET
DATA
INPUTS
P1
P2
P3
CLOCK (HC160)
CLOCK (HC162)
COUNT
ENABLES
ENABLE P
ENABLE T
Q0
Q1
OUTPUTS
Q2
Q3
RIPPLE
CARRY
OUT
7
8
9
0
1
COUNT
RESET
MOTOROLA
2
3
INHIBIT
LOAD
8
High–Speed CMOS Logic Data
DL129 — Rev 6
High–Speed CMOS Logic Data
DL129 — Rev 6
9
LOAD
CLOCK
RESET
ENABLE T
ENABLE P
P3
P2
P1
P0
3
2
1
10
7
6
5
4
3
LOAD
LOAD
C
C
R
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
VCC = PIN 16
GND = PIN 8
Q3
Q2
Q1
Q0
15 RIPPLE
CARRY
OUT
11
12
13
14
The flip–flops shown in the circuit diagrams are Toggle–Enable flip–flops. A Toggle–
Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data from
Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flip–flop. The logic level at the Pn input is then clocked to the Q output of the flip–flop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
output of the flip–flop low.
T3
R
C
C
LOAD
LOAD
P3
T2
R
C
C
LOAD
LOAD
P2
T1
R
C
C
LOAD
LOAD
P1
T0
R
C
C
LOAD
LOAD
P0
MC54HC160 • MC74HC160
BCD Counter with Synchronous Reset
MC54/74HC160 MC54/74HC162
MOTOROLA
MC54/74HC160 MC54/74HC162
TYPICAL APPLICATIONS
CASCADING
N–Bit Synchronous Counters
LOAD
INPUTS
INPUTS
LOAD
H = COUNT
L = DISABLE
H = COUNT
L = DISABLE
P0 P1 P2 P3
LOAD
P0 P1 P2 P3
RIPPLE
CARRY
OUT
ENABLE T
LOAD
P0 P1 P2 P3
ENABLE P
ENABLE P
ENABLE P
INPUTS
RIPPLE
CARRY
OUT
ENABLE T
CLOCK
CLOCK
CLOCK
R
R
R
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
RIPPLE
CARRY
OUT
ENABLE T
TO
MORE
SIGNIFICANT
STAGES
Q0 Q1 Q2 Q3
RESET
OUTPUTS
OUTPUTS
OUTPUTS
CLOCK
NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on
number of stages. This limitation is due to set up times between Enable (Port) and Clock.
Nibble Ripple Counter
INPUTS
INPUTS
INPUTS
LOAD
ENABLE P
ENABLE T
LOAD
P0 P1 P2 P3
CLOCK
P0 P1 P2 P3
RIPPLE
CARRY
OUT
LOAD
P0 P1 P2 P3
ENABLE P
ENABLE P
ENABLE P
ENABLE T
LOAD
RIPPLE
CARRY
OUT
ENABLE T
ENABLE T
CLOCK
CLOCK
CLOCK
R
R
R
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
RIPPLE
CARRY
OUT
TO
MORE
SIGNIFICANT
STAGES
Q0 Q1 Q2 Q3
RESET
OUTPUTS
MOTOROLA
OUTPUTS
10
OUTPUTS
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC160 MC54/74HC162
TYPICAL APPLICATION
HC162
OTHER
INPUTS
Q0
OPTIONAL BUFFER
FOR NOISE REJECTION
Q1
Q2
OUTPUT
Q3
RESET
Modulo–5 Counter
The HC162 facilitates designing counters of any modulus with minimal external logic. The output is glitch–free due to the
synchronous Reset.
High–Speed CMOS Logic Data
DL129 — Rev 6
11
MOTOROLA
MC54/74HC160 MC54/74HC162
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
–B
–
L
C
DIM
A
B
C
D
E
F
G
J
K
L
M
N
–T
K
N
SEATING
–
PLANE
E
M
F
J 16 PL
0.25 (0.010)
G
D 16 PL
0.25 (0.010)
T A
M
9
1
8
T B
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A
–
16
M
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
1
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
MOTOROLA
J
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
12
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
MILLIMETERS
MIN
MAX
19.05 19.93
6.10
7.49
—
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
15°
0°
1.01
0.51
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
S
S
INCHES
MIN
MAX
0.750 0.785
0.240 0.295
—
0.200
0.015 0.020
0.050 BSC
0.055 0.065
0.100 BSC
0.008 0.015
0.125 0.170
0.300 BSC
15°
0°
0.020 0.040
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0°
7°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC160 MC54/74HC162
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
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associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
CODELINE
13
*MC54/74HC160/D*
MC54/74HC160/D
MOTOROLA