The following document contains information on Cypress products.
MB9B560R Series
®
®
32-bit ARM Cortex -M4F based Microcontroller
MB9BF566M/N/R, MB9BF567M/N/R,
MB9BF568M/N/R, MB9BF568F
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9B560R_DS709-00001
CONFIDENTIAL
Revision 2.0
Issue Date February 2, 2015
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion
data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this
proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has
been completed, and that initial production has begun. Due to the phases of the manufacturing
process that require maintaining efficiency and quality, this document may be revised by subsequent
versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
2
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
MB9B560R Series
32-bit ARM® Cortex®-M4F based Microcontroller
MB9BF566M/N/R, MB9BF567M/N/R,
MB9BF568M/N/R, MB9BF568F
Data Sheet (Full Production)
1.
Description
Devices in the MB9B560R Series are highly integrated 32-bit microcontrollers with high performance and
competitive cost.
This series is based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM. The series
has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, CAN,
2
UART, CSIO, I C, LIN).
Note:
−
ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Publication Number MB9B560R_DS709-00001
Revision 2.0
Issue Date February 2, 2015
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
Table of Contents
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
4
CONFIDENTIAL
Description ..................................................................................................................................... 3
Features ......................................................................................................................................... 5
Product Lineup ............................................................................................................................. 13
Packages ...................................................................................................................................... 15
Pin Assignment............................................................................................................................. 16
Pin Description ............................................................................................................................. 22
I/O Circuit Type............................................................................................................................. 51
Handling Precautions ................................................................................................................... 58
Handling Devices.......................................................................................................................... 62
Block Diagram .............................................................................................................................. 65
Memory Size ................................................................................................................................ 66
Memory Map ................................................................................................................................ 66
Pin Status In Each CPU State ...................................................................................................... 69
Electrical Characteristics .............................................................................................................. 77
Ordering Information................................................................................................................... 170
Package Dimensions .................................................................................................................. 171
Major Changes ........................................................................................................................... 178
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
2.
Features
32-bit ARM Cortex-M4F Core
Processor version: r0p1
Up to 160 MHz Frequency Operation
FPU built-in
Support DSP instruction
Memory Protection Unit (MPU): improves the reliability of an embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral
interrupts and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories
Flash memory
These series are based on two independent on-chip Flash memories.
− MainFlash memory
−
−
−
Up to 1024 Kbytes
−
Security function for code protection
Built-in Flash Accelerator System with 16 Kbytes trace buffer memory
The read access to Flash memory can be achieved without wait-cycle up to operation frequency of
72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory
can be obtained by Flash Accelerator System.
− WorkFlash memory
−
−
−
−
−
−
−
32 Kbytes
Read cycle:
6wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz
4wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz
2wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz
0wait-cycle: the operation frequency up to 40 MHz
Security function is shared with code protection
SRAM
This is composed of three independent SRAMs (SRAM0, SRAM1, and SRAM2). SRAM0 is connected to
I-code bus and D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of
Cortex-M4F core.
− SRAM0: Up to 64 Kbytes
− SRAM1: Up to 32 Kbytes
− SRAM2: Up to 32 Kbytes
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
5
D a t a S h e e t
External Bus Interface
Supports SRAM, NOR, NAND Flash, and SDRAM device
Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
8-/16-bit Data width
Up to 25-bit Address bit
Supports Address/Data multiplex
Supports external RDY function
Supports scramble function
− Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to
0xDFFF_FFFF in 4 Mbytes units.
− Possible to set two kinds of the scramble key
Note:
−
It is necessary to prepare the dedicated software library to use the scramble function.
USB Interface
USB interface is composed of Function and Host.
[USB function]
USB2.0 Full-Speed supported
Max 6 EndPoint supported
− EndPoint 0 is control transfer
− EndPoint 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer
− EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer
− EndPoint 1 to 5 comprise Double Buffer
− The size of each endpoint is according to the follows.
−
−
Endpoint 0, 2 to 5: 64 bytes
Endpoint 1: 256 bytes
[USB host]
USB2.0 Full/Low-speed supported
Bulk-transfer, interrupt-transfer and Isochronous-transfer support
USB Device connected/dis-connected automatically detect
IN/OUT token handshake packet automatically
Max 256-byte packet-length supported
Wake-up function supported
CAN Interface (Max two channels)
Compatible with CAN Specification 2.0A/B
Maximum transfer rate: 1 Mbps
Built-in 32 message buffer
6
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Multi-function Serial Interface (Max eight channels)
64 bytes with FIFO (the FIFO step numbers are variable depending on the settings of the communication
mode or bit length.)
Operation mode is selectable from the followings for each channel.
− UART
− CSIO
− LIN
− I2 C
UART
− Full-duplex double buffer
− Selection with or without parity supported
− Built-in dedicated baud rate generator
− External clock available as a serial clock
− Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)
− Various error detect functions available (parity errors, framing errors, and overrun errors)
CSIO
− Full-duplex double buffer
− Built-in dedicated baud rate generator
− Overrun error detect function available
− Serial chip select function (ch.6 and ch.7 only)
− Supports high-speed SPI (ch.4 and ch.6 only)
− Data length 5 to 16-bit
LIN
− LIN protocol Rev.2.1 supported
− Full-duplex double buffer
− Master/Slave mode supported
− LIN break field generation (can change to 13 to 16-bit length)
− LIN break delimiter generation (can change to 1 to 4-bit length)
− Various error detect functions available (parity errors, framing errors, and overrun errors)
I2 C
− Standard mode (Max 100 kbps) / High-speed mode (Max 400 kbps) supported
− Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A and ch.7=ch.B) supported
DMA Controller (Eight channels)
DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand transfer
Transfer data type: bytes/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
7
D a t a S h e e t
DSTC (Descriptor System data Transfer Controller) (128 channels)
The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the Descriptor
system and, following the specified contents of the Descriptor which has already been constructed on the
memory, can access directly the memory /peripheral device and performs the data transfer operation.
It supports the software activation, the hardware activation and the chain activation functions.
A/D Converter (Max 24 channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 3 units
Conversion time: 0.5 μs @ 5 V
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps)
DA Converter (Max two channels)
R-2R type
12-bit resolution
Base Timer (Max eight channels)
Operation mode is selectable from the followings for each channel.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
General Purpose I/O Port
This series can use its pins as general purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 100 high-speed general-purpose I/O ports @ 120 pin Package
Some pin is 5 V tolerant I/O.
See 6. Pin Description and 7. I/O Circuit Type for the corresponding pins.
8
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Multi-function Timer (Max two units)
The Multi-function timer is composed of the following blocks.
Minimum resolution : 6.25 ns
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
Output compare × 6 ch./unit
A/D activation compare × 6 ch./unit
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
The following function can be used to achieve the motor control.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.
Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the week.)
is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Quadrature Position/Revolution Counter (QPRC) (Max two channels)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use up/down counter.
The detection edge of the three external event input pins AIN, BIN, and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down counters.
Operation mode is selectable from the followings for each channel.
Free-running
Periodic (=Reload)
One-shot
Watch Counter
The Watch counter is used for wake up from the low-power consumption mode. It is possible to select the
main clock, sub clock, built-in high-speed CR clock or built-in low-speed CR clock as the clock source.
Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
9
D a t a S h e e t
External Interrupt Controller Unit
External interrupt input pin: Max 16 pins
Include one non-maskable interrupt (NMI)
Watchdog Timer (two channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, "Hardware" watchdog
is active in any power saving mode except STOP.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
SD Card Interface
It is possible to use the SD card that conforms to the following standards.
Part 1 Physical Layer Specification version 3.01
Part E1 SDIO Specification version 3.00
Part A2 SD Host Controller Standard Specification version 3.00
1-bit or 4-bit data bus
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically
selectable.
Main clock:
Sub Clock :
High-speed internal CR Clock:
Low-speed internal CR Clock:
Main PLL Clock
4 MHz to 48 MHz
32.768 kHz
4 MHz
100 kHz
[Resets]
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timers reset
Low voltage detector reset
Clock supervisor reset
10
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.
External OSC clock failure (clock stop) is detected, reset is asserted.
External OSC frequency anomaly is detected, interrupt or reset is asserted.
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage
has been set, Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-power Consumption Mode
Six low-power consumption modes are supported.
SLEEP
TIMER
RTC
STOP
Deep standby RTC (selectable from with/without RAM retention)
Deep standby stop (selectable from with/without RAM retention)
VBAT
The consumption power during the RTC operation can be reduced by supplying the power supply
independent from the RTC (calendar circuit)/32 kHz oscillation circuit. The following circuits can also be
used.
RTC
32 kHz oscillation circuit
Power-on circuit
Back up register: 32 bytes
Port circuit
Voice Function
These features are enabled for the voice function.
A dedicated library is necessary for using the voice function.
Automatic Speech Recognition (ASR)
− 100 custom commands in multiple languages
− User commands defined with a text file (no audio input or training required)
Natural Language Understanding (NLU)
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities.
Unique ID
Unique value of the device (41-bit) is set.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
11
D a t a S h e e t
Power Supply
Three Power Supplies
12
CONFIDENTIAL
Wide range voltage:
Power supply for USB I/O:
VCC
USBVCC
Power supply for VBAT:
VBAT
= 2.7 V to 5.5 V
= 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
= 2.7 V to 5.5 V
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
3.
Product Lineup
Memory Size
Product name
MB9BF566M/N/R
MB9BF567M/N/R
MB9BF568M/N/R/F
MainFlash memory
512 Kbytes
768 Kbytes
1024 Kbytes
WorkFlash memory
32 Kbytes
32 Kbytes
32 Kbytes
On-chip SRAM
64 Kbytes
96 Kbytes
128 Kbytes
SRAM0
32 Kbytes
48 Kbytes
64 Kbytes
SRAM1
16 Kbytes
24 Kbytes
32 Kbytes
SRAM1
16 Kbytes
24 Kbytes
32 Kbytes
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
13
D a t a S h e e t
Function
Product name
Pin count
MB9BF566M
MB9BF566N
MB9BF567M
MB9BF567N
MB9BF568M
MB9BF568N
80
100/112
MB9BF567R
MB9BF568R
MB9BF568F
120/144
Cortex-M4F, MPU, NVIC 128ch.
CPU
Freq.
160 MHz
Power supply voltage range
2.7 V to 5.5 V
USB2.0 (Function/Host)
1ch.
CAN
2ch. (Max)
DMAC
8ch.
DSTC
128ch.
Addr:19-bit (Max),
R/W data: 8-bit
(Max),
External Bus Interface
CS:5 (Max),
SRAM,
NOR Flash
Multi-function Serial Interface
Addr:25-bit (Max),
Addr:25-bit (Max),
R/W data: 8-/16-bit
R/W data: 8-/16-bit
(Max),
(Max),
CS:9 (Max),
CS:9 (Max),
SRAM,
SRAM,
NOR Flash,
NOR Flash,
SDRAM
NAND Flash, SDRAM
8ch. (Max)
(UART/CSIO/LIN/I2C)
Base Timer
8ch. (Max)
(PWC/Reload timer/PWM/PPG)
MF Timer
MB9BF566R
A/D activation compare
6ch.
Input capture
4ch.
Free-run timer
3ch.
Output compare
6ch.
Waveform generator
3ch.
PPG
3ch.
2 units (Max)
SD Card Interface
1 unit
QPRC
2ch. (Max)
Dual Timer
1 unit
Real-Time Clock
1 unit
Watch Counter
1 unit
CRC Accelerator
Yes
Watchdog Timer
1ch. (SW) + 1ch. (HW)
External Interrupts
16 pins (Max) + NMI × 1
I/O Ports
63 pins (Max)
12-bit A/D Converter
16ch. (3 units)
12-bit D/A Converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
Built-in CR
Debug Function
Unique ID
80 pins (Max)
100 pins (Max)
24ch. (3 units)
2 units (Max)
Yes
2ch.
High-speed
4 MHz (±2%)
Low-speed
100 kHz (Typ)
SWJ-DP/ETM
Yes
Note:
−
14
CONFIDENTIAL
All signals of the peripheral function in each product cannot be allocated by limiting the pins of
package.
It is necessary to use the port relocate function of the I/O port according to your function use.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
4.
Packages
Product Name
Package
MB9BF566M
MB9BF566N
MB9BF567M
MB9BF567N
MB9BF568M
MB9BF568N
LQFP: FPT-80P-M37 (0.5 mm pitch)
LQFP: FPT-80P-M40 (0.65 mm pitch)
QFP: FPT-100P-M36 (0.65 mm pitch)
MB9BF566R
MB9BF567R
MB9BF568R
MB9BF568F
-
-
-
-
-
-
LQFP: FPT-100P-M23 (0.5 mm pitch)
-
-
LQFP: FPT-120P-M37 (0.5 mm pitch)
-
-
BGA: BGA-112P-M05 (0.5 mm pitch)
-
-
BGA: BGA-144P-M09 (0.5 mm pitch)
-
-
: Supported
Note:
−
See 16. Package Dimensions for detailed information on each package.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
15
D a t a S h e e t
5.
Pin Assignment
FPT-80P-M37/M40
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/RX0_2/INT03_0/S_CD_0/MWEX_0
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
P03/TMS/SWDIO
P04/TDO/SWO
P09/AN19/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
(TOP VIEW)
VCC
1
60
VSS
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
2
59
P21/AN17/SIN0_0/INT06_1
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0
3
58
P22/CROUT_0/AN16/TIOB7_1/SOT0_0
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0
4
57
P23/AN15/TIOA7_1/SCK0_0/RTO00_1
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0
5
56
P1B/AN11/SCK4_1/IC02_1/MAD18_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0
6
55
P1A/AN10/SOT4_1/IC01_1/MAD17_0
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0
7
54
P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0
8
53
P18/AN08/SCK2_2/MAD15_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0
9
52
AVRH
P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0
10
51
AVRL
P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0
11
50
AVSS
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0
12
49
AVCC
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2
13
48
P17/AN07/SOT2_2/WKUP3/MAD14_0
P3A/TIOA0_1/AIN0_0/RTO00_0
14
47
P16/AN06/SIN2_2/INT14_1/MAD13_0
P3B/TIOA1_1/BIN0_0/RTO01_0
15
46
P15/AN05/SCK0_1/MAD12_0
P3C/TIOA2_1/ZIN0_0/RTO02_0
16
45
P14/AN04/SOT0_1/IC03_2/MAD11_0
P3D/TIOA3_1/RTO03_0/MAD00_0
17
44
P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
P3E/TIOA4_1/RTO04_0/MAD01_0
18
43
P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
P3F/TIOA5_1/RTO05_0/MAD02_0
19
42
P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0
VSS
20
41
P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0
29
30
31
32
33
34
35
36
37
38
39
C
VSS
VCC
P4B/TIOB1_0/SCS7_1/MAD03_0
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
PE0/MD1
MD0
PE2/X0
PE3/X1
40
28
VSS
27
25
P47/X1A
VBAT
24
P46/X0A
26
23
INITX
P48/VREGCTL
22
P49/VWAKEUP
21
P44/TIOA4_0/RTO14_1/DA0
P45/TIOB0_0/RTO15_1/DA1
LQFP - 80
Note:
−
16
CONFIDENTIAL
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the
relocated port number. For these pins, there are multiple pins that provide the same function for the
same channel. Use the extended port function register (EPFR) to select the pin.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
FPT-100P-M23
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/RX0_2/INT03_0/S_CD_0/MWEX_0
VSS
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
P03/TMS/SWDIO
P04/TDO/SWO
P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0
P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0
P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0
P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0
P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
(TOP VIEW)
VCC
1
75
VSS
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
2
74
P20/AN18/AIN1_1/INT05_0/MAD24_0
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0
3
73
P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0
4
72
P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0
5
71
P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0
6
70
P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0
7
69
P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0
8
68
P1C/AN12/CTS4_1/IC03_1/MAD19_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0
9
67
P1B/AN11/SCK4_1/IC02_1/MAD18_0
P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0
10
66
P1A/AN10/SOT4_1/IC01_1/MAD17_0
P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0
11
65
P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0
12
64
P18/AN08/SCK2_2/MAD15_0
LQFP - 100
41
42
43
44
45
46
47
48
49
50
P4B/TIOB1_0/SCS7_1/MAD03_0
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
VCC
40
51
VSS
25
VCC
P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0
VSS
39
52
C
24
38
P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0
P3F/TIOA5_1/RTO05_0/MAD02_0
37
P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
53
VBAT
54
23
P49/VWAKEUP
22
P3E/TIOA4_1/RTO04_0/MAD01_0
36
P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
P3D/TIOA3_1/RTO03_0/MAD00_0
P48/VREGCTL
55
35
21
34
P14/AN04/SOT0_1/IC03_2/MAD11_0
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0
P47/X1A
P15/AN05/SCK0_1/MAD12_0
56
P46/X0A
57
20
33
19
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0
INITX
P16/AN06/SIN2_2/INT14_1/MAD13_0
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0
32
58
31
18
P44/TIOA4_0/RTO14_1/DA0
P17/AN07/SOT2_2/WKUP3/MAD14_0
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0
P45/TIOB0_0/RTO15_1/DA1
AVCC
59
30
60
17
P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0
16
P38/SCK5_2/IC00_0/INT06_2/MADATA15_0
29
AVSS
P37/SOT5_2/IC01_0/INT05_2/MADATA14_0
28
61
P41/TIOA1_0/RTO11_1/INT13_1
15
P42/TIOA2_0/RTO12_1/MSDWEX_0
AVRL
P36/SIN5_2/IC02_0/INT09_1/MADATA13_0
27
AVRH
62
26
63
14
VCC
13
P40/TIOA0_0/RTO10_1/INT12_1
P34/TX0_1/TIOB4_1/FRCK0_0/MADATA11_0
P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MADATA12_0
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the
relocated port number. For these pins, there are multiple pins that provide the same function for the
same channel. Use the extended port function register (EPFR) to select the pin.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
17
D a t a S h e e t
FPT-120P-M37
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/RX0_2/SIN5_1/INT03_0/S_CD_0/MWEX_0
P64/TIOA7_0/SOT5_1/INT10_2
P65/TIOB7_0/SCK5_1
P66/ADTG_8/SIN3_0/INT11_2
P67/TIOA7_2/SOT3_0
P68/TIOB7_2/SCK3_0/INT00_2
VSS
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
P03/TMS/SWDIO
P04/TDO/SWO
P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0
P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0
P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0
P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0
P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
(TOP VIEW)
VCC
1
90
VSS
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
2
89
P20/AN18/AIN1_1/INT05_0/MAD24_0
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0
3
88
P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0
4
87
P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0
5
86
P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0
6
85
P24/RX1_0/SIN2_1/RTO01_1/INT01_2
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0
7
84
P25/TX1_0/TIOA5_0/SOT2_1/RTO02_1
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0
8
83
P26/TIOB5_0/SCK2_1/RTO03_1
P57/SCK6_0/MADATA07_0
9
82
P27/TIOA6_2/RTO04_1/INT02_2
P58/SIN4_2/AIN1_0/INT04_2/MADATA08_0
10
81
P1F/ADTG_4/TIOB6_2/RTO05_1
P59/RX1_1/SOT4_2/BIN1_0/INT07_1/MADATA09_0
11
80
P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
P5A/TX1_1/SCK4_2/ZIN1_0/MADATA10_0
12
79
P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
P5B/CTS4_2/MADATA11_0
13
78
P1C/AN12/CTS4_1/IC03_1/MAD19_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA12_0
14
77
P1B/AN11/SCK4_1/IC02_1/MAD18_0
76
P1A/AN10/SOT4_1/IC01_1/MAD17_0
75
P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
P31/TIOB1_1/SIN3_1/INT09_2/MADATA13_0
15
P32/TIOB2_1/SOT3_1/INT10_1/MADATA14_0
16
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA15_0
17
74
P18/AN08/SCK2_2/MAD15_0
P34/TX0_1/TIOB4_1/FRCK0_0/MNALE_0
18
73
AVRH
P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MNCLE_0
19
72
AVRL
LQFP - 120
59
60
56
PE0/MD1
VSS
55
P74/SCK2_0/DTTI1X_1
PE3/X1
54
P73/TIOB6_0/SOT2_0/IC10_1/INT03_2
58
53
P72/TIOA6_0/SIN2_0/ZIN0_1/IC11_1/INT14_2
57
52
P71/RX0_0/TIOB4_2/BIN0_1/IC12_1/INT15_1
MD0
51
P70/TX0_0/TIOA4_2/AIN0_1/IC13_1
PE2/X0
50
48
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
49
47
P4B/TIOB1_0/SCS7_1/MAD03_0
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
46
VCC
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
45
VCC
44
61
C
30
VSS
P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0
VSS
43
62
VBAT
29
42
P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0
P3F/TIOA5_1/RTO05_0/MAD02_0
41
63
P48/VREGCTL
28
P49/VWAKEUP
P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
P3E/TIOA4_1/RTO04_0/MAD01_0
40
64
39
27
P47/X1A
P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
P3D/TIOA3_1/RTO03_0/MAD00_0
P46/X0A
P14/AN04/SOT0_1/IC03_2/MAD11_0
65
38
66
26
INITX
25
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0
37
P15/AN05/SCK0_1/MAD12_0
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0
36
67
P44/TIOA4_0/RTO14_1/DA0
24
P45/TIOB0_0/RTO15_1/DA1
P16/AN06/SIN2_2/INT14_1/MAD13_0
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0
35
68
34
23
P42/TIOA2_0/RTO12_1/MSDWEX_0
P17/AN07/SOT2_2/WKUP3/MAD14_0
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0
P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0
69
33
22
32
AVCC
P38/SCK5_2/IC00_0/INT06_2
31
AVSS
70
VCC
71
21
P41/TIOA1_0/RTO11_1/INT13_1
20
P40/TIOA0_0/RTO10_1/INT12_1
P36/SIN5_2/IC02_0/INT09_1/MNWEX_0
P37/SOT5_2/IC01_0/INT05_2/MNREX_0
Note:
−
18
CONFIDENTIAL
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the
relocated port number. For these pins, there are multiple pins that provide the same function for the
same channel. Use the extended port function register (EPFR) to select the pin.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
FPT-100P-M36
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
VCC
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/RX0_2/INT03_0/S_CD_0/MWEX_0
VSS
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
P03/TMS/SWDIO
P04/TDO/SWO
P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0
P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0
P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0
P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0
P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
VSS
P20/AN18/AIN1_1/INT05_0/MAD24_0
P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
(TOP VIEW)
81
50
P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0
82
49
P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0
83
48
P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0
84
47
P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0
85
46
P1C/AN12/CTS4_1/IC03_1/MAD19_0
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0
86
45
P1B/AN11/SCK4_1/IC02_1/MAD18_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0
87
44
P1A/AN10/SOT4_1/IC01_1/MAD17_0
P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0
88
43
P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
42
P18/AN08/SCK2_2/MAD15_0
41
AVRH
P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0
89
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0
90
P34/TX0_1/TIOB4_1/FRCK0_0/MADATA11_0
91
40
AVRL
P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MADATA12_0
92
39
AVSS
P36/SIN5_2/IC02_0/INT09_1/MADATA13_0
93
38
AVCC
P37/SOT5_2/IC01_0/INT05_2/MADATA14_0
94
37
P17/AN07/SOT2_2/WKUP3/MAD14_0
QFP - 100
30
28
VSS
29
27
VCC
26
PE3/X1
P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0
25
MD0
PE2/X0
24
18
VSS
23
17
C
PE0/MD1
16
VBAT
22
15
P49/VWAKEUP
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
14
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
13
P47/X1A
P48/VREGCTL
21
12
P46/X0A
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
11
20
10
INITX
19
9
P44/TIOA4_0/RTO14_1/DA0
P45/TIOB0_0/RTO15_1/DA1
VCC
8
P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0
P4B/TIOB1_0/SCS7_1/MAD03_0
7
P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0
6
31
P41/TIOA1_0/RTO11_1/INT13_1
P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
P3D/TIOA3_1/RTO03_0/MAD00_0 100
P42/TIOA2_0/RTO12_1/MSDWEX_0
P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
32
5
33
99
P40/TIOA0_0/RTO10_1/INT12_1
98
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0
4
P14/AN04/SOT0_1/IC03_2/MAD11_0
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0
3
34
VSS
97
VCC
P15/AN05/SCK0_1/MAD12_0
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0
2
P16/AN06/SIN2_2/INT14_1/MAD13_0
35
1
36
96
P3F/TIOA5_1/RTO05_0/MAD02_0
95
P3E/TIOA4_1/RTO04_0/MAD01_0
P38/SCK5_2/IC00_0/INT06_2/MADATA15_0
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the
relocated port number. For these pins, there are multiple pins that provide the same function for the
same channel. Use the extended port function register (EPFR) to select the pin.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
19
D a t a S h e e t
BGA-112P-M05
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VSS
UDP0
UDM0
USBVCC
VSS
TCK/
SWCLK
VSS
AN21
P0A
P0B
VSS
P0E
VSS
B
VCC
VSS
P60
P61
P62
TRSTX SWDIO
AN22
AN19
P0C
P0D
VSS
VCC
C
P50
P51
P52
AN23
AN20
VSS
AN18
AN17
D
P53
P54
AN16
AN15
E
P55
P56
P30
AN14
AN13
AVRH
F
P31
P32
P33
AN12
AN11
AVRL
G
P34
P35
P36
AN10
AN09
AVSS
H
VSS
P37
P38
AN08
AN07
AVCC
J
P39
P3A
P3B
AN06
AN05
AN04
K
P3C
P3D
AN03
AN02
L
P3E
P3F
P43
VSS
AN01
AN00
M
VCC
VSS
P42
N
VSS
P40
P41
P63
TMS/
TDI
TDO/
SWO
index
P45
P48
P4B
P4C
P4E
P44
VSS
INITX
P49
VCC
P4D
MD1
MD0
VSS
VCC
VSS
X0A
X1A
VSS
VBAT
C
VSS
X0
X1
VSS
Note:
−
20
CONFIDENTIAL
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the
relocated port number. For these pins, there are multiple pins that provide the same function for the
same channel. Use the extended port function register (EPFR) to select the pin.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
BGA-144P-M09
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VSS
UDP0
UDM0
USBVCC
VSS
P66
VSS
VSS
AN21
VSS
P0C
VCC
VSS
B
VCC
VSS
P60
P61
P63
P67
TCK/
SWCLK
TDO/
SWO
AN20
P0B
VSS
VSS
P0E
C
P50
P51
VSS
P62
P64
P68
TDI
AN23
AN19
P0D
VSS
AN18
VSS
D
P52
P53
P54
VSS
P65
AN22
P0A
VSS
AN17
AN16
AN15
E
P55
P56
P57
P58
index
P24
P25
P26
P27
F
P59
P5A
P5B
P30
P1F
AN14
AN13
AN12
G
P31
P32
P33
P34
AN11
AN10
AN09
AVRH
H
P35
P36
P37
P38
AN08
AN07
AN06
AVRL
J
P39
P3A
P3B
P3C
AN05
AN04
AN03
AVSS
K
VSS
P3D
P3E
VSS
P45
P49
P4C
P70
P72
VSS
AN02
AN01
AVCC
L
P3F
P41
VSS
P44
VSS
P48
P4B
P4E
P71
P74
VSS
AN00
VSS
M
VCC
VSS
P43
VSS
X1A
VSS
VSS
P4D
VCC
P73
MD0
VSS
VCC
N
VSS
P40
P42
INITX
X0A
VSS
VBAT
C
VSS
MD1
X0
X1
VSS
TMS/
TRSTX SWDIO
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the
relocated port number. For these pins, there are multiple pins that provide the same function for the
same channel. Use the extended port function register (EPFR) to select the pin.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
21
D a t a S h e e t
6.
Pin Description
6.1
List of Pin Numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port
number. For these pins, there are multiple pins that provide the same function for the same channel. Use the
extended port function register (EPFR) to select the pin.
Pin No
I/O
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
1
1
1
79
B1
B1
Pin Name
Circuit
Type
VCC
Pin State
Type
-
-
E
K
E
K
E
I
E
I
E
K
P50
CTS4_0
AIN0_2
2
2
2
80
C1
C1
RTO10_0
(PPG10_0)
INT00_0
MADATA00_0
P51
RTS4_0
BIN0_2
3
3
3
81
C2
C2
RTO11_0
(PPG10_0)
INT01_0
MADATA01_0
P52
SCK4_0
(SCL4_0)
4
4
4
82
C3
D1
ZIN0_2
RTO12_0
(PPG12_0)
MADATA02_0
P53
TIOA1_2
SOT4_0
5
5
5
83
D1
D2
(SDA4_0)
RTO13_0
(PPG12_0)
MADATA03_0
P54
TIOB1_2
SIN4_0
6
6
6
84
D2
D3
RTO14_0
(PPG14_0)
INT02_0
MADATA04_0
22
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Pin No
LQFP120
LQFP100
LQFP80
I/O
QFP100
BGA112
BGA144
Pin Name
Circuit
Type
Pin State
Type
P55
ADTG_1
SIN6_0
7
7
7
85
E1
E1
RTO15_0
E
K
E
K
E
I
E
K
E
K
E
I
E
I
E
Q
(PPG14_0)
INT07_2
MADATA05_0
P56
SOT6_0
8
8
8
86
E2
E2
(SDA6_0)
DTTI1X_0
INT08_2
MADATA06_0
P57
9
-
-
-
-
E3
SCK6_0
(SCL6_0)
MADATA07_0
P58
SIN4_2
10
-
-
-
-
E4
AIN1_0
INT04_2
MADATA08_0
P59
RX1_1
SOT4_2
11
-
-
-
-
F1
(SDA4_2)
BIN1_0
INT07_1
MADATA09_0
P5A
TX1_1
12
-
-
-
-
F2
SCK4_2
(SCL4_2)
ZIN1_0
MADATA10_0
P5B
13
-
-
-
-
F3
CTS4_2
MADATA11_0
P30
TIOB0_1
14
9
9
87
E3
F4
RTS4_2
INT15_2
WKUP1
14
-
-
-
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
-
-
MADATA07_0
F4
MADATA12_0
23
D a t a S h e e t
Pin No
LQFP120
LQFP100
LQFP80
I/O
QFP100
BGA112
BGA144
Pin Name
Circuit
Type
Pin State
Type
P31
15
10
10
88
F1
G1
TIOB1_1
SIN3_1
INT09_2
15
-
-
-
-
-
MADATA08_0
G1
MADATA13_0
I
K
N
K
N
K
E
I
E
K
E
K
E
K
P32
TIOB2_1
16
11
11
89
F2
G2
SOT3_1
(SDA3_1)
INT10_1
16
-
-
-
-
-
MADATA09_0
G2
MADATA14_0
P33
ADTG_6
17
12
12
90
F3
G3
TIOB3_1
SCK3_1
(SCL3_1)
INT04_0
17
-
-
-
-
-
MADATA10_0
G3
MADATA15_0
P34
18
13
-
91
G1
G4
TX0_1
TIOB4_1
FRCK0_0
18
-
-
-
-
-
MADATA11_0
G4
MNALE_0
P35
RX0_1
19
14
-
92
G2
H1
TIOB5_1
IC03_0
INT08_1
19
-
-
-
-
-
MADATA12_0
H1
MNCLE_0
P36
20
15
-
93
G3
H2
SIN5_2
IC02_0
INT09_1
20
-
-
-
-
-
MADATA13_0
H2
MNWEX_0
P37
SOT5_2
21
16
-
94
H2
H3
(SDA5_2)
IC01_0
INT05_2
21
24
CONFIDENTIAL
-
-
-
-
-
MADATA14_0
H3
MNREX_0
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Pin No
LQFP120
LQFP100
LQFP80
I/O
QFP100
BGA112
BGA144
Pin Name
Circuit
Type
Pin State
Type
P38
SCK5_2
22
17
-
95
H3
H4
(SCL5_2)
IC00_0
E
K
L
I
G
I
G
I
G
I
G
I
G
I
G
I
INT06_2
-
-
MADATA15_0
P39
ADTG_2
23
18
13
96
J1
J1
DTTI0X_0
RTCCO_2
SUBOUT_2
-
MSDCLK_0
P3A
TIOA0_1
24
19
14
97
J2
J2
AIN0_0
RTO00_0
(PPG00_0)
-
MSDCKE_0
P3B
TIOA1_1
25
20
15
98
J3
J3
BIN0_0
RTO01_0
(PPG00_0)
-
MRASX_0
P3C
TIOA2_1
26
21
16
99
K1
J4
ZIN0_0
RTO02_0
(PPG02_0)
-
MCASX_0
P3D
TIOA3_1
27
22
17
100
K2
K2
RTO03_0
(PPG02_0)
MAD00_0
P3E
TIOA4_1
28
23
18
1
L1
K3
RTO04_0
(PPG04_0)
MAD01_0
P3F
TIOA5_1
29
24
19
2
L2
L1
RTO05_0
(PPG04_0)
MAD02_0
30
25
20
3
N1
N1
VSS
-
-
31
26
-
4
M1
M1
VCC
-
-
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
25
D a t a S h e e t
Pin No
LQFP120
LQFP100
LQFP80
I/O
QFP100
BGA112
BGA144
Pin Name
Circuit
Type
Pin State
Type
P40
TIOA0_0
32
27
-
5
N2
N2
G
K
G
K
G
I
G
I
R
J
R
J
B
C
P
S
Q
T
O
U
O
U
VBAT
-
-
RTO10_1
(PPG10_1)
INT12_1
P41
TIOA1_0
33
28
-
6
N3
L2
RTO11_1
(PPG10_1)
INT13_1
P42
TIOA2_0
34
29
-
7
M3
N3
RTO12_1
(PPG12_1)
MSDWEX_0
P43
ADTG_7
35
30
-
8
L3
M3
TIOA3_0
RTO13_1
(PPG12_1)
MCSX8_0
P44
TIOA4_0
36
31
21
9
M4
L4
RTO14_1
(PPG14_1)
DA0
P45
TIOB0_0
37
32
22
10
L5
K5
RTO15_1
(PPG14_1)
DA1
38
33
23
11
M6
N4
INITX
P46
39
34
24
12
N5
N5
40
35
25
13
N6
M5
41
36
26
14
L6
L6
42
37
27
15
M7
K6
43
38
28
16
N8
N7
44
39
29
17
N9
N8
C
-
-
45
40
30
18
N10
N9
VSS
-
-
46
41
31
19
M8
M9
VCC
-
-
E
I
X0A
P47
X1A
P48
VREGCTL
P49
VWAKEUP
P4B
47
42
32
20
L7
L7
TIOB1_0
SCS7_1
MAD03_0
26
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Pin No
LQFP120
LQFP100
LQFP80
I/O
QFP100
BGA112
BGA144
Pin Name
Circuit
Type
Pin State
Type
P4C
TIOB2_0
48
43
33
21
L8
K7
SCK7_1
(SCL7_1)
N
I
N
K
I
Q
E
I
E
K
E
K
E
K
E
I
AIN1_2
MAD04_0
P4D
TIOB3_0
SOT7_1
49
44
34
22
M9
M8
(SDA7_1)
BIN1_2
INT13_2
MAD05_0
P4E
TIOB4_0
SIN7_1
50
45
35
23
L9
L8
ZIN1_2
FRCK1_1
INT11_1
WKUP2
MAD06_0
P70
TX0_0
51
-
-
-
-
K8
TIOA4_2
AIN0_1
IC13_1
P71
RX0_0
52
-
-
-
-
L9
TIOB4_2
BIN0_1
IC12_1
INT15_1
P72
TIOA6_0
53
-
-
-
-
K9
SIN2_0
ZIN0_1
IC11_1
INT14_2
P73
TIOB6_0
54
-
-
-
-
M10
SOT2_0
(SDA2_0)
IC10_1
INT03_2
P74
55
-
-
-
-
L10
SCK2_0
(SCL2_0)
DTTI1X_1
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
27
D a t a S h e e t
Pin No
I/O
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
56
46
36
24
M10
N10
57
47
37
25
M11
M11
Pin Name
Circuit
Type
PE0
MD1
MD0
PE2
Pin State
Type
C
E
J
D
A
A
A
B
58
48
38
26
N11
N11
59
49
39
27
N12
N12
60
50
40
28
N13
N13
VSS
-
-
61
51
-
29
M13
M13
VCC
-
-
F
M
F
L
F
L
F
M
F
L
F
L
X0
PE3
X1
P10
AN00
RX1_2
62
52
41
30
L13
L12
SIN1_1
FRCK0_2
INT02_1
MAD07_0
P11
AN01
TX1_2
63
53
42
31
L12
K12
SOT1_1
(SDA1_1)
IC00_2
MAD08_0
P12
AN02
SCK1_1
64
54
43
32
K13
K11
(SCL1_1)
IC01_2
RTCCO_1
SUBOUT_1
MAD09_0
P13
AN03
65
55
44
33
K12
J12
SIN0_1
IC02_2
INT03_1
MAD10_0
P14
AN04
66
56
45
34
J13
J11
SOT0_1
(SDA0_1)
IC03_2
MAD11_0
P15
AN05
67
57
46
35
J12
J10
SCK0_1
(SCL0_1)
MAD12_0
28
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Pin No
LQFP120
LQFP100
LQFP80
I/O
QFP100
BGA112
BGA144
Pin Name
Circuit
Type
Pin State
Type
P16
AN06
68
58
47
36
J11
H12
SIN2_2
F
M
F
P
INT14_1
MAD13_0
P17
AN07
69
59
48
37
H12
H11
SOT2_2
(SDA2_2)
WKUP3
MAD14_0
70
60
49
38
H13
K13
AVCC
-
-
71
61
50
39
G13
J13
AVSS
-
-
72
62
51
40
F13
H13
AVRL
-
-
73
63
52
41
E13
G13
AVRH
-
-
F
L
F
M
M
L
M
L
F
L
F
L
P18
AN08
74
64
53
42
H11
H10
SCK2_2
(SCL2_2)
MAD15_0
P19
AN09
75
65
54
43
G12
G12
SIN4_1
IC00_1
INT05_1
MAD16_0
P1A
AN10
76
66
55
44
G11
G11
SOT4_1
(SDA4_1)
IC01_1
MAD17_0
P1B
AN11
77
67
56
45
F12
G10
SCK4_1
(SCL4_1)
IC02_1
MAD18_0
P1C
AN12
78
68
-
46
F11
F13
CTS4_1
IC03_1
MAD19_0
P1D
AN13
79
69
-
47
E12
F12
RTS4_1
DTTI0X_1
MAD20_0
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
29
D a t a S h e e t
Pin No
LQFP120
LQFP100
LQFP80
I/O
QFP100
BGA112
BGA144
Pin Name
Circuit
Type
Pin State
Type
P1E
AN14
80
70
-
48
E11
F11
ADTG_5
F
L
E
I
E
K
E
I
E
I
E
K
F
L
F
L
FRCK0_1
MAD21_0
P1F
ADTG_4
81
-
-
-
-
F10
TIOB6_2
RTO05_1
(PPG04_1)
P27
TIOA6_2
82
-
-
-
-
E13
RTO04_1
(PPG04_1)
INT02_2
P26
TIOB5_0
83
-
-
-
-
E12
SCK2_1
(SCL2_1)
RTO03_1
(PPG02_1)
P25
TX1_0
TIOA5_0
84
-
-
-
-
E11
SOT2_1
(SDA2_1)
RTO02_1
(PPG02_1)
P24
RX1_0
85
-
-
-
-
E10
SIN2_1
RTO01_1
(PPG00_1)
INT01_2
P23
AN15
TIOA7_1
86
71
57
49
D13
D13
SCK0_0
(SCL0_0)
RTO00_1
(PPG00_1)
-
MAD22_0
P22
CROUT_0
87
72
58
AN16
50
D12
D12
TIOB7_1
SOT0_0
(SDA0_0)
30
CONFIDENTIAL
ZIN1_1
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Pin No
LQFP120
LQFP100
LQFP80
I/O
QFP100
BGA112
BGA144
Pin Name
Circuit
Type
Pin State
Type
P21
59
88
73
-
AN17
51
C13
D11
SIN0_0
BIN1_1
59
INT06_1
-
MAD23_0
F
M
F
M
P20
AN18
89
74
-
52
C12
C12
AIN1_1
INT05_0
MAD24_0
90
75
60
53
A13
A13
VSS
-
-
91
76
61
54
B13
A12
VCC
-
-
L
I
L
I
L
I
L
K
L
K
P0E
TIOB5_2
92
77
62
55
A12
B13
SCS6_1
IC13_0
S_CLK_0
MDQM1_0
P0D
TIOA5_2
SCK6_1
93
78
63
56
B11
C10
(SCL6_1)
IC12_0
S_CMD_0
MDQM0_0
P0C
TIOA6_1
SOT6_1
94
79
64
57
B10
A11
(SDA6_1)
IC11_0
S_DATA1_0
MALE_0
P0B
TIOB6_1
SIN6_1
95
80
65
58
A10
B10
IC10_0
INT00_1
S_DATA0_0
MCSX0_0
P0A
SIN1_0
96
81
66
59
A9
D9
FRCK1_0
INT12_2
S_DATA3_0
MCSX1_0
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
31
D a t a S h e e t
Pin No
LQFP120
LQFP100
LQFP80
I/O
QFP100
BGA112
BGA144
Type
Pin State
Type
AN19
82
Circuit
P09
67
97
Pin Name
TRACED0
60
B9
C9
TIOA3_2
SOT1_0
M
N
F
N
F
N
F
N
F
O
E
G
E
G
E
H
E
G
(SDA1_0)
67
S_DATA2_0
MCSX5_0
P08
AN20
TRACED1
98
83
-
61
C9
B9
TIOB3_2
SCK1_0
(SCL1_0)
MCSX4_0
P07
AN21
TRACED2
99
84
-
62
A8
A9
TIOA0_2
SCK7_0
(SCL7_0)
MCLKOUT_0
P06
AN22
TRACED3
100
85
-
63
B8
D8
TIOB0_2
SOT7_0
(SDA7_0)
MCSX3_0
P05
AN23
ADTG_0
101
86
-
64
C8
C8
TRACECLK
SIN7_0
INT01_1
MCSX2_0
P04
102
87
68
65
C7
B8
TDO
SWO
P03
103
88
69
66
B7
D7
TMS
SWDIO
P02
104
89
70
67
C6
C7
TDI
MCSX6_0
P01
105
90
71
68
A6
B7
TCK
SWCLK
32
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Pin No
I/O
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
106
91
72
69
B6
D6
107
92
-
70
A5
A7
Pin Name
Circuit
Type
Pin State
Type
P00
TRSTX
E
H
-
-
E
K
E
I
E
K
E
I
E
K
E
K
I
K
E
I
MCSX7_0
VSS
P68
TIOB7_2
108
-
-
-
-
C6
SCK3_0
(SCL3_0)
INT00_2
P67
109
-
-
-
-
B6
TIOA7_2
SOT3_0
(SDA3_0)
P66
110
-
-
-
-
A6
ADTG_8
SIN3_0
INT11_2
P65
111
-
-
-
-
D5
TIOB7_0
SCK5_1
(SCL5_1)
P64
TIOA7_0
112
-
-
-
-
C5
SOT5_1
(SDA5_1)
INT10_2
P63
93
73
71
C5
-
-
-
-
93
73
71
C5
CROUT_1
RX0_2
113
B5
SIN5_1
INT03_0
S_CD_0
MWEX_0
P62
ADTG_3
TX0_2
114
94
74
72
B5
C4
SIN5_0
INT04_1
S_WP_0
MOEX_0
P61
UHCONX0
TIOB2_2
115
95
75
73
B4
B4
SOT5_0
(SDA5_0)
RTCCO_0
SUBOUT_0
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
33
D a t a S h e e t
Pin No
LQFP120
LQFP100
LQFP80
I/O
QFP100
BGA112
BGA144
Pin Name
Circuit
Type
Pin State
Type
P60
TIOA2_2
SCK5_0
116
96
76
74
B3
B3
(SCL5_0)
I
F
-
-
H
R
H
R
NMIX
WKUP0
MRDY_0
117
97
77
75
A4
A4
118
98
78
76
A3
A3
119
99
79
77
A2
A2
120
100
80
78
A1
A1
-
-
-
-
-
-
A7
A5
-
-
-
-
-
-
B2
A8
-
-
-
-
-
-
B12
A10
-
-
-
-
-
-
C11
B2
-
-
-
-
-
-
H1
B11
-
-
-
-
-
-
N4
B12
-
-
-
-
-
-
M5
C3
-
-
-
-
-
-
N7
C11
-
-
-
-
-
-
L11
C13
-
-
-
-
-
-
A11
D4
-
-
-
-
-
-
M12
D10
-
-
-
-
-
-
M2
K1
-
-
-
-
-
-
-
K4
-
-
-
-
-
-
-
K10
-
-
-
-
-
-
-
L3
-
-
-
-
-
-
-
L5
-
-
-
-
-
-
-
L11
-
-
-
-
-
-
-
L13
-
-
-
-
-
-
-
M2
-
-
-
-
-
-
-
M4
-
-
-
-
-
-
-
M6
-
-
-
-
-
-
-
M7
-
-
-
-
-
-
-
M12
-
-
-
-
-
-
-
N6
-
-
34
CONFIDENTIAL
USBVCC
P80
UDM0
P81
UDP0
VSS
VSS
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
6.2
List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port
number. For these pins, there are multiple pins that provide the same function for the same channel. Use the
extended port function register (EPFR) to select the pin.
Pin
Function
Pin No
Pin Name
Function Description
ADTG_0
LQFP
QFP
BGA
BGA
100
80
100
112
144
101
86
-
64
C8
C8
E1
7
7
7
85
E1
ADTG_2
23
18
13
96
J1
J1
ADTG_3
114
94
74
72
B5
C4
81
-
-
-
-
F10
ADTG_5
A/D converter external trigger input pin
80
70
-
48
E11
F11
ADTG_6
17
12
12
90
F3
G3
ADTG_7
35
30
-
8
L3
M3
ADTG_8
110
-
-
-
-
A6
AN00
62
52
41
30
L13
L12
AN01
63
53
42
31
L12
K12
AN02
64
54
43
32
K13
K11
AN03
65
55
44
33
K12
J12
AN04
66
56
45
34
J13
J11
AN05
67
57
46
35
J12
J10
AN06
68
58
47
36
J11
H12
AN07
69
59
48
37
H12
H11
AN08
74
64
53
42
H11
H10
AN09
75
65
54
43
G12
G12
AN10
76
66
55
44
G11
G11
AN11
A/D converter analog input pin.
77
67
56
45
F12
G10
AN12
ANxx describes ADC ch.xx.
78
68
-
46
F11
F13
AN13
79
69
-
47
E12
F12
AN14
80
70
-
48
E11
F11
AN15
86
71
57
49
D13
D13
AN16
87
72
58
50
D12
D12
AN17
88
73
59
51
C13
D11
AN18
89
74
-
52
C12
C12
AN19
97
82
67
60
B9
C9
AN20
98
83
-
61
C9
B9
AN21
99
84
-
62
A8
A9
AN22
100
85
-
63
B8
D8
AN23
101
86
-
64
C8
C8
32
27
-
5
N2
N2
24
19
14
97
J2
J2
99
84
-
62
A8
A9
37
32
22
10
L5
K5
14
9
9
87
E3
F4
100
85
-
63
B8
D8
TIOA0_0
TIOA0_1
Base
TIOA0_2
Timer 0
TIOB0_0
TIOB0_1
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
TIOB0_2
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
LQFP
120
ADTG_1
ADTG_4
ADC
LQFP
35
D a t a S h e e t
Pin
Function
Pin No
Pin Name
Function Description
TIOA1_0
TIOA1_1
Base timer ch.1 TIOA pin
LQFP
LQFP
LQFP
QFP
BGA
BGA
120
100
80
100
112
144
33
28
-
6
N3
L2
25
20
15
98
J3
J3
Base
TIOA1_2
5
5
5
83
D1
D2
Timer 1
TIOB1_0
47
42
32
20
L7
L7
TIOB1_1
15
10
10
88
F1
G1
TIOB1_2
6
6
6
84
D2
D3
TIOA2_0
34
29
-
7
M3
N3
TIOA2_1
Base timer ch.1 TIOB pin
26
21
16
99
K1
J4
Base
TIOA2_2
116
96
76
74
B3
B3
Timer 2
TIOB2_0
48
43
33
21
L8
K7
TIOB2_1
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
TIOB2_2
TIOA3_0
TIOA3_1
Base
TIOA3_2
Timer 3
TIOB3_0
TIOB3_1
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
TIOB3_2
TIOA4_0
TIOA4_1
Base timer ch.4 TIOA pin
16
11
11
89
F2
G2
115
95
75
73
B4
B4
35
30
-
8
L3
M3
27
22
17
100
K2
K2
97
82
67
60
B9
C9
49
44
34
22
M9
M8
17
12
12
90
F3
G3
98
83
-
61
C9
B9
36
31
21
9
M4
L4
28
23
18
1
L1
K3
K8
Base
TIOA4_2
51
-
-
-
-
Timer 4
TIOB4_0
50
45
35
23
L9
L8
18
13
-
91
G1
G4
TIOB4_2
52
-
-
-
-
L9
TIOA5_0
84
-
-
-
-
E11
29
24
19
2
L2
L1
TIOB4_1
TIOA5_1
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base
TIOA5_2
93
78
63
56
B11
C10
Timer 5
TIOB5_0
83
-
-
-
-
E12
TIOB5_1
19
14
-
92
G2
H1
TIOB5_2
92
77
62
55
A12
B13
TIOA6_0
53
-
-
-
-
K9
TIOA6_1
Base timer ch.5 TIOB pin
94
79
64
57
B10
A11
Base
TIOA6_2
82
-
-
-
-
E13
Timer 6
TIOB6_0
54
-
-
-
-
M10
95
80
65
58
A10
B10
81
-
-
-
-
F10
TIOB6_1
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
TIOB6_2
TIOA7_0
TIOA7_1
Base
TIOA7_2
Timer 7
TIOB7_0
Base timer ch.7 TIOA pin
-
-
C5
57
49
D13
D13
109
-
-
-
-
B6
-
-
-
-
D5
72
58
50
D12
D12
108
-
-
-
-
C6
51
-
-
-
-
K8
18
13
-
91
G1
G4
TX0_2
114
94
74
72
B5
C4
RX0_0
52
-
-
-
-
L9
19
14
-
92
G2
H1
113
93
73
71
C5
B5
TX0_0
TX0_1
RX0_1
RX0_2
CONFIDENTIAL
-
71
87
Base timer ch.7 TIOB pin
TIOB7_2
36
-
86
111
TIOB7_1
CAN 0
112
CAN interface ch.0 TX output pin
CAN interface ch.0 RX output pin
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Pin
Function
Pin No
Pin Name
Function Description
LQFP
LQFP
LQFP
QFP
BGA
120
100
80
100
112
144
84
-
-
-
-
E11
12
-
-
-
-
F2
TX1_2
63
53
42
31
L12
K12
RX1_0
85
-
-
-
-
E10
TX1_0
TX1_1
CAN 1
RX1_1
CAN interface ch.1 TX output pin
CAN interface ch.1 RX output pin
RX1_2
SWCLK
SWDIO
Debugger
Serial wire debug interface clock input pin
Serial wire debug interface data input / output
pin
-
-
-
F1
41
30
L13
L12
105
90
71
68
A6
B7
103
88
69
66
B7
D7
C7
B8
102
87
68
65
TCK
J-TAG test clock input pin
105
90
71
68
A6
B7
TDI
J-TAG test data input pin
104
89
70
67
C6
C7
TDO
J-TAG debug data output pin
102
87
68
65
C7
B8
TMS
J-TAG test mode state input/output pin
103
88
69
66
B7
D7
Trace CLK output pin of ETM
101
86
-
64
C8
C8
TRACED0
97
82
-
60
B9
C9
TRACED1
98
83
-
61
C9
B9
99
84
-
62
A8
A9
100
85
-
63
B8
D8
106
91
72
69
B6
D6
MAD00_0
27
22
17
100
K2
K2
MAD01_0
28
23
18
1
L1
K3
MAD02_0
29
24
19
2
L2
L1
MAD03_0
47
42
32
20
L7
L7
MAD04_0
48
43
33
21
L8
K7
MAD05_0
49
44
34
22
M9
M8
MAD06_0
50
45
35
23
L9
L8
MAD07_0
62
52
41
30
L13
L12
MAD08_0
63
53
42
31
L12
K12
MAD09_0
64
54
43
32
K13
K11
MAD10_0
65
55
44
33
K12
J12
66
56
45
34
J13
J11
67
57
46
35
J12
J10
MAD13_0
68
58
47
36
J11
H12
MAD14_0
69
59
48
37
H12
H11
MAD15_0
74
64
53
42
H11
H10
MAD16_0
75
65
54
43
G12
G12
MAD17_0
76
66
55
44
G11
G11
MAD18_0
77
67
56
45
F12
G10
MAD19_0
78
68
-
46
F11
F13
MAD20_0
79
69
-
47
E12
F12
MAD21_0
80
70
-
48
E11
F11
MAD22_0
86
71
-
49
D13
D13
MAD23_0
88
73
-
51
C13
D11
MAD24_0
89
74
-
52
C12
C12
Trace data output pin of ETM
TRACED3
TRSTX
J-TAG test reset input pin
MAD11_0
MAD12_0
External bus interface address bus
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
52
Serial wire viewer output pin
TRACED2
Bus
11
62
SWO
TRACECLK
External
BGA
37
D a t a S h e e t
Pin
Function
Pin No
Pin Name
Function Description
LQFP
LQFP
LQFP
QFP
BGA
BGA
120
100
80
100
112
144
MCSX0_0
95
80
65
58
A10
B10
MCSX1_0
96
81
66
59
A9
D9
MCSX2_0
101
86
-
64
C8
C8
MCSX3_0
100
85
-
63
B8
D8
MCSX4_0
98
83
-
61
C9
B9
MCSX5_0
External bus interface chip select output pin
97
82
67
60
B9
C9
MCSX6_0
104
89
70
67
C6
C7
MCSX7_0
106
91
72
69
B6
D6
MCSX8_0
35
30
-
8
L3
M3
MADATA00_0
2
2
2
80
C1
C1
MADATA01_0
3
3
3
81
C2
C2
MADATA02_0
4
4
4
82
C3
D1
MADATA03_0
5
5
5
83
D1
D2
MADATA04_0
6
6
6
84
D2
D3
MADATA05_0
7
7
7
85
E1
E1
MADATA06_0
8
8
8
86
E2
E2
MADATA07_0
External bus interface data bus
9
9
9
87
E3
E3
MADATA08_0
(Address / data multiplex bus)
10
10
10
88
F1
E4
MADATA09_0
11
11
11
89
F2
F1
MADATA10_0
12
12
12
90
F3
F2
F3
MADATA11_0
13
13
-
91
G1
External
MADATA12_0
14
14
-
92
G2
F4
Bus
MADATA13_0
15
15
-
93
G3
G1
MADATA14_0
16
16
-
94
H2
G2
MADATA15_0
17
17
-
95
H3
G3
MDQM0_0
External bus interface byte mask signal output
93
78
63
56
B11
C10
MDQM1_0
pin
92
77
62
55
A12
B13
94
79
64
57
B10
A11
116
96
76
74
B3
B3
99
84
-
62
A8
A9
18
-
-
-
-
G4
19
-
-
-
-
H1
21
-
-
-
-
H3
20
-
-
-
-
H2
114
94
74
72
B5
C4
113
93
73
71
C5
B5
MALE_0
MRDY_0
MCLKOUT_0
MNALE_0
MNCLE_0
MNREX_0
MNWEX_0
MOEX_0
MWEX_0
38
CONFIDENTIAL
External bus interface Address Latch enable
output signal for multiplex
External bus interface external RDY input
signal
External bus interface external clock output pin
External bus interface ALE signal to control
NAND Flash output pin
External bus interface CLE signal to control
NAND Flash output pin
External bus interface read enable signal to
control NAND Flash
External bus interface write enable signal to
control NAND Flash
External bus interface read enable signal for
SRAM
External bus interface write enable signal for
SRAM
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Pin
Function
Pin No
Pin Name
MSDCLK_0
MSDCKE_0
External
Bus
MRASX_0
MCASX_0
MSDWEX_0
Function Description
SDRAM interface
SDRAM clock output pin
SDRAM interface
SDRAM clock enable pin
SDRAM interface
SDRAM row address strobe pin
SDRAM interface
SDRAM column address strobe pin
SDRAM interface
SDRAM write enable pin
INT00_0
INT00_1
LQFP
LQFP
QFP
BGA
BGA
120
100
80
100
112
144
23
18
-
96
J1
J1
24
19
-
97
J2
J2
25
20
-
98
J3
J3
26
21
-
99
K1
J4
34
29
-
7
M3
N3
2
2
2
80
C1
C1
95
80
65
58
A10
B10
INT00_2
108
-
-
-
-
C6
INT01_0
3
3
3
81
C2
C2
INT01_1
External interrupt request 00 input pin
LQFP
101
86
-
64
C8
C8
INT01_2
85
-
-
-
-
E10
INT02_0
6
6
6
84
D2
D3
62
52
41
30
L13
L12
82
-
-
-
-
E13
113
93
73
71
C5
B5
65
55
44
33
K12
J12
54
-
-
-
-
M10
INT02_1
External interrupt request 01 input pin
External interrupt request 02 input pin
INT02_2
INT03_0
INT03_1
External interrupt request 03 input pin
INT03_2
INT04_0
INT04_1
External interrupt request 04 input pin
INT04_2
INT05_0
INT05_1
External interrupt request 05 input pin
17
12
12
90
F3
G3
114
94
74
72
B5
C4
10
-
-
-
-
E4
89
74
-
52
C12
C12
75
65
54
43
G12
G12
INT05_2
21
16
-
94
H2
H3
External
INT06_1
88
73
59
51
C13
D11
Interrupt
INT06_2
22
17
-
95
H3
H4
INT07_1
INT07_2
INT08_1
INT08_2
INT09_1
INT09_2
INT10_1
INT10_2
INT11_1
INT11_2
INT12_1
INT12_2
INT13_1
INT13_2
INT14_1
INT14_2
INT15_1
INT15_2
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
External interrupt request 09 input pin
External interrupt request 10 input pin
External interrupt request 11 input pin
External interrupt request 12 input pin
External interrupt request 13 input pin
External interrupt request 14 input pin
External interrupt request 15 input pin
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
11
-
-
-
-
F1
7
7
7
85
E1
E1
19
14
-
92
G2
H1
8
8
8
86
E2
E2
20
15
-
93
G3
H2
15
10
10
88
F1
G1
16
11
11
89
F2
G2
112
-
-
-
-
C5
50
45
35
23
L9
L8
110
-
-
-
-
A6
32
27
-
5
N2
N2
96
81
66
59
A9
D9
33
28
-
6
N3
L2
49
44
34
22
M9
M8
68
58
47
36
J11
H12
53
-
-
-
-
K9
52
-
-
-
-
L9
14
9
9
87
E3
F4
39
D a t a S h e e t
Pin
Function
External
Interrupt
Pin No
Pin Name
LQFP
LQFP
LQFP
QFP
BGA
BGA
120
100
80
100
112
144
116
96
76
74
B3
B3
P00
106
91
72
69
B6
D6
P01
105
90
71
68
A6
B7
P02
104
89
70
67
C6
C7
P03
103
88
69
66
B7
D7
P04
102
87
68
65
C7
B8
P05
101
86
-
64
C8
C8
P06
100
85
-
63
B8
D8
99
84
-
62
A8
A9
P08
98
83
-
61
C9
B9
P09
97
82
67
60
B9
C9
P0A
96
81
66
59
A9
D9
NMIX
P07
GPIO
General-purpose I/O port 0
P0B
95
80
65
58
A10
B10
94
79
64
57
B10
A11
P0D
93
78
63
56
B11
C10
P0E
92
77
62
55
A12
B13
P10
62
52
41
30
L13
L12
P11
63
53
42
31
L12
K12
P12
64
54
43
32
K13
K11
P13
65
55
44
33
K12
J12
P14
66
56
45
34
J13
J11
P15
67
57
46
35
J12
J10
P16
68
58
47
36
J11
H12
P17
69
59
48
37
H12
H11
74
64
53
42
H11
H10
G12
General-purpose I/O port 1
P19
75
65
54
43
G12
P1A
76
66
55
44
G11
G11
P1B
77
67
56
45
F12
G10
P1C
78
68
-
46
F11
F13
P1D
79
69
-
47
E12
F12
P1E
80
70
-
48
E11
F11
P1F
81
-
-
-
-
F10
P20
89
74
-
52
C12
C12
P21
88
73
59
51
C13
D11
P22
87
72
58
50
D12
D12
86
71
57
49
D13
D13
P23
P24
CONFIDENTIAL
Non-Maskable Interrupt input pin
P0C
P18
40
Function Description
General-purpose I/O port 2
85
-
-
-
-
E10
P25
84
-
-
-
-
E11
P26
83
-
-
-
-
E12
P27
82
-
-
-
-
E13
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Pin
Function
Pin No
Pin Name
LQFP
LQFP
QFP
BGA
BGA
144
120
100
80
100
112
14
9
9
87
E3
F4
P31
15
10
10
88
F1
G1
P32
16
11
11
89
F2
G2
P33
17
12
12
90
F3
G3
P34
18
13
-
91
G1
G4
P35
19
14
-
92
G2
H1
P36
20
15
-
93
G3
H2
21
16
-
94
H2
H3
22
17
-
95
H3
H4
P39
23
18
13
96
J1
J1
P3A
24
19
14
97
J2
J2
P3B
25
20
15
98
J3
J3
P3C
26
21
16
99
K1
J4
P3D
27
22
17
100
K2
K2
P3E
28
23
18
1
L1
K3
P3F
29
24
19
2
L2
L1
P40
32
27
-
5
N2
N2
P41
33
28
-
6
N3
L2
P42
34
29
-
7
M3
N3
P43
35
30
-
8
L3
M3
P44
36
31
21
9
M4
L4
P45
37
32
22
10
L5
K5
39
34
24
12
N5
N5
M5
P38
P46
P47
General-purpose I/O port 3
General-purpose I/O port 4
40
35
25
13
N6
P48
41
36
26
14
L6
L6
P49
42
37
27
15
M7
K6
P4B
47
42
32
20
L7
L7
P4C
48
43
33
21
L8
K7
P4D
49
44
34
22
M9
M8
P4E
50
45
35
23
L9
L8
P50
2
2
2
80
C1
C1
P51
3
3
3
81
C2
C2
P52
4
4
4
82
C3
D1
P53
5
5
5
83
D1
D2
P54
6
6
6
84
D2
D3
P55
7
7
7
85
E1
E1
P56
General-purpose I/O port 5
8
8
8
86
E2
E2
P57
9
-
-
-
-
E3
P58
10
-
-
-
-
E4
P59
11
-
-
-
-
F1
P5A
12
-
-
-
-
F2
P5B
13
-
-
-
-
F3
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
LQFP
P30
P37
GPIO
Function Description
41
D a t a S h e e t
Pin
Function
Pin No
Pin Name
100
112
144
76
74
B3
B3
P61
115
95
75
73
B4
B4
P62
114
94
74
72
B5
C4
P63
113
93
73
71
C5
B5
112
-
-
-
-
C5
P65
111
-
-
-
-
D5
P66
110
-
-
-
-
A6
P67
109
-
-
-
-
B6
P68
108
-
-
-
-
C6
P70
51
-
-
-
-
K8
52
-
-
-
-
L9
53
-
-
-
-
K9
P73
54
-
-
-
-
M10
P74
55
-
-
-
-
L10
P80
118
98
78
76
A3
A3
119
99
79
77
A2
A2
56
46
36
24
M10
N10
58
48
38
26
N11
N11
PE3
59
49
39
27
N12
N12
SIN0_0
88
73
59
51
C13
D11
65
55
44
33
K12
J12
87
72
58
50
D12
D12
66
56
45
34
J13
J11
86
71
57
49
D13
D13
67
57
46
35
J12
J10
96
81
66
59
A9
D9
62
52
41
30
L13
L12
97
82
67
60
B9
C9
63
53
42
31
L12
K12
98
83
-
61
C9
B9
64
54
43
32
K13
K11
SIN0_1
SOT0_0
(SDA0_0)
General-purpose I/O port 6
General-purpose I/O port 7
General-purpose I/O port 8
(SDA0_1)
SCK0_0
SCK0_1
(SCL0_1)
SIN1_0
SIN1_1
SOT1_0
(SDA1_0)
Serial
1
General-purpose I/O port E
Multi-function serial interface ch.0 input pin
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
SOT0_1
(SCL0_0)
function
BGA
80
PE2
Multi-
BGA
96
P81
0
QFP
100
PE0
Serial
LQFP
116
P72
function
LQFP
120
P71
Multi-
LQFP
P60
P64
GPIO
Function Description
as SDA0 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.0 clock I/O
pin.
This pin operates as SCK0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SCL0 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.1 input pin
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
SOT1_1
(SDA1_1)
as SDA1 when it is used in an I2C (operation
mode 4).
SCK1_0
Multi-function serial interface ch.1 clock I/O
(SCL1_0)
pin.
This pin operates as SCK1 when it is used in a
42
CONFIDENTIAL
SCK1_1
CSIO (operation modes 4) and as SCL1 when
(SCL1_1)
it is used in an I2C (operation mode 4).
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Pin
Function
Pin No
Pin Name
Function Description
LQFP
LQFP
LQFP
QFP
BGA
BGA
120
100
80
100
112
144
53
-
-
-
-
K9
85
-
-
-
-
E10
68
58
47
36
J11
H12
54
-
-
-
-
M10
84
-
-
-
-
E11
mode 4).
69
59
48
37
H12
H11
Multi-function serial interface ch.2 clock I/O
55
-
-
-
-
L10
83
-
-
-
-
E12
74
64
53
42
H11
H10
SIN2_0
SIN2_1
Multi-function serial interface ch.2 input pin
SIN2_2
SOT2_0
(SDA2_0)
Multifunction
Serial
2
SOT2_1
(SDA2_1)
SOT2_2
(SDA2_2)
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
SCK2_2
(SCL2_2)
SIN3_0
SIN3_1
SOT3_0
(SDA3_0)
Multifunction
Serial
3
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
2
as SDA2 when it is used in an I C (operation
pin.
This pin operates as SCK2 when it is used in a
CSIO (operation modes 2) and as SCL2 when
it is used in an I2C (operation mode 4).
Multi-function serial interface ch.3 input pin
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in a
110
-
-
-
-
A6
15
10
10
88
F1
G1
109
-
-
-
-
B6
16
11
11
89
F2
G2
108
-
-
-
-
C6
17
12
12
90
F3
G3
UART/CSIO/LIN (operation modes 0 to 3) and
SOT3_1
(SDA3_1)
as SDA3 when it is used in an I2C (operation
mode 4).
SCK3_0
Multi-function serial interface ch.3 clock I/O
(SCL3_0)
pin.
This pin operates as SCK3 when it is used in a
SCK3_1
CSIO (operation modes 2) and as SCL3 when
(SCL3_1)
it is used in an I2C (operation mode 4).
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
43
D a t a S h e e t
Pin
Function
Pin No
Pin Name
Function Description
LQFP
LQFP
LQFP
QFP
BGA
BGA
120
100
80
100
112
144
6
6
6
84
D2
D3
75
65
54
43
G12
G12
10
-
-
-
-
E4
5
5
5
83
D1
D2
76
66
55
44
G11
G11
mode 4).
11
-
-
-
-
F1
Multi-function serial interface ch.4 clock I/O
4
4
4
82
C3
D1
77
67
56
45
F12
G10
12
-
-
-
-
F2
2
2
2
80
C1
C1
78
68
-
46
F11
F13
SIN4_0
SIN4_1
Multi-function serial interface ch.4 input pin
SIN4_2
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
Multifunction
Serial
4
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
CTS4_0
CTS4_1
CTS4_2
RTS4_0
RTS4_1
RTS4_2
Multi-function serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
2
as SDA4 when it is used in an I C (operation
pin.
This pin operates as SCK4 when it is used in a
CSIO (operation modes 2) and as SCL4 when
it is used in an I2C (operation mode 4).
Multi-function serial interface ch.4 CTS input
pin
Multi-function serial interface ch.4 RTS output
pin
(SDA5_0)
Multifunction
Serial
5
SOT5_1
(SDA5_1)
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_1
(SCL5_1)
SCK5_2
(SCL5_2)
44
CONFIDENTIAL
-
-
-
F3
3
3
81
C2
C2
79
69
-
47
E12
F12
14
9
9
87
E3
F4
94
74
72
B5
C4
113
-
-
-
-
B5
20
15
-
93
G3
H2
115
95
75
73
B4
B4
112
-
-
-
-
C5
mode 4).
21
16
-
94
H2
H3
Multi-function serial interface ch.5 clock I/O
116
96
76
74
B3
B3
111
-
-
-
-
D5
22
17
-
95
H3
H4
Multi-function serial interface ch.5 input pin
SIN5_2
SOT5_0
-
3
114
SIN5_0
SIN5_1
13
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SDA5 when it is used in an I2C (operation
pin.
This pin operates as SCK5 when it is used in a
CSIO (operation modes 2) and as SCL5 when
it is used in an I2C (operation mode 4).
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Pin
Function
Pin No
Pin Name
SIN6_0
SIN6_1
SOT6_0
(SDA6_0)
Function Description
Multi-function serial interface ch.6 input pin
Multi-function serial interface ch.6 output pin.
This pin operates as SOT6 when it is used in a
LQFP
LQFP
LQFP
QFP
BGA
BGA
120
100
80
100
112
144
7
7
7
85
E1
E1
95
80
65
58
A10
B10
8
8
8
86
E2
E2
94
79
64
57
B10
A11
9
-
-
-
-
E3
93
78
63
56
B11
C10
92
77
62
55
A12
B13
101
86
-
64
C8
C8
50
45
35
23
L9
L8
100
85
-
63
B8
D8
49
44
34
22
M9
M8
99
84
-
62
A8
A9
48
43
33
21
L8
K7
47
42
32
20
L7
L7
UART/CSIO/LIN (operation modes 0 to 3) and
Multifunction
Serial
6
SOT6_1
(SDA6_1)
as SDA6 when it is used in an I2C (operation
mode 4).
SCK6_0
Multi-function serial interface ch.6 clock I/O
(SCL6_0)
pin.
This pin operates as SCK6 when it is used in a
SCK6_1
CSIO (operation modes 2) and as SCL6 when
(SCL6_1)
it is used in an I2C (operation mode 4).
SCS6_1
SIN7_0
SIN7_1
SOT7_0
(SDA7_0)
Multi-function serial interface ch.6 serial chip
select pin
Multi-function serial interface ch.7 input pin
Multi-function serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
SOT7_1
Multi-
(SDA7_1)
as SDA7 when it is used in an I2C (operation
mode 4).
function
Serial
7
SCK7_0
Multi-function serial interface ch.7 clock I/O
(SCL7_0)
pin.
This pin operates as SCK7 when it is used in a
SCK7_1
CSIO (operation modes 2) and as SCL7 when
(SCL7_1)
it is used in an I2C (operation mode 4).
SCS7_1
Multi-function serial interface ch.7 serial chip
select pin
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
45
D a t a S h e e t
Pin
Function
Pin No
Pin Name
DTTI0X_0
Function Description
Input signal controlling wave form generator
LQFP
LQFP
LQFP
QFP
BGA
BGA
120
100
80
100
112
144
23
18
13
96
J1
J1
79
69
-
47
E12
F12
18
13
-
91
G1
G4
80
70
-
48
E11
F11
L12
outputs RTO00 to RTO05 of Multi-function
DTTI0X_1
FRCK0_0
FRCK0_1
FRCK0_2
52
41
30
L13
22
17
-
95
H3
H4
IC00_1
75
65
54
43
G12
G12
IC00_2
63
53
42
31
L12
K12
IC01_0
21
16
-
94
H2
H3
76
66
55
44
G11
G11
64
54
43
32
K13
K11
20
15
-
93
G3
H2
IC02_0
IC02_1
Multi-function timer 0.
ICxx describes channel number.
77
67
56
45
F12
G10
65
55
44
33
K12
J12
IC03_0
19
14
-
92
G2
H1
IC03_1
78
68
-
46
F11
F13
IC03_2
66
56
45
34
J13
J11
24
19
14
97
J2
J2
86
71
57
49
D13
D13
25
20
15
98
J3
J3
85
-
-
-
-
E10
26
21
16
99
K1
J4
84
-
-
-
-
E11
27
22
17
100
K2
K2
83
-
-
-
-
E12
28
23
18
1
L1
K3
82
-
-
-
-
E13
29
24
19
2
L2
L1
81
-
-
-
-
F10
(PPG00_0)
function
RTO00_1
Timer
(PPG00_1)
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
RTO02_0
(PPG02_0)
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
RTO05_1
(PPG04_1)
CONFIDENTIAL
16-bit input capture ch.0 input pin of
IC02_2
RTO00_0
46
pin
62
IC01_2
0
16-bit free-run timer ch.0 external clock input
IC00_0
IC01_1
Multi-
timer 0.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Pin
Function
Pin No
Pin Name
DTTI1X_0
Function Description
Input signal controlling wave form generator
LQFP
LQFP
LQFP
QFP
BGA
BGA
120
100
80
100
112
144
8
8
8
86
E2
E2
outputs RTO10 to RTO15 of Multi-function
DTTI1X_1
timer 1.
55
-
-
-
-
L10
FRCK1_0
16-bit free-run timer ch.1 external clock input
96
81
66
59
A9
D9
FRCK1_1
pin
50
45
35
23
L9
L8
IC10_0
95
80
65
58
A10
B10
IC10_1
54
-
-
-
-
M10
94
79
64
57
B10
A11
IC11_0
IC11_1
IC12_0
IC12_1
1
-
-
-
K9
78
63
56
B11
C10
-
-
-
-
L9
77
62
55
A12
B13
IC13_1
51
-
-
-
-
K8
2
2
2
80
C1
C1
32
27
-
5
N2
N2
3
3
3
81
C2
C2
33
28
-
6
N3
L2
4
4
4
82
C3
D1
34
29
-
7
M3
N3
5
5
5
83
D1
D2
35
30
-
8
L3
M3
6
6
6
84
D2
D3
36
31
21
9
M4
L4
7
7
7
85
E1
E1
37
32
22
10
L5
K5
(PPG10_1)
RTO11_0
(PPG10_0)
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
RTO14_1
(PPG14_1)
RTO15_0
(PPG14_0)
RTO15_1
(PPG14_1)
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
-
93
92
RTO10_1
Timer
ICxx describes channel number.
53
52
RTO10_0
function
Multi-function timer 1.
IC13_0
(PPG10_0)
Multi-
16-bit input capture ch.1 input pin of
47
D a t a S h e e t
Pin No
Pin Function
Pin Name
Function Description
AIN0_0
AIN0_1
QPRC ch.0 AIN input pin
LQFP
LQFP
LQFP
QFP
BGA
BGA
120
100
80
100
112
144
24
19
14
97
J2
J2
51
-
-
-
-
K8
Quadrature
AIN0_2
2
2
2
80
C1
C1
Position/
BIN0_0
25
20
15
98
J3
J3
Revolution
BIN0_1
52
-
-
-
-
L9
Counter
BIN0_2
3
3
3
81
C2
C2
0
ZIN0_0
26
21
16
99
K1
J4
ZIN0_1
QPRC ch.0 BIN input pin
53
-
-
-
-
K9
ZIN0_2
4
4
4
82
C3
D1
AIN1_0
10
-
-
-
-
E4
89
74
-
52
C12
C12
48
43
33
21
L8
K7
AIN1_1
Quadrature
AIN1_2
Position/
BIN1_0
Revolution
BIN1_1
Counter
BIN1_2
1
ZIN1_0
ZIN1_1
QPRC ch.0 ZIN input pin
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
ZIN1_2
RTCCO_0
RTCCO_1
Real-time
RTCCO_2
clock
SUBOUT_0
0.5 seconds pulse output pin of Real-time
clock
Mode
DAC
49
44
34
22
M9
M8
12
-
-
-
-
F2
87
72
-
50
D12
D12
50
45
35
23
L9
L8
115
95
75
73
B4
B4
64
54
43
32
K13
K11
96
J1
J1
73
B4
B4
Sub clock output pin
64
54
43
32
K13
K11
23
18
13
96
J1
J1
UDM0
USB function/host D – pin
118
98
78
76
A3
A3
UDP0
USB function/host D + pin
119
99
79
77
A2
A2
USB external pull-up control pin
115
95
75
73
B4
B4
WKUP0
Deep standby mode return signal input pin 0
116
96
76
74
B3
B3
WKUP1
Deep standby mode return signal input pin 1
14
9
9
87
E3
F4
WKUP2
Deep standby mode return signal input pin 2
50
45
35
23
L9
L8
WKUP3
Deep standby mode return signal input pin 3
69
59
48
37
H12
H11
DA0
D/A converter ch.0 analog output pin
36
31
21
9
M4
L4
DA1
D/A converter ch.1 analog output pin
37
32
22
10
L5
K5
On-board regulator control pin
41
36
26
14
L6
L6
42
37
27
15
M7
K6
92
77
62
55
A12
B13
93
78
63
56
B11
C10
VWAKEUP
The return signal input pin from a hibernation
state
SD memory card interface
SD memory card clock output pin
SD memory card interface
SD memory card command output
S_DATA1_0
94
79
64
57
B10
A11
S_DATA0_0
SD memory card interface
95
80
65
58
A10
B10
S_DATA3_0
SD memory card data bus
96
81
66
59
A9
D9
97
82
67
60
B9
C9
113
93
73
71
C5
B5
114
94
74
72
B5
C4
S_DATA2_0
S_CD_0
S_WP_0
CONFIDENTIAL
D11
75
S_CMD_0
48
F1
C13
13
S_CLK_0
SD I/F
-
51
95
VREGCTL
VBAT
-
-
18
UHCONX0
Consumption
-
23
SUBOUT_2
Low-Power
73
115
SUBOUT_1
USB
11
88
SD memory card interface
SD memory card detection pin
SD memory card interface
SD memory card write protection
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Pin No
Pin Function
RESET
Pin Name
INITX
Function Description
External Reset Input pin.
A reset is valid when INITX="L".
LQFP
LQFP
LQFP
QFP
BGA
BGA
120
100
80
100
112
144
38
33
23
11
M6
N4
56
46
36
24
M10
N10
57
47
37
25
M11
M11
Mode 1 pin.
MD1
During serial programming to Flash memory,
MD1="L" must be input.
MODE
Mode 0 pin.
MD0
During normal operation, MD0="L" must be
input. During serial programming to Flash
memory, MD0="H" must be input.
POWER
VCC
USBVCC
GND
VSS
Power supply Pin
3.3 V Power supply port for USB I/O
GND Pin
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
1
1
1
79
B1
B1
31
26
-
4
M1
M1
46
41
31
19
M8
M9
61
51
-
29
M13
M13
91
76
61
54
B13
A12
A4
117
97
77
75
A4
107
92
-
70
A5
A7
30
25
20
3
N1
N1
45
40
30
18
N10
N9
60
50
40
28
N13
N13
90
75
60
53
A13
A13
120
100
80
78
A1
A1
-
-
-
-
A7
A5
-
-
-
-
B2
A8
-
-
-
-
B12
A10
-
-
-
-
C11
B2
-
-
-
-
H1
B11
-
-
-
-
N4
B12
-
-
-
-
M5
C3
-
-
-
-
N7
C11
-
-
-
-
L11
C13
-
-
-
-
A11
D4
-
-
-
-
M12
D10
-
-
-
-
M2
K1
-
-
-
-
-
K4
-
-
-
-
-
K10
-
-
-
-
-
L3
-
-
-
-
-
L5
-
-
-
-
-
L11
-
-
-
-
-
L13
-
-
-
-
-
M2
-
-
-
-
-
M4
-
-
-
-
-
M6
-
-
-
-
-
M7
-
-
-
-
-
M12
-
-
-
-
-
N6
49
D a t a S h e e t
Pin No
Pin Function
CLOCK
Pin Name
ADC
GND
C pin
50
CONFIDENTIAL
QFP
BGA
BGA
100
80
100
112
144
58
48
38
26
N11
N11
X1
Main clock (oscillation) I/O pin
59
49
39
27
N12
N12
X0A
Sub clock (oscillation) input pin
39
34
24
12
N5
N5
X1A
Sub clock (oscillation) I/O pin
40
35
25
13
N6
M5
AVRL
AVRH
POWER
LQFP
120
AVCC
VBAT
LQFP
Main clock (oscillation) input pin
CROUT_1
ADC
LQFP
X0
CROUT_0
POWER
Function Description
Built-in high-speed CR-osc clock output port
A/D converter and D/A converter
analog power supply pin
A/D converter analog reference voltage input
pin
A/D converter analog reference voltage input
pin
87
72
58
50
D12
D12
113
93
73
71
C5
B5
70
60
49
38
H13
K13
72
62
51
40
F13
H13
73
63
52
41
E13
G13
43
38
28
16
N8
N7
71
61
50
39
G13
J13
44
39
29
17
N9
N8
VBAT power supply pin.
VBAT
Backup power supply (battery etc.) and system
power supply.
AVSS
C
A/D converter and D/A converter
GND pin
Power supply stabilization capacity pin
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
7.
I/O Circuit Type
Type
Circuit
P-ch
P-ch
Remarks
Digital output
X1
N-ch
Digital output
R
It is possible to select the main
oscillation / GPIO function
Pull-up resistor control
When the main oscillation is
Digital input
selected.
−
Standby mode control
Clock input
A
Oscillation feedback resistor
: Approximately 1 MΩ
−
With Standby mode control
When the GPIO is selected.
Standby mode control
Digital input
−
CMOS level output.
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
Standby mode control
−
IOH = -4 mA, IOL = 4 mA
−
CMOS level hysteresis input
−
Pull-up resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
B
Pull-up resistor
Digital input
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
: Approximately 50 kΩ
51
D a t a S h e e t
Type
Circuit
Remarks
Digital input
C
Digital output
N-ch
P-ch
P-ch
E
N-ch
−
Open drain output
−
CMOS level hysteresis input
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Digital output
Digital output
R
: Approximately 50 kΩ
−
IOH = -4 mA, IOL = 4 mA
−
CMOS level output
−
CMOS level hysteresis input
−
With input control
−
Analog input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Pull-up resistor control
Digital input
Standby mode control
P-ch
P-ch
N-ch
Digital output
Digital output
F
Pull-up resistor control
R
Digital input
: Approximately 50 kΩ
−
IOH = -4 mA, IOL = 4 mA
Standby mode control
Analog input
Input control
52
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Type
Circuit
P-ch
Remarks
Digital output
P-ch
G
N-ch
Digital output
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
R
: Approximately 50 kΩ
−
IOH = -12 mA, IOL = 12 mA
Pull-up resistor
control
Digital input
Standby mode
control
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
It is possible to select the USB I/O /
UDP output
UDP/Pxx
GPIO function.
USB Full-speed/Low-speed control
UDP input
When the USB I/O is selected.
−
H
Differential
UDM/Pxx
Full-speed, Low-speed control
Differential input
USB/GPIO select
UDM input
UDM output
When the GPIO is selected.
−
CMOS level output
−
CMOS level hysteresis input
−
With standby mode control
−
IOH = -20.5 mA, IOL = 18.5 mA
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
53
D a t a S h e e t
Type
Circuit
P-ch
P-ch
I
N-ch
Remarks
Digital output
Digital output
R
−
CMOS level output
−
CMOS level hysteresis input
−
5 V tolerant
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
−
IOH = -4 mA, IOL = 4 mA
−
Available to control of PZR
registers.
Pull-up resistor
control
Digital input
Standby mode control
J
Mode input
P-ch
L
P-ch
N-ch
CMOS level hysteresis input
Digital output
Digital output
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
−
R
IOH = -8 mA, IOL = 8 mA
Pull-up resistor
control
Digital input
Standby mode
control
54
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Type
Circuit
P-ch
P-ch
N-ch
Remarks
Digital output
Digital output
M
Pull-up resistor
control
Digital input
R
−
CMOS level output
−
CMOS level hysteresis input
−
With input control
−
Analog input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
−
IOH = -8 mA, IOL = 8 mA
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Standby mode
control
Analog input
Input control
P-ch
N
P-ch
N-ch
Digital output
Digital output
: Approximately 50 kΩ
−
IOH = -4 mA, IOL = 4 mA
(GPIO)
−
R
Pull-up resistor
control
IOL = 20 mA
(Fast Mode Plus)
Digital input
Standby mode
control
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
55
D a t a S h e e t
Type
Circuit
P-ch
P-ch
O
N-ch
Remarks
Pull-up resistor
control
Digital output
Digital output
−
CMOS level output
−
CMOS level hysteresis input
−
5 V tolerant
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
−
IOH = -4 mA, IOL = 4 mA
−
For I/O setting, refer to VBAT
Domain in the Peripheral Manual
R
Digital input
Standby mode
control
P-ch
X0A
P-ch
N-ch
P
Pull-up resistor
control
Digital output
Digital output
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
−
IOH = -4 mA, IOL = 4 mA
−
For I/O setting, refer to VBAT
Domain in the Peripheral Manual
R
Digital input
Standby mode
control
OSC
56
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Type
Circuit
Remarks
It is possible to select the sub
Pull-up resistor
control
Digital output
P-ch
P-ch
X1A
oscillation / GPIO function
When the sub oscillation is selected.
−
Oscillation feedback resistor
: Approximately 10 MΩ
Digital output
N-ch
Q
R
Digital input
Standby mode
control
OSC
RX
−
With Standby mode control
−
When the GPIO is selected.
−
CMOS level output.
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
−
IOH = -4 mA, IOL = 4 mA
−
For I/O setting, refer to VBAT
Domain in the Peripheral Manual
Standby mode
control
Clock input
P-ch
P-ch
N-ch
Pull-up resistor
control
Digital output
Digital output
R
−
CMOS level output
−
CMOS level hysteresis input
−
Analog output
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
−
IOH = -12 mA, IOL = 12 mA
(4.5 V to 5.5 V)
R
−
Digital input
IOH = -8 mA, IOL = 8 mA
(2.7 V to 4.5 V)
Standby mode
control
Analog output
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
57
D a t a S h e e t
8.
Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
8.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try
to prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground
pin.
Code: DS00-00004-3E
58
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be
formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include
attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage
or loss from such failures by incorporating safety design measures into your facility and equipment such as
redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office
automation and other office equipment, industrial, communications, and measurement equipment, personal
or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal
operation may directly affect human lives or cause physical injury or property damage, or where extremely
high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with
sales representatives before such use. The company will not be responsible for damages arising from such
use without prior approval.
8.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat
resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board
and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering
process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage
temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
59
D a t a S h e e t
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads
are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results
in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and have
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To
prevent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for
storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for
ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize
shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board
assemblies.
60
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
8.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If
high humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near
combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic
gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
61
D a t a S h e e t
9.
Handling Devices
Power Supply Pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within
the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected
externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent
abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total
output current rating.
Moreover, connect the current supply source with each POWER pins and GND pins of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between VCC and VSS near this device.
Power Supply Pins
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is
within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization,
suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial
frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate
does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power supply.
Crystal Oscillator Circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to
ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub Crystal Oscillator
This series sub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the
oscillation.
− Surface mount type
Size
Load capacitance
− Lead type
Load capacitance
62
CONFIDENTIAL
: More than 3.2 mm × 1.5 mm
: Approximately 6 pF to 7 pF
: Approximately 6 pF to 7 pF
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Using an External Clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input
the clock to X0. X1 (PE3) can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input,
and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Set as External
clock input
Can be used as
general-purpose
I/O ports.
X1(PE3), X1A (P47)
2
Handling when Using Multi-function Serial Pin as I C Pin
2
If it is using the multi-function serial pin as I C pins, P-ch transistor of digital output is always disabled.
2
However, I C pins need to keep the electrical characteristic like other pins and not to connect to the external
2
I C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency
characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to
thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the
specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode Pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS
pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as
for switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
63
D a t a S h e e t
Notes on Power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.
Turning on:
VBAT → VCC → USBVCC
VCC → AVCC → AVRH
Turning off:
USBVCC → VCC → VBAT
AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
Differences in Features among the Products with Different Memory Sizes and between
Flash Products and MASK Products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash products and
MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
Pull-Up Function of 5 V Tolerant I/O
Please do not input the signal more than VCC voltage at the time of pull-up function use of 5V tolerant I/O.
Adjoining Wiring on Circuit Board
If wiring of the crystal oscillation circuit X1A adjoins and also runs in parallel with the wiring of
P48/VREGCTL, there is a possibility that the oscillation erroneously counts because X1A has noise with the
change of P48/VREGCTL. Keep as much distance as possible between both wirings and insert the ground
pattern between them in order to avoid this possibility.
Device
P46/
X0A
P47/
X1A
P48/
P49/
VREGCTL VWAKEUP
Not allowed to run
both wirings in parallel
Ground
Insert the ground pattern
Handling when Using Debug Pins
When debug pins (TDO/TMS/TDI/TCK/TRSTX or SWO/SWDIO/SWCLK) are set to GPIO or other
peripheral functions, only set them as output, do not set them as input.
64
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
10. Block Diagram
MB9BF566M/N/R, F567M/N/R, F568M/N/R
TRSTX,TCK,
TDI,TMS
TDO
SWJ-DP
ETM*
TRACEDx,
TRACECLK
TPIU*
ROM
Table
SRAM0
32/48/64 Kbytes
SRAM1
16/24/32 Kbytes
Cortex-M4 Core I
@160 MHz(Max)
D
MPU NVIC
Multi-layer AHB (Max 160 MHz)
FPU
Sys
AHB-APB Bridge:
APB0(Max 80 MHz)
Dual-Timer
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardware)
CSV
SRAM2
16/24/32 Kbytes
MainFlash I/F
MainFlash
1 Mbytes/
768 Kbytes/
512 Kbytes
Trace Buffer
(16 Kbytes)
Security
WorkFlash
32 Kbytes
WorkFlash I/F
USB2.0
(Host/
Func)
PHY
USBVCC
UDP0,UDM0
UHCONX0
DMAC
8ch.
CLK
DSTC
SD-CARD I/F
CAN
X0A
X1A
Main
Osc
PLL
VBAT Domain
Sub
Osc
AHB-AHB Bridge
Source Clock
X0
X1
CR
100 kHz
CR
4 MHz
CAN
GPIO
PIN-Function-Ctrl
CROUT
S_CLK,S_CMD
S_DATAx
S_CD,S_WP
TX0,
RX0
TX1,
RX1
P0x,
P1x,
.
.
.
PEx
MADx
AVCC,
AVSS,
AVRH
ANxx
ADTGx
External Bus I/F
Unit 1
CAN Prescaler
QPRC
2ch.
A/D Activation Compare
6ch.
IC0x
FRCK0
16-bit Input Capture
4ch.
16-bit Free-run Timer
3ch.
16-bit Output Compare
6ch.
DTTI0X
RTO0x
Waveform Generator
3ch.
16-bit PPG
3ch.
Multi-function Timer × 2
AHB-APB Bridge : APB2 (Max 80 MHz)
AINx
BINx
ZINx
Base Timer
16-bit 16ch./
32-bit 8ch.
AHB-APB Bridge : APB1 (Max 160 MHz)
TIOBx
MCSXx,MDQMx,
MOEX,MWEX,
MALE,MRDY,
MNALE,MNCLE,
MNWEX,MNREX,
MCLKOUT,MSDWEX,
MSDCLK,MSDCKE,
MRASX,MCASX
Unit 2
USB Clock Ctrl
TIOAx
MADATAx
12-bit A/D Converter
Unit 0
PLL
Power-On
Reset
LVD Ctrl
LVD
IRQ-Monitor
Regulator
C
CRC Accelerator
Watch Counter
Deep Standby Ctrl
WKUPx
Peripheral Clock Gating
Low-speed CR Prescaler
VBAT Domain
Real-Time Clock
Port Ctrl.
VWAKEUP
VREGCTL
RTCCO,
SUBOUT
External Interrupt
Controller
16pin + NMI
INTx
NMIX
MODE-Ctrl
MD0,
MD1
Multi-function Serial I/F
8ch.
HW flow control(ch.4)
SCKx
SINx
SOTx
CTS4
RTS4
12-bit D/A Converter
2units
DAx
*: For the MB9BF566M, MB9BF567M and MB9BF568M, ETM is not available.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
65
D a t a S h e e t
11. Memory Size
See Memory size in 3. Product Lineup to confirm the memory size.
12. Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0x4007_0000
0x4006_F000
0x4006_E000
0x4006_4000
0xFFFF_FFFF
0x4006_3000
Reserved
0xE010_0000
0xE000_0000
0x4006_2000
0x4006_1000
Cortex-M4 Private
Peripherals
0x4006_0000
0x4005_0000
0x4004_0000
0x4003_F000
External Device
Area
0x4003_C800
0x4003_C100
GPIO
SD-Card I/F
Reserved
CAN ch.1
CAN ch.0
DSTC
DMAC
Reserved
USB ch.0
EXT-bus I/F
Reserved
Peripheral Clock Gating
0x4003_C000 Low Speed CR Prescaler
0x6000_0000
0x4003_7000
RTC/Port Ctrl
Watch Counter
CRC
MFS
CAN prescaler
0x4003_6000
USB Clock ctrl
0x4003_5000
0x4003_4000
LVD/DS mode
0x4003_B000
0x4003_A000
Reserved
0x4400_0000
0x4200_0000
0x4003_8000
32 Mbytes
Bit band alias
Peripherals
0x4000_0000
Reserved
0x2400_0000
0x2200_0000
0x200C_0000
0x2004_8000
0x2004_0000
0x2003_8000
See "lMemory Map (2)"
for the memory size
details.
0x2000_0000
0x1FFF_0000
0x0050_0000
0x0040_0000
Reserved
0x4003_1000
Int-Req.Read
EXTI
Reserved
CR Trim
0x4002_E000
Reserved
0x4002_8000
0x4002_F000
0x4002_7000
Reserved
SRAM2
SRAM1
Reserved
SRAM0
Reserved
Security/CR Trim
MainFlash
0x0000_0000
D/AC
0x4003_2000
32 Mbytes
Bit band alias
WorkFlash I/F
WorkFlash
0x4002_6000
0x4002_5000
0x4002_4000
0x4002_2000
0x4002_1000
0x4002_0000
0x4001_6000
0x4001_5000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
0x4000_1000
0x4000_0000
66
CONFIDENTIAL
Reserved
0x4003_3000
0x4003_0000
0x2010_0000
0x200E_0000
0x4003_9000
Reserved
A/DC
QPRC
Base Timer
PPG
Reserved
MFT Unit1
MFT Unit0
Reserved
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
MainFlash I/F
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Memory Map (2)
MB9BF568M/N/R
0x2008_0000
MB9BF567M/N/R
0x2008_0000
Reserved
0x200C_8000
0x200C_0000
0x2008_0000
Reserved
0x200C_8000
WorkFlash
32 Kbytes
MB9BF566M/N/R
0x200C_0000
Reserved
Reserved
0x200C_8000
WorkFlash
32 Kbytes
0x200C_0000
Reserved
0x2004_8000
WorkFlash
32 Kbytes
Reserved
0x2004_6000
SRAM2
32 Kbytes
0x2004_0000
0x2004_0000
SRAM1
32 Kbytes
0x2003_A000
SRAM2
24 Kbytes
SRAM1
24 Kbytes
0x2004_4000
0x2004_0000
0x2003_C000
SRAM2
16 Kbytes
SRAM1
16 Kbytes
0x2003_8000
0x2000_0000
0x2000_0000
SRAM0
64 Kbytes
Reserved
Reserved
Reserved
0x1FFF_4000
0x2000_0000
SRAM0
48 Kbytes
0x1FFF_8000
SRAM0
32 Kbytes
0x1FFF_0000
0x0050_0000
0x0040_2000
0x0040_0000
0x0050_0000
CR trimming
Security
Reserved
Reserved
Reserved
0x0040_2000
0x0040_0000
0x0050_0000
CR trimming
Security
0x0040_2000
0x0040_0000
CR trimming
Security
Reserved
Reserved
0x0010_0000
Reserved
0x000C_0000
MainFlash
1 Mbytes
0x0000_0000
0x0008_0000
MainFlash
768 Kbytes
0x0000_0000
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
MainFlash
512 Kbytes
0x0000_0000
67
D a t a S h e e t
Peripheral Address Map
Start address
End address
0x4000_0000
0x4000_0FFF
Bus
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
AHB
APB0
Peripherals
MainFlash I/F register
Reserved
Software Watchdog timer
Reserved
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function timer unit0
0x4002_1000
0x4002_1FFF
Multi-function timer unit1
0x4002_2000
0x4003_FFFF
Reserved
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
0x4002_6000
0x4002_6FFF
APB1
Base Timer
Quadrature Position/Revolution Counter
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Internal CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt Controller
0x4003_1000
0x4003_1FFF
Interrupt Request Batch-Read Function
0x4003_2000
0x4003_4FFF
Reserved
0x4003_3000
0x4003_3FFF
D/A Converter
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_57FF
Low Voltage Detector
0x4003_5800
0x4003_5FFF
Deep standby mode Controller
0x4003_6000
0x4003_6FFF
0x4003_7000
0x4003_7FFF
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
USB clock generator
APB2
CAN prescaler
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_BFFF
RTC/Port Ctrl
0x4003_C000
0x4003_C0FF
Low-speed CR Prescaler
0x4003_C100
0x4003_C7FF
Peripheral Clock Gating
0x4003_C800
0x4003_EFFF
Reserved
0x4003_F000
0x4003_FFFF
External Memory interface
0x4004_0000
0x4004_FFFF
USB ch.0
0x4005_0000
0x4005_FFFF
Reserved
0x4006_0000
0x4006_0FFF
DMAC register
0x4006_1000
0x4006_1FFF
DSTC register
0x4006_2000
0x4006_2FFF
0x4006_3000
0x4006_3FFF
CAN ch.0
AHB
CAN ch.1
0x4006_4000
0x4006_DFFF
Reserved
0x4006_E000
0x4006_EFFF
SD-Card I/F
0x4006_F000
0x4006_FFFF
GPIO
0x4006_7000
0x41FF_FFFF
Reserved
0x200E_0000
0x200E_FFFF
WorkFlash I/F register
68
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
13. Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the L level.
INITX=1
This is the period when the INITX pin is the H level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL)
is set to 0.
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL)
is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
Setting prohibition
Prohibition of a setting by specification limitation.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
69
D a t a S h e e t
List of Pin Status
Pin status Type
Power-on
Function
Reset or
INITX
Low-voltage
Input
Detection
State
State
Internal
Reset
State
Run
Mode
Timer Mode,
Deep Standby RTC
or Sleep
RTC Mode, or
Mode or Deep Standby
Mode
Stop Mode State
Stop Mode State
Power Supply
Power Supply
Stable
Stable
INITX=1
INITX=1
State
Return from
Deep
Standby
Mode State
Group
Power
Supply
Power Supply
Stable
Unstable
A
Device
Power
Supply
Stable
‐
INITX=0
INITX=1
INITX=1
‐
‐
‐
‐
GPIO
Setting
Setting
Setting
selected
disabled
disabled
disabled
SPL=0
Maintain
Maintain
previous
previous
state
state
SPL=1
Hi-Z /
Internal
input fixed
at 0
SPL=0
GPIO
selected
Internal
input fixed
at 0
Power
Supply
Stable
INITX=1
SPL=1
-
Hi-Z /
Internal
GPIO
input fixed
selected
at 0
Main crystal
oscillator
input pin/
External
main clock
Input
Input
Input
Input
Input
Input
Input
Input
Input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Maintain
Maintain
previous
previous
state
state
input
selected
GPIO
Setting
Setting
Setting
selected
disabled
disabled
disabled
External
B
main clock
Setting
Setting
Setting
input
disabled
disabled
disabled
selected
Maintain
Maintain
previous
previous
state
state
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Maintain
previous
state
Hi-Z /
Hi-Z /
Hi-Z /
Main crystal
Internal input
Internal
Internal
Maintain previous state /
oscillator
fixed at "0"/
input
input
When oscillation stops*1, Hi-Z /
output pin
or Input
fixed
fixed
Internal input fixed at 0
INITX
C
input pin
D
Hi-Z /
Internal
GPIO
input fixed
selected
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
enable
at 0
at 0
Pull-up /
Pull-up /
Pull-up /
Pull-up /
Pull-up /
Pull-up /
Pull-up /
Pull-up /
Pull-up /
Input
Input
Input
Input
Input
Input
Input
Input
Input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
70
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Run
Pin status Type
Power-on
Function
Group
Reset or
INITX
Low-voltage
Input
Detection
State
State
Power
Supply
Internal
or
Reset
SLEEP
State
Mode
Power Supply
Stable
TIMER Mode,
Deep Standby RTC
RTC Mode, or
Mode or Deep Standby
STOP Mode State
STOP Mode State
Power
Supply
Power Supply
Power Supply
Stable
Stable
Stable
Mode State
Power
Supply
Stable
INITX=0
INITX=1
INITX=1
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
input pin
enabled
enabled
enabled
enabled
enabled
enabled
GPIO
Setting
Setting
Setting
selected
disabled
disabled
disabled
NMIX
Setting
Setting
Setting
selected
disabled
disabled
disabled
other than
above
Hi-Z /
Hi-Z
GPIO
Hi-Z /
Input
Input
enabled
enabled
INITX=1
INITX=1
enabled
enabled
enabled
Maintain
Maintain
Hi-Z /
previous
previous
Input
state
state
enabled
GPIO
selected
INITX=1
Hi-Z /
Input
enabled
JTAG
selected
previous
state
Maintain
Maintain
WKUP
previous
previous
Hi-Z /
input
state
state
Internal
enabled
input fixed
Hi-Z /
WKUP
Hi-Z
input
enabled
Maintain
at 0
previous
Pull-up /
Pull-up /
Maintain
Maintain
Maintain
Maintain
Input
Input
previous
previous
previous
previous
enabled
enabled
state
state
state
state
GPIO
Setting
Setting
Setting
selected
disabled
disabled
disabled
Maintain
Maintain
previous
previous
Hi-Z /
state
state
Internal
input fixed
at 0
selected
Pull-up /
Hi-Z
at 0
Maintain
Input
Input
previous
previous
previous
previous
enabled
enabled
state
state
state
state
previous
previous
Hi-Z /
state
state
Internal
above
Setting
Setting
Setting
selected
disabled
disabled
disabled
input fixed
at 0
GPIO
selected
Resource
Hi-Z /
Hi-Z /
Maintain
Maintain
Input
Input
previous
previous
enabled
enabled
state
state
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
at 0
selected
Maintain
other than
selected
input fixed
GPIO
input fixed
Maintain
Maintain
Hi-Z
Internal
Hi-Z /
Internal
Maintain
Maintain
selected
GPIO
selected
Pull-up /
Resource
GPIO
GPIO
selected
state
G
JTAG
GPIO
selected
Maintain
selected
I
Deep
Standby
‐
selected
H
Return from
‐
Resource
F
Mode
State
Unstable
E
Device
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
GPIO
input fixed
selected
at 0
Hi-Z /
Internal
GPIO
input fixed
selected
at 0
71
D a t a S h e e t
Pin status Type
Power-on
Reset or
INITX
Low-voltage
Input
Detection
State
Function
State
Group
Power
Supply
output
selected
Internal
Reset
State
Power Supply
Stable
Unstable
Analog
Device
selected
Deep Standby RTC
or Sleep
RTC Mode, or
Mode or Deep Standby
Mode
Stop Mode State
Stop Mode State
Power Supply
Power Supply
Stable
Stable
INITX=1
INITX=1
State
Power
Supply
‐
INITX=0
INITX=1
INITX=1
‐
‐
‐
‐
Setting
Setting
Setting
disabled
disabled
disabled
SPL=0
SPL=1
*2
*3
Hi-Z
GPIO
Hi-Z /
Hi-Z /
Input
Input
enabled
enabled
SPL=0
GPIO
Maintain
other than
above
Timer Mode,
Stable
Resource
J
Run
Mode
previous
state
selected
Maintain
previous
state
Hi-Z /
Internal
Internal
input fixed
input fixed
at 0
Return from
Deep
Standby
Mode State
Power
Supply
Stable
INITX=1
SPL=1
-
Hi-Z /
Internal
GPIO
input fixed
selected
at 0
at 0
selected
External
interrupt
Setting
Setting
Setting
enabled
disabled
disabled
disabled
selected
Resource
K
other than
above
selected
Hi-Z
GPIO
Hi-Z /
Hi-Z /
Input
Input
enabled
enabled
Maintain
previous
state
Maintain
Maintain
previous
previous
state
state
GPIO
selected
Hi-Z /
Internal
input fixed
Internal
input fixed
at 0
Hi-Z /
Internal
GPIO
input fixed
selected
at 0
at 0
selected
Analog input
selected
Hi-Z
L
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
input
input
input
fixed at
fixed at
fixed
0/
0/
at 0 /
Analog
Analog
Analog
input
input
input
enabled
enabled
enabled
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
input fixed
input fixed
input fixed
input fixed
input fixed
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
Resource
other than
above
Setting
Setting
Setting
selected
disabled
disabled
disabled
GPIO
selected
72
CONFIDENTIAL
Maintain
Maintain
previous
previous
state
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
GPIO
input fixed
selected
at 0
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Pin status Type
Power-on
Reset or
INITX
Low-voltage
Input
Detection
State
Function
State
Group
Power
Supply
‐
Analog input
selected
M
Hi-Z
Internal
Reset
State
Power Supply
Stable
Unstable
‐
Device
INITX=0
Run
Mode
Timer Mode,
Deep Standby RTC
or Sleep
RTC Mode, or
Mode or Deep Standby
Mode
Stop Mode State
Stop Mode State
Power Supply
Power Supply
Stable
Stable
INITX=1
INITX=1
State
Power
Supply
Stable
INITX=1
INITX=1
‐
‐
‐
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
input
input
input
fixed
fixed
fixed
at 0 /
at 0 /
at 0 /
Analog
Analog
Analog
input
input
input
enabled
enabled
enabled
SPL=0
SPL=1
SPL=0
Return from
Deep
Standby
Mode State
Power
Supply
Stable
INITX=1
SPL=1
-
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
input fixed
input fixed
input fixed
input fixed
input fixed
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
External
Maintain
interrupt
previous
enabled
state
selected
Resource
Setting
Setting
Setting
other than
disabled
disabled
disabled
above
GPIO
Maintain
Maintain
selected
previous
previous
Internal
state
state
Hi-Z /
Internal
selected
input fixed
GPIO
at 0
input fixed
at 0
Hi-Z /
Internal
GPIO
input fixed
selected
at 0
selected
Analog input
selected
N
Hi-Z
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
input
input
input
fixed
fixed
fixed
at 0 /
at 0 /
at 0 /
Analog
Analog
Analog
input
input
input
enabled
enabled
enabled
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
input fixed
input fixed
input fixed
input fixed
input fixed
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
Trace
Trace
selected
output
Resource
other than
Setting
Setting
Setting
above
disabled
disabled
disabled
selected
GPIO
Maintain
Maintain
previous
previous
state
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
GPIO
input fixed
selected
at 0
selected
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
73
D a t a S h e e t
Pin status Type
Power-on
Reset or
INITX
Low-voltage
Input
Detection
State
Function
State
Group
Power
Supply
‐
Analog input
selected
O
Hi-Z
Internal
Reset
State
Power Supply
Stable
Unstable
‐
Device
INITX=0
Run
Mode
Timer Mode,
Deep Standby RTC
or Sleep
RTC Mode, or
Mode or Deep Standby
Mode
Stop Mode State
Stop Mode State
Power Supply
Power Supply
Stable
Stable
INITX=1
INITX=1
State
Power
Supply
Stable
INITX=1
INITX=1
‐
‐
‐
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
input
input
input
fixed
fixed
fixed
at 0 /
at 0 /
at 0 /
Analog
Analog
Analog
input
input
input
enabled
enabled
enabled
SPL=0
SPL=1
SPL=0
Return from
Deep
Standby
Mode State
Power
Supply
Stable
INITX=1
SPL=1
-
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
input fixed
input fixed
input fixed
input fixed
input fixed
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
Trace
Trace
selected
output
External
Maintain
interrupt
enabled
selected
Setting
Setting
Setting
Resource
disabled
disabled
disabled
other than
Maintain
Maintain
previous
previous
state
state
previous
GPIO
state
selected
Internal
Hi-Z /
above
Internal
selected
input fixed
GPIO
at 0
input fixed
at 0
Hi-Z /
Internal
GPIO
input fixed
selected
at 0
selected
Analog input
selected
P
Hi-Z
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
input
input
input
fixedat
fixedat
fixed
0/
0/
at 0 /
Analog
Analog
Analog
input
input
input
enabled
enabled
enabled
Hi-Z /
above
Setting
Setting
Setting
disabled
disabled
disabled
Internal
Internal
Internal
Internal
input fixed
input fixed
input fixed
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
Maintain
WKUP
Hi-Z /
previous
input
WKUP input
state
enabled
enabled
Maintain
Maintain
previous
previous
Hi-Z /
state
state
Internal
input fixed
GPIO
at 0
74
CONFIDENTIAL
Hi-Z /
input fixed
selected
selected
Hi-Z /
Internal
enabled
Resource
Hi-Z /
input fixed
WKUP
other than
Hi-Z /
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
GPIO
selected
input fixed
at 0
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Pin status Type
Power-on
Reset or
INITX
Low-voltage
Input
Detection
State
Function
State
Group
Power
Supply
Device
Internal
Reset
State
Power Supply
Stable
Unstable
Run
Mode
Timer Mode,
Deep Standby RTC
or Sleep
RTC Mode, or
Mode or Deep Standby
Mode
Stop Mode State
Stop Mode State
Power Supply
Power Supply
Stable
Stable
INITX=1
INITX=1
State
Power
Supply
Stable
‐
INITX=0
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
Return from
Deep
Standby
Mode State
Power
Supply
Stable
INITX=1
SPL=1
-
Hi-Z /
WKUP
WKUP input
enabled
External
Setting
Setting
Setting
disabled
disabled
disabled
interrupt
Q
enabled
selected
Resource
other than
above
selected
Hi-Z
GPIO
Maintain
enabled
WKUP
input
enabled
previous
state
Maintain
Maintain
previous
previous
GPIO
state
state
selected
Hi-Z /
Hi-Z /
Hi-Z /
Input
Input
enabled
enabled
Hi-Z /
Hi-Z /
Maintain
Input
Input
previous
enabled
enabled
state
Internal
input fixed
Internal
input fixed
at 0
GPIO
Hi-Z /
selected
Internal
input fixed
at 0
at 0
selected
GPIO
selected
Hi-Z
Maintain
R
previous
state
USB I/O pin
Setting
Setting
Setting
disabled
disabled
disabled
Hi-Z at
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
GPIO
input fixed
selected
at 0
Hi-Z at
trans-
trans-
mission/
mission/
Input
Input
Hi-Z /
Hi-Z /
Hi-Z /
enabled/
enabled/
Input
Input
Input
Internal
Internal
enabled
enabled
enabled
input fixed
input fixed
at 0 at
at 0 at
reception
reception
*1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, Stop mode, Deep Standby
RTC mode, and Deep Standby Stop mode.
*2: Maintain previous state at timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode.
*3: Maintain previous state at timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
75
D a t a S h e e t
VBAT Pin Status Type
List of VBAT Domain Pin Status
VBAT
INITX
Power-on
Input
Reset
State
Device
Internal
Reset
State
Function
Return
Run
Mode or
Timer Mode,
Sleep
RTC Mode, or
Mode
Stop Mode State
Deep Standby
from
VBAT
from
RTC Mode or Deep
Deep
RTC
VBAT
Standby Stop Mode
Standby
Mode
RTC
State
Mode
State
Mode
Power
Power
Power
Supply
Supply
Supply
Stable
Stable
Stable
INITX=1
-
-
State
State
Group
Power
Supply
Power Supply
Stable
Unstable
‐
‐
INITX=0
Power
Supply
Power Supply
Stable
Stable
INITX=1
Return
INITX=1
Power Supply Stable
INITX=1
INITX=1
State
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
-
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
Setting
previous
previous
previous
previous
previous
previous
previous
previous
prohibiti
state
state
state
state
state
state
state
state
on
Input
Input
Input
Input
Input
Input
Input
Input
Input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
Setting
previous
previous
previous
previous
previous
previous
previous
previous
prohibiti
state
state
state
state
state
state
state
state
on
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
previous
previous
previous
previous
previous
previous
previous
previous
previous
previous
state
state
state
state
state
state
state
state
state
state
Maintain
Maintain
Maintain
previous
previous
previous
state
state
state
GPIO
Setting
selected
disabled
-
Sub crystal
oscillator
S
input pin /
External
sub clock
Maintain
Maintain
previous
previous
state
state
input
selected
GPIO
Setting
selected
disabled
External
sub clock
Setting
input
disabled
selected
T
Sub crystal
oscillator
output pin
Maintain
Maintain
Hi-Z /
previous
previous
Internal
state/W
state/Wh
hen
en
oscillati
oscillatio
on
n
stops,
stops,
Hi-Z*
Hi-Z*
input
fixed at 0/
or Input
Maintain
Maintain
Maintain
previous
previous
previous
state
state
state
enable
Maintain
previous
state/Whe
n
oscillation
stops,
Hi-Z*
-
Maintain
previous
state/Wh
en
oscillatio
n
stops,
Hi-Z*
Resource
selected
U
Hi-Z
GPIO
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
previous
previous
previous
previous
previous
previous
previous
previous
previous
previous
state
state
state
state
state
state
state
state
state
state
selected
*: When the SOSCNTL bit in the WTOSCCNT Register is 0, Sub crystal oscillator output pin is maintain
previous state.
When the SOSCNTL bit in the WTOSCCNT Register is 1,oscillation is stopped at Stop mode and
Deep Standby Stop mode.
76
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
14. Electrical Characteristics
14.1 Absolute Maximum Ratings
Parameter
Rating
Symbol
Power supply voltage *1, *2
Min
Max
Unit
VCC
VSS - 0.5
VSS + 6.5
V
USBVCC
VSS - 0.5
VSS + 6.5
V
Power supply voltage (VBAT) * *
VBAT
VSS - 0.5
VSS + 6.5
V
Analog power supply voltage *1 ,*5
AVCC
VSS - 0.5
VSS + 6.5
V
AVRH
VSS - 0.5
VSS + 6.5
V
Power supply voltage (for USB)*1, * 3
1, 4
1, 5
Analog reference voltage * *
VSS - 0.5
Input voltage *1
VI
VSS - 0.5
VSS - 0.5
Analog pin input voltage *1
VIA
VSS - 0.5
Output voltage *1
VO
VSS - 0.5
"L" level maximum output current *6
IOL
"L" level average output current *7
IOLAV
"L" level total maximum output current
"L" level total maximum output current *
8
"H" level maximum output current *6
"H" level average output current *
7
-
-
∑IOL
-
∑IOLAV
-
IOH
IOHAV
-
-
VCC + 0.5
(≤ 6.5V)
USBVCC + 0.5
(≤ 6.5V)
VSS + 6.5
AVCC + 0.5
(≤ 6.5V)
VCC + 0.5
(≤ 6.5V)
V
Except for USB pin
V
USB pin
V
5 V tolerant
V
V
10
mA
4 mA type
20
mA
8 mA type
20
mA
12 mA type
22.4
mA
I2C Fm+
4
mA
4 mA type
8
mA
8 mA type
12
mA
12 mA type
20
mA
I2C Fm+
100
mA
50
mA
- 10
mA
4 mA type
20
mA
8 mA type
- 20
mA
12 mA type
-4
mA
4 mA type
8
mA
8 mA type
- 12
mA
12 mA type
- 100
mA
"H" level total maximum output current
∑IOH
"H" level total average output current *8
∑IOHAV
-
- 50
mA
TSTG
- 55
+ 150
°C
Storage temperature
-
Remarks
*1: These parameters are based on the condition that V SS = AVSS = 0.0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: USBVCC must not drop below VSS - 0.5 V.
*4: VBAT must not drop below VSS - 0.5 V.
*5: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on.
*6: The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*7: The average output current is defined as the average current value flowing through any one of the
corresponding pins for a 100ms period.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
77
D a t a S h e e t
*8: The total average output current is defined as the average current value flowing through all of
corresponding pins for a period of 100 ms.
WARNING:
−
Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
78
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
14.2 Recommended Operating Conditions
Parameter
Power supply voltage
Symbol
Conditions
VCC
-
Value
Min
Max
2.7*5
5.5
3.0
Power supply voltage (for USB)
USBVCC
Unit
V
3.6
*1
(≤ VCC)
-
Remarks
V
2.7
5.5
*2
(≤ VCC)
Power supply voltage (VBAT)
VBAT
-
2.7
5.5
V
Analog power supply voltage
AVCC
-
2.7
5.5
V
Analog reference voltage
AVRH
-
*4
AVCC
V
Operating
Junction temperature
Tj
-
- 40
+ 125
°C
temperature
Ambient temperature
Ta
-
- 40
*3
°C
AVCC=VCC
*1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0).
*2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80).
*3: The maximum temperature of the ambient temperature (Ta) can guarantee a range that does not exceed
the junction temperature (Tj).
The calculation formula of the ambient temperature (Ta) is shown below.
Ta(Max) = Tj(Max) - Pd(Max) × θja
Pd: Power dissipation (W)
θja: Package thermal resistance (°C/W)
Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH))
IOL: L level output current
IOH: H level output current
VOL: L level output voltage
VOH: H level output voltage
Package thermal resistance and maximum permissible power for each package are shown below.
The operation is guaranteed maximum permissible power or less for semiconductor devices.
*4: The minimum value of Analog reference voltage depends on the value of compare clock cycle
(Tcck). See "5. 12-bit A/D Converter" for the details.
*5: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including
Main PLL is used) or built-in Low-speed CR is possible to operate only.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
79
D a t a S h e e t
Table for Package Thermal Resistance and Maximum Permissible Power
Package
Printed Circuit Board
Thermal Resistance
θja (°C/W)
Maximum Permissible Power
(mW)
Ta=+85 °C
Ta=+105 °C
Single-layered both sides
60
667
333
(0.5 mm pitch)
4 layers
39
1026
513
FPT-80P-M40
Single-layered both sides
58
690
335
(0.65 mm pitch)
4 layers
38
1053
526
FPT-100P-M23
Single-layered both sides
57
702
351
(0.5 mm pitch)
4 layers
38
1053
526
FPT-100P-M36
Single-layered both sides
48
833
417
(0.65 mm pitch)
4 layers
34
1177
588
FPT-120P-M37
Single-layered both sides
62
645
323
(0.5 mm pitch)
4 layers
43
930
465
BGA-112P-M05
Single-layered both sides
60
667
333
(0.5 mm pitch)
4 layers
40
1000
500
Single-layered both sides
55
727
364
4 layers
40
1000
500
FPT-80P-M37
BGA-144P-M09
(0.5 mm pitch)
1.
80
CONFIDENTIAL
WARNING:
The recommended operating conditions are required to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are warranted when the device is operated under these
conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and could
result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this data
sheet. If you are considering application under any conditions other than listed herein, please contact sales
representatives beforehand.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Calculation Method of Power Dissipation (Pd)
The power dissipation is shown in the following formula.
Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH))
IOL: "L" level output current
IOH: "H" level output current
VOL: "L" level output voltage
VOH: "H" level output voltage
ICC is a current consumed in device.
It can be analyzed as follows.
ICC = ICC(INT) + ΣICC(IO)
ICC(INT): Current consumed in internal logic and memory, etc. through regulator
ΣICC(IO): Sum of current (I/O switching current) consumed in output pin
For ICC (INT), it can be anticipated by "(1) Current Rating" in "3. DC Characteristics" (This rating value does
not include ICC (IO) for a value at pin fixed).
For Icc (IO), it depends on system used by customers.
The calculation formula is shown below.
ICC(IO) = (CINT + CEXT) × VCC × fsw
CINT: Pin internal load capacitance
CEXT: External load capacitance of output pin
fSW: Pin switching frequency
Parameter
Symbol
Pin internal load capacitance
CINT
Conditions
Capacitance Value
4 mA type
1.93 pF
8 mA type
3.45 pF
12 mA type
3.42 pF
Calculate ICC (Max) as follows when the power dissipation can be evaluated.
1. Measure current value ICC (Typ) at normal temperature (+25°C).
2. Add maximum leak current value ICC (leak_max) at operating on a value in (1).
ICC(Max) = ICC(Typ) + ICC(leak_max)
Parameter
Maximum leak current at operating
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
Symbol
ICC(leak_max)
Conditions
Current Value
Tj = +125 °C
45.5 mA
Tj = +105 °C
26.8 mA
Tj = +85 °C
16.2 mA
81
D a t a S h e e t
Current Explanation Diagram
Pd = VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH))
ICC = ICC(INT)＋ΣICC(IO)
VCC
A
ICC
Chip
ICC(INT)
ΣICC(IO)
A
Regulator
VOL
V
A
・・・
V
IOL
Flash
VOH
・・・
Logic
IOH
RAM
ICC(IO)
CEXT
・・・
82
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
14.3 DC Characteristics
14.3.1 Current Rating
Table 14-1 Typical and maximum current consumption in Normal operation(PLL), code running from Flash memory
(Flash accelerator mode and trace buffer function enabled)
Parameter
Symbol
Pin
Name
Power
supply
ICC
VCC
current
Frequency*4
Conditions
Normal operation
(PLL)
*5, *6
Value
Typ*1
Max*2
160 MHz
54
103
144 MHz
49
98
120 MHz
41
90
100 MHz
35
84
80 MHz
28
77
60 MHz
22
71
40 MHz
16
64
20 MHz
8.9
58
8 MHz
5.1
54
4 MHz
3.8
53
160 MHz
34
83
144 MHz
31
80
120 MHz
26
75
100 MHz
22
71
80 MHz
18
67
60 MHz
14
63
40 MHz
10
59
20 MHz
6.2
55
8 MHz
3.8
53
4 MHz
3.1
52
Unit
Remarks
*3
mA
When all peripheral
clocks are ON
*3
mA
When all peripheral
clocks are OFF
Table 14-2 Typical and maximum current consumption in Normal operation(PLL), code with data accessing running
from Flash memory (Flash accelerator mode and trace buffer function disabled)
Parameter
Symbol
Pin
Name
Power
supply
current
Normal
ICC
VCC
operation
(PLL)
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
Frequency*7
Conditions
*8
Value
1
Typ*
Max*2
160 MHz
74
126
144 MHz
68
120
120 MHz
59
112
100 MHz
52
104
80 MHz
44
97
60 MHz
36
89
40 MHz
27
79
20 MHz
17
67
8 MHz
8.3
58
4 MHz
5.4
55
160 MHz
51
103
144 MHz
47
100
120 MHz
42
94
100 MHz
37
90
80 MHz
33
85
60 MHz
28
80
40 MHz
21
73
20 MHz
13
64
8 MHz
6.9
56
4MHz
4.6
54
Unit
Remarks
*3
mA
When all peripheral
clocks are ON
*3
mA
When all peripheral
clocks are OFF
83
D a t a S h e e t
*1: Ta=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1)
*6: Data access is nothing to MainFlash memory
*7: Frequency is a value of HCLK. PCLK0=PCLK2=HCLK/2, PCLK1=HCLK
*8: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0)
Table 14-3 Typical and maximum current consumption in Normal operation(PLL), code with data accessing running
from Flash memory (flash 0 wait-cycle mode and read access 0 wait)
Parameter
Symbol
Pin
Name
Power
supply
current
Frequency*4
Conditions
Normal
ICC
VCC
operation
(PLL)
*5
Value
(MHz)
Typ*1
Max*2
72 MHz
46
98
60 MHz
40
92
48 MHz
33
85
36 MHz
27
78
24 MHz
19
70
12 MHz
11
61
8 MHz
8.5
58
4 MHz
5.5
55
72 MHz
33
85
60 MHz
29
81
48 MHz
25
76
36 MHz
20
71
24 MHz
15
65
12 MHz
9.2
59
8 MHz
6.9
56
4 MHz
4.6
54
Unit
Remarks
*3
mA
When all peripheral
clocks are ON
*3
mA
When all peripheral
clocks are OFF
*1: Ta=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK
*5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 00)
84
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Table 14-4 Typical and maximum current consumption in Normal operation(other than PLL), code with data accessing
running from Flash memory (flash 0 wait-cycle mode and read access 0 wait)
Parameter
Symbol
Pin
Name
Frequency*4
Conditions
Value
Typ*1
Max*2
3.3
51
Unit
Remarks
*3
Normal operation
(built-in
*5
mA
clocks are ON
4 MHz
high-speed CR)
When all peripheral
*3
2.8
51
mA
When all peripheral
clocks are OFF
*3
0.64
Power
supply
current
ICC
VCC
Normal operation
(sub oscillation)
*5
48
mA
When all peripheral
clocks are ON
32 kHz
*3
0.56
48
mA
When all peripheral
clocks are OFF
*3
0.64
Normal operation
(built-in
low-speed CR)
*5
48
mA
When all peripheral
clocks are ON
100 kHz
*3
0.58
48
mA
When all peripheral
clocks are OFF
*1: Ta=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000)
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
85
D a t a S h e e t
Table 14-5 Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 =
HCLK/2
Parameter
Symbol
Pin
Name
Power
supply
current
86
CONFIDENTIAL
Conditions
SLEEP
ICCS
VCC
operation
(PLL)
Frequency*4
Value
Typ*1
Max*2
160 MHz
35
84
144 MHz
32
81
120 MHz
27
76
100 MHz
23
72
80 MHz
19
68
60 MHz
15
64
40 MHz
11
60
20 MHz
6.5
55
8 MHz
4.1
53
4 MHz
3.3
52
160 MHz
16
65
144 MHz
14
63
120 MHz
12
61
100 MHz
11
60
80 MHz
9.0
58
60 MHz
7.4
56
40 MHz
5.6
54
20 MHz
3.9
53
8 MHz
2.9
52
4 MHz
2.6
51
Unit
Remarks
*3
mA
When all peripheral
clocks are ON
*3
mA
When all peripheral
clocks are OFF
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Table 14-6 Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 =
HCLK
Parameter
Symbol
Pin
Name
Power
supply
current
Conditions
SLEEP
ICCS
VCC
operation
(PLL)
Frequency*5
Value
Typ*1
Max*2
72 MHz
22
71
60 MHz
19
68
48 MHz
16
64
36 MHz
12
61
24 MHz
9.0
58
12 MHz
5.8
55
8 MHz
4.6
54
4 MHz
3.6
52
72 MHz
9.5
58
60 MHz
8.3
57
48 MHz
7.1
56
36 MHz
5.8
55
24 MHz
4.6
53
12 MHz
3.5
52
8 MHz
3.0
52
4 MHz
2.7
51
Unit
Remarks
*3
mA
When all peripheral
clocks are ON
*3
mA
When all peripheral
clocks are OFF
*1: Ta=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3 : When all ports are fixed.
*4 : Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5 : Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
87
D a t a S h e e t
Table 14-7 Typical and maximum current consumption in Sleep operation(other than PLL), when PCLK0 = PCLK1 =
PCLK2 = HCLK/2
Parameter
Symbol
Pin Name
Conditions
Frequency*4
Value
Typ*1
Max*2
1.5
49
Unit
Remarks
*3
SLEEP
operation
(built-in
mA
clocks are ON
4 MHz
high-speed CR)
When all peripheral
*3
1.0
49
mA
When all peripheral
clocks are OFF
*3
supply
current
0.59
SLEEP
Power
ICCS
VCC
operation
48
mA
clocks are ON
32 kHz
(sub oscillation)
When all peripheral
*3
0.51
48
mA
When all peripheral
clocks are OFF
*3
0.61
SLEEP
operation
(built-in
low-speed CR)
48
mA
When all peripheral
clocks are ON
100 kHz
*3
0.53
48
mA
When all peripheral
clocks are OFF
*1: Ta=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
88
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Table 14-8 Typical and maximum current consumption in STOP mode, TIMER mode and RTC mode
Parameter
Symbol
Pin Name
Conditions
ICCH
STOP mode
Frequency
-
Value
Unit
Typ*1
Max*2
0.33
1.8
mA
-
15
mA
-
22
mA
0.70
2.2
mA
-
16
mA
-
22
mA
0.33
1.8
mA
-
15
mA
-
22
mA
0.34
1.8
mA
-
15
mA
-
22
mA
0.33
1.8
mA
-
15
mA
-
22
mA
TIMER mode
(built-in
4 MHz
high-speed CR)
Power supply
current
ICCT
VCC
TIMER mode
(sub oscillation)
32 kHz
TIMER mode
(built-in
100 kHz
low-speed CR)
ICCR
RTC mode
(sub oscillation)
32 kHz
Remarks
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*1: VCC=3.3 V
*2: VCC=5.5 V
*3: When all ports are fixed.
*4: When LVD is OFF
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
89
D a t a S h e e t
Table 14-9 Typical and maximum current consumption in Deep Standby STOP mode, Deep Standby RTC mode and
VBAT
Parameter
Symbol
Pin
Name
Conditions
Frequency
Deep standby
STOP mode
(When RAM is
OFF)
ICCHD
Value
Unit
Typ*1
Max*2
29
140
µA
-
644
µA
-
1011
µA
48
273
µA
-
2676
µA
-
4162
µA
29
140
µA
-
644
µA
-
1011
µA
48
273
µA
-
2676
µA
-
4162
µA
0.015
0.29
µA
-
5.77
µA
-
10.6
µA
1.53
22.6
µA
-
35.2
µA
-
41.8
µA
Deep standby
STOP mode
(When RAM is
ON)
VCC
Deep standby
RTC mode
(When RAM is
OFF)
Power
supply
ICCRD
32 kHz
current
Deep standby
RTC mode
(When RAM is
ON)
RTC stop
ICCVBAT
VBAT
-
RTC operation
Remarks
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4, *5
Ta=+25°C
*3, *4, *5
Ta=+85°C
*3, *4, *5
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*1: VCC=3.3 V
*2: VCC=5.5 V
*3: When all ports are fixed.
*4: When LVD is OFF
*5: When sub oscillation is OFF
90
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Table 14-10 Typical and maximum current consumption in Low-voltage detection circuit, Main flash memory
write/erase
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
At operation
-
4
7
μA
At Write/Erase
-
13.4
15.9
mA
At Write/Erase
-
11.5
13.6
mA
Remarks
Low-voltage
detection circuit
(LVD) power
ICCLVD
For occurrence of
interrupt
supply current
Main flash
memory
write/erase
ICCFLASH
VCC
current
Work flash
memory
write/erase
ICCWFLASH
current
Peripheral current dissipation
Clock System
HCLK
Peripheral
Unit
GPIO
80
160
All ports
0.22
0.43
0.85
DMAC
-
0.74
1.48
2.88
DSTC
-
0.32
0.61
1.17
External bus I/F
-
0.14
0.27
0.55
SD card I/F
-
0.93
1.81
3.63
CAN
1ch.
0.02
0.06
0.11
USB
1ch.
0.34
0.67
1.33
Base timer
4ch.
0.16
0.34
0.66
1 unit/4ch.
0.55
1.09
2.17
1 unit
0.04
0.09
0.17
A/DC
1 unit
0.20
0.39
0.78
Multi-function serial
1ch.
0.31
0.62
-
Multi-functional
timer/PPG
PCLK1
Frequency (MHz)
40
Remarks
mA
mA
Quadrature
position/Revolution
Unit
counter
PCLK2
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
mA
91
D a t a S h e e t
14.3.2
Pin Characteristics
(VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Pin Name
Value
Conditions
Unit
Min
Typ
Max
-
VCC×0.8
-
VCC + 0.3
V
-
VCC×0.8
-
VSS + 5.5
V
-
VCC×0.7
-
VSS + 5.5
V
-
VSS - 0.3
-
VCC×0.2
V
-
VSS - 0.3
-
VCC×0.2
V
-
VSS
-
VCC×0.3
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
USBVCC - 0.4
-
USBVCC
V
VCC - 0.5
-
VCC
V
Remarks
CMOS
hysteresis
input pin,
"H" level input
voltage
(hysteresis
MD0, MD1
VIHS
5V tolerant
input pin
input)
Input pin
doubled as I2C
Fm+
CMOS
hysteresis
input pin,
"L" level input
voltage
(hysteresis
MD0, MD1
VILS
5V tolerant
input pin
input)
Input pin
doubled as I2C
Fm+
VCC ≥ 4.5 V,
IOH = - 4 mA
4mA type
VCC < 4.5 V,
IOH = - 2 mA
VCC ≥ 4.5 V,
IOH = - 8 mA
8mA type
VCC < 4.5 V,
IOH = - 4 mA
VCC ≥ 4.5 V,
"H" level output
voltage
IOH = - 12 mA
VOH
12mA type
VCC < 4.5 V,
IOH = - 8 mA
USBVCC ≥ 4.5 V,
The pin
doubled as
USB I/O
IOH = - 13.0 mA
VCC ≥ 4.5 V,
The pin
2
doubled as I C
Fm+
92
CONFIDENTIAL
IOH = - 20.5 mA
USBVCC < 4.5 V,
IOH = - 4 mA
VCC < 4.5 V,
At GPIO
IOH = - 3 mA
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Min
Typ
Max
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
Remarks
VCC ≥ 4.5 V,
IOL = 4 mA
4 mA type
VCC < 4.5 V,
IOL = 2 mA
VCC ≥ 4.5 V,
IOH = 8 mA
8 mA type
VCC < 4.5 V,
IOH = 4 mA
VCC ≥ 4.5 V,
"L" level output
voltage
IOL = 12 mA
12 mA type
VCC < 4.5 V,
VOL
IOL = 8 mA
USBVCC ≥ 4.5 V,
The pin
doubled as
USB I/O
IOL = 18.5 mA
USBVCC < 4.5 V,
IOL = 10.5 mA
VCC ≥ 4.5 V,
The pin
doubled as I2C
Fm+
IOH = 4 mA
VCC < 4.5 V,
IOH = 3 mA
At GPIO
VCC ≤ 5.5 V,
At I2C Fm+
IOH = 20 mA
Input leak
current
Pull-up resistor
value
IIL
-
RPU
Pull-up pin
-
-5
-
+5
VCC ≥ 4.5 V
25
50
100
VCC < 4.5 V
30
80
200
-
-
5
15
μA
kΩ
Other than
VCC,
Input
capacitance
USBVCC,
CIN
VBAT,
pF
VSS,
AVCC,
AVSS, AVRH
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
93
D a t a S h e e t
14.4 AC Characteristics
14.4.1 Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Input frequency
Pin Name
fCH
Input clock cycle
tCYLH
Input clock pulse
Input clock rising time
tCF,
and falling time
tCR
Internal operating
1
clock* frequency
Internal operating
1
clock* cycle time
Value
Min
Max
VCC ≥ 4.5 V
4
48
VCC < 4.5 V
4
20
Unit
Remarks
MHz
When crystal oscillator is connected
MHz
When using external clock
ns
When using external clock
VCC ≥ 4.5 V
4
48
VCC < 4.5 V
4
20
X0,
VCC ≥ 4.5 V
20.83
250
X1
VCC < 4.5 V
50
250
45
55
%
When using external clock
-
-
5
ns
When using external clock
PWH/tCYLH,
-
width
Conditions
PWL/tCYLH
fCC
-
-
-
160
MHz
Base clock (HCLK/FCLK)
fCP0
-
-
-
80
MHz
APB0 bus clock*2
fCP1
-
-
-
160
MHz
APB1 bus clock*2
fCP2
-
-
-
80
MHz
APB2 bus clock*2
tCYCC
-
-
6.25
-
ns
Base clock (HCLK/FCLK)
tCYCP0
-
-
12.5
-
ns
APB0 bus clock*2
tCYCP1
-
-
6.25
-
ns
APB1 bus clock*2
tCYCP2
-
-
12.5
-
ns
APB2 bus clock*2
*1 : For more information about each internal operating clock, see CHAPTER 2-1: Clock in FM4 Family
Peripheral Manual Main part (MN709-00001).
*2 : For about each APB bus which each peripheral is connected to, see 10. Block Diagram in this data
sheet.
X0
94
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
14.4.2
Sub Clock Input Characteristics
(VBAT = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Input frequency
1/ tCYLL
Input clock cycle
tCYLL
Input clock pulse width
Pin
Conditions
Name
Value
Remarks
Typ
Max
-
-
32.768
-
kHz
X0A,
-
32
-
100
kHz
When using external clock
X1A
-
10
-
31.25
μs
When using external clock
45
-
55
%
When using external clock
PWH/tCYLL,
-
PWL/tCYLL
0.8 × VBAT
When crystal oscillator is
connected
VBAT
X0A
14.4.3
Unit
Min
VBAT
VBAT
VBAT
Built-in CR Oscillation Characteristics
Built-in High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Clock frequency
Clock frequency
Symbol
Conditions
Value
Min
Typ
Max
TJ = -20°C to +105°C
3.92
4
4.08
TJ = - 40°C to +125°C
3.88
4
4.12
fCRH
TJ = - 40°C to +125°C
3
4
5
tCRWT
-
-
-
30
Unit
fCRH
Remarks
When trimming*1
MHz
When not trimming
Frequency
stabilization
μs
*2
time
*1: In the case of using the values in CR trimming area of Flash memory at shipment for
frequency/temperature trimming.
*2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value.
This period is able to use high-speed CR clock as source clock.
Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Clock frequency
Symbol
Condition
fCRL
-
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
Value
Min
Typ
Max
50
100
150
Unit
Remarks
kHz
95
D a t a S h e e t
14.4.4
Operating Conditions of Main PLL (In the Case of Using Main Clock
for Input Clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
PLL oscillation stabilization wait time*1
(LOCK UP time)
PLL input clock frequency
PLL multiplication rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
Unit
Min
Typ
Max
200
-
-
fPLLI
4
-
16
MHz
-
13
-
80
multiplier
fPLLO
200
-
320
MHz
fCLKPLL
-
-
160
MHz
tLOCK
Remarks
μs
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see CHPATER 2-1: Clock in FM4
Family Peripheral Manual Main part (MN709-00001).
14.4.5
Operating Conditions of USB PLL (In the Case of Using Main Clock
for Input Clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
PLL oscillation stabilization wait time*1
(LOCK UP time)
PLL input clock frequency
PLL multiplication rate
PLL macro oscillation clock frequency
USB clock frequency*
2
Unit
Min
Typ
Max
tLOCK
100
-
-
μs
fPLLI
4
-
16
MHz
-
13
-
80
multiplier
fPLLO
200
-
320
MHz
fCLKSPLL
-
-
48
MHz
Remarks
After the M frequency division
*1 : Time from when the PLL starts operating until the oscillation stabilizes.
*2 : For more information about USB clock, see CHAPTER 2-2: USB Clock Generation in FM4
Family Peripheral Manual Communication Macro part (MN709-00004).
14.4.6
Operating Conditions of Main PLL (In the Case of Using Built-in
High-speed CR Clock for Input Clock of Main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
PLL oscillation stabilization wait time*1
(LOCK UP time)
PLL input clock frequency
PLL multiplication rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
Unit
Min
Typ
Max
tLOCK
200
-
-
fPLLI
3.8
4
4.2
MHz
-
50
-
75
multiplier
fPLLO
190
-
320
MHz
fCLKPLL
-
-
160
MHz
Remarks
μs
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see CHAPTER 2-1: Clock in FM4
Family Peripheral Manual Main part (MN709-00001).
Note:
−
96
CONFIDENTIAL
Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the
frequency and temperature has been trimmed.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
14.4.7
Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Pin
Symbol
Reset input time
Name
tINITX
14.4.8
Value
Condition
INITX
-
Unit
Min
Max
500
-
Remarks
ns
Power-on Reset Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Power supply rising time
Pin Name
Tr
Power supply shut down time
Time until releasing
Toff
VCC
Tprt
Power-on reset
Unit
Min
Max
0
-
ms
1
-
ms
0.33
0.60
ms
Remarks
VCC_minimum
VCC
VDL_minimum
0.2V
0.2V
0.2V
Tr
Tprt
Internal RST
RST Active
CPU Operation
Toff
Release
start
Glossary
− VCC_minimum: Minimum VCC of recommended operating conditions.
− VDL_minimum: Minimum detection voltage of Low-Voltage detection reset.
See 8. Low-Voltage Detection Characteristics.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
97
D a t a S h e e t
14.4.9
GPIO Output Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Output frequency
Symbol
Pin Name
tPCYCLE
Pxx*
Conditions
Value
Unit
Min
Max
VCC ≥ 4.5 V
-
50
MHz
VCC < 4.5 V
-
32
MHz
*: GPIO is a target.
Pxx
tPCYCLE
98
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
14.4.10 External Bus Timing
External Bus Clock Output Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin Name
tCYCLE
MCLKOUT*1
Output frequency
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
Value
Unit
Min
Max
-
50*2
MHz
-
3
MHz
32*
*1: The external bus clock (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see CHAPTER 14: External Bus Interface in FM4
Family Peripheral Manual Main part (MN709-00001).
*2: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 100 MHz.
*3: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 64 MHz.
0.8 × Vcc
0.8 × Vcc
MCLK
tCYCLE
External Bus Signal Input/output Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
0.8 × VCC
V
0.2 × VCC
V
VOH
0.8 × VCC
V
VOL
0.2 × VCC
V
VIH
Remarks
Signal input characteristics
VIL
Signal output characteristics
Signal input
VIH
VIL
VIH
VIL
Signal output
VOH
VOL
VOH
VOL
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
99
D a t a S h e e t
Separate Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
MOEX
Mininum pulse width
MCSX↓→Address output
delay time
MOEX↑→Address hold time
MCSX↓→
Symbol
Pin Name
tOEW
MOEX
tCSL – AV
tOEH - AX
tCSL - OEL
MOEX↓ delay time
MOEX↑→
tOEH - CSH
MCSX↑ time
MCSX↓→MDQM↓
tCSL - RDQML
delay time
Data set up→MOEX↑ time
MOEX↑→
tDS - OE
tDH - OE
Data hold time
MWEX
tWEW
Mininum pulse width
MWEX↑→Address output
delay time
tWEH - AX
MCSX↓→MWEX↓ delay time
tCSL - WEL
MWEX↑→MCSX↑ delay time
tWEH - CSH
MCSX↓→MDQM↓ delay time
tCSL-WDQML
MWEX↓→
tCSL-DX
Data output time
MWEX↑→
tWEH - DX
Data hold time
Conditions
VCC ≥ 4.5V
VCC < 4.5V
Value
Min
Max
MCLK×n-3
-
MCSX[7:0],
VCC ≥ 4.5V
-9
+9
MAD[24:0]
VCC < 4.5V
-12
+12
MOEX,
VCC ≥ 4.5V
MAD[24:0]
VCC < 4.5V
MOEX,
MCSX[7:0]
0
MCLK×m+9
MCLK×m+12
VCC ≥ 4.5V
MCLK×m-9
MCLK×m+9
VCC < 4.5V
MCLK×m-12
MCLK×m+12
VCC ≥ 4.5V
VCC < 4.5V
0
MCLK×m+9
MCLK×m+12
Unit
ns
ns
ns
ns
ns
MCSX,
VCC ≥ 4.5V
MCLK×m-9
MCLK×m+9
MDQM[1:0]
VCC < 4.5V
MCLK×m-12
MCLK×m+12
MOEX,
VCC ≥ 4.5V
20
-
MADATA[15:0]
VCC < 4.5V
38
-
MOEX,
VCC ≥ 4.5V
MADATA[15:0]
VCC < 4.5V
0
-
ns
MCLK×n-3
-
ns
MWEX
VCC ≥ 4.5V
VCC < 4.5V
MWEX,
VCC ≥ 4.5V
MAD[24:0]
VCC < 4.5V
0
MCLK×m+9
MCLK×m+12
VCC ≥ 4.5V
MCLK×n-9
MCLK×n+9
MWEX,
VCC < 4.5V
MCLK×n-12
MCLK×n+12
MCSX[7:0]
VCC ≥ 4.5V
VCC < 4.5V
0
MCLK×m+9
MCLK×m+12
MCSX,
VCC ≥ 4.5V
MCLK×n-9
MCLK×n+9
MDQM[1:0]
VCC < 4.5V
MCLK×n-12
MCLK×n+12
MCSX,
VCC ≥ 4.5V
MCLK-9
MCLK+9
MADATA[15:0]
VCC < 4.5V
MCLK-12
MCLK+12
MWEX,
VCC ≥ 4.5V
MADATA[15:0]
VCC < 4.5V
0
MCLK×m+9
MCLK×m+12
ns
ns
ns
ns
ns
ns
ns
ns
Note:
−
100
CONFIDENTIAL
When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16)
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
MCSX[7:0]
tCSL-AV
MAD[24:0]
tOEH-AX
Address
tWEH-AX
tCSL-AV
Address
tCSL-OEL
tOEW
MOEX
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
tCSL-WEL
tWEW
MWEX
MADATA[15:0]
tDS-OE
tDH-OE
RD
tWEH-DX
WD
Invalid
tCSL-DX
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
101
D a t a S h e e t
Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Address delay time
tAV
tCSL
MCSX delay time
tCSH
tREL
MOEX delay time
tREH
Data set up
tDS
→MCLK↑ time
MCLK↑→
tDH
Data hold time
tWEL
MWEX delay time
tWEH
tDQML
MDQM[1:0]
delay time
tDQMH
MCLK↑→
tODS
Data output time
MCLK↑→
tOD
Data hold time
Pin Name
Conditions
MCLK,
VCC ≥ 4.5 V
MAD[24:0]
VCC < 4.5 V
MCLK,
VCC < 4.5 V
MCSX[7:0]
VCC ≥ 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
MCLK,
MOEX
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
Value
Min
1
1
1
1
1
MCLK,
VCC ≥ 4.5 V
19
MADATA[15:0]
VCC < 4.5 V
37
MCLK,
VCC ≥ 4.5 V
MADATA[15:0]
VCC < 4.5 V
VCC ≥ 4.5 V
MCLK,
MWEX
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
MCLK,
VCC < 4.5 V
MDQM[1:0]
VCC ≥ 4.5 V
VCC < 4.5 V
MCLK,
VCC ≥ 4.5 V
MADATA[15:0]
VCC < 4.5 V
MCLK,
VCC ≥ 4.5 V
MADATA[15:0]
VCC < 4.5 V
0
1
1
1
1
MCLK+1
1
Max
9
12
9
12
9
12
9
12
9
12
Unit
ns
ns
ns
ns
ns
-
ns
-
ns
9
12
9
12
9
12
9
12
MCLK+18
MCLK+24
18
24
ns
ns
ns
ns
ns
ns
Note:
−
102
CONFIDENTIAL
When the external load capacitance CL = 30 pF
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
MAD[24:0]
tAV
Address
Address
tREL
tREH
tDQML
tDQMH
MOEX
tDQML
tDQMH
tWEL
tWEH
MDQM[1:0]
MWEX
tDS
MADATA[15:0]
tDH
RD
tOD
WD
Invalid
tODS
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
103
D a t a S h e e t
Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Multiplexed address delay time
tALE-CHMADV
Multiplexed address hold time
tCHMADH
Value
Pin Name
Conditions
MALE,
VCC < 4.5 V
MADATA[15:0]
VCC ≥ 4.5 V
MCLK×n+0
MCLK×n+10
VCC < 4.5 V
MCLK×n+0
MCLK×n+20
VCC ≥ 4.5 V
Min
0
Max
10
20
Unit
ns
ns
Note:
−
When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16)
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
104
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
tCHAL
MALE delay time
tCHAH
Pin Name
Conditions
MCLK,
VCC < 4.5 V
VCC ≥ 4.5 V
ALE
VCC ≥ 4.5 V
VCC < 4.5 V
Value
Min
1
Max
Unit
9
ns
12
ns
9
ns
12
ns
1
tOD
ns
1
tOD
ns
1
Remarks
VCC ≥ 4.5 V
MCLK↑→
Multiplexed address delay time
tCHMADV
MCLK,
MADATA[15:0]
MCLK↑→
Multiplexed data output time
VCC < 4.5 V
VCC ≥ 4.5 V
tCHMADX
VCC < 4.5 V
Note:
−
When the external load capacitance CL = 30 pF
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
105
D a t a S h e e t
NAND Flash Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
MNREX
Min pulse width
Data set up
Symbol
Pin Name
tNREW
MNREX
tDS – NRE
→MNREX↑ time
MNREX↑→
tDH – NRE
Data hold time
MNALE↑→
tALEH - NWEL
MNWEX delay time
MNALE↓→
tALEL - NWEL
MNWEX delay time
MNCLE↑→
tCLEH - NWEL
MNWEX delay time
MNWEX↑→
tNWEH - CLEL
MNCLE delay time
MNWEX
tNWEW
Min pulse width
MNWEX↓→
tNWEL – DV
Data output time
MNWEX↑→
tNWEH – DX
Data hold time
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
Value
Min
Max
MCLK×n-3
-
MNREX,
VCC ≥ 4.5 V
20
-
MADATA[15:0]
VCC < 4.5 V
38
-
MNREX,
VCC ≥ 4.5 V
MADATA[15:0]
VCC < 4.5 V
0
-
MNALE,
VCC ≥ 4.5 V
MCLK×m-9
MCLK×m+9
MNWEX
VCC < 4.5 V
MCLK×m-12
MCLK×m+12
MNALE,
VCC ≥ 4.5 V
MCLK×m-9
MCLK×m+9
MNWEX
VCC < 4.5 V
MCLK×m-12
MCLK×m+12
MNCLE,
VCC ≥ 4.5 V
MCLK×m-9
MCLK×m+9
MNWEX
VCC < 4.5 V
MCLK×m-12
MCLK×m+12
MNCLE,
VCC ≥ 4.5 V
MNWEX
VCC < 4.5 V
MNWEX
VCC ≥ 4.5 V
VCC < 4.5 V
0
MCLK×n-3
MCLK×m+9
MCLK×m+12
-
MNWEX,
VCC ≥ 4.5 V
-9
+9
MADATA[15:0]
VCC < 4.5 V
-12
+12
MNWEX,
VCC ≥ 4.5 V
MADATA[15:0]
VCC < 4.5 V
0
MCLK×m+9
MCLK×m+12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
−
When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16)
NAND Flash Read
MCLK
MNREX
MADATA[15:0]
Read
106
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
NAND Flash Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
107
D a t a S h e e t
External Ready Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
MCLK↑
MRDY input
tRDYI
setup time
Value
Pin Name
Conditions
MCLK,
VCC ≥ 4.5 V
19
MRDY
VCC < 4.5 V
37
Min
Max
-
Unit
Remarks
ns
When RDY is input
···
MCLK
Over 2cycle
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
MCLK
··· ···
2 cycle
Extended
MOEX
MWEX
tRDYI
MRDY
108
CONFIDENTIAL
0.5×VCC
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
SDRAM Mode
(VCC = 2.7V to 3.6V, VSS = 0V)
Value
Parameter
Symbol
Output frequency
tCYCSD
Address delay time
tAOSD
MSDCLK↑→Data output delay time
tDOSD
MSDCLK↑→Data output
Hi-Z time
tDOZSD
MDQM[1:0] delay time
tWROSD
MCSX delay time
tMCSSD
MRASX delay time
tRASSD
MCASX delay time
tCASSD
MSDWEX delay time
tMWESD
MSDCKE delay time
tCKESD
Data set up time
tDSSD
Data hold time
tDHSD
Pin Name
MSDCLK
MSDCLK,
MAD[15:0]
MSDCLK,
MADATA[31:0]
MSDCLK,
MADATA[31:0]
MSDCLK,
MDQM[1:0]
MSDCLK,
MCSX8
MSDCLK,
MRASX
MSDCLK,
MCASX
MSDCLK,
MSDWEX
MSDCLK,
MSDCKE
MSDCLK,
MADATA[31:0]
MSDCLK,
MADATA[31:0]
Unit
Min
Max
-
32
MHz
2
12
ns
2
12
ns
2
20
ns
1
12
ns
2
12
ns
2
12
ns
2
12
ns
2
12
ns
2
12
ns
23
-
ns
0
-
ns
Note:
−
When the external load capacitance CL = 30 pF
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
109
D a t a S h e e t
SDRAM Access
tCYCSD
MSDCLK
tAOSD
MAD[24:0]
MDQM[1:0]
MCSX
MRASX
MCASX
MSDWEX
MSDCKE
Address
tWROSD
tMCSSD
tRASSD
tCASSD
tMWESD
tCKESD
tDSSD
MADATA[15:0]
tDOSD
MADATA[15:0]
110
CONFIDENTIAL
tDHSD
RD
tDOZSD
WD
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
14.4.11 Base Timer Input Timing
Timer Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin Name
Value
Min
Max
2tCYCP
-
Unit
Remarks
TIOAn/TIOBn
tTIWH,
Input pulse width
Conditions
(when using as
tTIWL
-
ns
ECK, TIN)
tTIWH
tTIWL
ECK
VIHS
TIN
VIHS
VILS
VILS
Trigger Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin Name
(when using as
tTRGL
Min
Max
2tCYCP
-
Unit
Remarks
-
ns
TGIN)
tTRGH
TGIN
Value
TIOAn/TIOBn
tTRGH,
Input pulse width
Conditions
VIHS
tTRGL
VIHS
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see 10. Block Diagram in this
data sheet.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
111
D a t a S h e e t
14.4.12 UART Timing
Synchronous Serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Serial clock cycle time
tSCYC
SCK↓→SOT delay time
SIN→SCK↑
tSLOVI
tIVSHI
setup time
SCK↑→SIN hold time
tSHIXI
Serial clock "L" pulse width
tSLSH
Serial clock "H" pulse width
tSHSL
SCK↓→SOT delay time
SIN→SCK↑
tSLOVE
tIVSHE
setup time
SCK↑→SIN hold time
tSHIXE
Pin Name
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
Unit
Min
Max
Min
Max
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
SCKx
SCKx,
SOTx
Internal shift
SCKx,
clock
SINx
operation
SCKx,
SINx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
External shift
clock
operation
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
−
−
−
−
112
CONFIDENTIAL
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
VIH
VIL
SIN
tSHIXI
VIH
VIL
MS bit = 0
tSLSH
SCK
VIH
tF
SOT
VIL
tSHSL
VIL
VIH
VIH
tR
tSLOVE
VOH
VOL
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
113
D a t a S h e e t
Synchronous Serial (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Serial clock cycle time
tSCYC
SCK↑→SOT delay time
SIN→SCK↓
tSHOVI
tIVSLI
setup time
SCK↓→SIN hold time
tSLIXI
Serial clock "L" pulse width
tSLSH
Serial clock "H" pulse width
tSHSL
SCK↑→SOT delay time
SIN→SCK↓
tSHOVE
tIVSLE
setup time
SCK↓→SIN hold time
tSLIXE
Pin
Name
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
Unit
Min
Max
Min
Max
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
SCKx
SCKx,
SOTx
SCKx,
SINx
Internal shift
clock operation
SCKx,
SINx
SCKx,
SOTx
SCKx,
External shift
SINx
clock operation
SCKx,
SINx
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
−
−
−
−
114
CONFIDENTIAL
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
SCK
tSLSH
VIH
VIH
VIL
tR
SOT
VIL
VIL
tF
tSHOVE
VOH
VOL
SIN
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
MS bit = 1
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
115
D a t a S h e e t
Synchronous Serial (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Serial clock cycle time
tSCYC
SCK↑→SOT delay time
SIN→SCK↓
tSHOVI
tIVSLI
setup time
Pin Name
Conditions
SCKx
SCKx,
SOTx
SCKx,
Internal shift
SINx
clock
SCKx,
operation
VCC ≥ 4.5 V
VCC < 4.5 V
Unit
Min
Max
Min
Max
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
SCK↓→SIN hold time
tSLIXI
SOT→SCK↓ delay time
tSOVLI
Serial clock "L" pulse width
tSLSH
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
SIN→SCK↓
tIVSLE
setup time
SCK↓→SIN hold time
tSLIXE
SINx
SCKx,
SOTx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
External shift
clock
operation
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
−
116
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tSCYC
VOH
SCK
VOL
SOT
VOH
VOL
VOH
VOL
tIVSLI
SIN
VOL
tSHOVI
tSOVLI
tSLIXI
VIH
VIL
VIH
VIL
MS bit = 0
tSLSH
tSHSL
SCK
VIH
SOT
VIL
VIH
VIL
tF
*
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
117
D a t a S h e e t
Synchronous Serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Serial clock cycle time
tSCYC
SCK↓→SOT delay time
SIN→SCK↑
tSLOVI
tIVSHI
setup time
Pin Name
Conditions
SCKx
SCKx,
SOTx
SCKx,
Internal shift
SINx
clock
SCKx,
operation
VCC ≥ 4.5 V
VCC < 4.5 V
Unit
Min
Max
Min
Max
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
SCK↑→SIN hold time
tSHIXI
SOT→SCK↑ delay time
tSOVHI
Serial clock "L" pulse width
tSLSH
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
SIN→SCK↑
tIVSHE
setup time
SCK↑→SIN hold time
tSHIXE
SINx
SCKx,
SOTx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
External
shift clock
operation
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
−
118
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tSCYC
SCK
VOH
tSOVHI
SOT
tSLOVI
VOH
VOL
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
MS bit = 0
tSHSL
tR
SCK
VIL
VIH
tSLSH
VIH
VIL
tF
VIL
VIH
tSLOVE
SOT
VOH
VOL
VOH
VOL
tIVSHE
SIN
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
119
D a t a S h e e t
When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS=0, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↓→SCK↓setup time
SCK↑→SCS↑ hold time
tCSSI
tCSHI
Internal shift
clock
operation
VCC ≥ 4.5 V
VCC < 4.5 V
Conditions
Unit
Min
Max
Min
Max
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
ns
(*2)+0
(*2)+50
(*2)+0
(*2)+50
(*3)-50
(*3)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
+5tCYCP
+5tCYCP
3tCYCP+30
-
3tCYCP+30
-
ns
SCS deselect time
tCSDI
ns
SCS↓→SCK↓setup time
tCSSE
SCK↑→SCS↑ hold time
tCSHE
External shift
0
-
0
-
ns
SCS deselect time
tCSDE
clock
3tCYCP+30
-
3tCYCP+30
-
ns
SCS↓→SUT delay time
tDSE
operation
-
40
-
40
ns
SCS↑→SUT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
120
CONFIDENTIAL
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral
Manual Main part (MN709-00001).
When the external load capacitance CL = 30 pF.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tCSDI
tCSSI
tCSHI
SOT
(SPI=1)
tCSDE
tCSSE
tCSHE
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
121
D a t a S h e e t
When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS=0, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↓→SCK↑setup time
SCK↓→SCS↑ hold time
tCSSI
tCSHI
Internal shift
clock
operation
VCC ≥ 4.5 V
VCC < 4.5 V
Conditions
Unit
Min
Max
Min
Max
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
ns
(*2)+0
(*2)+50
(*2)+0
(*2)+50
(*3)-50
(*3)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
+5tCYCP
+5tCYCP
3tCYCP+30
-
3tCYCP+30
-
ns
SCS deselect time
tCSDI
ns
SCS↓→SCK↑setup time
tCSSE
SCK↓→SCS↑ hold time
tCSHE
External shift
0
-
0
-
ns
SCS deselect time
tCSDE
clock
3tCYCP+30
-
3tCYCP+30
-
ns
SCS↓→SOT delay time
tDSE
operation
-
40
-
40
ns
SCS↑→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
122
CONFIDENTIAL
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral
Manual Main part (MN709-00001).
When the external load capacitance CL = 30 pF.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tCSDI
tCSSI
tCSHI
SOT
(SPI=0)
SOT
(SPI=1)
tCSDE
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
123
D a t a S h e e t
When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS=0, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↑→SCK↓setup time
tCSSI
SCK↑→SCS↓ hold time
tCSHI
SCS deselect time
tCSDI
SCS↑→SCK↓setup time
SCK↑→SCS↓ hold time
SCS deselect time
Conditions
Internal shift
clock
VCC ≥ 4.5 V
VCC < 4.5 V
Min
Max
Unit
Max
Min
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
(*3)-50
(*3)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
+5tCYCP
+5tCYCP
tCSSE
3tCYCP+30
-
3tCYCP+30
-
ns
tCSHE
External shift
0
-
0
-
ns
tCSDE
clock
3tCYCP+30
-
3tCYCP+30
-
ns
SCS↑→SOT delay time
tDSE
operation
-
40
-
40
ns
SCS↓→SOT delay time
tDEE
0
-
0
-
ns
operation
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
−
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral
Manual Main part (MN709-00001).
When the external load capacitance CL = 30 pF.
−
124
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tCSDI
tCSSI
tCSHI
SOT
(SPI=0)
SOT
(SPI=1)
tCSDE
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
SOT
(SPI=1)
tDSE
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
125
D a t a S h e e t
When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS=0, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↑→SCK↑setup time
tCSSI
SCK↓→SCS↓ hold time
tCSHI
SCS deselect time
tCSDI
Conditions
Internal shift
clock
operation
VCC ≥ 4.5 V
VCC < 4.5 V
Min
Max
Unit
Max
Min
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
(*3)-50
(*3)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
+5tCYCP
+5tCYCP
ns
SCS↑→SCK↑setup time
tCSSE
3tCYCP+30
-
3tCYCP+30
-
ns
SCK↓→SCS↓ hold time
tCSHE
External shift
0
-
0
-
ns
SCS deselect time
tCSDE
clock
3tCYCP+30
-
3tCYCP+30
-
ns
SCS↑→SOT delay time
tDSE
operation
-
40
-
40
ns
SCS↓→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
−
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral
Manual Main part (MN709-00001).
When the external load capacitance CL = 30 pF.
−
126
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tCSDI
tCSSI
tCSHI
SOT
(SPI=0)
SOT
(SPI=1)
tCSDE
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
SOT
(SPI=1)
tDSE
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
127
D a t a S h e e t
High-speed Synchronous Serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Serial clock cycle time
tSCYC
SCK↓→SOT delay time
tSLOVI
Pin Name
Conditions
SCKx
SCKx,
SOTx
Internal shift
SIN→SCK↑
tIVSHI
setup time
SCKx,
clock operation
SINx
Unit
Min
Max
Min
Max
4tCYCP
-
4tCYCP
-
ns
-10
+10
-10
+10
ns
-
12.5
-
ns
5
-
5
-
ns
14
12.5*
SCKx,
VCC ≥ 4.5V
VCC < 4.5V
SCK↑→SIN hold time
tSHIXI
Serial clock "L" pulse width
tSLSH
SCKx
2tCYCP – 5
-
2tCYCP – 5
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
-
15
-
15
ns
5
-
5
-
ns
5
-
5
-
ns
SIN→SCK↑
tIVSHE
setup time
SCK↑→SIN hold time
tSHIXE
SINx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
External shift
clock operation
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
128
CONFIDENTIAL
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
−
−
−
−
These characteristics only guarantee the following pins.
No chip select:SIN4_1, SOT4_1, SCK4_1
Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
VIH
VIL
SIN
tSHIXI
VIH
VIL
MS bit = 0
tSLSH
SCK
VIH
tF
SOT
VIL
tSHSL
VIL
VIH
VIH
tR
tSLOVE
VOH
VOL
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
129
D a t a S h e e t
High-speed Synchronous Serial (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Serial clock cycle time
tSCYC
SCK↑→SOT delay time
tSHOVI
SIN→SCK↓
tIVSLI
setup time
Pin Name
Conditions
SCKx
SCKx,
SOTx
Internal shift
SCKx,
clock operation
SINx
Unit
Min
Max
Min
Max
4tCYCP
-
4tCYCP
-
ns
-10
+10
-10
+10
ns
-
12.5
-
ns
5
-
5
-
ns
14
12.5*
SCKx,
VCC ≥ 4.5 V
VCC < 4.5 V
SCK↓→SIN hold time
tSLIXI
Serial clock "L" pulse width
tSLSH
SCKx
2tCYCP – 5
-
2tCYCP – 5
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
-
15
-
15
ns
5
-
5
-
ns
5
-
5
-
ns
SIN→SCK↓
tIVSLE
setup time
tSLIXE
SCK↓→SIN hold time
SINx
SCKx,
SOTx
External shift
SCKx,
clock operation
SINx
SCKx,
SINx
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
−
−
−
−
−
−
130
CONFIDENTIAL
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
These characteristics only guarantee the following pins.
No chip select:SIN4_1, SOT4_1, SCK4_1
Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
SCK
VIH
VIH
VIL
tR
SOT
tSLSH
VIL
VIL
tF
tSHOVE
VOH
VOL
SIN
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
MS bit = 1
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
131
D a t a S h e e t
High-speed Synchronous Serial (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Serial clock cycle time
tSCYC
SCK↑→SOT delay time
tSHOVI
SIN→SCK↓
tIVSLI
setup time
Pin Name
Conditions
SCKx
SCKx,
SOTx
Unit
Min
Max
Min
Max
4tCYCP
-
4tCYCP
-
ns
-10
+10
-10
+10
ns
-
12.5
-
ns
5
-
5
-
ns
2tCYCP – 10
-
2tCYCP – 10
-
ns
SCKx,
Internal shift
14
SINx
clock operation
12.5*
SCKx,
VCC ≥ 4.5 V
VCC < 4.5 V
SCK↓→SIN hold time
tSLIXI
SOT→SCK↓ delay time
tSOVLI
Serial clock "L" pulse width
tSLSH
SCKx
2tCYCP – 5
-
2tCYCP – 5
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
-
15
-
15
ns
5
-
5
-
ns
5
-
5
-
ns
SIN→SCK↓
tIVSLE
setup time
SCK↓→SIN hold time
tSLIXE
SINx
SCKx,
SOTx
SCKx,
SOTx
External shift
SCKx,
clock operation
SINx
SCKx,
SINx
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
−
−
−
−
−
−
132
CONFIDENTIAL
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
These characteristics only guarantee the following pins.
No chip select:SIN4_1, SOT4_1, SCK4_1
Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tSCYC
VOH
VOL
SCK
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
MS bit = 0
tSLSH
SCK
VIH
VIH
VIL
tF
*
SOT
VIL
tSHSL
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
133
D a t a S h e e t
High-speed Synchronous Serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Internal shift clock operation
tSCYC
SCK↓→SOT delay time
tSLOVI
SIN→SCK↑
tIVSHI
setup time
Pin Name
Conditions
SCKx
SCKx,
SOTx
SCKx,
SINx
Internal shift
clock
operation
SCKx,
VCC ≥ 4.5 V
VCC < 4.5 V
Unit
Min
Max
Min
Max
4tCYCP
-
4tCYCP
-
ns
-10
+10
-10
+10
ns
-
12.5
-
ns
5
-
5
-
ns
2tCYCP – 10
-
2tCYCP – 10
-
ns
14
12.5*
SCK↑→SIN hold time
tSHIXI
SOT→SCK↑ delay time
tSOVHI
Serial clock "L" pulse width
tSLSH
SCKx
2tCYCP – 5
-
2tCYCP – 5
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
-
15
-
15
ns
5
-
5
-
ns
5
-
5
-
ns
SIN→SCK↑
tIVSHE
setup time
tSHIXE
SCK↑→SIN hold time
SINx
SCKx,
SOTx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
External shift
clock
operation
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
−
−
−
−
−
−
134
CONFIDENTIAL
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
These characteristics only guarantee the following pins.
No chip select:SIN4_1, SOT4_1, SCK4_1
Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tSCYC
SCK
VOH
tSOVHI
SOT
tSLOVI
VOH
VOL
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
MS bit = 0
tSHSL
tR
SCK
VIL
VIH
tSLSH
VIH
VIL
tF
VIL
VIH
tSLOVE
SOT
VOH
VOL
VOH
VOL
tIVSHE
SIN
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
135
D a t a S h e e t
When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS=0,
CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↓→SCK↓setup time
tCSSI
SCK↑→SCS↑ hold time
tCSHI
Internal shift
clock operation
SCS deselect time
tCSDI
SCS↓→SCK↓setup time
tCSSE
SCK↑→SCS↑ hold time
tCSHE
External shift
VCC ≥ 4.5 V
VCC < 4.5 V
Conditions
Unit
Min
Max
Min
Max
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
(*2)+0
(*2)+20
(*2)+0
(*2)+20
ns
(*3)-20
(*3)+20
(*3)-20
(*3)+20
+5tCYCP
+5tCYCP
+5tCYCP
+5tCYCP
3tCYCP+15
-
3tCYCP+15
-
ns
0
-
0
-
ns
ns
SCS deselect time
tCSDE
3tCYCP+15
-
3tCYCP+15
-
ns
SCS↓→SOT delay time
tDSE
-
25
-
25
ns
SCS↑→SOT delay time
tDEE
0
-
0
-
ns
clock operation
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
136
CONFIDENTIAL
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral
Manual.
When the external load capacitance CL = 30 pF.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tCSDI
tCSSI
tCSHI
SOT
(SPI=1)
tCSDE
tCSSE
tCSHE
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
137
D a t a S h e e t
When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS=0,
CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↓→SCK↑setup time
tCSSI
SCK↓→SCS↑ hold time
tCSHI
SCS deselect time
tCSDI
SCS↓→SCK↑setup time
tCSSE
SCK↓→SCS↑ hold time
tCSHE
SCS deselect time
SCS↓→SOT delay time
SCS↑→SOT delay time
tDEE
Internal shift
clock
VCC ≥ 4.5 V
VCC < 4.5 V
Conditions
Unit
Min
Max
Min
Max
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
(*2)+0
(*2)+20
(*2)+0
(*2)+20
ns
(*3)-20
(*3)+20
(*3)-20
(*3)+20
+5tCYCP
+5tCYCP
+5tCYCP
+5tCYCP
3tCYCP+15
-
3tCYCP+15
-
ns
External shift
0
-
0
-
ns
tCSDE
clock
3tCYCP+15
-
3tCYCP+15
-
ns
tDSE
operation
-
25
-
25
ns
0
-
0
-
ns
operation
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
138
CONFIDENTIAL
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral
Manual Main part (MN709-00001).
When the external load capacitance CL = 30 pF.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tCSDI
tCSSI
tCSHI
SOT
(SPI=0)
SOT
(SPI=1)
tCSDE
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
139
D a t a S h e e t
When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS=0,
CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↑→SCK↓setup time
SCK↑→SCS↓ hold time
tCSSI
tCSHI
Internal shift
clock
operation
VCC ≥ 4.5 V
VCC < 4.5 V
Conditions
Unit
Min
Max
Min
Max
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
ns
(*2)+0
(*2)+20
(*2)+0
(*2)+20
(*3)-20
(*3)+20
(*3)-20
(*3)+20
+5tCYCP
+5tCYCP
+5tCYCP
+5tCYCP
3tCYCP+15
-
3tCYCP+15
-
ns
SCS deselect time
tCSDI
ns
SCS↑→SCK↓setup time
tCSSE
SCK↑→SCS↓ hold time
tCSHE
External shift
0
-
0
-
ns
SCS deselect time
tCSDE
clock
3tCYCP+15
-
3tCYCP+15
-
ns
SCS↑→SOT delay time
tDSE
operation
-
25
-
25
ns
SCS↓→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
140
CONFIDENTIAL
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral
Manual Main part (MN709-00001).
When the external load capacitance CL = 30 pF.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tCSDI
tCSSI
tCSHI
SOT
(SPI=0)
SOT
(SPI=1)
tCSDE
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
SOT
(SPI=1)
tDSE
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
141
D a t a S h e e t
When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS=0,
CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↑→SCK↑setup time
SCK↓→SCS↓ hold time
tCSSI
tCSHI
Internal shift
clock
operation
VCC ≥ 4.5 V
VCC < 4.5 V
Conditions
Unit
Min
Max
Min
Max
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
ns
(*2)+0
(*2)+20
(*2)+0
(*2)+20
(*3)-20
(*3)+20
(*3)-20
(*3)+20
+5tCYCP
+5tCYCP
+5tCYCP
+5tCYCP
3tCYCP+15
-
3tCYCP+15
-
ns
SCS deselect time
tCSDI
ns
SCS↑→SCK↑setup time
tCSSE
SCK↓→SCS↓ hold time
tCSHE
External shift
0
-
0
-
ns
SCS deselect time
tCSDE
clock
3tCYCP+15
-
3tCYCP+15
-
ns
SCS↑→SOT delay time
tDSE
operation
-
25
-
25
ns
SCS↓→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
142
CONFIDENTIAL
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 10. Block Diagram in this data sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral
Manual Main part (MN709-00001).
When the external load capacitance CL = 30 pF.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tCSDI
tCSSI
tCSHI
SOT
(SPI=0)
SOT
(SPI=1)
tCSDE
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
SOT
(SPI=1)
tDSE
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
143
D a t a S h e e t
External Clock (EXT = 1): when in Asynchronous Mode Only
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Condition
Value
Min
Max
Unit
Serial clock "L" pulse width
tSLSH
tCYCP + 10
-
ns
Serial clock "H" pulse width
tSHSL
tCYCP + 10
-
ns
-
5
ns
-
5
ns
SCK falling time
tF
SCK rising time
tR
CL = 30 pF
tR
SCK
144
CONFIDENTIAL
VIL
tSHSL
VIH
tF
tSLSH
VIH
VIL
Remarks
VIL
VIH
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
14.4.13 External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Max
-
2tCYCP*1
-
ns
-
2tCYCP*1
-
ns
Waveform generator
ADTG
FRCKx
Input pulse
tINH,
ICxx
width
tINL
DTTIxX
INT00 to INT31,
NMIX
WKUPx
Remarks
Min
A/D converter trigger input
Free-run timer input clock
Input capture
-
2tCYCP + 100*
1
-
ns
External interrupt,
500*2
-
ns
NMI
3
-
ns
Deep standby wake up
500*
*1: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode.
About the APB bus number which the A/D converter, multi-function timer, external interrupt are
connected to, see 10. Block Diagram in this data sheet.
*2: When in Stop mode, in timer mode.
*3: When in deep standby RTC mode, in Deep Standby Stop mode.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
145
D a t a S h e e t
14.4.14 Quadrature Position/Revolution Counter Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Value
Symbol
Conditions
AIN pin H width
tAHL
-
AIN pin L width
tALL
-
BIN pin H width
tBHL
-
BIN pin L width
tBLL
-
tAUBU
PC_Mode2 or PC_Mode3
tBUAD
PC_Mode2 or PC_Mode3
tADBD
PC_Mode2 or PC_Mode3
tBDAU
PC_Mode2 or PC_Mode3
tBUAU
PC_Mode2 or PC_Mode3
tAUBD
PC_Mode2 or PC_Mode3
tBDAD
PC_Mode2 or PC_Mode3
tADBU
PC_Mode2 or PC_Mode3
ZIN pin H width
tZHL
QCR:CGSC = 0
ZIN pin L width
tZLL
QCR:CGSC = 0
tZABE
QCR:CGSC = 1
tABEZ
QCR:CGSC = 1
BIN rising time from
AIN pin H level
AIN falling time from
BIN pin H level
BIN falling time from
AIN pin L level
AIN rising time from
BIN pin L level
AIN rising time from
BIN pin H level
BIN falling time from
AIN pin H level
AIN falling time from
BIN pin L level
BIN rising time from
AIN pin L level
AIN/BIN rising and falling time from
determined ZIN level
Determined ZIN level from AIN/BIN rising
and falling time
Min
Max
2tCYCP*
-
Unit
ns
*: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see 10. Block
Diagram in this data sheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
146
CONFIDENTIAL
tBLL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
147
D a t a S h e e t
14.4.15 I2C Timing
Typical Mode, High-speed Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
Typical Mode
High-speed Mode
Unit
Min
Max
Min
Max
FSCL
0
100
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
SCL clock "L" width
tLOW
4.7
-
1.3
-
μs
SCL clock "H" width
tHIGH
4.0
-
0.6
-
μs
4.7
-
0.6
-
μs
0
3.45*2
0
0.9*3
μs
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
2tCYCP*4
-
2tCYCP*4
-
ns
4tCYCP*4
-
4tCYCP*4
-
ns
6tCYCP*4
-
6tCYCP*4
-
ns
8tCYCP*4
-
8tCYCP*4
-
ns
SCL clock frequency
Remarks
(Repeated) START condition
hold time
SDA ↓ → SCL ↓
(Repeated) START condition
setup time
tSUSTA
SCL ↑ → SDA ↓
CL = 30 pF,
Data hold time
tHDDAT
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
R = (Vp/IOL)*1
Bus free time between
"STOP condition" and
"START condition"
2 MHz ≤
tCYCP<40 MHz
40 MHz ≤
tCYCP<60 MHz
60 MHz ≤
tCYCP<80 MHz
80 MHz ≤
Noise filter
tSP
tCYCP<100 MHz
100 MHz ≤
tCYCP<120 MHz
120 MHz ≤
tCYCP<140 MHz
140 MHz ≤
tCYCP<160 MHz
160 MHz ≤
tCYCP<180 MHz
*5
4
-
4
10tCYCP*
10tCYCP*
-
ns
12tCYCP*4
-
12tCYCP*4
-
ns
14tCYCP*4
-
14tCYCP*4
-
ns
16tCYCP*4
-
16tCYCP*4
-
ns
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
2
2
*3: A high-speed mode I C bus device can be used on a typical mode I C bus system as long as the device
satisfies the requirement of tSUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
2
About the APB bus number that I C is connected to, see "10. Block Diagram" in this data sheet.
*5: The noise filter time can be changed by register settings.
Change the number of the noise filter steps according to APB bus clock frequency.
148
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Fast Mode Plus (Fm+)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCL clock frequency
(Repeated) START condition hold time
SDA ↓ → SCL ↓
Conditions
Fast Mode Plus (Fm+)*6
Unit
Min
Max
FSCL
0
1000
kHz
tHDSTA
0.26
-
μs
SCL clock "L" width
tLOW
0.5
-
μs
SCL clock "H" width
tHIGH
0.26
-
μs
SCL clock frequency
tSUSTA
0.26
-
μs
0
0.45*2, *3
μs
tSUDAT
50
-
ns
tSUSTO
0.26
-
μs
tBUF
0.5
-
μs
6 tCYCP*4
-
ns
8 tCYCP*4
-
ns
10 tCYCP*4
-
ns
12 tCYCP*4
-
ns
14 tCYCP*4
-
ns
16 tCYCP*4
-
ns
(Repeated) START condition hold time
tHDDAT
SDA ↓ → SCL ↓
CL = 30 pF,
Remarks
1
R = (Vp/IOL)*
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
Bus free time between
"STOP condition" and
"START condition"
60 MHz ≤
tCYCP<80 MHz
80 MHz ≤
tCYCP<100 MHz
100 MHz ≤
Noise filter
tSP
tCYCP<120 MHz
120 MHz ≤
tCYCP<140 MHz
140 MHz ≤
tCYCP<160 MHz
160 MHz ≤
tCYCP<180 MHz
*5
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
2
2
*3: A high-speed mode I C bus device can be used on a typical mode I C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4: tCYCP is the APB bus clock cycle time.
2
About the APB bus number that I C is connected to, see 10. Block Diagram in this data sheet.
To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more.
*5: The noise filter time can be changed by register settings.
Change the number of the noise filter steps according to APB bus clock frequency.
2
*6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I C Fm+ in the EPFR
register. See CHAPTER 12: I/O Port in FM4 Family Peripheral Manual Main part (MN709-00001) for the
details.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
149
D a t a S h e e t
SDA
SCL
150
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
14.4.16 SD Card Interface Timing
Default-Speed Mode
Clock CLK (All values are referred to VIH and VIL)
(VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Clock frequency Data Transfer Mode
fPP
S_CLK
Clock frequency Identification Mode
fOD
S_CLK
Conditions
Value
Remarks
Min
Max
0
16
MHz
0*/100
400
kHz
10
-
ns
CCARD ≤ 10 pF
Clock low time
tWL
S_CLK
Clock high time
tWH
S_CLK
10
-
ns
Clock rising time
tTLH
S_CLK
-
10
ns
tTHL
S_CLK
-
10
ns
Clock falling time
(1 card)
*: 0 Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is
required.
Card Inputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Input set-up time
tISU
Input hold time
tIH
Pin Name
Conditions
S_CMD,
S_DATA3:0
CCARD ≤ 10 pF
S_CMD,
(1 card)
S_DATA3:0
Value
Remarks
Min
Max
5
-
ns
5
-
ns
Card Outputs CMD, DAT (referenced to Clock CLK)
Parameter
Output Delay time during Data
Transfer Mode
Output Delay time durinn
Identification Mode
Symbol
tODLY
tODLY
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
Pin Name
Conditions
S_CMD,
S_DATA3:0
CCARD ≤ 40 pF
S_CMD,
(1 card)
S_DATA3:0
Value
Remarks
Min
Max
0
22
ns
0
50
ns
151
D a t a S h e e t
tWH
tWL
S_CLK
(SD Clock)
VIH
VIH
VIH
VIL
VIL
tTLH
tTHL
tIH
tISU
S_CMD,
S_DATA3:0
(Card Input)
VIH
VIH
VIL
VIL
tODLY(Min)
tODLY(Max)
S_CMD,
S_DATA3:0
(Card Output)
VOH
VOH
VOL
VOL
Defalt-Speed Mode
Note:
−
152
CONFIDENTIAL
The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input
because this model is the Host.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
High-Speed Mode
Clock CLK (All values are referred to VIH and VIL)
(VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Clock frequency Data Transfer Mode
fPP
S_CLK
Clock low time
tWL
S_CLK
Clock high time
tWH
S_CLK
Clock rising time
tTLH
S_CLK
Clock falling time
tTHL
S_CLK
Value
Conditions
Remarks
Min
Max
0
32
MHz
CCARD ≤ 10 pF
7
-
ns
(1 card)
7
-
ns
-
3
ns
-
3
ns
Card Inputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Input set-up time
tISU
Input hold time
tIH
Pin Name
Value
Conditions
S_CMD,
S_DATA3:0
CCARD ≤ 10 pF
S_CMD,
(1 card)
S_DATA3:0
Remarks
Min
Max
8
-
ns
2
-
ns
Card Outputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Output Delay time during Data Transfer
tODLY
Mode
Output Hold time
tOH
Total System capacitance for each line*
Pin Name
Conditions
S_CMD,
CL ≤ 40 pF
S_DATA3:0
(1 card)
S_CMD,
CL ≥ 15 pF
S_DATA3:0
(1 card)
-
1 card
CL
Value
Remarks
Min
Max
-
22
ns
2.5
-
ns
-
40
pF
*: In order to satisfy severe timing, host shall drive only one card.
tWH
tWL
S_CLK
(SD Clock)
50%VCC
VIH
VIH
VIL
VIL
50%VCC
tTLH
tTHL
tIH
tISU
S_CMD,
S_DATA3:0
(Card Input)
VIH
VIH
VIL
VIL
tOH(Min)
tODLY(Max)
S_CMD,
S_DATA3:0
(Card Output)
VIH
VOH
VOH
VOL
VOL
High-Speed Mode
Notes:
−
−
The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input
because this model is the Host.
In high-speed mode, set the Clock frequency (fPP) and the AHB Bus Clock frequency to the same
values.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
153
D a t a S h e e t
14.4.17 ETM Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Data hold
tETMH
TRACECLK
Pin Name
Conditions
TRACECLK,
TRACED[3:0]
Value
Unit
Min
Max
VCC ≥ 4.5 V
2
9
VCC < 4.5 V
2
15
VCC ≥ 4.5 V
-
50
MHz
VCC < 4.5 V
-
32
MHz
VCC ≥ 4.5 V
20
-
ns
VCC < 4.5 V
31.25
-
ns
Remarks
ns
1/ tTRACE
frequency
TRACECLK
TRACECLK
tTRACE
clock cycle
Note:
−
When the external load capacitance CL= 30 pF.
HCLK
TRACECLK
TRACED[3:0]
154
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
14.4.18 JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
TMS, TDI setup time
tJTAGS
TMS, TDI hold time
tJTAGH
TDO delay time
tJTAGD
Pin Name
Conditions
TCK,
VCC ≥ 4.5 V
TMS, TDI
VCC < 4.5 V
TCK,
VCC ≥ 4.5 V
TMS, TDI
VCC < 4.5 V
Value
Unit
Min
Max
15
-
ns
15
-
ns
TCK,
VCC ≥ 4.5 V
-
25
TDO
VCC < 4.5 V
-
45
Remarks
ns
Note:
−
When the external load capacitance CL= 30 pF.
TCK
TMS/TDI
TDO
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
155
D a t a S h e e t
14.5 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V)
Parameter
Symbol
Pin Name
Resolution
-
Integral Nonlinearity
Differential Nonlinearity
Value
Unit
Remarks
Min
Typ
Max
-
-
-
12
bit
-
-
-4.5
-
+4.5
LSB
-
-
-2.5
-
+2.5
LSB
AVRH =
Zero transition voltage
VZT
AN00 to AN23
-15
-
+15
mV
2.7 V to 5.5 V
Full-scale transition voltage
VFST
AN00 to AN23
AVRH - 15
-
AVRH + 15
mV
-
-
μs
10
μs
Conversion time
-
Sampling time
Ts
Compare clock cycle*3
State transition time to
operation permission
Power supply current (analog
+ digital)
Tcck
-
0.5*
1
*2
-
*2
-
25
-
Tstt
-
-
AVCC
ns
-
AVRH
AVCC ≥ 4.5V
AVCC < 4.5V
AVCC ≥ 4.5V
50
-
1000
1.0
-
-
μs
-
0.69
0.92
mA
A/D 1 unit operation
-
1.0
18
μA
When A/D stop
1.1
1.97
mA
0.3
6.3
μA
12.05
pF
Reference power supply
current
1000
-
AVCC ≥ 4.5V
-
(between AVRH and AVSS)
Analog input capacity
CAIN
-
-
-
Analog input resistance
RAIN
-
-
-
1.2
1.8
AVCC < 4.5V
kΩ
Interchannel disparity
-
-
-
-
4
LSB
Analog port input current
-
AN00 to AN23
-
-
5
μA
Analog input voltage
-
AN00 to AN23
AVSS
-
AVRH
V
Reference voltage
-
AVRH
4.5
-
AVCC
2.7
-
AVCC
V
A/D 1unit operation
AVRH=5.5 V
When A/D stop
AVCC ≥ 4.5 V
AVCC < 4.5 V
Tcck < 50 ns
Tcck ≥ 50 ns
*1: The conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is when the value of sampling time: 150 ns, the value of
compare time: 350 ns (AVCC ≥ 4.5 V). Ensure that it satisfies the value of sampling time (Ts) and compare
4
clock cycle (Tcck). For setting* of sampling time and compare clock cycle, see CHAPTER 1-1: A/D
Converter in FM4 Family Peripheral Manual Analog macro part (MN709-00001). The register setting of
the A/D Converter is reflected by the peripheral clock timing. The sampling and compare clock are set at
Base clock (HCLK).
*2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to
satisfy (Equation 1).
*3: The compare time (Tc) is the value of (Equation 2).
*4: The register setting of the A/D Converter is reflected by the timing of the APB bus clock. The sampling
clock and compare clock are set in base clock (HCLK). About the APB bus number which the A/D
Converter is connected to, see 10. Block Diagram in this data sheet.
156
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Comparator
AN00 to AN23
Analog input pin
Analog signal
source
Rext
RAIN
CAIN
(Equation 1) Ts ≥ (RAIN + Rext ) × CAIN × 9
Ts
: Sampling time
RAIN : Input resistance of A/D = 1.2kΩ at 4.5 V < AVCC < 5.5 V
Input resistance of A/D = 1.8kΩ at 2.7 V < AVCC < 4.5 V
CAIN : Input capacity of A/D = 12.05pF at 2.7 V < AVCC < 5.5 V
Rext : Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc
: Compare time
Tcck : Compare clock cycle
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
157
D a t a S h e e t
Definition of 12-bit A/D Converter Terms
− Resolution: Analog variation that is recognized by an A/D converter.
− Integral Nonlinearity: Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→
0b111111111111) from the actual conversion characteristics.
− Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
0xN
Ideal characteristics
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
AVss
Actual conversion characteristics
AVRH
AVss
AVRH
Analog input
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VZT
4094
N: A/D converter digital output value.
VZT: Voltage at which the digital output changes from 0x000 to 0x001.
VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN.
158
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
14.6 12-bit D/A Converter
Electrical Characteristics for the D/A Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Resolution
Conversion time
Remarks
Max
-
-
-
12
bit
tc20
0.56
0.69
0.81
μs
Load 20 pF
tc100
2.79
3.42
4.06
μs
Load 100 pF
INL
DNL
Power supply current*
Unit
Typ
Differential Nonlinearity*
Analog output impedance
Value
Min
Integral Nonlinearity*
Output voltage offset
Pin Name
DAx
VOFF
RO
IDDA
AVCC
IDSA
-16
-
+16
LSB
-0.98
-
+1.5
LSB
-
-
10.0
mV
When setting 0x000
-20.0
-
+1.4
mV
When setting 0xFFF
3.10
3.80
4.50
kΩ
D/A operation
2.0
-
-
MΩ
When D/A stop
260
330
410
μA
D/A 1unit operation AVCC=3.3 V
400
510
620
μA
D/A 1unit operation AVCC=5.0 V
-
-
14
μA
When D/A stop
*: During no load
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
159
D a t a S h e e t
14.7 USB Characteristics
(VCC = 2.7V to 5.5V, USBVCC = 3.0V to 3.6V, VSS = 0V)
Parameter
Input
Symbol
Pin
Name
Conditions
Value
Min
Max
USBVCC +
Unit
Remarks
V
*1
Input H level voltage
VIH
-
2.0
Input L level voltage
VIL
-
VSS - 0.3
0.8
V
*1
Differential input sensitivity
VDI
-
0.2
-
V
*2
VCM
-
0.8
2.5
V
*2
2.8
3.6
V
*3
0.0
0.3
V
*3
0.3
characte
r-istics
Different common mode
range
Output
characte
r-istics
Output "H" level voltage
VOH
Output "L" level voltage
VOL
Crossover voltage
VCRS
External pull-down
resistance = 15 kΩ
External pull-up
UDP0,
resistance = 1.5 kΩ
UDM0
-
1.3
2.0
V
*4
Rising time
tFR
Full-Speed
4
20
ns
*5
Falling time
tFF
Full-Speed
4
20
ns
*5
tFRFM
Full-Speed
90
111.11
%
*5
Rising/falling time
matching
ZDRV
Full-Speed
28
44
Ω
*6
Rising time
tLR
Low-Speed
75
300
ns
*7
Falling time
tLF
Low-Speed
75
300
ns
*7
tLRFM
Low-Speed
80
125
%
*7
Output impedance
Rising/falling time
matching
*1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) =
0.8 V, VIH (Min) = 2.0 V (TTL input standard).
There are some hysteresis to lower noise sensitivity.
Minimum differential input
sensitivity [V]
*2: Use differential-Receiver to receive USB differential data signal.
Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within
0.8 V to 2.5 V to the local ground reference level.
Above voltage range is the common mode input voltage range.
Common mode input voltage [V]
160
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
*3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and
2.8 V or above (to the VSS and 1.5 kΩ load) at High-State (VOH).
*4: The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to
2.0 V.
VCRS specified range
*5: They indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.
Rising time
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
Falling time
161
D a t a S h e e t
*6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic
impedance (Differential Mode).
USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So,
discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) Series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistance.
Rs series resistor 25 Ω to 30 Ω
Series resistor of 27 Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence".
*7 : They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
Rising time
Falling time
See Low-Speed Load (Compliance Load) for conditions of external load.
162
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Low-Speed Load (Upstream Port Load) - Reference 1
CL = 50pF to 150pF
CL = 50pF to 150pF
Low-Speed Load (Downstream Port Load) - Reference 2
CL =200pF to
600pF
CL =200pF to
600pF
Low-Speed Load (Compliance Load)
CL = 200pF to 450pF
CL = 200pF to 450pF
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
163
D a t a S h e e t
14.8 Low-Voltage Detection Characteristics
14.8.1
Low-Voltage Detection Reset
Parameter
Symbol
Conditions
Detected voltage
VDL
Released voltage
VDH
14.8.2
Value
Unit
Remarks
Min
Typ
Max
-
2.25
2.45
2.65
V
When voltage drops
-
2.30
2.50
2.70
V
When voltage rises
Interrupt of Low-Voltage Detection
Parameter
Symbol
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
LVD stabilization wait time
TLVDW
Conditions
SVHI = 00111
SVHI = 00100
SVHI = 01100
SVHI = 01111
SVHI = 01110
SVHI = 01001
SVHI = 01000
SVHI = 11000
-
Value
Unit
Remarks
Min
Typ
Max
2.58
2.8
3.02
V
When voltage drops
2.67
2.9
3.13
V
When voltage rises
2.76
3.0
3.24
V
When voltage drops
2.85
3.1
3.34
V
When voltage rises
2.94
3.2
3.45
V
When voltage drops
3.04
3.3
3.56
V
When voltage rises
3.31
3.6
3.88
V
When voltage drops
3.40
3.7
3.99
V
When voltage rises
3.40
3.7
3.99
V
When voltage drops
3.50
3.8
4.10
V
When voltage rises
3.68
4.0
4.32
V
When voltage drops
3.77
4.1
4.42
V
When voltage rises
3.77
4.1
4.42
V
When voltage drops
3.86
4.2
4.53
V
When voltage rises
3.86
4.2
4.53
V
When voltage drops
3.96
4.3
4.64
V
When voltage rises
-
-
4480×
tCYCP*
μs
*: tCYCP indicates the APB2 bus clock cycle time.
164
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
14.9 MainFlash Memory Write/Erase Characteristics
(VCC = 2.7V to 5.5V)
Value
Parameter
Min
Sector erase
Large Sector
time
Small Sector
-
Typ
Max
0.7
3.7
0.3
1.1
Write cycles
Half word
< 100 times
(16-bit)
Write cycles >
write time
Remarks
s
Includes write time prior to internal erase
μs
Not including system-level overhead time
s
Includes write time prior to internal erase
100
-
12
200
100 times
Chip erase time
Unit
-
13.6
68
Write cycles and data hold time
Erase/Write cycles (cycle)
Data hold time (year)
1,000
20 *
10,000
10 *
100,000
5*
*: This value comes from the technology qualification (using Arrhenius equation to translate high
temperature acceleration test result into average temperature value at +85°C) .
14.10 WorkFlash Memory Write/Erase Characteristics
(VCC = 2.7V to 5.5V)
Value
Parameter
Sector erase time
Half word (16-bit)
write time
Chip erase time
Unit
Remarks
1.5
s
Includes write time prior to internal erase
20
200
μs
Not including system-level overhead time
1.2
6
s
Includes write time prior to internal erase
Min
Typ
Max
-
0.3
-
Write cycles and data hold time
Erase/Write cycles (cycle)
Data hold time (year)
1,000
20 *
10,000
10 *
100,000
5*
*: This value comes from the technology qualification (using Arrhenius equation to translate high
temperature acceleration test result into average temperature value at +85°C) .
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
165
D a t a S h e e t
14.11 Standby Recovery Time
14.11.1 Recovery cause: Interrupt/WKUP
The time from recovery cause reception of the internal circuit to the program operation start is
shown.
Recovery Count Time
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Unit
Typ
Sleep mode
Remarks
Max*
μs
HCLK×1
High-speed CR Timer mode
40
80
μs
Low-speed CR timer mode
450
900
μs
Sub timer mode
896
1136
μs
316
540
μs
270
480
365
667
μs
365
667
μs
Main Timer mode
PLL Timer mode
RTC mode
stop mode
(High-speed CR /Main/PLL run mode
Ticnt
return)
RTC mode
stop mode
(Low-speed CR/sub run mode return)
Deep standby RTC mode with RAM
retention
Deep standby stop mode with RAM
retention
without RAM
retention
with RAM
retention
*: The maximum value depends on the built-in CR accuracy.
Example of Standby Recovery Operation (when in External Interrupt Recovery*)
Ext.INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
166
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Example of Standby Recovery Operation (when in Internal Resource Interrupt Recovery*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause.
Notes:
−
−
The return factor is different in each Low-Power consumption modes.
See CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family
Peripheral Manual Main part (MN709-00001).
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the
Low-Power consumption mode transition. See CHAPTER 6: Low Power Consumption Mode in FM4
Family Peripheral Manual Main part (MN709-00001).
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
167
D a t a S h e e t
14.11.2 Recovery Cause: Reset
The time from reset release to the program operation start is shown.
Recovery Count Time
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Sleep mode
Unit
Typ
Max*
155
266
μs
155
266
μs
315
567
μs
315
567
μs
315
567
μs
Remarks
High-speed CR timer mode
Main timer mode
PLL timer mode
Low-speed CR timer mode
Sub timer mode
Trcnt
RTC mode
Stop mode
μs
Deep standby RTC mode with RAM retention
336
Deep standby stop mode with RAM retention
667
μs
without RAM
retention
with RAM
retention
*: The maximum value depends on the built-in CR accuracy.
Example of Standby Recovery Operation (when in INITX Recovery)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
168
CONFIDENTIAL
Start
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Example of Standby Recovery Operation (when in Internal Resource Reset Recovery*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Depending on the standby mode, the reset issue from the internal resource is not included in the recovery
cause.
Notes:
−
−
−
−
The return factor is different in each Low-Power consumption modes.
See CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family
Peripheral Manual Main part (MN709-00001).
The time during the power-on reset/low-voltage detection reset is excluded to the recovery source.
See (6) Power-on Reset Timing in 14.4 AC Characteristics in 14. Electrical Characteristics for the
detail on the time during the power-on reset/low-voltage detection reset.
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main
clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the
main PLL clock stabilization wait time.
The internal resource reset means the watchdog reset and the CSV reset.
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
169
D a t a S h e e t
15. Ordering Information
Part Number
Flash
RAM
MB9BF568MPMC-G-JNE2
1 MB
128 KB
MB9BF567MPMC-G-JNE2
768 KB
96 KB
MB9BF566MPMC-G-JNE2
512 KB
64 KB
MB9BF568MPMC1-G-JNE2
1 MB
128 KB
MB9BF567MPMC1-G-JNE2
768 KB
96 KB
MB9BF566MPMC1-G-JNE2
512 KB
64 KB
MB9BF568NPMC-G-JNE2
1 MB
128 KB
MB9BF567NPMC-G-JNE2
768 KB
96 KB
MB9BF566NPMC-G-JNE2
512 KB
64 KB
MB9BF568RPMC-G-JNE2
1 MB
128 KB
MB9BF567RPMC-G-JNE2
768 KB
96 KB
MB9BF566RPMC-G-JNE2
512 KB
64 KB
MB9BF568NBGL-GE1
1 MB
128 KB
MB9BF567NBGL-GE1
768 KB
96 KB
MB9BF566NBGL-GE1
512 KB
64 KB
MB9BF568RBGL-GE1
1 MB
128 KB
MB9BF567RBGL-GE1
768 KB
96 KB
Plastic・PFBGA (0.5 mm pitch), 144 pin
MB9BF566RBGL-GE1
512 KB
64 KB
(BGA-144P-M09)
1 MB
128 KB
MB9BF568NPQC-G-JNE2
1 MB
128 KB
MB9BF567NPQC-G-JNE2
768 KB
96 KB
MB9BF566NPQC-G-JNE2
512 KB
64 KB
MB9BF568FBGL-000GE1
170
CONFIDENTIAL
Package
Plastic・LQFP (0.5 mm pitch), 80 pin
(FPT-80P-M37)
Plastic・LQFP (0.65 mm pitch), 80 pin
(FPT-80P-M40)
Plastic・LQFP (0.5 mm pitch), 100 pin
(FPT-100P-M23)
Plastic・LQFP (0.5 mm pitch), 120 pin
(FPT-120P-M37)
Plastic・PFBGA (0.5 mm pitch), 112 pin
(BGA-112P-M05)
Plastic・QFP (0.65 mm pitch), 100 pin
(FPT-100P-M36)
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
16. Package Dimensions
120-pin plastic LQFP
(FPT-120P-M37)
120-pin plastic LQFP
(FPT-120P-M37)
Lead pitch
0.50 mm
Package width ×
package length
16.0 mm × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.88 g
Code
(Reference)
P-LFQFP120-16 × 16-0.50
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00 ± 0.20(.709 ± .008) SQ
* 16.00 ± 0.10(.630 ± .004) SQ
90
61
91
Details of "A" part
60
+0.20
+.008
1.50 –0.10 .059 –.004
(Mounting height)
0.25(.010)
0.08(.003)
0˚~8˚
INDEX
0.60 ± 0.15
(.024 ± .006)
"A"
120
LEAD No.
1
30
0.50(.020)
C
0.22 ± 0.05
(.009 ± .002)
0.08(.003)
2010 FUJITSU SEMICONDUCTOR LIMITED F120037Sc(1)-1-1
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
0.10 ± 0.05
(.004 ± .002)
(Stand off)
31
+0.05
0.145–0.03
( .006+.002
–.001 )
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values
171
D a t a S h e e t
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.00 mm × 14.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.65 g
(FPT-100P-M23)
100-pin plastic LQFP
(FPT-100P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +0.20
- 0.10
(.059+.008
-.004)
(Mounting height)
INDEX
100
26
"A"
1
C
0.22±0.05
(.009±.002)
0.08(.003)
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4
172
CONFIDENTIAL
0.60±0.15
(.024±.006)
25
0.50(.020)
0°~8°
0.50±0.20
(.020±.008)
M
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
0.145±0.055
(.006±.002)
Dimensions in mm (inches).
Note:The values in parentheses are reference values.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 mm × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14 × 20-0.65
(FPT-100P-M36)
100-pin plastic QFP
(FPT-100P-M36)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90± 0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
0.32 ± 0.05
(.013±.002)
0.13(.005)
"A"
C
2011 FUJITSU SEMICONDUCTOR LIMITED HMbF100-36Sc-1-1
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8°
31
M
0.17 ± 0.06
(.007 ±. 002)
0.80 ± 0.20
(.031 ±. 008)
0.88 ± 0.15
(.035 ±. 006)
0.25 ± 0.20
(.010 ±. 008)
(Stand off)
Dimensions in mm (inches).
Note: The valuesin parentheses are reference values.
173
D a t a S h e e t
80-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
(FPT-80P-M37)
80-pin plastic LQFP
(FPT-80P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00± 0.20(.551 ± .008)SQ
*12.00± 0.10(.472 ± .004)SQ
60
0.145± 0.055
(.006 ± .002)
41
Details of "A" part
61
40
+0.20
1.50 –0.10
(Mounting height)
+.008
.059 –.004
0.25(.010)
0~8°
0.08(.003)
INDEX
80
0.50 ± 0.20
(.020 ± .008)
0.60 ± 0.15
(.024 ± .006)
0.10 ± 0.05
(.004 ± .002)
(Stand off)
21
"A"
1
20
0.50(.020)
0.22± 0.05
(.009± .002)
C
0.08(.003)
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2
174
CONFIDENTIAL
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
80-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 mm × 14.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.60 mm Max.
Code
(Reference)
P-LQFP80-14 × 14-0.65
(FPT-80P-M40)
80-pin plastic LQFP
(FPT-80P-M40)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
60
0.145±0.055
(.006±.002)
41
Details of "A" part
40
61
1.50±0.10
(.059±.004)
0.25(.010)
0.10(.004)
0˚~7˚
INDEX
0.50±0.20
(.020±.008)
21
80
0.65(.026)
C
0.60±0.15
(.024±.006)
20
1
0.32±0.06
(.013±.002)
0.13(.005)
M
2012 FUJITSU SEMICONDUCTOR LIMITED HMbF80-40Sc-1-1
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
0.10±0.05
(.004±.002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
175
D a t a S h e e t
112-ball plastic FBGA
Ball pitch
0.50 mm
Package width ×
package length
7.00 mm × 7.00 mm
Lead shape
Ball
Sealing method
Plastic mold
Mounting height
1.35 mm Max.
Weight
0.10 g
(BGA-112P-M05)
112-ball plastic FBGA
(BGA-112P-M05)
6.00(.236)REF
7.00±0.10(.276±.004)
0.20(.008) S B
B
A
7.00±0.10
(.276±.004)
6.00(.236)
REF
0.50(.020)
TYP
0.20(.008) S A
(INDEX AREA)
S
0.10(.004) S
C
0.25±0.10
(.010±.004)
(Stand off)
2008-2010 FUJITSU SEMICONDUCTOR LIMITED B112005S-c-2-3
176
CONFIDENTIAL
0.50(.020)
TYP
13
12
11
10
9
8
7
6
5
4
3
2
1
N M L K J H G F E D C B A
INDEX
(NO BALL)
112-ø0.30±0.10
ø0.05(.002) M S A B
(112-ø.012±.004)
1.15±0.20
(.045±.008)
(Seated height)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
144-pin plastic FBGA
Lead pitch
0.5 mm
Package width ×
package length
7.0 mm × 7.0 mm
Sealing method
Plastic mold
Mounting height
1.3 mm MAX
Weight
0.11 g
(BGA-144P-M09)
144-pin plastic FBGA
(BGA-144P-M09)
7.00±0.10(.276±.004)
0.20(.008) S A
6.00(.236)
0.50(.020)
A
13
12
11
10
9
8
7
6
5
4
3
2
1
B
7.00±0.10
(.276±.004)
6.00(.236)
0.50(.020)
INDEX AREA
N M L K J H G F E D C B A
INDEX
(No Ball)
0.20(.008) S B
S
0.08(.003) S
C
0.25±0.10
(.010±.004)
(STAND OFF)
2010 FUJITSU SEMICONDUCTOR LIMITED HMbB144-09Sc-1-1
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
144-ø0.30±0.10
(144-ø.012±.004)
ø0.05(.002)
M
S A B
1.15±0.15
(.045±.006)
(SEATED HEIGHT)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
177
D a t a S h e e t
17. Major Changes
Page
Section
Change Results
Revision 1.0
-
-
Preliminary → Data Sheet
Deleted the following description :
1
The products which are described in this data sheet are placed into
■DESCRIPTION
TYPE4 product categories in "FM4
Family PERIPHERAL MANUAL".
Added the following description :
3
■FEATURES
・The size of each endpoint is according to the follows.
[USB function]
- Endpoint 0, 2 to 5 : 64bytes
- Endpoint 1 : 256bytes
Revised the following description :
4
■FEATURES
Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3 and ch.7)
lMulti-function Serial Interface
supported
[I2C]
→Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A and
ch.7=ch.B) supported
7
9
51,52
59
60
74
■FEATURES
Added new section
lUnique ID
■PRODUCT LINEUP
Added “Unique ID”
lFunction
■I/O CIRCUIT TYPE
Revised the remarks of “Type O, P, Q”
■HANDLING DEVICES
lHandling when using debug pins
■BLOCK DIAGRAM
Revised the block diagram
■ELECTRICAL CHARACTERISTICS
Revised “Table for package thermal resistance and maximum
2. Recommended Operating Conditions
permissible power”
■ELECTRICAL CHARACTERISTICS
77 to 82
Added new section
3. DC Characteristics
• Revised the value of TBD
• Revised the unit of “ICCHD”, “ICCRD”, “ICCVBAT”
mA → µA
(1) Current Rating
• Added the note to “ICCVBAT”
■ELECTRICAL CHARACTERISTICS
87
4. AC Characteristics
Revised the waveform chart
(2) Sub Clock Input Characteristics
■ELECTRICAL CHARACTERISTICS
87
4. AC Characteristics
(3) Built-in CR OscillationCharacteristics
■ELECTRICAL CHARACTERISTICS
146
5. 12-bit A/D Converter
・Electrical Characteristics for the A/D Converter
149
• Revised the value of TBD
• Revised the condition of the electrical characteristics table
• Revised the value of TBD
6. 12-bit D/A Converter
• Revised the condition and Remarks of the electrical
・Electrical Characteristics for the D/A Converter
characteristics table
11. Standby Recovery Time
(1) Recovery cause: Interrupt/WKUP
■ELECTRICAL CHARACTERISTICS
158
• Revised the table and the note of “Built-in High-speed CR”
■ELECTRICAL CHARACTERISTICS
■ELECTRICAL CHARACTERISTICS
156
• Revised the value of TBD
11. Standby Recovery Time
• Revised the value of TBD
• Revised the table of Recovery count time
• Revised the value of TBD
• Revised the table of Recovery count time
(2) Recovery cause:Reset
Revision 1.1
178
CONFIDENTIAL
-
Company name and layout design change
MB9B560R_DS709-00001-2v0-E, February 2, 2015
D a t a S h e e t
Page
Section
Change Results
Revision 2.0
1,3
5
13,14
Title
2. Features
3. Product Lineup
15
4. Packages
169
15. Ordering Information
February 2, 2015, MB9B560R_DS709-00001-2v0-E
CONFIDENTIAL
Added the following product.
MB9BF568F
Added the Voice Function
Added the following product.
MB9BF568F
Added the following product.
MB9BF568F
Added the following product.
MB9BF568FBGL-000GE1
179
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control,
mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where
chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions. If any products described in this document
represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law
of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the
respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion
product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without
notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy,
completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other
warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of
the information in this document.
®
®
®
TM
Copyright © 2014-2015 Spansion
All rights reserved. Spansion , the Spansion logo, MirrorBit , MirrorBit Eclipse ,
TM
TM
TM
ORNAND , Easy DesignSim , Traveo and combinations thereof, are trademarks and registered trademarks of Spansion
LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks
of their respective owners.
180
CONFIDENTIAL
MB9B560R_DS709-00001-2v0-E, February 2, 2015