A6985F
38 V 500 mA synchronous step-down switching regulator
with 30 µA quiescent current
Datasheet - production data
Description
HTSSOP16 (RTH = 40 °C/W)
Features
AECQ100 qualification
0.5 A DC output current
4 V to 38 V operating input voltage
Low consumption mode or low noise mode
30 µA IQ at light-load (LCM VOUT = 3.3 V)
8 µA IQ-SHTDWN
Fixed output voltage (3.3 V and 5 V) or
adjustable from 0.85 V to VIN
Adjustable fSW (250 kHz - 2 MHz)
Embedded output voltage supervisor
Synchronization
Adjustable soft-start time
Internal current limiting
The A6985F automotive grade device is a stepdown monolithic switching regulator able to
deliver up to 0.5 A DC. The output voltage
adjustability ranges from 0.85V to VIN. The 100%
duty cycle capability and the wide input voltage
range meet the cold crank and load dump
specifications for automotive systems. The “Low
Consumption Mode” (LCM) is designed for
applications active during car parking, so it
maximizes the efficiency at light-load with
controlled output voltage ripple. The “Low Noise
Mode” (LNM) makes the switching frequency
constant and minimizes the output voltage ripple
overload current range, meeting the low noise
application specification like car audio. The output
voltage supervisor manages the reset phase for
any digital load (µC, FPGA). The RST open
collector output can also implement output
voltage sequencing during the power-up phase.
The synchronous rectification, designed for high
efficiency at medium - heavy load, and the high
switching frequency capability make the size of
the application compact. Pulse by pulse current
sensing on both power elements implements an
effective constant current protection.
Overvoltage protection
Output voltage sequencing
Peak current mode architecture
RDSON HS = 360 m, RDSON LS = 150 m
Thermal shutdown
Applications
Designed for automotive systems
Battery powered applications
Car body applications (LCM)
Car audio and low noise applications (LNM)
April 2015
This is information on a product in full production.
DocID027738 Rev 2
1/77
www.st.com
Contents
A6985F
Contents
1
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Datasheet parameters over the temperature range . . . . . . . . . . . . . . . 13
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2
Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3
Soft-start and inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.1
Ratiometric startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3.2
Output voltage sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4
Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.5
Light-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.6
5.7
5.5.1
Low noise mode (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.5.2
Low consumption mode (LCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.6.1
LCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.6.2
LNM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
OCP and switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2/77
5.8
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.9
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DocID027738 Rev 2
A6985F
6
7
8
Contents
Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1
GCO(s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2
Error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3
Voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.1
Internal voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.2
External voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4
Total loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.5
Compensation network design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.1
Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2
Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.3
MLF pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.4
Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5
Synchronization (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.6
Design of the power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.6.1
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.6.2
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.6.3
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1
A6985F3V3 evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.2
A6985F5V evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.3
A6985F (VOUT = 6 V) evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9
Efficiency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10
EMC testing results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
HTSSOP16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DocID027738 Rev 2
3/77
77
Application schematic
1
A6985F
Application schematic
Figure 1. A6985F3V3 application schematic
4/77
DocID027738 Rev 2
A6985F
Pin settings
2
Pin settings
2.1
Pin connection
Figure 2. Pin connection (top view)
2.2
345
7#*"4
7$$
7*/
44*/)
-9
-9
1(/%
&9104&%
1"%50
4(/%
4:/$)*4,*1
'48
.-'
1(/%
$0.1
4(/%
%&-":
7065
Pin description
Table 1. Pin description
No.
Pin
Description
1
RST
The RST open collector output is driven low when the output voltage is out of regulation. The RST
is released after an adjustable time DELAY once the output voltage is over the active delay
threshold.
2
VCC
Connect a ceramic capacitor (≥ 470 nF) to filter internal voltage reference. This pin supplies the
embedded analog circuitry.
3
SS/INH
An open collector stage can disable the device clamping this pin to GND (INH mode). An internal
current generator (2 A typ.) charges the external capacitor to implement the soft-start.
4
SYNCH/
ISKP
The pin features Master / Slave synchronization in LNM (see Section 7.5 on page 47) and skip
current level selection in LCM (see Section 5.5.2 on page 26).
5
FSW
A pull up resistor (E24 series only) to VCC or pull down to GND selects the switching frequency.
Pinstrapping is active only before the soft-start phase to minimize the IC consumption.
6
MLF
A pull up resistor (E24 series only) to VCC or pull down to GND selects the low noise mode/low
consumption mode and the active RST threshold. Pinstrapping is active only before the soft-start
phase to minimize the IC consumption.
7
COMP
Output of the error amplifier. The designed compensation network is connected at this pin.
8
DELAY
An external capacitor connected at this pin sets the time DELAY to assert the rising edge of the
RST o.c. after the output voltage is over the reset threshold. If this pin is left floating, RST is like
a Power Good.
9
VOUT
Output voltage sensing
10
SGND
Signal GND
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77
Pin settings
A6985F
Table 1. Pin description (continued)
No.
Pin
11
PGND
Power GND
12
PGND
Power GND
13
LX
Switching node
14
LX
Switching node
15
VIN
DC input voltage
16
VBIAS
Typically connected to the regulated output voltage. An external voltage reference can be used to
supply part of the analog circuitry to increase the efficiency at light-load. Connect to GND if not
used.
-
E. p.
Exposed pad must be connected to SGND, PGND.
2.3
Description
Maximum ratings
Stressing the device above the rating listed in Table 2: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Table 2. Absolute maximum ratings
Symbol
Description
Min.
Max.
Unit
VIN
-0.3
40
V
DELAY
-0.3
VCC + 0.3
V
PGND
SGND - 0.3
SGND + 0.3
V
SGND
V
VCC
-0.3
(VIN + 0.3) or (max. 4)
V
SS / INH
-0.3
VIN + 0.3
V
-0.3
VCC + 0.3
V
-0.3
VCC + 0.3
V
VOUT
-0.3
10
V
FSW
-0.3
VCC + 0.3
V
SYNCH
-0.3
VIN + 0.3
V
VBIAS
-0.3
(VIN + 0.3) or (max. 6)
V
RST
-0.3
VIN + 0.3
V
LX
-0.3
VIN + 0.3
V
-40
150
°C
MLF
COMP
See Table 1
TJ
Operating temperature range
TSTG
Storage temperature range
-65 to 150
°C
TLEAD
Lead temperature (soldering 10 sec.)
260
°C
IHS, ILS
High-side / low-side switch current
2
A
6/77
DocID027738 Rev 2
A6985F
2.4
Pin settings
Thermal data
Table 3. Thermal data
Symbol
Rth JA
2.5
Parameter
Value
Unit
40
C/W
Value
Unit
HBM
2
kV
MM
200
V
CDM
500
V
Thermal resistance junction ambient (device soldered on the
STMicroelectronics® demonstration board)
ESD protection
Table 4. ESD protection
Symbol
ESD
Test condition
DocID027738 Rev 2
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77
Electrical characteristics
3
A6985F
Electrical characteristics
TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.
Table 5. Electrical characteristics
Symbol
Parameter
VIN
Operating input voltage range
VINH
VINL
IPK
IVY
ISKIP
IVY_SNK
Test condition
Note Min.
Typ.
Max.
4
38
VCC UVLO rising threshold
2.7
3.5
VCC UVLO falling threshold
2.4
3.5
Peak current limit
Duty cycle < 20%
0.8
Duty cycle = 100%
closed loop operation
0.65
Valley current limit
Skip current limit
Reverse current limit
0.9
LCM, VSYNCH = GND
(1)
LCM, VSYNCH = VCC
(2)
LNM or VOUT overvoltage
0.15
0.35
0.5
0.1
0.5
1
2
ISW = 0.5 A
0.36
0.72
RDSON LS Low-side RDSON
ISW = 0.5 A
0.15
0.30
fSW
Selected switching frequency
FSW pinstrapping before SS
IFSW
FSW biasing current
SS ended
IMLF
D
TON MIN
MLF biasing current
V
A
RDSON HS High-side RDSON
Low noise mode /
LCM/LNM Low consumption mode
selection
Unit
See Table 6: fSW selection
0
500
nA
See Table 7 on
page 11,Table 8 on page 12,
Table 9 on page 12
MLF pinstrapping before SS
SS ended
0
(2)
Duty cycle
0
Minimum On time
500
nA
100
%
80
ns
VCC regulator
VCC
LDO output voltage
SWO
VBIAS threshold
(3 V< VBIAS < 5.5 V)
8/77
VBIAS = GND (no switchover)
2.9
3.3
3.6
VBIAS = 5 V (switchover)
2.9
3.3
3.6
Switch internal supply from VIN to
VBIAS
2.85
3.2
Switch internal supply from VBIAS
to VIN
2.78
3.15
DocID027738 Rev 2
V
A6985F
Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Note Min.
Typ.
Max.
Unit
4
8
15
A
4
10
15
Power consumption
ISHTDWN
Shutdown current from VIN
VSS/INH = GND
LCM - SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = 3.3 V
IQ OPVIN
Quiescent current from VIN
IQ OPVBIAS Quiescent current from VBIAS
LCM - NO SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = GND
(3)
A
(3)
35
70
120
LNM - SWO
VFB = GND (NO SLEEP)
VBIAS = 3.3 V
0.5
1.5
5
LNM - NO SWO
VFB = GND (NO SLEEP)
VBIAS = GND
2
2.8
6
25
50
115
A
LNM - SWO
VFB = GND (NO SLEEP)
VBIAS = 3.3 V
0.5
1.2
5
mA
SS rising
200
460
700
100
140
LCM - SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = 3.3 V
mA
(3)
Soft-start
VINH
VSS threshold
VINH HYST VSS hysteresis
ISS CH
CSS charging current
VSS < VINH OR
t < TSS SETUP OR
VEA+ > VFB
t > TSS SETUP AND
VEA+ < VFB
VSS START
SSGAIN
Start of internal error amplifier
ramp
(2)
mV
1
A
(2)
4
0.995
SS/INH to internal error
amplifier gain
1.1
1.150
V
3
Error amplifier
VOUT
Voltage feedback
3.3 V (A6985F3V3)
3.25
3.3
3.35
5 V (A6985F5V)
4.925
5.0
5.075
A6985F
0.841 0.85
0.859
3.3 V (A6985F3V3)
IVOUT
VOUT biasing current
5 V (A6985F5V)
A6985F
DocID027738 Rev 2
4
6
8.5
7.5
10
13.5
50
500
V
A
nA
9/77
77
Electrical characteristics
A6985F
Table 5. Electrical characteristics (continued)
Symbol
AV
ICOMP
Parameter
Test condition
Note Min.
(2)
Error amplifier gain
(4)
Max.
100
±6
EA output current capability
Typ.
±12
Unit
dB
±25
±4
A
Inner current loop
gCS
V PP g CS
Current sense
transconductance (VCOMP to
inductor current gain)
IPK = 0.5 A
(2)
(5)
Slope compensation
1.67
A/V
0.2
0.3
0.4
A
Overvoltage protection
VOVP
Overvoltage trip (VOVP/VREF)
1.15
1.2
1.25
VOVP
Overvoltage hysteresis
0.5
2
5
HYST
%
Synchronization (fan out: 6 slave devices typ.)
fSYN MIN
VSYN TH
ISYN
VSYN OUT
Synchronization frequency
LNM; fSW = VCC
266.5
SYNCH input threshold
LNM, SYNCH rising
0.70
SYNCH pulldown current
LNM, VSYN = 1.2 V
High level output
LNM, 5 mA sinking load
Low level output
LNM, 0.7 mA sourcing load
Selected RST threshold
MLF pinstrapping before SS
kHz
1.2
0.7
V
mA
1.40
0.6
V
Reset
VTHR
VTHR HYST RST hysteresis
VRST
RST open collector output
See Table 7,Table 8, Table 9
(2)
2
%
VIN > VINH AND VFB < VTH
4 mA sinking load
0.4
2 < VIN < VINH
4 mA sinking load
0.8
V
Delay
VTHD
RST open collector released
as soon as VDELAY > VTHD
VFB > VTHR
1.19
ID CH
CDELAY charging current
VFB > VTHR
1
1.234 1.258
2
3
V
A
Thermal shutdown
TSHDWN
THYS
Thermal shutdown
temperature
(2)
Thermal shutdown hysteresis
(2)
165
°C
30
1. Parameter tested in static condition during testing phase. Parameter value may change over dynamic application condition.
2. Not tested in production.
3. LCM enables SLEEP mode at light-load.
4. TJ = -40°C.
5. Measured at fsw = 250 kHz.
10/77
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A6985F
Electrical characteristics
TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.
Table 6. fSW selection
Symbol
fSW
RVCC (E24 series)
RGND (E24 series)
Tj
fSW min.
fSW typ.
fSW max.
0
NC
225
250
275
1.8 k
NC
3.3 k
NC
5.6 k
NC
380
10 k
NC
435
NC
0
18 k
NC
33 k
NC
56 k
NC
755
NC
1.8 k
870
NC
3.3 k
NC
5.6 k
NC
10 k
NC
18 k
NC
33 k
1575
1750
1925
NC
56 k
1800
2000
2200
Unit
285
330
(1)
450
500
550
575
660
(1)
900
kHz
1000
1100
1150
(1)
1310
1500
1. Not tested in production.
TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.
Table 7. LNM / LCM selection (A6985F3V3)
Symbol
VRST
RVCC
RGND
(E24 1%)
(E24 1%)
0
NC
8.2 k
NC
18 k
NC
39 k
Operating VRST/VOUT
mode
(tgt. value)
VRST
VRST
VRST
min.
typ.
max.
93%
3.008
3.069
3.130
80%
2.587
2.640
2.693
87%
2.814
2.871
2.928
NC
96%
3.105
3.168
3.231
NC
0
93%
3.008
3.069
3.130
NC
8.2 k
80%
2.587
2.640
2.693
NC
18 k
87%
2.814
2.871
2.928
NC
39 k
96%
3.105
3.168
3.231
LCM
LNM
DocID027738 Rev 2
Unit
V
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Electrical characteristics
A6985F
TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.
Table 8. LNM / LCM selection (A6985F5V)
Symbol
VRST
RVCC
RGND
(E24 1%)
(E24 1%)
0
NC
8.2 k
NC
18 k
NC
39 k
Operating VRST/VOUT
mode
(tgt. value)
VRST
VRST
VRST
min.
typ.
max.
93%
4.557
4.650
4.743
80%
3.920
4.000
4.080
87%
4.263
4.350
4.437
NC
96%
4.704
4.800
4.896
NC
0
93%
4.557
4.650
4.743
NC
8.2 k
80%
3.920
4.000
4.080
NC
18 k
87%
4.263
4.350
4.437
NC
39 k
96%
4.704
4.800
4.896
LCM
LNM
Unit
V
TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.
Table 9. LNM / LCM selection table (A6985F)
Symbol
VRST
12/77
RVCC
RGND
(E24 1%)
(E24 1%)
0
NC
8.2 k
NC
18 k
NC
39 k
Operating VRST/VOUT
mode
(tgt. value)
VRST
VRST
VRST
min.
typ.
max.
93%
0.779
0.791
0.802
80%
0.670
0.680
0.690
87%
0.728
0.740
0.751
NC
96%
0.804
0.816
0.828
NC
0
93%
0.779
0.791
0.802
NC
8.2 k
80%
0.670
0.680
0.690
NC
18 k
87%
0.728
0.740
0.751
NC
39 k
96%
0.804
0.816
0.828
LCM
LNM
DocID027738 Rev 2
Unit
V
A6985F
4
Datasheet parameters over the temperature range
Datasheet parameters over the temperature range
The 100% of the population in the production flow is tested at three different ambient
temperatures (-40 °C, +25 °C, +135 °C) to guarantee the datasheet parameters inside the
junction temperature range (-40 °C, +135 °C).
The device operation is guaranteed when the junction temperature is inside the (-40 °C,
+150 °C) temperature range. The designer can estimate the silicon temperature increase
respect to the ambient temperature evaluating the internal power losses generated during
the device operation.
However the embedded thermal protection disables the switching activity to protect the
device in case the junction temperature reaches the TSHTDWN (+165 °C typ.) temperature.
All the datasheet parameters can be guaranteed to a maximum junction temperature of
+135 °C to avoid triggering the thermal shutdown protection during the testing phase
because of self-heating.
DocID027738 Rev 2
13/77
77
Functional description
5
A6985F
Functional description
The A6985F device is based on a “peak current mode”, constant frequency control. As
a consequence, the intersection between the error amplifier output and the sensed inductor
current generates the PWM control signal to drive the power switch.
The device features LNM (low noise mode) that is forced PWM control, or LCM (low
consumption mode) to increase the efficiency at light-load.
The main internal blocks shown in the block diagram in Figure 3 are:
14/77
Embedded power elements. Thanks to the P-channel MOSFET as high-side switch the
device features low dropout operation
A fully integrated sawtooth oscillator with adjustable frequency
A transconductance error amplifier
An internal feedback divider GDIV INT
The high-side current sense amplifier to sense the inductor current
A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the
embedded power elements
The soft-start blocks to ramp the error amplifier reference voltage and so decreases the
inrush current at power-up. The SS/INH pin inhibits the device when driven low.
The switchover capability of the internal regulator to supply a portion of the quiescent
current when the VBIAS pin is connected to an external output voltage
The synchronization circuitry to manage master / slave operation and the
synchronization to an external clock
The current limitation circuit to implement the constant current protection, sensing
pulse by pulse high-side / low-side switch current. In case of heavy short-circuit the
current protection is fold back to decrease the stress of the external components
A circuit to implement the thermal protection function
The OVP circuitry to discharge the output capacitor in case of overvoltage event
MLF pin strapping sets the LNM/LCM mode and the thresholds of the RST comparator
FSW pinstrapping sets the switching frequency
The RST open collector output
DocID027738 Rev 2
A6985F
Functional description
Figure 3. Internal block diagram
5.1
Power supply and voltage reference
The internal regulator block consists of a start-up circuit, the voltage pre-regulator that
provides current to all the blocks and the bandgap voltage reference. The starter supplies
the startup current when the input voltage goes high and the device is enabled (SS/INH pin
over the inhibits threshold).
The pre-regulator block supplies the bandgap cell and the rest of the circuitry with
a regulated voltage that has a very low supply voltage noise sensitivity.
Switchover feature
The switchover scheme of the pre-regulator block features to derive the main contribution of
the supply current for the internal circuitry from an external voltage (3 V < VBIAS < 5.5 V is
typically connected to the regulated output voltage). This helps to decrease the equivalent
quiescent current seen at VIN. (please refer to Section 5.6: Switchover feature on page 30).
5.2
Voltages monitor
An internal block continuously senses the VCC, VBIAS and VBG. If the monitored voltages are
good, the regulator starts operating. There is also a hysteresis on the VCC (UVLO).
DocID027738 Rev 2
15/77
77
Functional description
A6985F
Figure 4. Internal circuit
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5.3
Soft-start and inhibit
The soft-start and inhibit features are multiplexed on the same pin. An internal current
source charges the external soft-start capacitor to implement a voltage ramp on the SS/INH
pin. The device is inhibited as long as the SS/INH pin voltage is lower than the VINH
threshold and the soft-start takes place when SS/INH pin crosses VSS START. (See Figure 5).
The internal current generator sources 1 A typ. current when the voltage of the VCC pin
crosses the UVLO threshold. The current increases to 4 A typ. as soon as the SS/INH
voltage is higher than the VINH threshold. This feature helps to decrease the current
consumption in inhibit mode. An external open collector can be used to set the inhibit
operation clamping the SS/INH voltage below VINH threshold.
The startup feature minimizes the inrush current and decreases the stress of the power
components during the power-up phase. The ramp implemented on the reference of the
error amplifier has a gain three times higher (SSGAIN) than the external ramp present at
SS/INH pin.
16/77
DocID027738 Rev 2
A6985F
Functional description
Figure 5. Soft-start phase
The CSS is dimensioned accordingly with Equation 1:
Equation 1
I SSCH T SS
4A T SS
C SS = SS GAIN -------------------------------- = 3 --------------------------V FB
0.85V
where TSS is the soft-start time, ISS CH the charging current and VFB the reference of the
error amplifier.
The soft-start block supports the precharged output capacitor.
DocID027738 Rev 2
17/77
77
Functional description
A6985F
Figure 6. Soft-start phase with precharged COUT
During normal operation a new soft-start cycle takes place in case of:
Thermal shutdown event
UVLO event
The device is driven in INH mode
The soft-start capacitor is discharged with a 0.6 mA typ. current capability for 1 msec time
max. For complete and proper capacitor discharge in case of fault condition, a maximum
CSS = 67 nF value is suggested.
The application example in Figure 7 shows how to enable the A6985F and perform the softstart phase driven by an external voltage step, for example the signal from the ignition
switch in automotive applications.
Figure 7. Enable the device with external voltage step
18/77
DocID027738 Rev 2
A6985F
Functional description
The maximum capacitor value has to be limited to guarantee the device can discharge it in
case of thermal shutdown and UVLO events (see Section 5.3.1), so restart the switching
activity ramping the error amplifier reference voltage.
Equation 2
– 1 msec
C SS ------------------------------------------------------------------------------------------V SS_FINAL – 0.9 V
R SS_EQ ln 1 – ----------------------------------------------
600 A – R SS_EQ
where:
Equation 3
R UP R DWN
R SS_EQ = --------------------------------R UP + R DWN
R DWN
V SS_FINAL = V STEP – V DIODE ---------------------------------R UP + R DWN
The optional diode prevents to disable the device if the external source drops to ground.
RUP value is selected in order to make the capacitor charge at first approximation
independent from the internal current generator (4 A typ. current capability, see Table 5 on
page 8), so:
Equation 4
V STEP – V DIODE – V SS END
----------------------------------------------------------------------- » I SS CHARGE 4 A
R UP
where:
Equation 5
V FB
V SS END = V SS START + --------------------SS GAIN
represents the SS/INH voltage correspondent to the end of the ramp on the error amplifier
(see Figure 5); refer to Table 5 for VSS START, VFB and SSGAIN parameters.
As a consequence the voltage across the soft-start capacitor can be written as:
Equation 6
1
v SS t = V SS_FINAL ----------------------------------------t
1–e
– --------------------------------C SS R SS_EQ
RSS_DOWN is selected to guarantee the device stays in inhibit mode when the internal
generator sources 1 A typ. out of the SS/INH pin and VSTEP is not present:
Equation 7
R DWN I SS INHIBIT R DWN 1 A « V INH 200 mV
so:
Equation 8
R DWN 100 k
DocID027738 Rev 2
19/77
77
Functional description
A6985F
RUP and RDWN are selected to guarantee:
Equation 9
V SS_FINAL 2 V V SS_END
The time to ramp the internal voltage reference can be calculated from Equation 10:
Equation 10
V SS_FINAL – V SS START
T SS = C SS R SS_EQ ln -----------------------------------------------------------
V SS_FINAL – V SS END
that is the equivalent soft-start time to ramp the output voltage.
Figure 8 shows the soft-start phase with the following component selection: RUP = 180 k,
RDWN = 33 k, CSS = 200 nF, the 1N4148 is a small signal diode and VSTEP = 13 V.
Figure 8. External soft-start network VSTEP driven
The circuit in Figure 7 introduces a time delay between VSTEP and the switching activity that
can be calculated as:
Equation 11
V SS_FINAL
T SS DELAY = C SS R SS_EQ ln -----------------------------------------------------------
V SS_FINAL – V SS START
20/77
DocID027738 Rev 2
A6985F
Functional description
Figure 9 shows how the device discharges the soft-start capacitor after an UVLO or thermal
shutdown event in order to restart the switching activity ramping the error amplifier reference
voltage.
Figure 9. External soft-start after UVLO or thermal shutdown
DocID027738 Rev 2
21/77
77
Functional description
5.3.1
A6985F
Ratiometric startup
The ratiometric startup is implemented sharing the same soft-start capacitor for a set of the
A6985F devices.
Figure 10. Ratiometric startup
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As a consequence all the internal current generators charge in parallel the external
capacitor. The capacitor value is dimensioned accordingly with Equation 12:
Equation 12
I SSCH T SS
4A T SS
C SS = n A6985F SS GAIN -------------------------------- = n A6985F 3 --------------------------0.85V
V FB
where n A6985Frepresents the number of devices connected in parallel.
For better tracking of the different output voltages the synchronization of the set of
regulators is suggested.
22/77
DocID027738 Rev 2
A6985F
Functional description
Figure 11. Ratiometric startup operation
DocID027738 Rev 2
23/77
77
Functional description
5.3.2
A6985F
Output voltage sequencing
The A6985F device implements sequencing connecting the RST pin of the master device to
the SS/INH of the slave. The slave is inhibited as long as the master output voltage is
outside regulation so implementing the sequencing (see Figure 12).
Figure 12. Output voltage sequencing
9
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High flexibility is achieved thanks to the programmable RST thresholds (see Table 7 on
page 11, Table 8 and Table 9 on page 12) and programmable delay time. To minimize the
component count the DELAY pin capacitor can be also omitted so the pin works as a normal
Power Good.
5.4
Error amplifier
The voltage error amplifier is the core of the loop regulation. It is a transconductance
operational amplifier whose non inverting input is connected to the internal voltage
reference (0.85 V), while the inverting input (FB) is connected to the external divider or
directly to the output voltage.
Table 10. Uncompensated error amplifier characteristics
Description
Values
Transconductance
155 µS
Low frequency gain
100 dB
The error amplifier output is compared with the inductor current sense information to
perform PWM control. The error amplifier also determines the burst operation at light-load
when the LCM is active.
24/77
DocID027738 Rev 2
A6985F
5.5
Functional description
Light-load operation
The MLF pinstrapping during the power-up phase determines the light-load operation (refer
to Table 7 on page 11, Table 8 and Table 9 on page 12).
5.5.1
Low noise mode (LNM)
The low noise mode implements a forced PWM operation over the different loading
conditions. The LNM features a constant switching frequency to minimize the noise in the
final application and a constant voltage ripple at fixed VIN. The regulator in steady loading
condition never skip pulses and it operates in continuous conduction mode (CCM) over the
different loading conditions.
Figure 13. Low noise mode operation
Typical applications for the LNM operation are car audio, sensors.
DocID027738 Rev 2
25/77
77
Functional description
5.5.2
A6985F
Low consumption mode (LCM)
The low consumption mode maximizes the efficiency at light-load. The regulator prevents
the switching activity whenever the switch peak current request is lower than the ISKIP
threshold (350 mA typical). As a consequence the A6985F device works in bursts and it
minimizes the quiescent current request in the meantime between the switching operation.
In LCM operation, the pin SYNCH/ISKIP level dynamically defines the ISKIP current
threshold (see Table 11).
Table 11. ISKIP current level
SYNCH / ISKIP (pin 4)
ISKIP current threshold
LOW
ISKIPH = 0.35 A typical
HIGH
ISKIPL = 0.1 A typical
The ISKIP programmability helps to optimize the performance in terms of the output voltage
ripple or efficiency at the light-load, that are parameters which disagree each other by
definition.
A lower skip current level minimizes the voltage ripple but increases the switching activity
(time between bursts gets closer) since less energy per burst is transfered to the output
voltage at the given load. On the other side, a higher skip level reduces the switching activity
and improves the efficiency at the light-load but worsen the voltage ripple.
No difference in terms of the voltage ripple and conversion efficiency for the medium and
high load current level, that is when the device operates in the discontinuous or continuous
mode (DCM vs. CCM).
Figure 14 and Figure 15 report the efficiency measurements to highlight the ISKIPH and
ISKIPL efficiency gap at the light-load also in comparison with the LNM operation. The same
efficiency at the medium / high load is confirmed at different ISKIP levels.
Figure 14. Light-load efficiency comparison at different ISKIP - linear scale
26/77
DocID027738 Rev 2
A6985F
Functional description
Figure 15. Light-load efficiency comparison at different ISKIP - log scale
Figure 16 and Figure 17 show the LCM operation at the different ISKIP level.
Figure 16 shows the ISKIPH = 350 mA typ. and so 34 mV output voltage ripple.
Figure 17 shows the ISKIPL = 100 mA typ. and so 13 mV output voltage ripple.
Figure 16. LCM operation with ISKIPH = 350 mA typ. at zero load
DocID027738 Rev 2
27/77
77
Functional description
A6985F
Figure 17. LCM operation with ISKIPH = 100 mA typ. at zero load
The LCM operation satisfies the requirements of the unswitched car body applications
(KL30). These applications are directly connected to the battery and are operating when the
engine is disabled. The typical load when the car is parked is represented by a CAN transceiver and a microcontroller in sleep mode (total load is around 20 - 30 µA). As soon as the
transceiver recognizes a valid word in the bus, it awakes the µC and the rest of the application.
The typical input current request of the module when the car is parked is 100 µA typ. to prevent the battery discharge over the parking time. In order to minimize the regulator quiescent current request from the input voltage, the VBIAS pin can be connected to an external
voltage source in the range 3 V < VBIAS < 5.5 V (see Section 5.1: Power supply and voltage
reference on page 15).
Given the energy stored in the inductor during a burst, the voltage ripple depends on the
capacitor value:
Equation 13
T
V OUT RIPPLE
28/77
BURST
i L t dt
Q IL
0
= -------------- = -------------------------------------------C OUT
C OUT
DocID027738 Rev 2
A6985F
Functional description
Figure 18. LCM operation over loading condition (part 1)
Figure 19. LCM operation over loading condition (part 2)
DocID027738 Rev 2
29/77
77
Functional description
A6985F
Figure 20. The regulator works in CCM
5.6
Switchover feature
The switchover maximizes the efficiency at light-load that is crucial for LCM applications.
5.6.1
LCM
The LCM operation satisfies the high efficiency requirements of the battery powered
applications. In order to minimize the regulator quiescent current request from the input
voltage, the VBIAS pin can be connected to an external voltage source in the range
3 V < VBIAS < 5.5 V (see Section 5.1: Power supply and voltage reference on page 15).
In case the VBIAS pin is connected to the regulated output voltage (VOUT), the total current
drawn from the input voltage can be calculated as:
Equation 14
V BIAS
1
I QVIN = I QOPVIN + -------------------- --------------- I QOPVBIAS
V IN
A6985F
where IQ OP VIN, IQ OP VBIAS are defined in Table 5: Electrical characteristics on page 8 and
A6985F is the efficiency of the conversion in the working point.
5.6.2
LNM
Equation 14 is also valid when the device works in LNM and it can increase the efficiency at
medium load since the regulator always operates in continuous conduction mode.
30/77
DocID027738 Rev 2
A6985F
5.7
Functional description
Overcurrent protection
The current protection circuitry features a constant current protection, so the device limits
the maximum peak current (see Table 5: Electrical characteristics on page 8) in overcurrent
condition.
The A6985F device implements a pulse by pulse current sensing on both power elements
(high-side and low-side switches) for effective current protection over the duty cycle range.
The high-side current sensing is called “peak” the low-side sensing “valley”.
The internal noise generated during the switching activity makes the current sensing
circuitry ineffective for a minimum conduction time of the power element. This time is called
“masking time” because the information from the analog circuitry is masked by the logic to
prevent an erroneous detection of the overcurrent event. As a consequence, the peak
current protection is disabled for a masking time after the high-side switch is turned on, the
valley for a masking time after the low-side switch is turned on. In other words, the peak
current protection can be ineffective at extremely low duty cycles, the valley current
protection at extremely high duty cycles.
The A6985F device assures an effective overcurrent protection sensing the current flowing
in both power elements. In case one of the two current sensing circuitry is ineffective
because of the masking time, the device is protected sensing the current on the opposite
switch. Thus, the combination of the “peak” and “valley” current limits assure the
effectiveness of the overcurrent protection even in extreme duty cycle conditions.
The valley current threshold is designed higher than the peak to guarantee a proper
operation. In case the current diverges because of the high-side masking time, the low-side
power element is turned on until the switch current level drops below the valley current
sense threshold. The low-side operation is able to prevent the high-side turn on, so the
device can skip pulses decreasing the swathing frequency.
DocID027738 Rev 2
31/77
77
Functional description
A6985F
Figure 21. Valley current sense operation in overcurrent condition
Figure 21 shows the switching frequency reduction during the valley current sense
operation in case of extremely low duty cycle (VIN =38 V, fSW = 2 MHz short-circuit
condition).
In a worst case scenario (like Figure 21) of the overcurrent protection the switch current is
limited to:
Equation 15
V IN – V OUT
I MAX = I VALLEYTH + ------------------------------ T MASKHS
L
where IVALLEY_TH is the current threshold of the valley sensing circuitry (see Table 5:
Electrical characteristics on page 8) and TMASK_HS is the masking time of the high-side
switch 100 nsec. typ.).
In most of the overcurrent conditions the conduction time of the high-side switch is higher
than the masking time and so the peak current protection limits the switch current.
Equation 16
IMAX = IPEAK_TH
32/77
DocID027738 Rev 2
A6985F
Functional description
Figure 22. Peak current sense operation in overcurrent condition
The DC current flowing in the load in overcurrent condition is:
Equation 17
I RIPPLE V OUT
V IN – V OUT
I DCOC V OUT = I MAX – ---------------------------------------- = I MAX – ------------------------------ T ON
2
2L
DocID027738 Rev 2
33/77
77
Functional description
A6985F
OCP and switchover feature
Output capacitor discharging the current flowing to ground during heavy short-circuit events
is only limited by parasitic elements like the output capacitor ESR and short-circuit
impedance.
Due to parasitic inductance of the short-circuit impedance, negative output voltage
oscillations can be generated with huge discharging current levels (see Figure 23).
Figure 23. Output voltage oscillations during heavy short-circuit
inductor current
short-circuit current
switching node
regulated output voltage
34/77
DocID027738 Rev 2
A6985F
Functional description
Figure 24. Zoomed waveform
inductor current
short-circuit current
switching node
regulated output voltage
The VBIAS pin absolute maximum ratings (see Table 2: Absolute maximum ratings on
page 6) must be satisfied over the different dynamic conditions.
If VBIAS is connected to GND there are no issues (see Figure 23 and Figure 24).
A small resistor value (few ) in series with the VBIAS can help to limit the pin negative
voltage (see Figure 25) during heavy short-circuit events if it is connected to the regulated
output voltage.
DocID027738 Rev 2
35/77
77
Functional description
A6985F
Figure 25. VBIAS in heavy short-circuit event
inductor current
switching node
VBIAS pin voltage
(cyan)
regulated output voltage
(purple)
5.8
Overvoltage protection
The overvoltage protection monitors the FB pin and enables the low-side MOSFET to
discharge the output capacitor if the output voltage is 20% over the nominal value.
This is a second level protection and should never be triggered in normal operating
conditions if the system is properly dimensioned. In other words, the selection of the
external power components and the dynamic performance determined by the compensation
network should guarantee an output voltage regulation within the overvoltage threshold
even during the worst case scenario in term of load transitions.
The protection is reliable and also able to operate even during normal load transitions for
a system whose dynamic performance is not in line with the load dynamic request. As
a consequence the output voltage regulation would be affected.
Figure 26 shows the overvoltage operation during a negative steep load transient for
a system designed with huge inductor value and small output capacitor. The inductor value
limits the switch current slew rate and the extra charge flowing into the small capacitor value
generates an overvoltage event. This can be considered as an example for a system with
dynamic performance not in line with the load request.
The A6985F device implements a 1 A typ. negative current limitation to limit the maximum
reversed switch current during the overvoltage operation.
36/77
DocID027738 Rev 2
A6985F
Functional description
Figure 26. Overvoltage operation
inductor current
switching node
VBIAS pin voltage
(cyan)
regulated output voltage
(purple)
5.9
Thermal shutdown
The shutdown block disables the switching activity if the junction temperature is higher than
a fixed internal threshold (165 °C typical). The thermal sensing element is close to the
power elements, ensuring fast and accurate temperature detection. A hysteresis of
approximately 30 °C prevents the device from turning ON and OFF continuously. When the
thermal protection runs away a new soft-start cycle will take place.
DocID027738 Rev 2
37/77
77
Closing the loop
6
A6985F
Closing the loop
Figure 27. Block diagram of the loop
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6.1
GCO(s) control to output transfer function
The accurate control to output transfer function for a buck peak current mode converter can
be written as:
Equation 18
G CO s
s
1 + ----
z
1
= R LOAD g cs -------------------------------------------------------------------------------------------------------- ---------------------- F H s
R LOAD T SW
s
------
1 + ----------------------------------- m C 1 – D – 0.5 1 +
L
p
where RLOAD represents the load resistance, Ri the equivalent sensing resistor of the
current sense circuitry, p the single pole introduced by the power stage and z the zero
given by the ESR of the output capacitor.
FH(s) accounts the sampling effect performed by the PWM comparator on the output of the
error amplifier that introduces a double pole at one half of the switching frequency.
38/77
DocID027738 Rev 2
A6985F
Closing the loop
Equation 19
1
z = --------------------------------ESR C OUT
Equation 20
m c 1 – D – 0.5
1
p = --------------------------------------- + ---------------------------------------------L C OUT f SW
R LOAD C OUT
where:
Equation 21
Se
m C = 1 + -----Sn
S = V g f
PP
CS SW
e
V
–
V
IN
OUT
S = --------------------------- n
L
Sn represents the on time slope of the sensed inductor current, Se the on time slope of the
external ramp (VPP peak-to-peak amplitude) that implements the slope compensation to
avoid sub-harmonic oscillations at duty cycle over 50%.
Se can be calculated from the parameter VPP × gCS given in Table 5 on page 8.
The sampling effect contribution FH(s) is:
Equation 22
1
F H s = --------------------------------------------2
s
s
1 + -------------------- + --------2n Qp
n
where:
Equation 23
1
Q p = ----------------------------------------------------------- m c 1 – D – 0.5
DocID027738 Rev 2
39/77
77
Closing the loop
6.2
A6985F
Error amplifier compensation network
The typical compensation network required to stabilize the system is shown in Figure 28.
Figure 28. Transconductance embedded error amplifier
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RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect
system stability but it is useful to reduce the noise at the output of the error amplifier.
The transfer function of the error amplifier and its compensation network is:
Equation 24
A V0 1 + s R c C c
A 0 s = --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2
s R0 C0 + Cp Rc Cc + s R0 Cc + R0 C0 + Cp + Rc Cc + 1
Where Avo = Gm · Ro
The poles of this transfer function are (if Cc >> C0 + CP):
Equation 25
1
f PLF = ------------------------------------2 R0 Cc
40/77
DocID027738 Rev 2
A6985F
Closing the loop
Equation 26
whereas the zero is defined as:
1
f PHF = -------------------------------------------------------2 R0 C0 + Cp
Equation 27
1
f Z = ------------------------------------2 Rc Cc
6.3
Voltage divider
6.3.1
Internal voltage divider
In the A6985F3V3 and A6985F5V, the voltage divider contribution is equal to:
Equation 28
0.85
------------ = 0.2576
3.3
V REF
G DIV s = G DIV INT s = -------------- =
V OUT
0.85
------------ = 0.17
5
6.3.2
A6985F3V3
A6985F5V
External voltage divider
In the A6985F the simple voltage divider contribution is:
Equation 29
R2
R2
G DIV s = -------------------- G DIV INT s = -------------------R1 + R2
R1 + R2
A6985F
A small signal capacitor in parallel to the upper resistor (see Figure 29) of the voltage divider
implements a leading network (fzero < fpole), sometimes necessary to improve the system
phase margin.
Figure 29. Leading network example
DocID027738 Rev 2
41/77
77
Closing the loop
A6985F
Laplace transformer of the leading network:
Equation 30
1 + s R 1 C R1
R2
G DIV s = -------------------- ------------------------------------------------------------R1 + R2
R1 R2
1 + s -------------------- C R1
R1 + R2
where:
Equation 31
1
f Z = ----------------------------------------2 R 1 C R1
1
f p = ------------------------------------------------------R1 R2
2 -------------------- C R1
R1 + R2
fZ fp
6.4
Total loop gain
In summary, the open loop gain can be expressed as:
Equation 32
G s = G DIV s G CO s A 0 s
Example 1
A6985F3V3 with VIN = 12 V and ROUT = 6.6
Selecting L = 4.7µH, COUT = 10 µF and ESR = 1 m, RC= 110 k, CC= 68 pF,
CP = 1.2 pF (please refer to Example 2), the gain and phase bode diagrams are plotted
respectively in Figure 30 and Figure 31.
Equation 33
BW = 112kHz
phase margin = 67
42/77
DocID027738 Rev 2
0
A6985F
Closing the loop
Figure 30. Module plot
Figure 31. Phase plot
The solid trace represents the transfer function including the sampling effect term (see
Equation 22 on page 39), the dotted trace neglects the contribution.
DocID027738 Rev 2
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77
Closing the loop
6.5
A6985F
Compensation network design
The maximum bandwidth of the system can be designed up to fSW/6 or up to 150 kHz to
guarantee a valid small signal model.
Equation 34
f SW
BW = min --------- 150kHz
6
Equation 35
2 BW C OUT V OUT
R C = ---------------------------------------------------------------0.85V g CS g m TYP
where gCS represents the current sense transconductance (see Table 5: Electrical
characteristics on page 8) and gm TYP the error amplifier transconductance.
Equation 36
5
C C = -------------------------------------2 R C BW
Example 2
Considering A6985F3V3, VIN = 12 V, L = 4.7 H, COUT = 10 F, fSW = 2 MHz.
Assuming to design the compensation network to achieve a system bandwidth of 110 kHz:
Equation 37
··
f POLE = 2. 4kHz
Equation 38
V OUT
R LOAD = -------------- = 6.6
I OUT
so accordingly with Equation 35 and Equation 36:
Equation 39
R C = 107k 110k
Equation 40
C C = 66pF 68pF
44/77
DocID027738 Rev 2
A6985F
Application notes
7
Application notes
7.1
Output voltage adjustment
In A6985F3V3 and A6985F5V the output voltage is fixed by an internal divider GDIV INT (see
Table 5 on page 8).
In A6985F the internal reference is equal to 0.85 V typical, and the output voltage is
adjusted accordingly to Equation 41 (see Figure 32):
Equation 41
R1
R1
V OUT = V REF 1 + ------- = 0.85 1 + -------
R2
R2
where Cr1 capacitor is sometimes useful to increase the small signal phase margin (please
refer to Section 6.5: Compensation network design).
Figure 32. A6985F application circuit
7.2
Switching frequency
A resistor connected to the FSW pin features the selection of the switching frequency. The
pinstrapping is performed at power-up, before the soft-start takes place. The FSW pin is
pinstrapped and then driven floating in order to minimize the quiescent current from VIN.
Please refer toTable 6: fSW selection on page 11 to identify the pull-up / pull-down resistor
value. fSW = 250 kHz / fSW = 500 kHz preferred codifications don't require any external
resistor.
DocID027738 Rev 2
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77
Application notes
7.3
A6985F
MLF pin
A resistor connected to the MLF pin features the selection of the between low noise mode /
low consumption mode and the different RST thresholds. The pinstrapping is performed at
power-up, before the soft-start takes place. The FSW pin is pinstrapped and then driven
floating in order to minimize the quiescent current from VIN.
Please refer to Table 7 on page 11, Table 8, and Table 9 on page 12 to identify the pull-up /
pull-down resistor value. (LNM, RST threshold 93%) / (LCM, RST threshold 93%) preferred
codifications don't require any external resistor.
7.4
Voltage supervisor
The embedded voltage supervisor (composed of the RST and the DELAY pins) monitors the
regulated output voltage and keeps the RST open collector output in low impedance as long
as the VOUT is out of regulation. In order to ensure a proper reset of digital devices with
a valid power supply, the device can delay the RST assertion with a programmable time.
Figure 33. Voltage supervisor operation
The comparator monitoring the FB voltage has four different programmable thresholds
(80%, 87%, 93%, 96% nominal output voltage) for high flexibility (see Section 7.3: MLF pin,
Table 7 on page 11, Table 8, and Table 9 on page 12).
When the RST comparator detects the output voltage is in regulation, a 2 A internal current
source starts to charge an external capacitor to implement a voltage ramp on the DELAY
pin. The RST open collector is then released as soon as VDELAY = 1.234 V (see Figure 33).
46/77
DocID027738 Rev 2
A6985F
Application notes
The CDELAY is dimensioned accordingly with Equation 42:
Equation 42
I SSCH T DELAY
2A T DELAY
C DELAY = ------------------------------------------ = ------------------------------------V DELAY
1.234V
The maximum suggested capacitor value is 270 nF.
7.5
Synchronization (LNM)
Beating frequency noise is an issue when multiple switching regulators populate the same
application board. The A6985F synchronization circuitry features the same switching
frequency for a set of regulators simply connecting their SYNCH pin together, so preventing
beating noise. The master device provides the synchronization signal to the others since the
SYNCH pin is I/O able to deliver or recognize a frequency signal.
For proper synchronization of multiple regulators, all of them have to be configured with the
same switching frequency (see Table 6 on page 11), so the same resistor connected at the
FSW pin.
In order to minimize the RMS current flowing through the input filter, the A6985F device
provides a phase shift of 180° between the master and the SLAVES. If more than two
devices are synchronized, all slaves will have a common 180° phase shift with respect to
the master.
Considering two synchronized A6985F which regulates the same output voltage (i.e.:
operating with the same duty cycle), the input filter RMS current is optimized and is
calculated as:
Equation 43
I RMS
I
OUT
----------- 2D 1 – 2D
2
=
I OUT
- 2D – 1 2 – 2D
---------- 2
if D < 0.5
if D > 0.5
The graphical representation of the input RMS current of the input filter in the case of two
devices with 0° phase shift (synchronized to an external signal) or 180° phase shift
(synchronized connecting their SYNCH pins) regulating the same output voltage is provided
in Figure 34. To dimension the proper input capacitor please refer to Section 7.6.1: Input
capacitor selection on page 52.
DocID027738 Rev 2
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77
Application notes
A6985F
Figure 34. Input RMS current
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Figure 35 shows two regulators not synchronized.
Figure 35. Two regulators not synchronized
48/77
DocID027738 Rev 2
A6985F
Application notes
Figure 36 shows the same regulators working synchronized. The MASTER regulator
(LX_5V trace) delivers the synchronization signal (SYNCH_3V3, SYNCH_5V pins are
connected together) to the SLAVE device (LX_3V3). The SLAVE regulator works in phase
with the synchronization signal which is out of phase with the MASTER switching operation.
Figure 36. Two regulators synchronized
Multiple A6985F devices can be synchronized to an external frequency signal fed to the
SYNCH pin. In this case the regulator set is phased to the reference and all the devices will
work with 0° phase shift.
The frequency range of the synchronization signal is 275 kHz - 2 MHz and the minimum
pulse width is 100 nsec (see Figure 37).
Figure 37. Synchronization pulse definition
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Since the slope compensation contribution that is required to prevent subharmonic
oscillations in peak current mode architecture depends on the switching frequency, it is
important to select the same oscillator frequency for all regulators (all of them operate as
SLAVE) as close as possible to the frequency of the reference signal (please refer to
Table 6: fSW selection on page 11). As a consequence all the regulators have the same
resistor value connected to the FSW pin, so the slope compensation is optimized
DocID027738 Rev 2
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77
Application notes
A6985F
accordingly with the frequency of the synchronization signal. The slope compensation
contribution is latched at power-up and so fixed during the device operation.
The A6985F normally operates in MASTER mode, driving the SYNCH line at the selected
oscillator frequency as shown in Figure 35 and Figure 36.
In SLAVE mode the A6985F sets the internal oscillator at 250 kHz typ. (see Table 6 on
page 11 - first row) and drives the line accordingly.
Figure 38. A6985F synchronization driving capability
In order to safely guarantee that each regulator recognizes itself in SLAVE mode during the
normal operation, the external master must drive the SYNCH pin with a clock signal
frequency higher than the maximum oscillator spread (refer to Table 6) for at least 10
internal clock cycles.
For example: selecting RFSW = 0 W to GND
Table 12. Example of oscillator frequency selection from Table 6
Symbol
RVCC (E24 series)
RGND (E24 series)
fSW min.
fSW typ.
fSW max.
fSW
NC
0
450
500
550
the device enters in slave mode after 10 pulses at frequency higher than 550 kHz and so it
is able to synchronize to a clock signal in the range 275 kHz - 2 MHz (see Figure 37).
Anyway it is suggested to limit the frequency range within ± 20% fSW resistor nominal
frequency (see details in text below). If not spread spectrum is required, all the regulators
synchronize to a frequency higher to the maximum oscillator spread (550 kHz in the
example).
The device keeps operating in slave mode as far as the master is able to drive the SYNCH
pin faster than 275 kHz (maximum oscillator spread for 250 kHz oscillator), otherwise it goes
back into MASTER mode at the nominal oscillator frequency after successfully driving one
pulse at 250 kHz (see Figure 39) in the SYNCH line.
50/77
DocID027738 Rev 2
A6985F
Application notes
Figure 39. Slave to master mode transition
switching node
SLAVE mode
250kHz typ. stand alone operation at nominal fsw
SYNCH signal
The external master can force a latched SLAVE mode driving the SYNCH pin low at powerup, before the soft-start starts the switching activity. So the oscillator frequency is 250 kHz
typ. fixed until a new UVLO event is triggered regardless FSW resistor value, that otherwise
counts to design the slope compensation. The same considerations above are also valid.
The master driving capability must be able to provide the proper signal levels at the SYNCH
pin (see Table 5 on page 8 - Synchronization section):
Low level < VSYN THL= 0.7 V sinking 5 mA
High level > VSYN THH = 1.2 V sourcing 0.7 mA
Figure 40. Master driving capability to synchronize the A6985F
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DocID027738 Rev 2
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77
Application notes
A6985F
As anticipated above, in SLAVE mode the internal oscillator operates at 250 kHz typ. but the
slope compensation is dimensioned accordingly with FSW resistors so, even if the A6985F
supports synchronization over the 275 kHz - 2 MHz frequency range, it is important to limit
the switching operation around a working point close to the selected frequency (FSW
resistor).
As a consequence, to guarantee the full output current capability and to prevent the
subharmonic oscillations the master must limit the driving frequency range within ± 20% of
the selected frequency.
A wider frequency range may generate subharmonic oscillation for duty > 50% or limit the
peak current capability (see IPK parameter in Table 5 on page 8) since the internal slope
compensation signal may be saturated.
7.6
Design of the power components
7.6.1
Input capacitor selection
The input capacitor voltage rating must be higher than the maximum input operating voltage
of the application. During the switching activity a pulsed current flows into the input capacitor
and so its RMS current capability must be selected accordingly with the application
conditions. Internal losses of the input filter depends on the ESR value so usually low ESR
capacitors (like multilayer ceramic capacitors) have higher RMS current capability. On the
other hand, given the RMS current value, lower ESR input filter has lower losses and so
contributes to higher conversion efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 44
D D
I RMS = I OUT 1 – ---- ---
Where IOUT is the maximum DC output current, D is the duty cycles, is the efficiency. This
function has a maximum at D = 0.5 and, considering = 1, it is equal to IOUT/2.
In a specific application the range of possible duty cycles has to be considered in order to
find out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 45
V OUT + V LOWSIDE
D MAX = -----------------------------------------------------------------------------------------------V INMIN + V LOWSIDE – V HIGHSIDE
Equation 46
V OUT + V LOWSIDE
D MIN = -------------------------------------------------------------------------------------------------V INMAX + V LOWSIDE – V HIGHSIDE
Where VHIGH_SIDE and VLOW_SIDE are the voltage drops across the embedded switches.
52/77
DocID027738 Rev 2
A6985F
Application notes
The peak-to-peak voltage across the input filter can be calculated as:
Equation 47
I OUT
D D
V PP = ------------------------- 1 – ---- ---- + ESR I OUT + I L
C IN f SW
In case of negligible ESR (MLCC capacitor) the equation of CIN as a function of the target
VPP can be written as follows:
Equation 48
I OUT
D D
C IN = -------------------------- 1 – ---- ---V PP f SW
Considering = 1 this function has its maximum in D = 0.5:
Equation 49
I OUT
C INMIN = ---------------------------------------------4 V PPMAX f SW
Typically CIN is dimensioned to keep the maximum peak-peak voltage across the input filter
in the order of 5% VIN_MAX.
Table 13. Input capacitors
Manufacturer
TDK
Taiyo Yuden
7.6.2
Series
Size
Cap value (F)
Rated voltage (V)
C3225X7S1H106M
1210
10
50
C3216X5R1H106M
1206
UMK325BJ106MM-T
1210
Inductor selection
The inductor current ripple flowing into the output capacitor determines the output voltage
ripple (please refer to Section 7.6.3). Usually the inductor value is selected in order to keep
the current ripple lower than 20% - 40% of the output current over the input voltage range.
The inductance value can be calculated by Equation 50:
Equation 50
V OUT
V IN – V OUT
I L = ------------------------------ T ON = -------------- T OFF
L
L
Where TON and TOFF are the on and off time of the internal power switch. The maximum
current ripple, at fixed VOUT, is obtained at maximum TOFF that is at minimum duty cycle
(see Section 7.6.1: Input capacitor selection to calculate minimum duty).
DocID027738 Rev 2
53/77
77
Application notes
A6985F
So fixing IL = 20% to 40% of the maximum output current, the minimum inductance value
can be calculated:
Equation 51
V OUT 1 – D MIN
L MIN = ------------------- ----------------------F SW
I LMAX
where fSW is the switching frequency 1/(TON + TOFF).
For example for VOUT = 3.3 V, VIN = 12 V, IOUT = 0.5 A and FSW = 2 MHz the minimum
inductance value to have IL = 30% of IOUT is about 8.2 µH.
The peak current through the inductor is given by:
Equation 52
I L
I L PK = I OUT + -------2
So if the inductor value decreases, the peak current (that has to be lower than the current
limit of the device) increases. The higher is the inductor value, the higher is the average
output current that can be delivered, without reaching the current limit.
In Table 14 some inductor part numbers are listed.
Table 14. Inductors
7.6.3
Manufacturer
Series
Inductor value (H)
Saturation current (A)
Coilcraft
XAL40xx
2.2 to 15
5.6 to 2.8
XAL50xx
2.2 to 22
9.2 to 3.6
XFL40xx
2.2 to 4.7
3.7 to 2.7
Output capacitor selection
The triangular shape current ripple (with zero average value) flowing into the output
capacitor gives the output voltage ripple, that depends on the capacitor value and the
equivalent resistive component (ESR). As a consequence the output capacitor has to be
selected in order to have a voltage ripple compliant with the application requirements.
The voltage ripple equation can be calculated as:
Equation 53
I LMAX
V OUT = ESR I LMAX + --------------------------------------8 C OUT f SW
Usually the resistive component of the ripple can be neglected if the selected output
capacitor is a multi layer ceramic capacitor (MLCC).
The output capacitor is important also for loop stability: it determines the main pole and the
zero due to its ESR. (see Section 6: Closing the loop on page 38 to consider its effect in the
system stability).
54/77
DocID027738 Rev 2
A6985F
Application notes
For example with VOUT = 3.3 V, VIN = 12 V, IL = 0.25 A, fSW = 2 MHz (resulting by the
inductor value) and COUT = 10 F MLCC:
Equation 54
0 · 25
V OUT
I LMAX
1
1 · 6mV
1
------------------ -------------- ------------------------------ = -------- ---------------------------------------------- = ------------------- = 0.05%
V OUT V OUT C OUT f SW
8
10F
2MHz
3.3
3.3
The output capacitor value has a key role to sustain the output voltage during a steep load
transient. When the load transient slew rate exceeds the system bandwidth, the output
capacitor provides the current to the load. In case the final application specifies high slew
rate load transient, the system bandwidth must be maximized and the output capacitor has
to sustain the output voltage for time response shorter than the loop response time.
In Table 15 some capacitor series are listed.
Table 15. Output capacitors
Manufacturer
Series
Cap value (F)
Rated voltage (V)
ESR (m)
GRM32
22 to 100
6.3 to 25
<5
GRM31
10 to 47
6.3 to 25
<5
ECJ
10 to 22
6.3
<5
EEFCD
10 to 68
6.3
15 to 55
SANYO
TPA/B/C
100 to 470
4 to 16
40 to 80
TDK
C3225
22 to 100
6.3
<5
MURATA
PANASONIC
DocID027738 Rev 2
55/77
77
Application board
8
A6985F
Application board
The reference evaluation board schematic is shown in Figure 41.
Figure 41. Evaluation board schematic
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The additional input filter (C16, L3, C15, L2, C14) limits the conducted emission on the
power supply (refer to Figure 56 on page 67).
Table 16. Common bill of material
Reference
Part number
C1, C10, C11
C2
Description
Manufacturer
Not mounted
C2012X7S2A105K
1 F - 0805 - 50 V - X7S - 10%
C3
470 nF - 10 V - 0603
C4, C7, C8
See Table 17, Table 18 on page 60,
Table 19 on page 62
C5
100 nF - 10 V - 0603
C6
10 nF - 10 V - 0603
TDK
C9
CGA5L3X5R1H106K
10 F - 1206 - 50 V - X5R - 10%
TDK
C14, C15, C16
CGA5L3X5R1H475k
4.7 F - 1206 - 50 V - X7R - 10%
TDK
C13
UWD1H101MCQ1GS
100 F - 50 V - 20%
Nichicon
R2
0 - 0603
R6
1 M - 1%- 0603
R4
56 k - 1% - 0603
R7, R8, R9
See Table 17, Table 18, Table 19
56/77
DocID027738 Rev 2
A6985F
Application board
Table 16. Common bill of material (continued)
Reference
Part number
Description
R11
10 - 1% - 0603
R1, R3, R5, R10
Not mounted
Manufacturer
L1
XAL4030-472MEC
4.7 H
Coilcraft
L2
XAL4030-472MEC
4.7 H
Coilcraft
L3
MPZ2012S221A
EMC bead
TDK
J1
Open
J2
Open
J3
Closed
J4
Open
To adjust the ISKIP current level in LCM
operation. Leave open in LNM.
J5
U1
Switchover
See Table 17, Table 18,
Table 19 on page 62
STMicroelectronics
DocID027738 Rev 2
57/77
77
Application board
A6985F
The layout of the board is shown in Figure 42 and in Figure 43.
Figure 42. Top layer
Figure 43. Bottom layer
58/77
DocID027738 Rev 2
A6985F
8.1
Application board
A6985F3V3 evaluation board
Table 17. Bill of material of A6985F3V3 demonstration board
Reference
Part number
Description
C4
1.2 pF - 10 V - 0603
C7
Not mounted
C8
68 pF - 10 V - 0603
R7
0 - 0603
R8
110 k - 1% - 0603
R9
Not mounted
U1
A6985F3V3
Manufacturer
STMicroelectronics
Equation 55 and Figure 44 show the magnitude and phase margin Bode’s plots related to
the evaluation board presented in Figure 41 with the BOM of Table 16 and Table 17.
The small signal dynamic performance of the demonstration board is:
Equation 55
BW = 110kHz
phase margin = 67
0
Figure 44. Magnitude Bode’s plot of A6985F3V3 evaluation board
DocID027738 Rev 2
59/77
77
Application board
A6985F
Figure 45. Phase margin Bode’s plot of A6985F3V3 evaluation board
8.2
A6985F5V evaluation board
Table 18. Bill of material of A6985F5V demonstration board
Reference
Part number
Description
C4
1.2 pF - 10 V - 0603
C7
Not mounted
C8
47 pF - 10 V - 0603
R7
0 - 0603
R8
150 k - 1% - 0603
R9
Not mounted
U1
A6985F5V
Manufacturer
STMicroelectronics
Figure 46 and Figure 47 show the magnitude and phase margin Bode’s plots related to the
evaluation board presented in Figure 41 on page 56 with the BOM of Table 16 on page 56
and Table 18.
The small signal dynamic performance of the demonstration board is:
Equation 56
BW = 100kHz
phase margin = 69
60/77
DocID027738 Rev 2
0
A6985F
Application board
Figure 46. Magnitude Bode’s plot of A6985F5V evaluation board
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Figure 47. Phase margin Bode’s plot of A6985F5V evaluation board
&95&3/"--001("*/1)"4&
Y
Y
Y
Y
Y
'SFRVFODZ<)[>
".
DocID027738 Rev 2
61/77
77
Application board
8.3
A6985F
A6985F (VOUT = 6 V) evaluation board
Table 19. Bill of material of A6985F (VOUT = 6 V) demonstration board
Reference
Part number
Description
Manufacturer
C4
1.2 pF - 10 V - 0603
C7
4.7 pF - 10 V - 0603
C8
27 pF - 10 V - 0603
R7
200 k - 1% - 0603
R8
200 k - 1% - 0603
R9
33 k - 1% - 0603
U1
A6985F
STMicroelectronics
Figure 48 and Figure 49 show the magnitude and phase margin Bode’s plots related to the
evaluation board presented in Figure 41 on page 56 with the BOM of Table 16 on page 56
and Table 19.
The small signal dynamic performance of the demonstration board is:
Equation 57
BW = 110kHz
phase margin = 60
0
Figure 48. Magnitude Bode’s plot of A6985F (VOUT = 6 V) evaluation board
&95&3/"--001.0%6-&
Y
Y
Y
Y
Y
'SFRVFODZ<)[>
".
62/77
DocID027738 Rev 2
A6985F
Application board
Figure 49. Phase Margin Bode’s plot of A6985F (VOUT = 6 V) evaluation board
&95&3/"--001("*/1)"4&
Y
'SFRVFODZ<)[>
DocID027738 Rev 2
Y
Y
Y
Y
".
63/77
77
Efficiency curves
9
A6985F
Efficiency curves
Figure 50. A6985F3V3 efficiency curves: VIN = 13.5 V - fsw = 2 MHz
Figure 51. A6985F3V3 efficiency curves: VIN = 13.5 V - fsw = 2 MHz (log scale)
64/77
DocID027738 Rev 2
A6985F
Efficiency curves
Figure 52. A6985F3V3 efficiency curves: VIN = 24V - fsw = 2 MHz
Figure 53. A6985F3V3 efficiency curves: VIN = 24 V - fsw = 2 MHz (log scale)
DocID027738 Rev 2
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77
Efficiency curves
A6985F
Figure 54. A6985F5V efficiency curves: VIN = 13.5 V - fsw = 2 MHz
Figure 55. A6985F5V efficiency curves: VIN = 13.5 V - fsw = 2 MHz (log scale)
66/77
DocID027738 Rev 2
A6985F
Efficiency curves
Figure 56. A6985F5V efficiency curves: VIN = 24 V - fsw = 2 MHz
Figure 57. A6985F5V efficiency curves: VIN = 24 V - fsw = 2 MHz (log scale)
DocID027738 Rev 2
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77
EMC testing results
10
A6985F
EMC testing results
This chapter reports EMC testing results for the A6985F evaluation board (see Section 8 on
page 56) accordingly with the following test methods:
CE 150R for conducted emission
DP for conducted immunity
All the measurement were performed on the A6985F5V at ILOAD = 10% and 75% as defined
in Table 22.
Table 20. CE 150R test method
Conducted emission, CE 150R
Frequency range
150 kHz - 30 MHz
30 MHz - 1 GHz
Bandwidth
9 kHz
120 kHz
Step size
5 kHz
60 kHz
Dwell time
2 complete software cycles minimum
Detectors
Peak + average
Table 21. DPI test method
Conducted Immunity, DPI
Frequency
range
10 kHz 150 kHz
Step size
(linear)
10 kHz
Dwell time
Modulation
150 kHz - 1 MHz 1 MHz
10 MHz
100 kHz
10 MHz 100 MHz
100 MHz 200 MHz
1 MHz
2 MHz
500 kHz
200 MHz - 400 MHz 400 MHz
1 GHz
4 MHz
10 MHz
2 sec. but min. 2 software complete cycles
CW
AM 1 kHz, 80% (same peak value as CW)
DPI: 30 dBm for global pins, 12 dBm for local pins.
All the pins under DPI testing (see Table 22) satisfy class 3 limits.
Table 22. Pin testing
68/77
Pin name
Remarks
classification
CE
DPI
VS1
Filtered VIN pin
Global
X
X
VIN
VIN pin
Global
X
X
VOUT
Regulated output voltage
Local
X
RST
RST pin
Local
X
SS/INH
SS/INH pin
Local
X
DocID027738 Rev 2
(X)
A6985F
EMC testing results
Figure 58 shows the schematic of the EMC board that can be configured for CE and DPI
testing.
Figure 58. CE - 150R / DPI
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EMC testing results
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Figure 59. CE 150R at VS1 test point (see Figure 58) at 75% ILOAD
Figure 60. CE 150R at VS1 test point (see Figure 58) at 10% ILOAD
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EMC testing results
Figure 61. CE 150R at VOUT test point (see Figure 58) at 75% ILOAD
Figure 62. CE 150R at VOUT test point (see Figure 58) at 10% ILOAD
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EMC testing results
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Figure 63. CE 150R at RST test point (see Figure 58) at 75% ILOAD
Figure 64. CE 150R at RST test point (see Figure 58) at 10% ILOAD
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EMC testing results
Figure 65. CE 150R at SS/INH test point (see Figure 58 on page 69) at 75% ILOAD
Figure 66. CE 150R at SS/INH test point (see Figure 58) at 10% ILOAD
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Package information
11
A6985F
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
HTSSOP16 package information
Figure 67. HTSSOP16 package outline
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Package information
.
Table 23. HTSSOP16 package mechanical data
Dimensions (mm)
Symbol
Min.
Typ.
Max.
A
1.20
A1
0.15
A2
0.80
b
0.19
0.30
c
0.09
0.20
D
4.90
5.00
5.10
D1
2.8
3
3.2
E
6.20
6.40
6.60
E1
4.30
4.40
4.50
E2
2.8
3
3.2
e
L
1.05
0.65
0.45
L1
k
1.00
0.60
0.75
1.00
0.00
aaa
8.00
0.10
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Order codes
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Order codes
Table 24. Order codes
Part numbers
Package
A6985F3V3
Tube
A6985F3V3TR
Tape and reel
A6985F5V
Tube
HTSSOP16
A6985F5VTR
13
Packaging
Tape and reel
A6985F
Tube
A6985FTR
Tape and reel
Revision history
Table 25. Document revision history
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Date
Revision
Changes
10-Apr-2015
1
Initial release.
15-Apr-2015
2
Updated Table 2 on page 6 (updated VIN and VOUT).
Updated units below Equation 3 on page 19 and below
Figure 33 on page 46.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
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