Renesas M32C80 16/32-bit single-chip microcomputer m16c family / m32c/80 sery Datasheet

REJ09B0271-0100
M32C/80 Group
16/32
Hardware Manual
RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY / M32C/80 SERIES
Before using this material, please visit our website to verify that this is the most
current document available.
Rev. 1.00
Revision Date: Nov. 01, 2005
www.renesas.com
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Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
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any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
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How to Use This Manual
1. Introduction
This hardware manual provides detailed information on the M32C/80 Group microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.
2. Register Diagram
The symbols, and descriptions, used for bit function in each register are shown below.
XXX Register
b7
b6
b5
b4
b3
b2
*1
b1
b0
0 0
Symbol
XXX
Address
After Reset
XXX
0016
Bit Name
Bit Symbol
Function
RW
*2
b1 b0
XXX0
XXX bit
XXX1
(b2)
0 0: XXX
0 1: XXX
1 0: Do not set a value
1 1: XXX
RW
Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.
Reserved bit
(b4 - b3)
Set to "0"
*3
WO
*4
XXX5
XXX bit
Function varies depending on mode
of operation
RW
RW
XXX6
XXX7
RW
XXX bit
0: XXX
1: XXX
RO
*1
Blank:Set to "0" or "1" according to the application
0:
Set to "0"
1:
Set to "1"
X:
Nothing is assigned
*2
RW:
RO:
WO:
–:
Read and write
Read only
Write only
Nothing is assigned
*3
• Reserved bit
Reserved bit. Set to specified value.
*4
• Nothing is assigned
Nothing is assigned to the bit concerned. As the bit may be use for future functions,
set to "0" when writing to this bit.
• Do not set a value
The operation is not guaranteed when a value is set.
• Function varies depending on mode of operation
Bit function varies depending on peripheral function mode.
Refer to respective register for each mode.
3. M16C Family Documents
The following documents were prepared for the M16C family. (1)
Document
Short Sheet
Data Sheet
Hardware Manual
Contents
Hardware overview
Hardware overview and electrical characteristics
Hardware specifications (pin assignments, memory maps, peripheral
specifications, electrical characteristics, timing charts)
Software Manual
Detailed description of assembly instructions and microcomputer performance of each instruction
Application Note
• Application examples of peripheral functions
• Sample programs
• Introduction to the basic functions in the M16C family
• Programming method with Assembly and C languages
RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc.
NOTES :
1. Before using this material, please visit the our website to verify that this is the most current document
available.
Table of Contents
Quick Reference by Address _____________________ B-1
1. Overview _____________________________________ 1
1.1
1.2
1.3
1.4
1.5
1.6
Applications ................................................................................................................ 1
Performance Overview .............................................................................................. 2
Block Diagram ............................................................................................................ 3
Product Information ................................................................................................... 4
Pin Assignment .......................................................................................................... 5
Pin Description ........................................................................................................... 9
2. Central Processing Unit (CPU) __________________ 12
2.1 General Registers .................................................................................................... 13
2.1.1 Data Registers (R0, R1, R2 and R3) ................................................................. 13
2.1.2 Address Registers (A0 and A1) ....................................................................... 13
2.1.3 Static Base Register (SB) ................................................................................. 13
2.1.4 Frame Base Register (FB) ................................................................................ 13
2.1.5 Program Counter (PC) ...................................................................................... 13
2.1.6 Interrupt Table Register (INTB) ........................................................................ 13
2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP) ............................... 13
2.1.8 Flag Register (FLG) ........................................................................................... 13
2.2 High-Speed Interrupt Registers .............................................................................. 14
2.3 DMAC-Associated Registers ................................................................................... 14
3. Memory _____________________________________ 15
4. Special Function Registers (SFRs)_______________ 16
5. Reset _______________________________________ 30
5.1 Hardware Reset 1 ..................................................................................................... 30
5.1.1 Reset on a Stable Supply Voltage .................................................................... 30
5.1.2 Power-on Reset .................................................................................................. 30
5.2 Software Reset ......................................................................................................... 33
5.3 Watchdog Timer Reset ............................................................................................ 33
5.4 Internal Space ........................................................................................................... 33
6. Processor Mode ______________________________ 34
6.1 Types of Processor Mode ........................................................................................ 34
6.2 Setting of Processor Mode ...................................................................................... 35
A-1
7. Bus_________________________________________ 39
7.1 Bus Settings ............................................................................................................. 39
7.1.1 Selecting External Address Bus ...................................................................... 40
7.1.2 Selecting External Data Bus ............................................................................ 40
7.1.3 Selecting Separate/Multiplexed Bus ............................................................... 40
7.2 Bus Control ............................................................................................................... 42
7.2.1 Address Bus and Data Bus .............................................................................. 42
7.2.2 Chip-Select Signal ............................................................................................ 42
7.2.3 Read and Write Signals .................................................................................... 44
7.2.4 Bus Timing ........................................................................................................ 45
7.2.5 ALE Signal ......................................................................................................... 53
_______
7.2.6 RDY Signal ......................................................................................................... 53
7.2.8 External Bus Status when Accessing Internal Space ................................... 55
_________
7.2.7 HOLD Signal ...................................................................................................... 55
7.2.9 BCLK Output ..................................................................................................... 55
8. Clock Generation Circuit _______________________ 56
8.1 Types of the Clock Generation Circuit ................................................................... 56
8.1.1 Main Clock ......................................................................................................... 65
8.1.2 Sub Clock .......................................................................................................... 66
8.1.3 On-Chip Oscillator Clock ................................................................................. 67
8.1.4 PLL Clock .......................................................................................................... 69
8.2 CPU Clock and BCLK .............................................................................................. 70
8.3 Peripheral Function Clock ....................................................................................... 70
8.3.1 f1, f8, f32 and f2n ......................................................................................................................... 70
8.3.2 fAD .................................................................................................................................................... 70
8.3.3 fC32 ................................................................................................................................................... 71
8.4 Clock Output Function ............................................................................................ 71
8.5 Power Consumption Control .................................................................................. 72
8.5.1 Normal Operating Mode ................................................................................... 72
8.5.2 Wait Mode .......................................................................................................... 73
8.5.3 Stop Mode .......................................................................................................... 75
8.6 System Clock Protect Function .............................................................................. 80
9. Protection ___________________________________ 81
10. Interrupts___________________________________ 82
10.1 Types of Interrupts ................................................................................................. 82
A-2
10.2 Software Interrupts ................................................................................................ 83
10.2.1 Undefined Instruction Interrupt ..................................................................... 83
10.2.2 Overflow Interrupt ........................................................................................... 83
10.2.3 BRK Interrupt .................................................................................................. 83
10.2.4 BRK2 Interrupt ................................................................................................ 83
10.2.5 INT Instruction Interrupt ................................................................................. 83
10.3 Hardware Interrupts ............................................................................................... 84
10.3.1 Special Interrupts ............................................................................................ 84
10.3.2 Peripheral Function Interrupt ........................................................................ 84
10.4 High-Speed Interrupt ............................................................................................. 85
10.5 Interrupts and Interrupt Vectors ........................................................................... 85
10.5.1 Fixed Vector Tables ........................................................................................ 86
10.5.2 Relocatable Vector Tables .............................................................................. 86
10.6 Interrupt Request Acknowledgement ................................................................... 89
10.6.1 I Flag and IPL ................................................................................................... 89
10.6.2 Interrupt Control Register and RLVL Register ............................................. 89
10.6.3 Interrupt Sequence ......................................................................................... 93
10.6.4 Interrupt Response Time ................................................................................ 94
10.6.5 IPL Change when Interrupt Request is Acknowledged ............................... 95
10.6.6 Saving a Register ............................................................................................ 96
10.6.7 Restoration from Interrupt Routine ............................................................... 96
10.6.8 Interrupt Priority .............................................................................................. 97
10.6.9 Interrupt Priority Level Select Circuit ........................................................... 97
______
10.7 INT Interrupt ............................................................................................................ 99
______
10.8 NMI Interrupt ......................................................................................................... 100
10.9 Key Input Interrupt ............................................................................................... 100
10.10 Address Match Interrupt .................................................................................... 101
10.11 Intelligent I/O Interrupt ....................................................................................... 102
11. Watchdog Timer ____________________________ 105
11.1 Count Source Protection Mode ........................................................................... 108
12. DMAC_____________________________________ 109
12.1 Transfer Cycle ...................................................................................................... 116
12.1.1 Effect of Source and Destination Addresses ............................................. 116
12.1.2 Effect of the DS Register .............................................................................. 116
12.1.3 Effect of Software Wait State ....................................................................... 116
________
12.1.4 Effect of RDY Signal ..................................................................................... 116
12.2 DMAC Transfer Cycle ........................................................................................... 118
12.3 Channel Priority and DMA Transfer Timing ....................................................... 118
A-3
13. DMAC II ___________________________________ 120
13.1 DMAC II Settings .................................................................................................. 120
13.1.1 RLVL Register................................................................................................ 120
13.1.2 DMAC II Index ................................................................................................ 122
13.1.3 Interrupt Control Register for the Peripheral Function ............................. 124
13.1.4 Relocatable Vector Table for the Peripheral Function ............................... 124
13.1.5 IRLT Bit in the IIOiIE Register (i=0 to 4) ...................................................... 124
13.2 DMAC II Performance .......................................................................................... 124
13.3 Transfer Data ........................................................................................................ 124
13.3.1 Memory-to-memory Transfer ....................................................................... 124
13.3.2 Immediate Data Transfer .............................................................................. 125
13.3.3 Calculation Transfer ..................................................................................... 125
13.4 Transfer Modes ..................................................................................................... 125
13.4.1 Single Transfer .............................................................................................. 125
13.4.2 Burst Transfer ............................................................................................... 125
13.5 Multiple Transfer .................................................................................................. 125
13.6 Chained Transfer .................................................................................................. 126
13.7 End-of-Transfer Interrupt ..................................................................................... 126
13.8 Execution Time ..................................................................................................... 127
14. Timer _____________________________________ 128
14.1 Timer A .................................................................................................................. 130
14.1.1 Timer Mode .................................................................................................... 136
14.1.2 Event Counter Mode ..................................................................................... 138
14.1.3 One-Shot Timer Mode ................................................................................... 142
14.1.4 Pulse Width Modulation Mode ..................................................................... 144
14.2 Timer B .................................................................................................................. 147
14.2.1 Timer Mode .................................................................................................... 150
14.2.2 Event Counter Mode ..................................................................................... 151
14.2.3 Pulse Period/Pulse Width Measurement Mode .......................................... 153
15. Three-Phase Motor Control Timer Functions ____ 156
16. Serial I/O __________________________________ 167
16.1 Clock Synchronous Serial I/O Mode .................................................................. 177
16.1.1 Selecting CLK Polarity Selecting ................................................................ 181
16.1.2 Selecting LSB First or MSB First ................................................................. 181
16.1.3 Continuous Receive Mode ........................................................................... 182
16.1.4 Serial Data Logic Inverse ............................................................................. 182
A-4
16.2 Clock Asynchronous Serial I/O (UART) Mode ................................................... 183
16.2.1 Bit Rate .......................................................................................................... 187
16.2.2 Selecting LSB First or MSB First ................................................................. 188
16.2.3 Serial Data Logic Inverse ............................................................................. 188
16.2.4 TxD and RxD I/O Polarity Inverse ................................................................ 189
16.3 Special Mode 1 (I2C Mode) .................................................................................. 190
16.3.1 Detecting Start Condition and Stop Condition .......................................... 196
16.3.2 Start Condition or Stop Condition Output .................................................. 196
16.3.3 Arbitration ...................................................................................................... 198
16.3.4 Transfer Clock ............................................................................................... 198
16.3.5 SDA Output .................................................................................................... 198
16.3.6 SDA Input ....................................................................................................... 199
16.3.7 ACK, NACK .................................................................................................... 199
16.3.8 Transmit and Receive Reset ........................................................................ 199
16.4 Special Mode 2 ..................................................................................................... 200
______
16.4.1 SSi Input Pin Function (i=0 to 4) .................................................................. 203
16.4.2 Clock Phase Setting Function ..................................................................... 204
16.5 Special Mode 3 (GCI Mode) ................................................................................. 206
16.6 Special Mode 4 (IE Mode) .................................................................................... 210
16.7 Special Mode 5 (SIM Mode) ................................................................................. 214
16.7.1 Parity Error Signal ........................................................................................ 218
16.7.2 Format ............................................................................................................ 219
17. A/D Converter ______________________________ 220
17.1 Mode Description ................................................................................................. 227
17.1.1 One-shot Mode .............................................................................................. 227
17.1.2 Repeat Mode .................................................................................................. 228
17.1.3 Single Sweep Mode ...................................................................................... 229
17.1.4 Repeat Sweep Mode 0 .................................................................................. 230
17.1.5 Repeat Sweep Mode 1 .................................................................................. 231
17.2 Functions .............................................................................................................. 232
17.2.1 Resolution Select Function .......................................................................... 232
17.2.2 Sample and Hold Function ........................................................................... 232
17.2.3 Trigger Select Function ................................................................................ 232
17.2.4 DMAC Operating Mode ................................................................................. 232
17.2.5 Extended Analog Input Pins ........................................................................ 233
17.2.6 External Operating Amplifier (Op-Amp) Connection Mode....................... 233
17.2.7 Power Consumption Reducing Function ................................................... 234
17.2.8 Output Impedance of Sensor Equivalent Circuit under A/D Conversion ... 234
A-5
18.
19.
20.
21.
D/A Converter ______________________________
CRC Calculation ____________________________
X/Y Conversion _____________________________
Intelligent I/O_______________________________
236
239
241
244
21.1 Communication Unit 0 and 1 Communication Function .................................. 246
21.1.1 Clock Synchronous Serial I/O Mode (Communication Units 0 and 1) ..... 256
21.1.2 HDLC Data Processing Mode (Communication Units 0 and 1) ................ 259
22. Programmable I/O Ports _____________________ 262
22.1
22.2
22.3
22.4
22.5
22.6
22.7
22.8
22.9
Port Pi Direction Register (PDi Register, i=0 to 10)........................................... 262
Port Pi Register (Pi Register, i=0 to 10) .............................................................. 262
Function Select Register Aj (PSj Register) (j=0 to 3) ........................................ 262
Function Select Register B0 to B3 (PSL0 to PSL3 Registers) ......................... 262
Function Select Register C (PSC and PSC3 Registers) ................................... 263
Function Select Register D (PSD1 Register) ..................................................... 263
Pull-up Control Register 0 to 3 (PUR0 to PUR3 Registers) .............................. 263
Port Control Register (PCR Register) ................................................................ 263
Analog Input and Other Peripheral Function Input ........................................... 263
23. Electrical Characteristics ____________________ 281
24. Precautions ________________________________ 307
24.1 Reset ..................................................................................................................... 307
24.2 Bus ........................................................................................................................ 308
__________
24.2.1 HOLD Signal .................................................................................................. 308
24.3 Special Function Registers (SFRs) .................................................................... 309
24.3.1 Register Settings .......................................................................................... 309
24.4 Clock Generation Circuit ..................................................................................... 310
24.4.1 CPU Clock ...................................................................................................... 310
24.4.2 Sub Clock ...................................................................................................... 310
24.4.3 PLL Frequency Synthesizer ......................................................................... 311
24.4.4 External Clock ............................................................................................... 311
24.4.5 Clock Divide Ratio ........................................................................................ 311
24.4.6 Power Consumption Control ....................................................................... 311
24.5 Protection ............................................................................................................. 314
24.6 Interrupts .............................................................................................................. 315
24.6.1 ISP Setting ..................................................................................................... 315
_______
24.6.2 NMI Interrupt .................................................................................................. 315
A-6
______
24.6.3 INT Interrupt .................................................................................................. 315
24.6.4 Watchdog Timer Interrupt ............................................................................ 316
24.6.5 Changing Interrupt Control Register .......................................................... 316
24.6.6 Changing IIOiIR Register (i = 0 to 4) ............................................................ 316
24.6.7 Changing RLVL Register .............................................................................. 316
24.7 DMAC .................................................................................................................... 317
24.8 Timer...................................................................................................................... 318
24.8.1 Timers A and B .............................................................................................. 318
24.8.2 Timer A ........................................................................................................... 318
24.8.3 Timer B ........................................................................................................... 320
24.9 Serial I/O ................................................................................................................ 321
24.9.1 Clock Synchronous Serial I/O Mode ........................................................... 321
24.9.2 UART Mode .................................................................................................... 322
24.9.3 Special Mode 1 (I2C Mode) ........................................................................... 322
24.10 A/D Converter ..................................................................................................... 323
24.11 Intelligent I/O ....................................................................................................... 325
24.11.1 Register Setting ........................................................................................... 325
24.12 Programmable I/O Ports .................................................................................... 326
24.13 Noise ................................................................................................................... 327
Package Dimensions ___________________________ 328
Register Index _________________________________ 329
A-7
Quick Reference by Address
Address
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
Register
Page
Processor Mode Register 0 (PM0)
Processor Mode Register 1 (PM1)
System Clock Control Register 0 (CM0)
System Clock Control Register 1 (CM1)
36
37
58
59
Address Match Interrupt Enable Register (AIER)
Protect Register (PRCR)
External Data Bus Width Control Register (DS)
Main Clock Division Register (MCD)
Oscillation Stop Detection Register (CM2)
Watchdog Timer Start Register (WDTS)
Watchdog Timer Control Register (WDC)
101
81
39
60
61
Address Match Interrupt Register 0 (RMAD0)
101
Processor Mode Register 2 (PM2)
64
Address Match Interrupt Register 1 (RMAD1)
101
Address Match Interrupt Register 2 (RMAD2)
101
Address Match Interrupt Register 3 (RMAD3)
101
PLL Control Register 0 (PLC0)
PLL Control Register 1 (PLC1)
68
Address Match Interrupt Register 4 (RMAD4)
101
Address Match Interrupt Register 5 (RMAD5)
101
106
Address
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
Register
Page
Address Match Interrupt Register 6 (RMAD6)
101
Address Match Interrupt Register 7 (RMAD7)
1201
External Space Wait Control Register 0 (EWCR0)
External Space Wait Control Register 1 (EWCR1)
External Space Wait Control Register 2 (EWCR2)
External Space Wait Control Register 3 (EWCR3)
45
Blank spaces are reserved. No access is allowed.
B-1
Quick Reference by Address
Address
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
Register
DMA0 Interrupt Control Register (DM0IC)
Timer B5 Interrupt Control Register (TB5IC)
DMA2 Interrupt Control Register (DM2IC)
UART2 Receive /ACK Interrupt Control Register (S2RIC)
Timer A0 Interrupt Control Register (TA0IC)
UART3 Receive /ACK Interrupt Control Register (S3RIC)
Timer A2 Interrupt Control Register (TA2IC)
UART4 Receive /ACK Interrupt Control Register (S4RIC)
Timer A4 Interrupt Control Register (TA4IC)
UART0 Bus Conflict Detect Interrupt Control Register (BCN0IC)/
UART3 Bus Conflict Detect Interrupt Control Register (BCN3IC)
UART0 Receive/ACK Interrupt Control Register (S0RIC)
A/D0 Conversion Interrupt Control Register (AD0IC)
UART1 Receive/ACK Interrupt Control Register (S1RIC)
Intelligent I/O Interrupt Control Register 0 (IIO0IC)/
CAN Interrupt 3 Control Register (CAN3IC)
Timer B1 Interrupt Control Register (TB1IC)
Intelligent I/O Interrupt Control Register 2 (IIO2IC)
Timer B3 Interrupt Control Register (TB3IC)
Intelligent I/O Interrupt Control Register 4 (IIO4IC)
INT5 Interrupt Control Register (INT5IC)
007616
007716
007816
007916
007A16
007B16
007C16 INT3 Interrupt Control Register (INT3IC)
007D16
007E16 INT1 Interrupt Control Register (INT1IC)
007F16
008016
008116
008216
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
DMA1 Interrupt Control Register (DM1IC)
UART2 Transmit /NACK Interrupt Control Register (S2TIC)
DMA3 Interrupt Control Register (DM3IC)
UART3 Transmit /NACK Interrupt Control Register (S3TIC)
Timer A1 Interrupt Control Register (TA1IC)
UART4 Transmit /NACK Interrupt Control Register (S4TIC)
Timer A3 Interrupt Control Register (TA3IC)
UART2 Bus Conflict Detect Interrupt Control Register (BCN2IC)
Blank spaces are reserved. No access is allowed.
B-2
Page
90
91
91
91
90
Address
Register
Page
009016 UART0 Transmit /NACK Interrupt Control Register (S0TIC)
UART1 Bus Conflict Detect Interrupt Control Register (BCN1IC)/
009116
UART4 Bus Conflict Detect Interrupt Control Register (BCN4IC)
009216 UART1 Transmit/NACK Interrupt Control Register (S1TIC)
009316 Key Input Interrupt Control Register (KUPIC)
009416 Timer B0 Interrupt Control Register (TB0IC)
91
Intelligent I/O Interrupt Control Register 1 (IIO1IC)/
009516
CAN Interrupt 4 Control Register (CAN4IC)
009616 Timer B2 Interrupt Control Register (TB2IC)
009716 Intelligent I/O Interrupt Control Register 3 (IIO3IC)
009816 Timer B4 Interrupt Control Register (TB4IC)
009916
009A16 INT4 Interrupt Control Register (INT4IC)
91
009B16
009C16 INT2 Interrupt Control Register (INT2IC)
91
009D16
009E16 INT0 Interrupt Control Register (INT0IC)
91
009F16
00A016
00A116
00A216
00A316
00A416
00A516
00A616
00A716
00A816
00A916
00AA16
00AB16
00AC16
00AD16
00AE16
00AF16
00B016
00B116
00B216
00B316
00B416
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
00BC16
00BD16
00BE16
00BF16
Exit Priority Control Register (RLVL)
Interrupt Request Register 0 (IIO0IR)
Interrupt Request Register 1 (IIO1IR)
Interrupt Request Register 2 (IIO2IR)
Interrupt Request Register 3 (IIO3IR)
Interrupt Request Register 4 (IIO4IR)
Interrupt Request Register 5 (IIO5IR)
Interrupt Enable Register 0 (IIO0IE)
Interrupt Enable Register 1 (IIO1IE)
Interrupt Enable Register 2 (IIO2IE)
Interrupt Enable Register 3 (IIO3IE)
Interrupt Enable Register 4 (IIO4IE)
92
103
104
Quick Reference by Address
Address
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
Register
Page
SI/O Receive Buffer Register0 (G0RB)
247
Transmit Buffer/Receive Data Register 0 (G0TB/G0DR)
253
Receive Input Register 0 (G0RI)
SI/O Communication Mode Register 0 (G0MR)
Transmit Output Register 0 (G0TO)
SI/O Communication Control Register 0 (G0CR)
246
248
246
247
Address
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
010016
010116
010216
010316
010416
010516
010616
010716
010816
010916
010A16
010B16
010C16
010D16
010E16
010F16
011016
011116
011216
011316
011416
011516
011616
011716
011816
011916
011A16
011B16
011C16
011D16
011E16
011F16
Register
Data Compare Register 00 (G0CMP0)
Data Compare Register 01 (G0CMP1)
Data Compare Register 02 (G0CMP2)
Data Compare Register 03 (G0CMP3)
Data Mask Register 00 (G0MSK0)
Data Mask Register 01 (G0MSK1)
Communication Clock Select Register (CCS)
Page
254
255
Receive CRC Code Register 0 (G0RCRC)
254
Tramsmit CRC Code Register 0 (G0TCRC)
SI/O Extended Mode Register 0 (G0EMR)
SI/O Extended Receive Control Register 0 (G0ERC)
SI/O Special Communication Interrupt Detect Register 0 (G0IRF)
SI/O Extended Transmit Control Register 0 (G0ETC)
249
251
252
250
Blank spaces are reserved. No access is allowed.
B-3
Quick Reference by Address
Address
012016
012116
012216
012316
012416
012516
012616
012716
012816
012916
012A16
012B16
012C16
012D16
012E16
012F16
013016
013116
013216
013316
013416
013516
013616
013716
013816
013916
013A16
013B16
013C16
013D16
013E16
013F16
014016
014116
014216
014316
014416
014516
014616
014716
014816
014916
014A16
014B16
014C16
014D16
014E16
014F16
Register
SI/O Receive Buffer Register 1 (G1RB)
247
Transmit Buffer/Receive Data Register 1 (G1TB/G1DR)
253
Receive Input Register 1 (G1RI)
SI/O Communication Mode Register 1 (G1MR)
Transmit Output Register 1 (G1TO)
SI/O Communication Control Register 1 (G1CR)
Data Compare Register 10 (G1CMP0)
246
248
246
247
Data Compare Register 11 (G1CMP1)
Data Compare Register 12 (G1CMP2)
Data Compare Register 13 (G1CMP3)
Data Mask Register 10 (G1MSK0)
Data Mask Register 11 (G1MSK1)
254
Receive CRC Code Register1 (G1RCRC)
254
Transmit CRC Code Register1 (G1TCRC)
SI/O Extended Mode Register 1 (G1EMR)
SI/O Extended Receive Control Register 1 (G1ERC)
SI/O Special Communication Interrupt Detect Register 1 (G1IRF)
SI/O Extended Transmit Control Register 1 (G1ETC)
Blank spaces are reserved. No access is allowed.
B-4
Page
249
251
253
250
Address
015016
015116
015216
015316
015416
015516
015616
015716
015816
015916
015A16
015B16
015C16
015D16
015E16
015F16
016016
016116
016216
016316
016416
016516
016616
016716
016816
016916
016A16
016B16
016C16
016D16
016E16
016F16
017016
017116
017216
017316
017416
017516
017616
017716
017816
017916
017A16
017B16
017C16
017D16
to
02AF16
Register
Page
Quick Reference by Address
Address
02B016
02B116
02B216
02B316
02B416
02B516
02B616
02B716
02B816
02B916
02BA16
02BB16
02BC16
02BD16
02BE16
02BF16
02C016
02C116
02C216
02C316
02C416
02C516
02C616
02C716
02C816
02C916
02CA16
02CB16
02CC16
02CD16
02CE16
02CF16
02D016
02D116
02D216
02D316
02D416
02D516
02D616
02D716
02D816
02D916
02DA16
02DB16
02DC16
02DD16
02DE16
02DF16
Register
Page
X0 Register Y0 Register (X0R,Y0R)
X1 Register Y1 Register (X1R,Y1R)
X2 Register Y2 Register (X2R,Y2R)
X3 Register Y3 Register (X3R,Y3R)
X4 Register Y4 Register (X4R,Y4R)
X5 Register Y5 Register (X5R,Y5R)
X6 Register Y6 Register (X6R,Y6R)
X7 Register Y7 Register (X7R,Y7R)
241
X8 Register Y8 Register (X8R,Y8R)
X9 Register Y9 Register (X9R,Y9R)
X10 Register Y10 Register (X10R,Y10R)
X11 Register Y11 Register (X11R,Y11R)
X12 Register Y12 Register (X12R,Y12R)
X13 Register Y13 Register (X13R,Y13R)
X14 Register Y14 Register (X14R,Y14R)
X15 Register Y15 Register (X15R,Y15R)
Address
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
02EB16
02EC16
02ED16
02EE16
02EF16
02F016
02F116
02F216
02F316
02F416
02F516
02F616
02F716
02F816
02F916
02FA16
02FB16
02FC16
02FD16
02FE16
02FF16
030016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
Register
X/Y Control Register (XYC)
UART1 Special Mode Register 4 (U1SMR4)
UART1 Special Mode Register 3 (U1SMR3)
UART1 Special Mode Register 2 (U1SMR2)
UART1 Special Mode Register (U1SMR)
UART1 Transmit/Receive Mode Register (U1MR)
UART1 Bit Rate Register (U1BRG)
Page
241
175
174
173
172
170
UART1 Transmit Buffer Register (U1TB)
169
UART1 Transmit/Receive Control Register 0 (U1C0)
UART1 Transmit/Receive Control Register 1 (U1C1)
171
172
UART1 Receive Buffer Register (U1RB)
169
UART4 Special Mode Register 4 (U4SMR4)
UART4 Special Mode Register 3 (U4SMR3)
UART4 Special Mode Register 2 (U4SMR2)
UART4 Special Mode Register (U4SMR)
UART4 Transmit/Receive Mode Register (U4MR)
UART4 Bit Rate Register (U4BRG)
175
174
173
172
170
UART4 Transmit Buffer Register (U4TB)
169
UART4 Transmit/Receive Control Register 0 (U4C0)
UART4 Transmit/Receive Control Register 1 (U4C1)
171
172
UART4 Receive Buffer Register (U4RB)
169
Timer B3,B4,B5 Count Start Flag (TBSR)
149
Timer A1-1 Register (TA11)
Timer A2-1 Register (TA21)
162
Timer A4-1 Register (TA41)
Three-Phase PWM Control Register 0 (INVC0)
Three-Phase PWM Control Register 1 (INVC1)
Three-Phase Output Buffer Register 0 (IDB0)
Three-Phase Output Buffer Register 1 (IDB1)
Dead Time Timer (DTT)
Timer B2 Interrupt Generating Frequency Set Counter (ICTB2)
159
160
161
161
162
Blank spaces are reserved. No access is allowed.
B-5
Quick Reference by Address
Address
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
Register
Timer B3 Register (TB3)
Timer B4 Register (TB4)
147
Timer B5 Register (TB5)
Timer B3 Mode Register (TB3MR)
Timer B4 Mode Register (TB4MR)
Timer B5 Mode Register (TB5MR)
148
External Interrupt Request Source Select Register (IFSR)
99
UART3 Special Mode Register 4 (U3SMR4)
UART3 Special Mode Register 3 (U3SMR3)
UART3 Special Mode Register 2 (U3SMR2)
UART3 Special Mode Register (U3SMR)
UART3 Transmit/Receive Mode Register (U3MR)
UART3 Bit Rate Register (U3BRG)
175
174
173
172
170
UART3 Transmit Buffer Register (U3TB)
169
UART3 Transmit/Receive Control Register 0 (U3C0)
UART3 Transmit/Receive Control Register 1 (U3C1)
171
172
UART3 Receive Buffer Register (U3RB)
169
UART2 Special Mode Register 4 (U2SMR4)
UART2 Special Mode Register 3 (U2SMR3)
UART2 Special Mode Register 2 (U2SMR2)
UART2 Special Mode Register (U2SMR)
UART2 Transmit/Receive Mode Register (U2MR)
UART2 Bit Rate Register (U2BRG)
175
174
173
172
170
UART2 Transmit Buffer Register (U2TB)
169
UART2 Transmit/Receive Control Register 0 (U2C0)
UART2 Transmit/Receive Control Register 1 (U2C1)
171
172
UART2 Receive Buffer Register (U2RB)
169
Blank spaces are reserved. No access is allowed.
B-6
Page
Address
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
Register
Count Start Flag (TABSR)
Clock Prescaler Reset Flag (CPSRF)
One-Shot Start Flag (ONSF)
Trigger Select Register (TRGSR)
Up/Down Flag (UDF)
Page
132
62
133
134
133
Timer A0 Register (TA0)
Timer A1 Register (TA1)
Timer A2 Register (TA2)
131
Timer A3 Register (TA3)
Timer A4 Register (TA4)
Timer B0 Register (TB0)
Timer B1 Register (TB1)
147
Timer B2 Register (TB2)
Timer A0 Mode Register (TA0MR)
Timer A1 Mode Register (TA1MR)
Timer A2 Mode Register (TA2MR)
Timer A3 Mode Register (TA3MR)
Timer A4 Mode Register (TA4MR)
Timer B0 Mode Register (TB0MR)
Timer B1 Mode Register (TB1MR)
Timer B2 Mode Register (TB2MR)
Timer B2 Special Mode Register (TB2SC)
Count Source Prescaler Register (TCSPR)
UART0 Special Mode Register 4 (U0SMR4)
UART0 Special Mode Register 3 (U0SMR3)
UART0 Special Mode Register 2 (U0SMR2)
UART0 Special Mode Register (U0SMR)
UART0 Transmit/Receive Mode Register (U0MR)
UART0 Bit Rate Register (U0BRG)
132
148
162
62
175
174
173
172
170
UART0 Transmit Buffer Register (U0TB)
169
UART0 Transmit/Receive Control Register 0 (U0C0)
UART0 Transmit/Receive Control Register 1 (U0C1)
171
172
UART0 Receive Buffer Register (U0RB)
169
Quick Reference by Address
Address
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
Register
DMA0 Request Source Select Register (DM0SL)
DMA1 Request Source Select Register (DM1SL)
DMA2 Request Source Select Register (DM2SL)
DMA3 Request Source Select Register (DM3SL)
CRC Data Register (CRCD)
Page
111
239
CRC Input Register (CRCIN)
A/D0 Register0 (AD00)
A/D0 Register1 (AD01)
A/D0 Register2 (AD02)
A/D0 Register3 (AD03)
226
A/D0 Register4 (AD04)
A/D0 Register5 (AD05)
A/D0 Register6 (AD06)
A/D0 Register7 (AD07)
A/D0 Control Register 2 (AD0CON2)
A/D0 Control Register 3 (AD0CON3)
A/D0 Control Register 0 (AD0CON0)
A/D0 Control Register 1 (AD0CON1)
D/A Register 0 (DA0)
224
225
222
223
238
D/A Register 1 (DA1)
238
D/A Control Register (DACON)
238
Address
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
Register
Page
Function Select Register D1 (PSD1)
274
Function Select Register C3 (PSC3)
274
Function Select Register C (PSC)
Function Select Register A0 (PS0)
Function Select Register A1 (PS1)
Function Select Register B0 (PSL0)
Function Select Register B1 (PSL1)
Function Select Register A2 (PS2)
Function Select Register A3 (PS3)
Function Select Register B2 (PSL2)
Function Select Register B3 (PSL3)
273
Port P6 Register (P6)
Port P7 Register (P7)
Port P6 Direction Register (PD6)
Port P7 Direction Register (PD7)
Port P8 Register (P8)
Port P9 Register (P9)
Port P8 Direction Register (PD8)
Port P9 Direction Register (PD9)
Port P10 Register (P10)
Port P10 Direction Register (PD10)
269
271
270
272
268
267
268
267
268
267
Blank spaces are reserved. No access is allowed.
B-7
Quick Reference by Address
Address
Register
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16 Pull-Up Control Register 2 (PUR2)
03DB16 Pull-Up Control Register 3 (PUR3)
03DC16
03DD16
03DE16
03DF16
03E016 Port P14 Register (P0)
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Port P14 Register (P1)
Port P14 Direction Register (PD0)
Port P14 Direction Register (PD1)
Port P14 Register (P2)
Port P14 Register (P3)
Port P14 Direction Register (PD2)
Port P14 Direction Register (PD3)
Port P14 Register (P4)
Port P14 Register (P5)
Port P14 Direction Register (PD4)
Port P14 Direction Register (PD5)
275
276
268
267
268
267
268
267
Pull-up Control Register 0 (PUR0)
Pull-up Control Register 1 (PUR1)
275
Port Control Register (PCR)
276
Blank spaces are reserved. No access is allowed.
B-8
Page
M32C/80 Group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
1. Overview
The M32C/80 Group microcomputer is a single-chip control unit that utilizes high-performance silicon gate
CMOS technology with the M32C/80 series CPU core. The M32C/80 Group is available in 100-pin plastic
molded LQFP/QFP package.
With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed.
It incorporates a multiplier and DMAC adequate for office automation, communication devices and industrial
equipments and other high-speed processing applications.
The M32C/80 Group is ROMless device.
Use the M32C/80 Group in microprocessor mode after reset.
1.1 Applications
Audio, cameras, office equipment, communications equipment, portable equipment, etc.
Rev. 1.00 Nov. 01, 2005 page 1
REJ09B0271-0100
of 330
1. Overview
M32C/80 Group
1.2 Performance Overview
Table 1.1 lists performance overview of the M32C/80 Group.
Table 1.1 M32C/80 Group Performance
CPU
Item
Basic Instructions
Minimum Instruction Execution Time
Operating Mode
Memory Space
Memory Capacity
Peripheral I/O Port
function Multifunction Timer
Intelligent I/O Communication Function
Serial I/O
A/D Converter
D/A Converter
DMAC
DMAC II
CRC Calculation Circuit
X/Y Converter
Watchdog Timer
Interrupt
Clock Generation Circuit
Oscillation Stop Detect Function
Electrical Supply Voltage
Characteristics Power Consumption
Operating AmbientTemperature
Package
NOTES:
Performance
108 instructions
31.3 ns ( f(BCLK)=32 MHz, VCC1=4.2 to 5.5 V )
41.7 ns ( f(BCLK)=24 MHz, VCC1=3.0 to 5.5 V )
Single-chip mode, Memory expansion mode, Microprocessor mode
16 Mbytes
See Table 1.2
47 I/O pins (when using 16-bit bus) and 1 input pin
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels
Three-phase motor control circuit
2 channels
5 channels
Clock synchronous serial I/O, Clock asynchronous serial I/O,
IEBus(1), I2C Bus(2)
10-bit A/D converter: 1 circuit, 10 channels
8 bits x 2 channels
4 channels
Can be activated by all peripheral function interrupt sources
Immediate transfer, operation and chain transfer function
CRC-CCITT
16 bits x 16 bits
15 bits x 1 channel (with prescaler)
34 internal sources and 8 external sources, 5 software sources
Interrupt priority level: 7
4 circuits
Main Clock oscillation circuit (*), Sub clock oscillation circuit (*),
On-chip oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resistor
Main clock oscillation stop detect circuit
VCC1=4.2 to 5.5 V, VCC2=3.0 to VCC1 (f(BCLK)=32 MHz)
VCC1=3.0 to 5.5 V, VCC2=3.0 to VCC1 (f(BCLK)=24 MHz)
22 mA (VCC1=VCC2=5 V, f(BCLK)=32 MHz)
17 mA (VCC1=VCC2=3.3 V, f(BCLK)=24 MHz)
10 µA (VCC1=VCC2=3.3 V, f(BCLK)=32 kHz, in wait mode)
–20 to 85oC, –40 to 85oC(optional)
100-pin plastic molded LQFP/QFP
1. IEBus is a trademark of NEC Electronics Corporation.
2. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
All options are on a request basis.
Rev. 1.00 Nov. 01, 2005
REJ09B0271-0100
page 2
of 330
1. Overview
M32C/80 Group
1.3 Block Diagram
Figure 1.1 shows a block diagram of the M32C/80 Group microcomputer.
8
8
(1)
Port P0
8
(2)
Port P1
8
(1)
8
(1)
Port P2
Port P3
8
(1)
Port P4
(1)
Port P5
<VCC2>
8
7
DMAC
8
UART/
Clock Synchronous Serial I/O
5 channels
Timer (16 bits)
Timer A: 5 channels
Timer B: 6 channels
Port P8
Clock Generating Circuit
XIN - XOUT
XCIN - XCOUT
On-chip Oscillator
PLL Frequency Synthesizer
Port P7
A/D Converter
1 circuit
Standard: 8 inputs
Maximum: 10 inputs
Port P6
Peripheral Functions
DMACII
Three-phase Motor Control Circuit
X/Y converter
16 bits X 16 bits
R0H
R0L
R1H
R1L
A1
ISP
R3
USP
RAM
PC
SVF
SVP
SB
VCT
Multiplier
Rev. 1.00 Nov. 01, 2005 page 3
REJ09B0271-0100
of 330
8
Port P10
FB
NOTES:
1. Ports P0 to P5 function as bus control pins when using memory expansion mode or microprocessor mode.
2. Port P1 functions as I/O port when the microcomputer is placed in memory expansion mode or microprocessor mode
and all external data buses are selected as 8-bit buses.
Figure 1.1 M32C/80 Group Block Diagram
8
A0
Intelligent I/O
Communication Function
2 channels
INTB
R2
Port P9
D/A Converter
8 bits X 2 channels
Memory
FLG
P85
M32C/80 series CPU core
<VCC1>
Watchdog Timer (15 bits)
CRC Calcilation Circuit (CCITT)
X16+X12+X5+1
1. Overview
M32C/80 Group
1.4 Product Information
Table 1.2 lists the product information. Figure 1.2 shows the product numbering system.
Table 1.2 M32C/80 Group
As of November, 2005
Type Number
Package Type
M30800SAGP
PLQP0100KB-A (100P6Q-A)
M30800SAFP
PRQP0100JB-A (100P6S-A)
M30800SAGP-BL
PLQP0100KB-A (100P6Q-A)
M30800SAFP-BL
PRQP0100JB-A (100P6S-A)
ROM
Capacity
RAM
Capacity
Remarks
ROMless
−
8K
ROMless with
on-chip boot loader
M30800 S A GP -BL
On-chip boot loader
Package type:
FP = Package PRQP0100JB-A (100P6S-A)
GP = Package PLQP0100KB-A (100P6Q-A)
Memory type:
S = ROMless version
RAM capacity, pin count, etc
M32C/80 Group
M16C Family
Figure 1.2 Product Numbering System
Rev. 1.00 Nov. 01, 2005
REJ09B0271-0100
page 4
of 330
1. P70 and P71 are ports for the N-channel open drain output.
Figure 1.3 Pin Assignment
Rev. 1.00 Nov. 01, 2005 page 5
REJ09B0271-0100
of 330
15
16
17
18
19
20
21
22
23
XIN
Vcc1
NMI / P85
INT2 / P84
INT1 / P83
INT0 / P82
U / TA4IN / P81
ISRxD0 / U / TA4OUT / P80
ISCLK0 / TA3IN / P77
30
14
Vss
29
13
XOUT
SRxD2 / SDA2 / TxD2 / TA0OUT / P70
12
RESET
STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71
11
XCOUT / P86
28
10
XCIN / P87
CLK2 / V / TA1OUT / P72
9
CNVss
27
8
BYTE
ISTxD1 / SS2 / RTS2 / CTS2 / V / TA1IN / P73
7
CLK3 / TB0IN / P90
26
6
STxD3 / SCL3 / RxD3 / TB1IN / P91
ISCLK1 / W / TA2OUT / P74
5
SRxD3 / SDA3 / TxD3 / TB2IN / P92
25
4
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
24
3
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
ISTxD0 / TA3OUT / P76
2
ISRxD1 / W / TA2IN / P75
1
CLK4 / ANEX0 / P95
STxD4 / SCL4 /
SRxD4 / SDA4 / TxD4 / ANEX1 / P96
P22 / A2 ( / D2 )
P23 / A3 ( / D3 )
P24 / A4 ( / D4 )
P25 / A5 ( / D5 )
P26 / A6 ( / D6 )
P27 / A7 ( / D7 )
Vss
P30 / A8 ( / D8 )
Vcc2
P31 / A9 ( / D9 )
P32 / A10 ( / D10 )
70
69
68
67
66
65
64
63
62
61
60
P40 / A16
P41 / A17
P42 / A18
P43 / A19
54
53
52
51
P37 / A15 ( / D15 )
P21 / A1 ( / D1 )
71
P36 / A14 ( / D14 )
P20 / A0 ( / D0 )
72
55
P17 / D15 / INT5
73
P35 / A13 ( / D13 )
P16 / D14 / INT4
74
56
P15 / D13 / INT3
75
57
P14 / D12
76
P33 / A11 ( / D11 )
P13 / D11
77
P34 / A12 ( / D12 )
P12 / D10
78
58
P11 / D9
79
59
P10 / D8
80
M32C/80 Group
1. Overview
1.5 Pin Assignment
Figures 1.3 and 1.4 show pin assignments (top view).
D7 / P07
81
D6 / P06
82
D5 / P05
83
D4 / P04
84
D3 / P03
85
46
P50 / WRL / WR
D2 / P02
86
45
P51 / WRH / BHE
D1 / P01
87
44
P52 / RD
D0 / P00
88
43
P53 / CLKOUT / BCLK / ALE
KI3 / AN7 / P107
89
42
P54 / HLDA / ALE
KI2 / AN6 / P106
90
41
P55 / HOLD
KI1 / AN5 / P105
91
40
P56 / ALE
KI0 / AN4 / P104
92
39
P57 / RDY
AN3 / P103
93
38
P60 / CTS0 / RTS0 / SS0
AN2 / P102
94
37
P61 / CLK0
AN1 / P101
95
36
P62 / RxD0 / SCL0 / STxD0
AVss
96
35
P63 / TxD0 / SDA0 / SRxD0
AN0 / P100
97
34
P64 / CTS1 / RTS1 / SS1
VREF
98
33
P65 / CLK1
AVcc
99
32
P66 / RxD1 / SCL1 / STxD1
RxD4 / ADTRG / P97
100
31
P67 / TxD1 / SDA1 / SRxD1
<VCC2>
M32C/80 GROUP
<VCC1>
50
P44 / CS3 / A20
49
P45 / CS2 / A21
48
P46 / CS1 / A22
47
P47 / CS0 / A23
NOTE:
PRQP0100JB-A
(100P6S-A)
1. Overview
P40 / A16
P41 / A17
51
P31 / A9 ( / D9 )
59
P37 / A15 ( / D15 )
Vcc2
60
52
P30 / A8 ( / D8 )
61
P36 / A14 ( / D14 )
Vss
62
53
P27 / A7 ( / D7 )
63
P35 / A13 ( / D13 )
P26 / A6 ( / D6 )
64
54
P25 / A5 ( / D5 )
65
P34 / A12 ( / D12 )
P24 / A4 ( / D4 )
66
55
P23 / A3 ( / D3 )
67
56
P22 / A2 ( / D2 )
68
P32 / A10 ( / D10 )
P21 / A1 ( / D1 )
69
P33 / A11 ( / D11 )
P20 / A0 ( / D0 )
70
57
P17 / D15 / INT5
71
58
P15 / D13 / INT3
P16 / D14 / INT4
72
P14 / D12
74
73
P13 / D11
75
M32C/80 Group
D10 / P12
76
50
P42 / A18
D9 / P11
77
49
P43 / A19
D8 / P10
78
D7 / P07
<VCC2>
48
P44 / CS3 / A20
79
47
P45 / CS2 / A21
D6 / P06
80
46
P46 / CS1 / A22
D5 / P05
81
45
P47 / CS0 / A23
D4 / P04
82
44
P50 / WRL / WR
D3 / P03
83
43
P51 / WRH / BHE
D2 / P02
84
42
P52 / RD
D1 / P01
85
41
P53 / CLKOUT / BCLK / ALE
D0 / P00
86
40
P54 / HLDA / ALE
KI3 / AN7 / P107
87
39
P55 / HOLD
KI2 / AN6 / P106
88
38
P56 / ALE
KI1 / AN5 / P105
89
37
P57 / RDY
KI0 / AN4 / P104
90
36
P60 / CTS0 / RTS0 / SS0
AN3 / P103
91
35
P61 / CLK0
AN2 / P102
92
34
P62 / RxD0 / SCL0 / STxD0
AN1 / P101
93
33
P63 / TxD0 / SDA0 / SRxD0
AVss
94
32
P64 / CTS1 / RTS1 / SS1
AN0 / P100
95
31
P65 / CLK1
VREF
96
30
P66 / RxD1 / SCL1 / STxD1
AVcc
97
29
P67 / TxD1 / SDA1 / SRxD1
STxD4 / SCL4 / RxD4 / ADTRG / P97
98
28
P70 / TA0OUT / TxD2 / SDA2 / SRxD2
SRxD4 / SDA4 / TxD4 / ANEX1 / P96
99
27
P71 / TA0IN / TB5IN / RxD2 / SCL2 / STxD2
CLK4 / ANEX0 / P95
100
26
P72 / TA1OUT / V / CLK2
M32C/80 GROUP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
SRxD3 / SDA3 / TxD3 / TB2IN / P92
STxD3 / SCL3 / RxD3 / TB1IN / P91
CLK3 / TB0IN / P90
BYTE
CNVss
XCIN / P87
XCOUT / P86
RESET
XOUT
Vss
XIN
Vcc1
NMI / P85
INT2 / P84
INT1 / P83
INT0 / P82
U / TA4IN / P81
ISRxD0 / U / TA4OUT / P80
ISCLK0 / TA3IN / P77
ISTxD0 / TA3OUT / P76
ISRxD1 / W / TA2IN / P75
ISCLK1 / W / TA2OUT / P74
ISTxD1 / SS2 / RTS2 / CTS2 / V / TA1IN / P73
<VCC1>
NOTE:
1. P70 and P71 are ports for the N-channel open drain output.
Figure 1.4 Pin Assignment
Rev. 1.00 Nov. 01, 2005
REJ09B0271-0100
page 6
of 330
PLQP0100KB-A
(100P6Q-A)
1. Overview
M32C/80 Group
Table 1.3 Pin Characteristics
Package
Pin No
FP GP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Control
pins
Port
Interrupt
pins
P96
P95
P94
P93
P92
P91
P90
BYTE
CNVSS
XCIN
XCOUT
RESET
XOUT
VSS
XIN
VCC1
Timer
pins
TB4IN
TB3IN
TB2IN
TB1IN
TB0IN
UART
pins
Analog
pins
TxD4/SDA4/SRxD4
CLK4
CTS4/RTS4/SS4
CTS3/RTS3/SS3
TxD3/SDA3/SRxD3
RxD3/SCL3/STxD3
CLK3
ANEX1
ANEX0
DA1
DA0
Bus control
pins
Intelligent I/O
pins
P87
P86
P85
P84
P83
P82
P81
P80
P77
P76
P75
P74
P73
P72
P71
P70
P67
P66
P65
P64
P63
P62
P61
P60
P57
P56
P55
P54
P53
P52
P51
P50
P47
P46
P45
P44
NMI
INT2
INT1
INT0
Rev. 1.00 Nov. 01, 2005 page 7
REJ09B0271-0100
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
TB5IN/TA0IN
TA0OUT
ISRxD0
ISCLK0
ISTxD0
ISRxD1
ISCLK1
ISTxD1
CTS2/RTS2/SS2
CLK2
RxD2/SCL2/STxD2
TxD2/SDA2/SRxD2
TxD1/SDA1/SRxD1
RxD1/SCL1/STxD1
CLK1
CTS1/RTS1/SS1
TxD0/SDA0/SRxD0
RxD0/SCL0/STxD0
CLK0
CTS0/RTS0/SS0
RDY
ALE
HOLD
HLDA/ALE
CLKOUT/BCLK/ALE
RD
WRH/BHE
WRL/WR
CS0/A23
CS1/A22
CS2/A21
CS3/A20
of 330
1. Overview
M32C/80 Group
Table 1.3 Pin Characteristics (Continued)
Package
pin No
FP GP
Control
pins
Port
Interrupt
pins
Timer
pins
UART
pins
Analog
pins
Bus control
pins
49
50
P43
A19
P42
A18
51
52
P41
A17
P40
A16
55
56
57
53
54
55
P37
P36
A15(/D15)
A14(/D14)
A13(/D13)
58
59
56
57
P34
P33
58
59
P32
A11(/D11)
A10(/D10)
P31
A9(/D9)
P30
A8(/D8)
P27
P26
A7(/D7)
51
52
53
54
60
61
62
63
64
65
66
P35
60
61
VCC2
62
63
64
VSS
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
83
84
85
81
82
83
86
87
84
85
A12(/D12)
A6(/D6)
A5(/D5)
P25
A4(/D4)
P24
P23
A3(/D3)
A2(/D2)
P22
P21
P20
P17
P16
P15
A1(/D1)
A0(/D0)
D15
INT5
INT4
INT3
D14
D13
P14
P13
D12
D11
P12
D10
P11
D9
P10
P07
D8
D7
P06
P05
D6
D5
P04
D4
P03
P02
D3
D2
P01
D1
D0
88
89
90
86
87
88
P00
91
89
92
93
94
90
91
92
P105
P104
95
96
97
93
94
95
98
99
96
97
100
98
P107
KI3
AN7
P106
KI2
KI1
AN6
AN5
KI0
P103
AN4
AN3
P102
AN2
P101
AN1
P100
AN0
VREF
AVSS
AVCC
P97
Rev. 1.00 Nov. 01, 2005
REJ09B0271-0100
page 8
RxD4/SCL4/STxD4
of 330
ADTRG
Intelligent I/O
pins
1. Overview
M32C/80 Group
1.6 Pin Description
Table 1.4 Pin Description
Signal name
Power supply
Analog power
supply input
Reset input
Pin name I/O type
VCC1, VCC2
VSS
AVCC
AVSS
____________
RESET
I
Supply
voltage
Description
-
Apply 3.0 to 5.5 V to both VCC1 and VCC2 pins. Apply 0 V to the
I
VCC1
VSS pin. VCC1 ≥ VCC2(1)
Supplies power for the A/D converter. Connect the AVCC pin to
I
VCC1
VCC1 and the AVSS pin to VSS
The microcomputer is in a reset state when "L" is applied to the
RESET pin
Connect this pin to VCC1
____________
CNVSS
External data
CNVSS
I
VCC1
BYTE
I
VCC1
D0 to D7
I/O
VCC2
when the this pin is held "H". Set it to either one.
Inputs and outputs data (D0 to D7) while accessing an external
D8 to D15
I/O
VCC2
memory space with separate bus
Inputs and outputs data (D8 to D15) while accessing an external
O
VCC2
memory space with 16-bit separate bus
Outputs address bits (A0 to A22)
O
I/O
VCC2
VCC2
Outputs inversed address bit A23
Inputs and outputs data (D0 to D7) and outputs 8 low-order
bus width
select input
Bus control
pins
A0 to A22
Switches the data bus in external memory space 3. The data
bus is 16 bits long when the this pin is held "L" and 8 bits long
______
A23
A0/D0 to
A7/D7
address bits (A0 to A7) by time-sharing while accessing an
external memory space with multiplexed bus
A8/D8 to
A15/D15
______
I/O
VCC2
______
CS0 to CS3
O
VCC2
O
VCC2
Inputs and outputs data (D8 to D15) and outputs 8 middle-order
address bits (A8 to A15) by time-sharing while accessing an
external memory space with multiplexed bus
______
______
Output CS0 to CS3 that are chip-select signals specifying an external space
________ ______
WRL/WR
_________ ________
WRH/BHE
_______
_____
________
RD
________
______
________
_____
_______
________
Outputs WRL, WRH, (WR, BHE) and RD signals. WRL and WRH
______
_______
can be switched with WR and BHE by program
_________
_____
WRL, WRH and RD are selected:
If external data bus is 16 bits wide, data is writtenn to an even
_______
address when WRL is held "L".
________
Data is written to an odd address when WRH is held "L".
_____
Data is read when RD is held "L".
______ ________
_____
WR, BHE and RD are selected
______
Data is written to external memory space when WR is held "L".
_____
Data is read when RD is held "L".
________
An odd address is accessed when BHE is held "L".
______ ________
_____
Select WR, BHE and RD for an external 8-bit data bus
ALE
__________
HOLD
O
I
VCC2
VCC2
ALE is a signal latching address
__________
The microcomputer is placed in a hold state while the HOLD pin
O
VCC2
is held "L"
Outputs an "L" siganl while the microcomputer is placed in a hold state
I
VCC2
Bus is placed in a wait state while the RDY pin is held "L"
__________
HLDA
________
RDY
I: Input
O: Output
I/O: Input and output
NOTE:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
Rev. 1.00 Nov. 01, 2005 page 9
REJ09B0271-0100
of 330
1. Overview
M32C/80 Group
Table 1.4 Pin Description (Continued)
Signal name
Main clock input XIN
XOUT
Main clock
output
I
Supply
voltage
VCC1
O
VCC1
Pin name I/O type
Description
I/O pins for the main clock generation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT. To apply
external clock, input the clock from XIN and leave XOUT open
I/O pins for a sub clock oscillation circuit. Connect a crystal
Sub clock input XCIN
Sub clock
XCOUT
I
O
VCC1
VCC1
output
BCLK output
BCLK
O
VCC2
Clock output
______
INT interrupt
CLKOUT
_______
_______
INT0 to INT2
O
I
VCC2
VCC1
I
VCC2
VCC1
I
I/O
VCC1
VCC1
TA4OUT
TA0IN to
I
VCC1
Input pins for the timer A0 to A4
TA4IN
TB0IN to
I
VCC1
Input pins for the timer B0 to B5
O
VCC1
output pins for the three-phase motor control timer
I
VCC1
Input pins for data transmission control
_______
Outputs BCLK signal
Outputs clock having thesame frequency as fC, f8, or f32
______
Input pins for the INT interrupt
_______
input
INT3 to INT5
_______
NMI interrupt input NMI
_______
_____
_____
Key input interrupt KI0 to KI3
Timer A
TA0OUT to
Timer B
oscillator between XCIN and XCOUT. To apply external clock,
input the clock from XCIN and leave XCOUT open
TB5IN
__
__
Three-phase motor U, U, V, V,
_______
Input pin for the NMI interrupt
Input pins for the key input interrupt
I/O pins for the timer A0 to A4
(TA0OUT is a pin for the N-channel open drain output.)
__
control output
Serial I/O
W, W
_________
CTS0 to
_________
CTS4
_________
RTS0 to
O
VCC1
Output pins for data reception control
RTS4
CLK0 to
I/O
VCC1
Inputs and outputs the transfer clock
CLK4
RxD0 to
I
VCC1
Inputs serial data
RxD4
TxD0 to
O
VCC1
Outputs serial data (TxD2 is a pin for the N-channel open drain
VCC1
output.)
Inputs and outputs serial data (SDA2 is a pin for for the N-
_________
I 2C
mode
TxD4
SDA0 to
I/O
SDA4
SCL0 to
I/O
VCC1
channel open drain output.)
Inputs and outputs the transfer clock (SCL2 is a pin for the N-
SCL4
STxD0 to
I
VCC1
channel open drain output.)
Outputs serial data when slave mode is selected (SDA2 is a pin
special function STxD4
SRxD0 to
I
VCC1
for the N-channel open drain output.)
Inputs serial data when slave mode is selected
I
VCC1
Input pins to control serial I/O special function
Serial I/O
SRxD4
______
_______
SS0 to SS4
I: Input
O: Output
Rev. 1.00 Nov. 01, 2005
REJ09B0271-0100
I/O: Input and output
page 10
of 330
1. Overview
M32C/80 Group
Table 1.5 Pin Description (Continued)
Signal name
Pin name I/O type
Supply
voltage
Reference
voltage input
VREF
I
-
A/D converter
AN0 to AN7
___________
ADTRG
I
I
VCC1
VCC1
I/O
VCC1
ANEX0
D/A converter
ANEX1
DA0, DA1
Intelligent I/O
ISCLK0
communication ISCLK1
function
ISTxD0
Description
Applies reference voltage for the A/D converter and D/A converter
Analog input pins for the A/D converter
Input pin for an external A/D trigger
Extended analog input pin for the A/D converter and output pin in
external op-amp connection mode
Extended analog input pin for the A/D converter
I
O
VCC1
VCC1
I/O
VCC1
Output pin for the D/A converter
Inputs and outputs clock for the intelligent I/O communication
O
VCC1
fucntion
Outputs data for the intelligent I/O communication fucntion
I
VCC1
Inputs data for the intelligent I/O communication fucntion
I/O
VCC2
I/O ports fro CMOS. Each port can be programmed for nput or
ISTxD1
ISRxD0
ISRxD1
I/O port
P00 to P07(1)
P10 to P17(2)
output under the control of the direction register. An input port
can be set, by program, for a pull-up resistor available or for no
P20 to P27(1)
P30 to P37(1)
pull-up resistor available in 4-bit units
P40 to P47(1)
P50 to P57(1)
P60 to P67
P70 to P77
P90 to P97
P100 to P107
P80 to P84,
I/O
VCC1
I/O ports having equivalent functions to P0
(P70 and P71 are ports for the N-channel open drain output.)
I/O
VCC1
I/O ports having equivalent functions to P0
I
VCC1
Shares a pin with NMI. NMI input state can be got by reading P8 5
P86, P87
_______
I: Input
NOTES:
P85
O: Output
_______
I/O: Input and output
1. Ports P0 to P5 function as bus control pins when using memory expansion mode or microprocessor mode. They
cannot be used as I/O ports.
2. Port P1 functions as I/O port when the microcomputer is placed in memory expansion mode or microprocessor
mode and all external data buses are selected as 8-bit buses.
Rev. 1.00 Nov. 01, 2005 page 11
REJ09B0271-0100
of 330
2. Central Processing Unit (CPU)
M32C/80 Group
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers.
The register bank is comprised of 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) out of 28 CPU registers.
Two sets of register banks are provided.
b31
b15
General Registers
b0
R2
R0H
R3
R1H
R0L
R1L
Data Register(1)
R2
R3
b23
A0
Address Register(1)
A1
SB
Static Base Register(1)
FB
Frame Base Register(1)
USP
User Stack Pointer
ISP
Interrupt Stack Pointer
INTB
Interrupt Table Register
Program Counter
PC
FLG
b15
Flag Register
b8 b7
IPL
b0
U I O B S Z D C
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Space
Processor Interrupt Priority Level
Reserved Space
b15
High-speed Interrupt Registers
b0
SVF
b23
Flag Save Register
SVP
PC Save Register
VCT
Vector Register
b7
DMAC-associated Registers
b0
DMD0
DMD1
b15
DCT0
DCT1
DMA Mode Register
DMA Transfer Count Register
DRC0
DRC1
b23
DMA Transfer Count Reload Register
DMA0
DMA1
DMA Memory Address Register
DRA0
DRA1
DMA Memory Address Reload Register
DSA0
DSA1
DMA SFR Address Register
NOTE:
1. The register bank is comprised of these registers. Two sets of register banks are provided.
Figure 2.1 CPU Register
Rev. 1.00 Nov. 01, 2005
REJ09B0271-0100
Page 12 of 330
2. Central Processing Unit (CPU)
M32C/80 Group
2.1 General Registers
2.1.1 Data Registers (R0, R1, R2 and R3)
R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be
split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers.
R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R1 and
R3.
2.1.2 Address Registers (A0 and A1)
A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arithmetic and logic operations.
2.1.3 Static Base Register (SB)
SB is a 24-bit register for SB-relative addressing.
2.1.4 Frame Base Register (FB)
FB is a 24-bit register for FB-relative addressing.
2.1.5 Program Counter (PC)
PC, 24 bits wide, indicates the address of an instruction to be executed.
2.1.6 Interrupt Table Register (INTB)
INTB is a 24-bit register indicating the starting address of an relocatable interrupt vector table.
2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP
and ISP. Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even
addresses to execute an interrupt sequence efficiently.
2.1.8 Flag Register (FLG)
FLG is a 16-bit register indicating a CPU state.
2.1.8.1 Carry Flag (C)
The C flag indicates whether carry or borrow has occurred after executing an instruction.
2.1.8.2 Debug Flag (D)
The D flag is for debug only. Set to "0".
2.1.8.3 Zero Flag (Z)
The Z flag is set to "1" when the value of zero is obtained from an arithmetic operation; otherwise "0".
2.1.8.4 Sign Flag (S)
The S flag is set to "1" when a negative value is obtained from an arithmetic operation; otherwise "0".
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2. Central Processing Unit (CPU)
M32C/80 Group
2.1.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this
flag is set to "1".
2.1.8.6 Overflow Flag (O)
The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0".
2.1.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
Interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1". The I flag is
set to "0" when an interrupt is acknowledged.
2.1.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1".
The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.1.8.9 Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.1.8.10 Reserved Space
When writing to a reserved space, set to "0". When reading, its content is indeterminate.
2.2 High-Speed Interrupt Registers
Registers associated with the high-speed interrupt are as follows:
- Flag save register (SVF)
- PC save register (SVP)
- Vector register (VCT)
Refer to 10.4 High-Speed Interrupt for details.
2.3 DMAC-Associated Registers
Registers associated with DMAC are as follows:
- DMA mode register (DMD0, DMD1)
- DMA transfer count register (DCT0, DCT1)
- DMA transfer count reload register (DRC0, DRC1)
- DMA memory address register (DMA0, DMA1)
- DMA SFR address register (DSA0, DSA1)
- DMA memory address reload register (DRA0, DRA1)
Refer to 12. DMAC for details.
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3. Memory
M32C/80 Group
3. Memory
Figure 3.1 shows a memory map of the M32C/80 Group.
The M32C/80 Group provides 16-Mbyte address space addressed from 00000016 to FFFFFF16.
The fixed interrupt vectors are allocated from address FFFFDC16 to FFFFFF16. It stores the starting address of each interrupt routine.
The internal RAM is allocated from address 00040016 to higher. For example, a 8-Kbyte internal RAM is
allocated from address 00040016 to 0023FF16. Besides storing data, it becomes stacks when the subroutine is called or an interrupt is acknowledged.
SFRs, consisting of control registers for peripheral functions such as I/O port, A/D converter, serial I/O,
timers, is allocated from address 00000016 to 0003FF16. All blank spaces within SFRs are reserved and
cannot be accessed by users.
The special page vector table is addressed from FFFE0016 to FFFFDB16. It is used for the JMPS instruction and JSRS instruction. Refer to the Renesas publication M32C/80 Series Software Manual for details.
In microprocessor mode, some spaces are reserved and cannot be accessed by users.
00000016
SFRs
00040016
0023FF16
Internal RAM
Reserved Space
FFFE00 16
01000016
Special Page
Vector Table
FFFFDC 16
Undefined Instruction
Overflow
BRK Instruction
Address Match
External Space
Watchdog Timer(1)
FFFFFF16
FFFFFF 16
NMI
Reset
NOTE:
1. Watchdog timer interrupt and oscillation stop detection interrupt share vectors.
Figure 3.1 Memory Map
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4. Special Function Registers (SFRs)
M32C/80 Group
4. Special Function Registers (SFRs)
Address
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
Register
Symbol
Value after RESET
Processor Mode Register(1)
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
PM0
PM1
CM0
CM1
0000 00112(CNVss pin ="H")
0016
0000 10002
0010 00002
Address Match Interrupt Enable Register
Protect Register
AIER
PRCR
0016
XXXX 00002
XXXX 10002(BYTE pin ="L")
000B16
External Data Bus Width Control Register
DS
000C16
000D16
000E16
000F16
001016
001116
Main Clock Division Register
Oscillation Stop Detection Register
Watchdog Timer Start Register
Watchdog Timer Control Register
MCD
CM2
WDTS
WDC
XXXX 00002(BYTE pin ="H")
XXX0 10002
0016
XX16
000X XXXX2
Address Match Interrupt Register 0
RMAD0
00000016
Processor Mode Register 2
PM2
0016
001216
001316
001416
001516
Address Match Interrupt Register 1
RMAD1
00000016
001616
001716
001816
001916
Address Match Interrupt Register 2
RMAD2
00000016
001A16
001B16
001C16
001D16
Address Match Interrupt Register 3
RMAD3
00000016
PLL Control Register 0
PLL Control Register 1
PLC0
PLC1
0001 X0102
000X 00002
Address Match Interrupt Register 4
RMAD4
00000016
Address Match Interrupt Register 5
RMAD5
00000016
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTE:
1. The PM01 and PM00 bits in the PM0 register maintain values set before reset, even after software reset or watchdog timer reset has been performed.
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4. Special Function Registers (SFRs)
M32C/80 Group
Address
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
Register
Symbol
Value after RESET
Address Match Interrupt Register 6
RMAD6
00000016
Address Match Interrupt Register 7
RMAD7
00000016
External Space Wait Control Register 0
External Space Wait Control Register 1
External Space Wait Control Register 2
External Space Wait Control Register 3
EWCR0
EWCR1
EWCR2
EWCR3
X0X0 00112
X0X0 00112
X0X0 00112
X0X0 00112
X: Indeterminate
Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
M32C/80 Group
Address
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
008016
008116
008216
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
Register
Symbol
Value after RESET
DMA0 Interrupt Control Register
Timer B5 Interrupt Control Register
DMA2 Interrupt Control Register
UART2 Receive /ACK Interrupt Control Register
Timer A0 Interrupt Control Register
UART3 Receive /ACK Interrupt Control Register
Timer A2 Interrupt Control Register
UART4 Receive /ACK Interrupt Control Register
Timer A4 Interrupt Control Register
UART0/UART3 Bus Conflict Detect Interrupt Control Register
DM0IC
TB5IC
DM2IC
S2RIC
TA0IC
S3RIC
TA2IC
S4RIC
TA4IC
BCN0IC/BCN3IC
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
UART0 Receive/ACK Interrupt Control Register
A/D0 Conversion Interrupt Control Register
UART1 Receive/ACK Interrupt Control Register
Intelligent I/O Interrupt Control Register 0
Timer B1 Interrupt Control Register
Intelligent I/O Interrupt Control Register 2
Timer B3 Interrupt Control Register
Intelligent I/O Interrupt Control Register 4
INT5 Interrupt Control Register
S0RIC
AD0IC
S1RIC
IIO0IC
TB1IC
IIO2IC
TB3IC
IIO4IC
INT5IC
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XX00 X0002
INT3 Interrupt Control Register
INT3IC
XX00 X0002
INT1 Interrupt Control Register
INT1IC
XX00 X0002
DMA1 Interrupt Control Register
UART2 Transmit /NACK Interrupt Control Register
DMA3 Interrupt Control Register
UART3 Transmit /NACK Interrupt Control Register
Timer A1 Interrupt Control Register
UART4 Transmit /NACK Interrupt Control Register
Timer A3 Interrupt Control Register
UART2 Bus Conflict Detect Interrupt Control Register
DM1IC
S2TIC
DM3IC
S3TIC
TA1IC
S4TIC
TA3IC
BCN2IC
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
X: Indeterminate
Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
M32C/80 Group
Address
009016
009116
009216
009316
009416
009516
009616
009716
009816
009916
009A16
009B16
009C16
009D16
009E16
009F16
00A016
00A116
00A216
00A316
00A416
00A516
00A616
00A716
00A816
00A916
00AA16
00AB16
00AC16
00AD16
00AE16
00AF16
00B016
00B116
00B216
00B316
00B416
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
00BC16
00BD16
00BE16
00BF16
Register
UART0 Transmit /NACK Interrupt Control Register
UART1/UART4 Bus Conflict Detect Interrupt Control Register
UART1 Transmit/NACK Interrupt Control Register
Key Input Interrupt Control Register
Timer B0 Interrupt Control Register
Intelligent I/O Interrupt Control Register 1
Timer B2 Interrupt Control Register
Intelligent I/O Interrupt Control Register 3
Timer B4 Interrupt Control Register
Symbol
S0TIC
BCN1IC/BCN4IC
S1TIC
KUPIC
TB0IC
IIO1IC
TB2IC
IIO3IC
TB4IC
Value after RESET
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
INT4 Interrupt Control Register
INT4IC
XX00 X0002
INT2 Interrupt Control Register
INT2IC
XX00 X0002
INT0 Interrupt Control Register
Exit Priority Control Register
Interrupt Request Register 0
Interrupt Request Register 1
Interrupt Request Register 2
Interrupt Request Register 3
Interrupt Request Register 4
INT0IC
RLVL
IIO0IR
IIO1IR
IIO2IR
IIO3IR
IIO4IR
XX00 X0002
XXXX 00002
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Enable Register 2
Interrupt Enable Register 3
Interrupt Enable Register 4
IIO0IE
IIO1IE
IIO2IE
IIO3IE
IIO4IE
0016
0016
0016
0016
0016
X: Indeterminate
Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
M32C/80 Group
Address
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
Register
Symbol
Value after RESET
SI/O Receive Buffer Register 0
G0RB
Transmit Buffer/Receive Data Register 0
G0TB/G0DR
XXXX XXXX2
XXX0 XXXX2
XX16
Receive Input Register 0
SI/O Communication Mode Register 0
Transmit Output Register 0
SI/O Communication Control Register 0
G0RI
G0MR
G0TO
G0CR
XX16
0016
XX16
0000 X0112
X: Indeterminate
Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
M32C/80 Group
Address
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
010016
010116
010216
010316
010416
010516
010616
010716
010816
010916
010A16
010B16
010C16
010D16
010E16
010F16
011016
011116
011216
011316
011416
011516
011616
011716
011816
011916
011A16
011B16
011C16
011D16
011E16
011F16
Register
Data Compare Register 00
Data Compare Register 01
Data Compare Register 02
Data Compare Register 03
Data Mask Register 00
Data Mask Register 01
Communication Clock Select Register
Symbol
G0CMP0
G0CMP1
G0CMP2
G0CMP3
G0MSK0
G0MSK1
CCS
Receive CRC Code Register 0
G0RCRC
Transmit CRC Code Register 0
G0TCRC
SI/O Expansion Mode Register 0
SI/O Expansion Receive Control Register 0
SI/O Special Communication Interrupt Detect Register 0
SI/O Expansion Transmit Control Register 0
G0EMR
G0ERC
G0IRF
G0ETC
Value after RESET
XX16
XX16
XX16
XX16
XX16
XX16
XXXX 00002
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
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XX16
0016
0016
0016
0016
0016
0000 0XXX2
4. Special Function Registers (SFRs)
M32C/80 Group
Address
012016
012116
012216
012316
012416
012516
012616
012716
012816
012916
012A16
012B16
012C16
012D16
012E16
012F16
013016
013116
013216
013316
013416
013516
013616
013716
013816
013916
013A16
013B16
013C16
013D16
013E16
013F16
014016
014116
014216
014316
014416
014516
014616
014716
014816
014916
014A16
014B16
014C16
014D16
to
02AF16
Register
Symbol
Value after RESET
XXXX XXXX2
SI/O Receive Buffer Register 1
G1RB
Transmit Buffer/Receive Data Register 1
G1TB/G1DR
XXX0 XXXX2
XX16
Receive Input Register 1
SI/O Communication Mode Register 1
Transmit Output Register 1
SI/O Communication Control Register 1
Data Compare Register 10
Data Compare Register 11
Data Compare Register 12
Data Compare Register 13
Data Mask Register 10
Data Mask Register 11
G1RI
G1MR
G1TO
G1CR
G1CMP0
G1CMP1
G1CMP2
G1CMP3
G1MSK0
G1MSK1
XX16
0016
XX16
0000 X0112
XX16
XX16
XX16
XX16
XX16
XX16
Receive CRC Code Register 1
G1RCRC
Transmit CRC Code Register 1
G1TCRC
SI/O Expansion Mode Register 1
SI/O Expansion Receive Control Register 1
SI/O Special Communication Interrupt Detection Register 1
SI/O Expansion Transmit Control Register 1
G1EMR
G1ERC
G1IRF
G1ETC
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
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XX16
0016
0016
0016
0016
0016
0000 0XXX2
4. Special Function Registers (SFRs)
M32C/80 Group
Address
02B116
02B216
02B316
02B416
02B516
02B616
02B716
02B816
02B916
02BA16
02BB16
02BC16
02BD16
02BE16
02BF16
02C016
02C116
02C216
02C316
02C416
02C516
02C616
02C716
02C816
02C916
02CA16
02CB16
02CC16
02CD16
02CE16
02CF16
02D016
02D116
02D216
02D316
02D416
02D516
02D616
02D716
02D816
02D916
02DA16
02DB16
02DC16
02DD16
02DE16
02DF16
Register
Symbol
Value after RESET
XX16
X0 Register Y0 Register
X0R,Y0R
X1 Register Y1 Register
X1R,Y1R
X2 Register Y2 Register
X2R,Y2R
X3 Register Y3 Register
X3R,Y3R
X4 Register Y4 Register
X4R,Y4R
X5 Register Y5 Register
X5R,Y5R
X6 Register Y6 Register
X6R,Y6R
X7 Register Y7 Register
X7R,Y7R
X8 Register Y8 Register
X8R,Y8R
X9 Register Y9 Register
X9R,Y9R
X10 Register Y10 Register
X10R,Y10R
X11 Register Y11 Register
X11R,Y11R
X12 Register Y12 Register
X12R,Y12R
X13 Register Y13 Register
X13R,Y13R
X14 Register Y14 Register
X14R,Y14R
X15 Register Y15 Register
X15R,Y15R
X: Indeterminate
Blank spaces are reserved. No access is allowed.
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XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
4. Special Function Registers (SFRs)
M32C/80 Group
Address
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
X/Y Control Register
Register
Symbol
XYC
Value after RESET
XXXX XX002
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
U1SMR4
U1SMR3
U1SMR2
U1SMR
U1MR
U1BRG
0016
0016
0016
0016
0016
XX16
XX16
UART1 Transmit Buffer Register
02EB16
02EC16 UART1 Transmit/Receive Control Register 0
02ED16 UART1 Transmit/Receive Control Register 1
02EE16
UART1 Receive Buffer Register
02EF16
02F016
02F116
02F216
02F316
02F416 UART4 Special Mode Register 4
02F516 UART4 Special Mode Register 3
02F616 UART4 Special Mode Register 2
02F716 UART4 Special Mode Register
02F816 UART4 Transmit/Receive Mode Register
02F916 UART4 Bit Rate Register
02FA16
UART4 Transmit Buffer Register
02FB16
02FC16 UART4 Transmit/Receive Control Register 0
02FD16 UART4 Transmit/Receive Control Register 1
02FE16
UART4 Receive Buffer Register
02FF16
030016 Timer B3, B4, B5 Count Start Flag
030116
030216
Timer A1-1 Register
030316
030416
Timer A2-1 Register
030516
030616
Timer A4-1 Register
030716
030816 Three-Phase PWM Control Register 0
030916 Three-Phase PWM Control Register 1
030A16 Three-Phase Output Buffer Register 0
030B16 Three-Phase Output Buffer Register 1
030C16 Dead Time Timer
030D16 Timer B2 Interrupt Generation Frequency Set Counter
030E16
030F16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
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U1TB
U1C0
U1C1
U1RB
U4SMR4
U4SMR3
U4SMR2
U4SMR
U4MR
U4BRG
U4TB
U4C0
U4C1
U4RB
TBSR
XX16
0000 10002
0000 00102
XX16
XX16
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
000X XXXX2
XX16
TA11
TA21
TA41
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
XX16
XX16
XX16
XX16
XX16
0016
0016
XX11 11112
XX11 11112
XX16
XX16
4. Special Function Registers (SFRs)
M32C/80 Group
Address
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
Register
Symbol
Value after RESET
XX16
Timer B3 Register
TB3
Timer B4 Register
TB4
Timer B5 Register
TB5
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
TB3MR
TB4MR
TB5MR
00XX 00002
00XX 00002
00XX 00002
External Interrupt Request Source Select Register
IFSR
0016
UART3 Special Mode Register 4
UART3 Special Mode Register 3
UART3 Special Mode Register 2
UART3 Special Mode Register
UART3 Transmit/Receive Mode Register
UART3 Bit Rate Register
U3SMR4
U3SMR3
U3SMR2
U3SMR
U3MR
U3BRG
UART3 Transmit Buffer Register
U3TB
UART3 Transmit/Receive Control Register 0
UART3 Transmit/Receive Control Register 1
U3C0
U3C1
UART3 Receive Buffer Register
U3RB
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
UART2 Transmit Buffer Register
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
U2C0
U2C1
UART2 Receive Buffer Register
U2RB
X: Indeterminate
Blank spaces are reserved. No access is allowed.
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XX16
XX16
XX16
XX16
XX16
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
4. Special Function Registers (SFRs)
M32C/80 Group
Address
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
Register
Count Start Flag
Clock Prescaler Reset Flag
One-Shot Start Flag
Trigger Select Register
Up/Down Flag
Symbol
TABSR
CPSRF
ONSF
TRGSR
UDF
Timer A0 Register
TA0
Timer A1 Register
TA1
Timer A2 Register
TA2
Timer A3 Register
TA3
Timer A4 Register
TA4
Timer B0 Register
TB0
Timer B1 Register
TB1
Timer B2 Register
TB2
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
Count Source Prescaler Register(1)
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
TCSPR
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
U0SMR4
U0SMR3
U0SMR2
U0SMR
U0MR
U0BRG
UART0 Transmit Buffer Register
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
U0C0
U0C1
UART0 Receive Buffer Register
U0RB
Value after RESET
0016
0XXX XXXX2
0016
0016
0016
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
0016
0016
0016
0016
0016
00XX 00002
00XX 00002
00XX 00002
XXXX XXX02
0XXX 00002
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTE:
1. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has
been performed.
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4. Special Function Registers (SFRs)
M32C/80 Group
Address
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
Register
Symbol
Value after RESET
DMA0 Request Source Select Register
DMA1 Request Source Select Register
DMA2 Request Source Select Register
DMA3 Request Source Select Register
DM0SL
DM1SL
DM2SL
DM3SL
CRC Data Register
CRCD
CRC Input Register
CRCIN
A/D0 Register 0
AD00
A/D0 Register 1
AD01
A/D0 Register 2
AD02
A/D0 Register 3
AD03
A/D0 Register 4
AD04
A/D0 Register 5
AD05
A/D0 Register 6
AD06
A/D0 Register 7
AD07
A/D0 Control Register 2
A/D0 Control Register 3
A/D0 Control Register 0
A/D0 Control Register 1
D/A Register 0
AD0CON2
AD0CON3
AD0CON0
AD0CON1
DA0
XX0X X0002
XXXX X0002
0016
0016
XX16
D/A Register 1
DA1
XX16
D/A Control Register
DACON
XXXX XX002
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.00 Nov. 01, 2005 Page 27
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0X00 00002
0X00 00002
0X00 00002
0X00 00002
XX16
XX16
XX16
XXXX XXXX2
0000 00002
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
4. Special Function Registers (SFRs)
M32C/80 Group
Address
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
Register
Symbol
Value after RESET
Function Select Register D1
PSD1
X0XX XX002
Function Select Register C3
PSC3
X0XX XXXX2
Function Select Register C
Function Select Register A0
Function Select Register A1
Function Select Register B0
Function Select Register B1
Function Select Register A2
Function Select Register A3
Function Select Register B2
Function Select Register B3
PSC
PS0
PS1
PSL0
PSL1
PS2
PS3
PSL2
PSL3
00X0 00002
0016
0016
0016
0016
00X0 00002
0016
00X0 00002
0016
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
XX16
XX16
0016
0016
XX16
XX16
00X0 00002
0016
XX16
Port P10 Direction Register
PD10
0016
X: Indeterminate
Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
M32C/80 Group
Address
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Register
Symbol
Value after RESET
Pull-Up Control Register 2
Pull-Up Control Register 3
PUR2
PUR3
0016
0016
Port P0 Register(1)
Port P1 Register(1)
P0
P1
XX16
XX16
Port P0 Direction Register(1)
Port P1 Direction Register(1)
Port P2 Register(1)
Port P3 Register(1)
Port P2 Direction Register(1)
Port P3 Direction Register(1)
Port P4 Register(1)
Port P5 Register(1)
Port P4 Direction Register(1)
Port P5 Direction Register(1)
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
0016
0016
XX16
XX16
0016
0016
XX16
XX16
0016
0016
Pull-up Control Register 0
Pull-up Control Register 1
PUR0
PUR1
0016
XXXX 00002
Port Control Register
PCR
XXXX XXX02
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTE:
1. Pins, functioning as bus control pins, cannot be selected as I/O ports.
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5. Reset
M32C/80 Group
5. Reset
Hardware reset 1, software reset, and watchdog timer reset are available to reset the microcomputer.
5.1 Hardware Reset 1
____________
Pins, the CPU and SFRs are reset by setting the RESET pin. If the supply voltage meets the recommended
___________
operating conditions, all pins are reset when a low-level ("L") signal is applied to the RESET pin (see Table
5.1). The oscillation circuit is also reset and the main clock starts oscillating. The CPU and SFR are reset
____________
when the signal applied to the RESET pin changes "L" to high level ("H"). The microcomputer executes the
program in an address indicated by the reset vector. The internal RAM is not reset. When an "L" signal is
____________
applied to the RESET pin while writing data to the internal RAM, the internal RAM is in an indeterminate
state.
Figure 5.1 shows an example of the reset circuit. Figure 5.2 shows a reset sequence. Table 5.1 lists pin
____________
states while the RESET pin is held "L".
5.1.1 Reset on a Stable Supply Voltage
____________
(1) Apply an "L" signal to the RESET pin
(2) Provide 20 or more clock cycle inputs into the XIN pin
____________
(3) Apply an "H" signal to the RESET pin
5.1.2 Power-on Reset
____________
(1) Apply an "L" signal to the RESET pin
(2) Raise the supply voltage to the recommended operating level
(3) Insert td(P-R) ms as wait time for the internal voltage to stabilize
(4) Provide 20 or more clock cycle inputs into the XIN pin
____________
(5) Apply an "H" signal to the RESET pin
Recommended
operating voltage
VCC1
0V
RESET
VCC1
RESET
0.2VCC1
or below
0.2VCC1 or below
0V
td(P-R) + 20 or more clock cycle
inputs provided into the XIN pin
NOTE:
1. If VCC1>VCC2, the VCC2 voltage must be lower than that of VCC1 when the power is
being turned on or off.
Figure 5.1 Reset Circuit
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5. Reset
M32C/80 Group
VCC1, VCC2
XIN
XIN
td(P-R) ms or more
is equired
20 or more cycles
are required
RESET
40 to 45 BCLK cycles
BCLK
Microprocessor Mode
BYTE="H"
Content of reset vector
Address
FFFFFC16
FFFFFD16
FFFFFE16
FFFFFF16
A23
RD
WR
Microprocessor Mode
BYTE="L"
Content of reset vector
Address
FFFFFC16
A23
RD
WR
Figure 5.2 Reset Sequence
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FFFFFE16
5. Reset
M32C/80 Group
____________
Table 5.1 Pin States while RESET Pin is Held "L"
Pin States(1)
Pin Name
CNVSS=VSS
P0
P1
P2, P3, P4
P50
P51
P52
P53
P54
Input port (high-impedance)
Input port (high-impedance)
Input port (high-impedance)
Input port (high-impedance)
Input port (high-impedance)
Input port (high-impedance)
Input port (high-impedance)
Input port (high-impedance)
CNVSS=VCC
BYTE=VSS
BYTE=VCC
Inputs data (high-impedance)
Inputs data (high-impedance)
Input port (high-impedance)
Output addresses (indeterminate)
______
Outputs the WR signal ("H")(2)
________
Outputs the BHE signal (indeterminate)
_____
Outputs the RD signal ("H")(2)
Outputs the BCLK(2)
_________
Outputs the HLDA signal (Output signal depends on an input
__________
signal to the HOLD pin)(2)
__________
Inputs the HOLD signal (high-impedance)
Outputs an "H" signal(2)
________
Inputs the RDY signal (high-impedance)
Input port (high-impedance)
P55
Input port (high-impedance)
P56
Input port (high-impedance)
P57
Input port (high-impedance)
P6 to P10 Input port (high-impedance)
NOTES:
1. The availability of pull-up resistors is indeterminate until internal supply voltage stabilizes.
2. Each port is in this state after power is on and internal supply voltage stabilizes, but in an indeterminate
state until internal supply voltage stabilizes.
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5. Reset
M32C/80 Group
5.2 Software Reset
Pins, the CPU and SFRs are reset when the PM03 bit in the PM0 register is set to "1" (microcomputer
reset). Then the microcomputer executes the program in an address determined by the reset vector.
Set the PM03 bit to "1" while the main clock is selected as the CPU clock and the main clock oscillation is
stable.
In the software reset, the microcomputer does not reset a part of SFR. Refer to 4. Special Function
Registers (SFRs) for details. Processor mode remains unchanged since the PM01 and PM00 bits in the
PM0 register are not reset.
5.3 Watchdog Timer Reset
Pins, the CPU and SFRs are reset when the CM06 bit in the CM0 register is set to "1" (reset) and the
watchdog timer underflows. Then the microcomputer executes the program in an address determined by
the reset vector.
In the watchdog timer reset, the microcomputer does not reset a part of the SFR. Refer to 4. Special
Function Registers (SFRs) for details. Processor mode remains unchanged since the PM01 and PM00
bits in the PM0 register are not reset.
5.4 Internal Space
Figure 5.3 shows CPU register states after reset. Refer to 4. Special Function Registers (SFRs) for SFR
states after reset.
0 : "0" after reset
X : Indeterminate after reset
General Registers
High-speed Interrupt Registers
b15
b15
b0
Flag Register (FLG)
b15
b8 b7
b0
X 0 0 0 X X X X 0 0 0 0 0 0 0 0
IPL
U I O B S Z D C
b0
XXXX16
b23
Flag Save Register (SVF)
XXXXXX16
PC Save Register (SVP)
XXXXXX16
Vector Register (VCT)
DMAC-associated Registers
b0
b7
0016
0016
Data Register (R0H/R0L)
0016
0016
Data Register (R1H/R1L)
b15
b0
0016
DMA Mode Register (DMD0)
0016
DMA Mode Register (DMD1)
000016
Data Register (R2)
XXXX16
DMA Transfer Count Register (DCT0)
000016
Data Register (R3)
XXXX16
DMA Transfer Count Register (DCT1)
00000016
Address Register (A0)
XXXX16
DMA Transfer Count Reload Register (DRC0)
00000016
Address Register (A1)
XXXX16
DMA Transfer Count Reload Register (DRC1)
00000016
Static Base Register (SB)
XXXXXX16
DMA Memory Address Register (DMA0)
00000016
Frame Base Register (FB)
XXXXXX16
DMA Memory Address Register (DMA1)
XXXXXX16
DMA Memory Address Reload Register (DRA0)
XXXXXX16
DMA Memory Address Reload Register (DRA1)
XXXXXX16
DMA SFR Address Register (DSA0)
XXXXXX16
DMA SFR Address Register (DSA1)
b23
00000016
User Stack Pointer (USP)
00000016
Interrupt Stack Pointer (ISP)
00000016
Contents of addresses
Interrupt Table Register (INTB)
Program Counter (PC)
FFFFFE16 to FFFFFC16
Figure 5.3 CPU Register States after Reset
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b23
6. Processor Mode
M32C/80 Group
6. Processor Mode
NOTE
The M32C/80 Group is ROMless device. Connect the CNVSS pin to VCC1.
Use the M32C/80 Group in microprocessor mode after reset.
6.1 Types of Processor Mode
Single-chip mode, memory expansion mode, or microprocessor mode can be selected as a processor
mode. Table 6.1 lists a feature of the processor mode.
Table 6.1 Processor Mode Feature
Processor Mode
Accessable Space
Pin Status as I/O Ports
Single-chip Mode
SFRs, Internal RAM
All pins assigned to I/O ports or to I/O pins
for the peripheral functions
Memory Expansion Mode
SFRs, Internal RAM, External Space(1)
Some pins assigned to bus control pins(1)
Microprocessor Mode
SFRs, Internal RAM, External Space(1)
Some pins assigned to bus control pins(1)
NOTE:
1. Refer to 7. Bus for details.
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6. Processor Mode
M32C/80 Group
6.2 Setting of Processor Mode
The CNVSS pin state and the PM01 and PM00 bit settings in the PM0 register determine which processor
mode is selected. Table 6.2 lists processor mode after hardware reset. Table 6.3 lists processor mode
selected by PM01 and PM00 bit settings.
Table 6.2 Processor Mode after Hardware Reset
Input Level into the CNVSS pin
Processor Mode
VCC1(1)
Microprocessor Mode
NOTE:
1. Multiplex bus cannot be assigned to all CS areas.
Table 6.3 Processor Mode Selected by the PM01 and PM00 bit Settings
PM01 and PM00 Bits
Processor Mode
002
Single-chip Mode
012
Memory Expansion Mode
102
Do not set to this value
112
Microprocessor Mode
If the PM01 and PM00 bits are rewritten, the PM01 and PM00 bits select a mode regardless of CNVSS pin
level.
Do not change the PM01 and PM00 bits to "012" (memory expansion mode) or "112" (microprocessor
mode) when the PM07 to PM02 bits in the PM0 register are being rewritten.
Figures 6.1 and 6.2 show the PM0 register and PM1 register. Figure 6.3 shows a memory map in each
processor mode.
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6. Processor Mode
M32C/80 Group
Processor Mode Register 0(1)
b7
b6
b5
b4
b3
b2
0
b1
b0
Symbol
PM0
Bit
Symbol
Address
000416
After Reset
0000 00112
Bit Name
Function
RW
b1 b0
PM00
Processor Mode
Bit(2, 3)
PM01
0 0: Single-chip mode
0 1: Memory expansion mode(8)
1 0: Do not set to this value
1 1: Microprocessor mode(8)
RW
RW
PM02
R/W Mode Select Bit
0: RD/BHE/WR
1: RD/WRH/WRL
RW
PM03
Software Reset Bit
The microcomputer is reset when
this bit is set to "1". When read, its
content is "0".
RW
Multiplexed Bus Space
Select Bit(4)
0 0: Multiplexed bus is not used
0 1: Access the CS2 area using the bus
1 0: Access the CS1 area using the bus
1 1: Access all CS areas using the bus(5)
RW
Reserved Bit
Set to "0"
RW
BCLK Output
Disable Bit(6)
0: BCLK is output(7)
1: BCLK is not output
RW
The CM01 and CM00 bits in the
CM0 register determine pin functions
b5 b4
PM04
PM05
(b6)
PM07
RW
NOTES:
1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1"(write enabled).
2. The PM01 and PM00 bits maintain values set before reset, even after software reset or watchdog
timer reset has performed.
3. Do not change the PM01 and PM00 bits to "012" and "112" when the PM07 to PM02 bits are being
rewritten. Set PM07 to PM02 bits, then the PM01 and PM00 bits.
4. The PM04 and PM05 bits are available in memory expansion mode or microprocessor mode.
• Set the PM05 and PM04 bits to "002" in mode 0.
• Do not set the PM05 and PM04 bits to "012" in mode 2.
5. The PM05 and PM04 bits cannot be set to "112" in microprocessor mode since the microcomputer
starts up with separate bus after reset.
When the PM05 and PM04 bits are set to "112" in memory expansion mode, the microcomputer can
access each 64-Kbyte chip-select-assigned address space. The multiplexed bus is not available in
mode 0. The microcomputer accesses the CS0 to CS2 in mode 1, CS0 and CS1 in mode 2 and
CS0 to CS3 in mode 3.
6. No BCLK is output in single-chip mode even if the PM07 bit is set to "0". When a clock output is
terminated in microprocessor mode or memory expansion mode, set the PM07 bit to "1" and the
CM01 and CM00 bits in the CM0 register to "002" (I/O port P53). P53 outputs "L".
7. When the PM07 bit is set to "0" (BCLK output), set the CM01 and CM00 bits to "002".
Figure 6.1 PM0 Register
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6. Processor Mode
M32C/80 Group
Processor Mode Register 1(1)
b7
b6
0
0
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
PM1
000516
0016
Bit
Symbol
Bit Name
Function
RW
b1 b0
PM10
PM11
0 0: Mode 0 (A20 to A23 for P44 to P47)
RW
0 1: Mode 1 (A20 for P44,
CS2 to CS0 for P45 to P47)
External Memory Space
1 0: Mode 2 (A20, A21 for P44, P45,
Mode Bit(2, 4)
CS1, CS0 for P46, P47)
RW
1 1: Mode 3
(CS3 to CS0 for P44 to P47)
PM12
Internal Memory
Wait Bit
0: No wait state
1: Wait state
RW
PM13
SFR Area Wait Bit
0: 1 wait state
1: 2 Wait states
RW
b5 b4
PM14
ALE Pin Select Bit(2, 4)
PM15
Reserved Bit
(b7-b6)
0 0: No ALE
0 1: P53/BCLK(3)
1 0: P56
1 1: P54/HLDA
RW
Set to "0"
RW
RW
NOTES:
1. Rewrite the PM1 register after the PRC1 bit in the PRCR register is set to "1" (write enabled).
2. The PM15 and PM14 bit setting, PM11 and PM10 bit setting are enabled in memory expansion mode
or microprocessor mode.
3. Set the CM01 and CM00 bits in the CM0 register to "002" (I/O port P53) when the PM15 and PM14
bits are set to "012" (P53/BCLK selected).
Figure 6.2 PM1 Register
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Figure 6.3 Memory Map in Each Processor Mode
FFFFFF 16
F0000016
E0000016
D0000016
C0000016
40000016
30000016
20000016
10000016
01000016
00040016
00000016
Reserved Space
External Space 3
External Space 2
External Space 1
Reserved Space
Not Used
CS0
2 Mbytes
External Space 3
External Space 2
CS2
2 Mbytes
External Space 1
CS1
2 Mbytes(1)
External Space0
Reserved Space
SFRs
Internal RAM
Mode 1
Reserved Space
CS0
3 Mbytes
External Space 3
External Space 2
CS1
4 Mbytes(2)
External Space 0
Reserved Space
SFRs
Internal RAM
Mode 2
Mode 3
External Space 3
External Space 2
External Space 1
External Space 0
Reserved Space
SFRs
Internal RAM
Mode 0
CS0
2 Mbytes
External Space 3
Not Used
External Space 2
CS2
2 Mbytes
External Space 1
CS1
2 Mbytes(1)
External Space 0
Reserved Space
SFRs
Internal RAM
Mode 1
CS0
4 Mbytes
External Space 3
External Space 2
CS1
4 Mbytes(2)
External Space 0
Reserved Space
SFRs
Internal RAM
Mode 2
Microprocessor Mode
NOTES:
1. 20000016 - 01000016=1984 Kbytes. 64K bytes less than 2 Mbytes.
2. 40000016 - 01000016=4032 Kbytes. 64K bytes less than 4 Mbytes.
Reserved Space
CS0 1 Mbyte
External Space 3
Not Used
CS3 1 Mbyte
External Space 2
Not Used
CS2 1 Mbyte
External Space 1
CS1 1 Mbyte
External Space 0
Not Used
Reserved Space
SFRs
Internal RAM
Memory Expansion Mode
The EWCRi register (i=0 to 3) can determine how many wait states are
inserted for each space CS0 to CS3.
Reserved Space
Not Used
Reserved Space
Reserved Space
External Space 0
SFRs
Internal RAM
Mode 0
Internal RAM
SFRs
Single-Chip
Mode
CS0 1 Mbyte
External Space 3
Not Used
CS3 1 Mbyte
External Space 2
Not Used
CS2 1 Mbyte
External Space 1
CS1 1 Mbyte
External Space 0
Not Used
Reserved Space
SFRs
Internal RAM
Mode 3
M32C/80 Group
6. Processor Mode
7. Bus
M32C/80 Group
7. Bus
In memory expansion mode or microprocessor mode, some pins function as bus control pins to control the
_____
______
______ _________ ______ _________ _______ _____
address bus and data bus. A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE,
_________
_________
_______
HLDA/ALE, HOLD, ALE, RDY are used as bus control pins.
7.1 Bus Settings
The BYTE pin, the DS register, the PM05 and PM04 bits in the PM0 register, and the PM11 and PM10 bits
in the PM1 register determine bus settings.
Table 7.1 lists how to change bus settings. Figure 7.1 shows the DS register.
Table 7.1 Bus Settings
Bus Setting
Selecting External Address Bus Width
Setting Bus Width after Reset
Selecting Between Separate Bus or Multiplexed Bus
Number of Chip-select
Changed By
DS register
BYTE pin (external space 3 only)
PM05 and PM04 bits in PM0 register
PM11 and PM10 bits in PM1 register
External Data Bus Width Control Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DS
Bit
Symbol
Address
000B16
Bit Name
After Reset
XXXX 10002 (BYTE pin = "L")
XXXX 00002 (BYTE pin = "H")
Function
RW
DS0
External Space 0 Data
Bus Width Select Bit
0: 8 bits wide
1: 16 bits wide
RW
DS1
External Space 1 Data
Bus Width Select Bit
0: 8 bits wide
1: 16 bits wide
RW
DS2
External Space 2 Data
Bus Width Select Bit
0: 8 bits wide
1: 16 bits wide
RW
DS3
External Space 3 Data
Bus Width Select Bit
0: 8 bits wide
1: 16 bits wide
RW
Nothing is assigned. When write, set to "0".
(b7 - b4) When read, its content is indeterminate.
Figure 7.1 DS Register
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7. Bus
M32C/80 Group
7.1.1 Selecting External Address Bus
The number of externally-output address buses, the number of chip-select signals and chip-select-as_____
signed address space (CS area) vary depending on each external space mode. The PM11 and PM10
bits in the PM1 register determine the external space mode.
7.1.2 Selecting External Data Bus
The DS register selects either external 8-bit or 16-bit data bus per external space. The data bus in the
external space 3, after reset, becomes 16 bits wide when a low-level ("L") signal is applied to the BYTE
pin and 8 bits wide when a high-level ("H") signal is applied. Keep the BYTE pin input level while the
microcomputer is operating. Internal bus is always 16 bits wide.
7.1.3 Selecting Separate/Multiplexed Bus
The PM05 and PM04 bits in the PM0 register determine either separate or multiplexed bus as bus format.
7.1.3.1 Separate Bus
The separate bus is a bus format which allows the microcomputer to input and output data and address separatelly. The DS register selects 8-bit or 16-bit data bus as the external data bus per external space. If all DSi bits in the DS register (i=0 to 3) are set to "0" (8-bit data bus), port P0 becomes the
data bus and port P1, the programmable I/O port. If one of the DSi bits is set to "1" (16-bit data bus),
ports P0 and P1 become the data bus. Port P1 is indeterminate when the microcomputer accesses a
space where the DSi bit is set to "0".
The EWCRi register (i=0 to 3) determines the number of software wait states inserted, when the
microcomputer accesses space using the separate bus.
7.1.3.2 Multiplexed Bus
The multiplexed bus is a bus format which allow the microcomputer to input and output data and
address by timesharing. D0 to D7 are multiplexed with A0 to A7 in space accessed by the 8-bit data
bus. D0 to D15 are multiplexed with A0 to A15 in space accessed by the 16-bit data bus. The DSi bit
controls the data bus width. The EWCRi register (i=0 to 3) controls the number of software wait states
inserted, when the microcomputer accesses a space using the multiplexed bus. Refer to 7.2.4 Bus
Timing for details.
_______
_______
_____
The multiplexed bus can be assigned to access the CS1 area, CS2 area or all CS areas. However,
because the microcomputer starts operation using the separate bus after reset, the multiplexed bus
_____
cannot be assigned to access all CS areas in microprocessor mode. When the PM05 and PM04 bits
_____
in the PM0 register are set to "112" (access all CS areas with the bus), 16 low-order bits, from A0 to
A15, of an address are output. See Table 7.2 for details.
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7. Bus
M32C/80 Group
Table 7.2 Processor Mode and Port Function
Processor
Mode
SingleChip Mode
PM05 to
PM04 Bits in
PM0 Register
Memory Expansion Mode/ Microprocessor Mode
Memory Expansion Mode
"112"(1)
"012", "102"
"002"
Access CS1 or CS2 using
the Multiplexed Bus
Access All Other CS Areas using
the Separate Bus
Access all CS Areas using
the Separate Bus
Access all CS Areas using
the Multiplexed Bus
Access one or more
Access all
Access one or more
Access all
Access one or more
Access all
external space with external space with external space with external space with external space with external space with
16-bit data bus
8-bit data bus
16-bit data bus
8-bit data bus
16-bit data bus
8-bit data bus
Data Bus Width
Data bus
Data bus
Data bus
Data bus
D0 to D7
D0 to D7
D0 to D7
D0 to D7
I/O port
I/O port
I/O port
I/O port
Data bus
I/O port
Data bus
I/O port
I/O port
P20 to P27
I/O port
Address bus
Data bus(2)
A0/D0 to A7/D7
Address bus
Data bus(2)
A0/D0 to A7/D7
Address bus
A0 to A7
Address bus
A0 to A7
Address bus
Data bus
A0/D0 to A7/D7
Address bus
Data bus
A0/D0 to A7/D7
P30 to P37
I/O port
Address bus
A8 to A15
Address bus/
Data bus(2)
A8/D8 to A15/D15
Address bus
A8 to A15
Address bus
A8 to A15
Address bus
A8 to A15
Address bus/
Data bus
A8/D8 to A15/D15
P40 to P43
I/O port
Address bus
A16 to A19
Address bus
A16 to A19
Address bus
A16 to A19
P44 to P46
I/O port
CS (Chip-select signal) or Address bus (A20 to A22)
(Refer to 7.2 Bus Control for details)(4)
P47
I/O port
CS (Chip-select signal) or Address bus (A23)
(Refer to 7.2 Bus Control for details)(4)
P50 to P53
I/O port
Outputs RD, WRL, WRH and BCLK or outputs RD, BHE, WR and BCLK
(Refer to 7.2 Bus Control for details)(3)
P54
I/O port
HDLA (3)
HDLA (3)
HDLA (3)
HDLA (3)
HDLA (3)
HDLA (3)
P55
I/O port
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
P56
I/O port
ALE (3)
ALE (3)
ALE (3)
ALE (3)
ALE (3)
ALE (3)
P57
I/O port
RDY
RDY
RDY
RDY
RDY
RDY
P00 to P07
I/O port
P10 to P17
D8 to D15
D8 to D15
Address bus
A16 to A19
I/O port
I/O port
NOTES:
1. The PM05 and PM04 bits cannot be set to "112" (access all CS areas using multiplexed bus) in microprocessor mode
because the microcomputer starts operation using the separate bus after reset.
When the PM05 and PM04 bits are set to "112" in memory expansion mode, the microcomputer accesses 64-Kbyte
memory space per chip-select using the address bus .
2. These ports become address buses when accessing space using the separate bus.
3. The PM15 and PM14 bits in the PM1 register determines which pin outputs the ALE signal. The PM02 bit in the PM0
register selects either "WRL,WRH" or "BHE,WR" combination.
P56 provides an indeterminate output when the PM15 and PM14 bits to "002" (no ALE). It cannot be used as an I/O port.
4. The PM11 and PM10 bits in the PM1 register determine the CS signal and address bus.
Rev. 1.00 Nov. 01, 2005 Page 41 of 330
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7. Bus
M32C/80 Group
7.2 Bus Control
Signals, required to access external devices, are provided and software wait states are inserted as follows.
The signals are available in memory expansion mode and microprocessor mode only.
7.2.1 Address Bus and Data Bus
______
_____
Address bus is a signal accessing 16-Mbyte space and uses 24 control pins; A0 to A22 and A23. A23 is the
inversed output signal of the highest-order address bit.
Data bus is a signal for data input and output. The DS register selects an 8-bit data bus from D0 to D7 or
a 16-bit data bus from D0 to D15 for each external space. When applying a high-level ("H") signal to the
BYTE pin, the data bus accessing the external memory space 3 becomes an 8-bit data bus after reset.
When applying a low-level ("L") signal to the BYTE pin, the data bus accessing the external memory
space 3 becomes the 16-bit data bus.
When changing single-chip mode to memory expansion mode, the address bus is in an indeterminate
state until the microcomputer accesses an external memory space.
7.2.2 Chip-Select Signal
_____
Chip-select signal shares pins with A20 to A22 and A23. The PM11 and PM10 bits in the PM1 register
_____
determine which CS area is accessed and how many chip-select signals are output. A maximum of four
chip-select signals can be output.
______
In microprocessor mode, no chip-select signal, aside from A23 which can perform as a chip-select signal,
is output after reset.
______
The chip-select signal becomes "L" while the microcomputer is accessing the external CSi area (i=0 to 3).
It becomes "H" while the microcomputer is accessing other external memory space.
Figure 7.2 shows an example of the address bus and chip-select signal output.
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7. Bus
M32C/80 Group
Example 2:
Example 1:
When the microcomputer accesses the external
space j specified by another chip-select signal in the
next cycle after having accessed the external space i,
both address bus and chip-select signal change.
Access
External
Space i
Data Bus
Address Bus
When the microcomputer accesses SFRs or the
internal RAM area in the next cycle after having
accessed an external space, the chip-select signal
changes but the address bus does not.
Access
External
Space
Access
External
Space j
Data
Data
Data Bus
Data
Address Bus
Address
Chip-Select Signal
CSk
Access
SFRs,
Internal
RAM Area
Address
Chip-Select Signal
CSk
Chip-Select Signal
CSp
i = 0 to 3
k = 0 to 3
j = 0 to 3, excluding i
p= 0 to 3, excluding k
(See Figure 6.3 for i, j and p, k)
Example 3:
Example 4:
When the microcomputer accesses the space i
specified by the same chip-select signal in the next
cycle after having accessed the external space i,
the address bus changes but the chip-select signal
does not.
Access
External
Space i
Data Bus
Address Bus
k = 0 to 3
Access
External
Space i
Data
Address
Chip-Select Signal
CSk
i = 0 to 3
When the microcomputer does not access any
space in the next cycle after having accessed an
external space (no pre-fetch of an instruction is
generated), neither address bus nor chip-select
signal changes.
Data
Access
External
No Access
Space
Data
Data Bus
Address Bus
Address
Chip-Select Signal
CSk
k = 0 to 3
k = 0 to 3
(See Figure 6.3 for i and k)
NOTE:
1. The above applies to the address bus and chip-select signal in two consecutive cycles.
By combining these examples, a chip-select signal added by two or more cycles may be output.
Figure 7.2 Address Bus and Chip-Select Signal Outputs (Separate Bus)
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7. Bus
M32C/80 Group
7.2.3 Read and Write Signals
_____
______
When using a 16-bit data bus, the PM02 bit in the PM0 register selects a combination of the "RD, WR and
________
_____ ________
_________
BHE" signals or the "RD, WRL and WRH" signals to determine the read or write signal. When the DS3 to
_____ ______ ________
DS0 bits in the DS register are set to "0" (8-bit data bus), set the PM02 bit to "0" (RD/WR/BHE). When
any of the DS3 to DS0 bits are set to "1" (16-bit data bus) to access an 8-bit space, the combination of
_____ ______
________
"RD, WR and BHE" is automatically selected regardless of the PM02 bit setting. Tables 7.3 and 7.4 list
each signal operation.
_____ ______
________
The RD, WR and BHE signals are combined for the read or write signal after reset.
_____ ________
_________
When changing the combination of "RD, WRL and WRH", set the PM02 bit first to write data to an external
memory.
_____
________
_________
Table 7.3 RD, WRL and WRH Signals
Data Bus
RD
L
H
H
H
H
L
16 Bits
8 Bits
WRL
H
L
H
L
L(1)
H(1)
WRH
H
H
L
L
Not used
Not used
Status of External Data Bus
Read data
Write 1-byte data to even address
Write 1-byte data to odd address
Write data to both even and odd addresses
Write 1-byte data
Read 1-byte data
NOTE:
______
_______
1. The WR signal is used instead of the WRL signal.
_____
______
________
Table 7.4 RD, WR and BHE Signals
Data Bus
16 Bits
8 Bits
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REJ09B0271-0100
RD
H
L
H
L
H
L
H
L
WR
L
H
L
H
L
H
L
H
Page 44 of 330
BHE
L
L
H
H
L
L
Not used
Not used
A0
H
H
L
L
L
L
H/L
H/L
Status of External Data Bus
Write 1-byte data to odd address
Read 1-byte data from odd address
Write 1-byte data to even address
Read 1-byte data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1-byte data
Read 1-byte data
7. Bus
M32C/80 Group
7.2.4 Bus Timing
Bus cycle for the internal memory is basically one BCLK cycle. When the PM12 bit in the PM1 register is
set to "1" (wait state), the bus cycles are two BCLK cycles.
Bus cycles for SFRs are basically two BCLK cycles. When the PM13 bit in the PM1 register is set to "1"
(2 wait states), the bus cycles are three BCLK cycles.
Basic bus cycle for an external space is 2ø (1ø+1ø) to read and to write. Bus cycle is selected by the
EWCRi register (i=0 to 3) from 12 types of separate bus settings and 7 types of multiplexed bus settings.
If the EWCRi04 to EWCRi00 bits are set to "000112" (1ø+3ø), bus cycles are four BCLK cycles.
Figure 7.3 shows the EWCRi register. Figures 7.4 to 7.8 show bus timing in an external space.
External Space Wait Control Register i (i=0 to 3)(3)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
EWCR0 to EWCR3
Bit
Symbol
Address
004816, 004916, 004A16, 004B16
Bit Name
Function
b4 b3 b2 b1 b0
EWCRi00
EWCRi01
EWCRi02 Bus Cycle Select Bit
EWCRi03
EWCRi04
(b5)
EWCRi06
(b7)
After Reset
X0X0 00112
(1)
RW
(2)
0 0 0 0 1: 1φ + 1φ
0 0 0 1 0: 1φ + 2φ
0 0 0 1 1: 1φ + 3φ
0 0 1 0 0: 1φ + 4φ
0 0 1 0 1: 1φ + 5φ
0 0 1 1 0: 1φ + 6φ
0 1 0 1 0: 2φ + 2φ
0 1 0 1 1: 2φ + 3φ
0 1 1 0 0: 2φ + 4φ
0 1 1 0 1: 2φ + 5φ
1 0 0 1 1: 3φ + 3φ
1 0 1 0 0: 3φ + 4φ
1 0 1 0 1: 3φ + 5φ
1 0 1 1 0: 3φ + 6φ
Do not set values other than the above
RW
RW
RW
RW
RW
Nothing is assigned.
When read, its content is indeterminate.
0: Adds no recovery cycle when
Recovery Cycle Addition
accessing external space i
1: Adds a recovery cycle when
Select Bit
accessing external space i
RW
Nothing is assigned.
When read, its content is indeterminate.
NOTES:
1. The number of bus cycles from "when bus access begins" to "when RD or WR signal becomes "L".
2. The number of bus cycles from "when RD or WR signal becomes "L" to "when it becomes "H".
Figure 7.3 EWCR0 to EWCR3 Registers
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7. Bus
M32C/80 Group
Table 7.5 Software Wait State and Bus Cycle
PM1 Register
Space
External Bus
Status
EWCRi Register
(i=0 to 3)
Bus Cycles
PM13 Bit
PM12 Bit
EWCRi04 to
EWCRi00 Bits
---
---
0
SFRs
---
2 BCLK cycles
1
3 BCLK cycles
0
Internal RAM
---
---
1 BCLK cycles
--
1
Separate Bus
---
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Page 46 of 330
---
000012
2 BCLK cycles
000102
3 BCLK cycles
000112
4 BCLK cycles
001002
5 BCLK cycles
001012
6 BCLK cycles
001102
7 BCLK cycles
010102
4 BCLK cycles
010112
5 BCLK cycles
011002
6 BCLK cycles
100112
6 BCLK cycles
101002
7 BCLK cycles
101102
9 BCLK cycles
010102
4 BCLK cycles
010112
5 BCLK cycles
011012
7 BCLK cycles
100112
6 BCLK cycles
101002
7 BCLK cycles
101012
8 BCLK cycles
101102
9 BCLK cycles
---
External
Memory
Multiplexed Bus
2 BCLK cycles
---
7. Bus
M32C/80 Group
• Bus Cycle 1φ + 1φ
1 bus cycle = 2φ
• Bus Cycle 1φ + 2φ
BCLK
BCLK
Address
Address
(1)
CSi (1)
Data (Read)
Data (Read)
CSi
RD
RD
Data (Write)
Data (Write)
WR, WRL, WRH
WR, WRL, WRH
• Bus Cycle 1φ + 3φ
1 bus cycle = 4φ
• Bus Cycle 1φ + 4φ
BCLK
BCLK
Address
Address
(1)
CSi (1)
Data (Read)
Data (Read)
CSi
1 bus cycle = 3φ
RD
RD
Data (Write)
Data (Write)
WR, WRL, WRH
• Bus Cycle 1φ + 5φ
1 bus cycle = 5φ
WR, WRL, WRH
1 bus cycle = 6φ
• Bus Cycle 1φ + 6φ
BCLK
BCLK
Address
Address
CSi (1)
CSi (1)
Data (Read)
Data (Read)
RD
Data (Write)
WR, WRL, WRH
1 bus cycle = 7φ
RD
Data (Write)
WR, WRL, WRH
i=0 to 3
NOTE:
1. When the microcomputer continuously accesses the same CS area, the CSi pin outputs an "L" signal continuously.
Figure 7.4 Bus Cycle with Separate Bus (1)
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7. Bus
M32C/80 Group
• Bus Cycle 2φ + 2φ
1 bus cycle = 4φ
• Bus Cycle 2φ + 3φ
BCLK
BCLK
Address
Address
CSi (1)
CSi (1)
Data (Read)
Data (Read)
RD
1 bus cycle = 5φ
RD
Data (Write)
Data (Write)
WR, WRL, WRH
WR, WRL, WRH
• Bus Cycle 2φ + 4φ
1 bus cycle = 6φ
BCLK
Address
CSi (1)
Data (Read)
RD
Data (Write)
WR, WRL, WRH
i=0 to 3
NOTE:
1. When the microcomputer continuously accesses the same CS area, the CSi pin outputs an "L" signal continuously.
Figure 7.5 Bus Cycle with Separate Bus (2)
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Page 48 of 330
7. Bus
M32C/80 Group
• Bus Cycle 3φ + 3φ
1 bus cycle = 6φ
BCLK
Address
CSi
(1)
Data (Read)
RD
Data (Write)
WR, WRL, WRH
• Bus Cycle 3φ + 4φ
1 bus cycle = 7φ
BCLK
Address
CSi
(1)
Data (Read)
RD
Data (Write)
WR, WRL, WRH
• Bus Cycle 3φ + 6φ
1 bus cycle = 9φ
BCLK
Address
CSi
(1)
Data (Read)
RD
Data (Write)
WR, WRL, WRH
i=0 to 3
NOTE:
1. When the microcomputer continuously accesses the same CS area, the CSi pin
outputs an "L" signal continuously.
Figure 7.6 Bus Cycle with Separate Bus (3)
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REJ09B0271-0100
7. Bus
M32C/80 Group
• Bus Cycle 2φ + 2φ
• Bus Cycle 2φ + 3φ
1 bus cycle = 4φ
BCLK
1 bus cycle = 5φ
BCLK
CSi (1)
CSi (1)
Data (Read)
LA
Data (Read)
RD
RD
LA
RD
RD
Data (Write)
LA
Data (Write)
WD
WR (WRL)
WR (WRL)
ALE
ALE
• Bus Cycle 2φ + 5φ
LA
WD
1 bus cycle = 7φ
BCLK
CSi (1)
Data (Read)
LA
RD
RD
Data (Write)
WD
LA
WR (WRL)
ALE
LA : Latch Address
RD : ReadData
WD : Write Data
i=0 to 3
NOTE:
1. When the microcomputer continuously accesses the same CS area, the CSi pin outputs an "L" signal continuously.
Figure 7.7 Bus Cycle with Multiplexed Bus (1)
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7. Bus
M32C/80 Group
• Bus Cycle 3φ + 3φ
1 bus cycle = 6φ
BCLK
CSi (1)
Data (Read)
LA
RD
RD
Data (Write)
LA
WD
WR (WRL)
ALE
• Bus Cycle 3φ + 4φ
1 bus cycle = 7φ
BCLK
CSi (1)
Data (Read)
LA
RD
RD
Data (Write)
LA
WD
WR (WRL)
ALE
• Bus Cycle 3φ + 5φ
1 bus cycle = 8φ
BCLK
CSi (1)
Data (Read)
LA
RD
RD
Data (Write)
LA
WD
WR (WRL)
ALE
• Bus Cycle 3φ + 6φ
1 bus cycle = 9φ
BCLK
CSi (1)
Data (Read)
LA
RD
RD
Data (Write)
LA
WD
WR (WRL)
ALE
LA : Latch Address
RD : Read Data
WD : Write Data
i=0 to 3
NOTE:
1. When the microcomputer continuously accesses the same CS area,
the CSi pin outputs an "L" signal continuously.
Figure 7.8 Bus Cycle with Multiplexed Bus (2)
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REJ09B0271-0100
7. Bus
M32C/80 Group
7.2.4.1 Bus Cycle with Recovery Cycle Added
The EWCRi06 bit in the EWCRi register (i=0 to 3) determines whether the recovery cycle is added or not.
In the recovery cycle, addresses and wrie data outputs are provided continuously (using the separate bus
only). Devices, which take longer address hold time and data hold time to write data, are connectable.
• Recovery Cycle with Separate Bus (For 1φ + 2φ)
Recovery Cycle
BCLK
Address
CSi
<--- Hold an Address
A
(1)
Data (Read)
RD
RD
Data (Write)
<--- Hold Data
WD
WR, WRL, WRH
• Recovery Cycle with Multiplexed Bus (For 2φ + 3φ)
Recovery Cycle
BCLK
CSi (1)
Data (Read)
LA
RD
RD
Data (Write)
LA
WD
<--- Hold Data
WR (WRL)
ALE
A : Address
LA : Latch Address
RD : Read Data
WD : Write Data
i=0 to 3
NOTE:
1. When the microcomputer continuously accesses the same CS area,
the CSi pin outputs an "L" signal continuously.
Figure 7.9 Recovery Cycle
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7. Bus
M32C/80 Group
7.2.5 ALE Signal
The ALE signal latches an address of the multiplexed bus. Latch an address on the falling edge of the
ALE signal. The PM15 and PM14 bits in the PM1 register determine the output pin for the ALE signal.
The ALE signal is output to internal space and external space.
(2) 16-Bit Data Bus
(1) 8-Bit Data Bus
ALE
ALE
D0/A0 to D7/A7
Address
Data
A8 to A15
Address
A16 to A19
Address
A20/CS3
A21/CS2
A22/CS1
A23/CS0
(1)
D0/A0 to D15/A15
(2)
Address
Address (2)
A16 to A19
A20/CS3
A21/CS2
A22/CS1
A23/CS0
Address or CS
(1)
Data
Address or CS
NOTES:
1. D0/A0 to D7/A7 are placed in high-impedance states when read.
2. When the multiplexed bus is selected for all CS areas, the address bus becomes an I/O port.
Figure 7.10 ALE Signal and Address/Data Bus
_______
7.2.6 RDY Signal
_______
The RDY signal facilitates access to external devices requiring longer access time. When a low-level ("L")
________
signal is applied to the RDY pin on the falling edge of the last BCLK of the bus cycle, wait states are
________
inserted into the bus cycle. When a high-level ("H") signal is applied to the RDY pin on the falling edge of
BCLK, the bus cycle starts running again.
________
Table 7.6 lists microcomputer states when the RDY signal inserts wait states into the bus cycle. Figure
_____
________
7.11 shows an example of the RD signal that is extended by the RDY signal.
Table 7.6 Microcomputer States in Wait State(1)
Item
Oscillation
State
On
RD Signal, WR Signal, Address Bus, Data Bus,
Maintains the same state as when RDY
CS, ALE Signal, HLDA, Programmable I/O Ports signal was received
Internal Peripheral Circuits
On
NOTE:
________
1. The RDY signal cannot be accepted immediately before software wait states are inserted.
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7. Bus
M32C/80 Group
(1) Separate Bus with 2 Wait States
1st cycle
2nd cycle
3rd cycle
4th cycle
BCLK
AAAAAAA
AAAAAAA
RD
CSi
(1)
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Timing to receive RDY
(2) Multiplexed Bus with 2 Wait States
1st cycle
2nd cycle
3rd cycle
4th cycle
BCLK
AAAAAA
RD
CSi
(1)
(i=0 to 3)
RDY
tsu(RDY - BCLK)
AA
Timing to receive RDY
: Wait states inserted by RDY
: Wait states inserted by program
tsu(RDY-BCLK): Setup time for RDY input
Timing to receive RDY for j wait(s): j+1 cycles (j = 1 to 3)
NOTE:
1. The chip-select signal (CSi) may be output longer depending on CPU state such as the instruction
queue buffer.
_____
________
Figure 7.11 RD Signal Output Extended by RDY Signal
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7. Bus
M32C/80 Group
_________
7.2.7 HOLD Signal
__________
The HOLD signal transfers bus privileges from the CPU to external circuits. When a low-level ("L") signal is
__________
applied to the HOLD pin, the microcomputer enters a hold state after bus access is completed. While the
__________
_________
HOLD pin is held "L", the microcomputer is in a hold state and the HLDA pin outputs an "L" signal.
Table 7.7 shows the microcomputer status in a hold state.
__________
Bus is used in the following priority order: HOLD, DMAC, CPU.
__________
HOLD > DMAC > CPU
Figure 7.12 Bus Priority Order
Table 7.7 Microcomputer Status in Hold State
Item
Status
Oscillation
On
RD Signal, WR Signal, Address Bus, Data Bus,
CS, BHE
High-impedance
Programmable I/O Ports
Maintains the same state as when HOLD signal was received
HLDA
Outputs "L"
Internal Peripheral Circuits
On (excluding the watchdog timer)
ALE Signal
Outputs "L"
7.2.8 External Bus Status when Accessing Internal Space
Table 7.8 shows external bus states when an internal space is accessed.
Table 7.8 External Bus States when Accessing Internal Space
Item
Address Bus
Data
Bus
State when Accessing SFRs, Internal ROM, and Internal RAM
Holds address of external space last accessed
When Reading
High-impedance
When Writing
High-impedance
RD, WR, WRL, WRH
Outputs "H"
BHE
Holds state of external space last accessed
CS
Outputs "H"
ALE
Outputs ALE
7.2.9 BCLK Output
The CPU clock operates the CPU. P53 outputs the CPU clock signal as BCLK when the PM07 bit in the
PM0 register is set to "0" (BCLK) and the CM01 and CM00 bits in the CM0 register are set to "002" (I/O
port P53).
No BCLK is output in single-chip mode. Refer to 8. Clock Generation Circuit for details.
Rev. 1.00 Nov. 01, 2005 Page 55 of 330
REJ09B0271-0100
8. Clock Generation Circuit
M32C/80 Group
8. Clock Generation Circuit
8.1 Types of the Clock Generation Circuit
Four circuits are included to generate the system clock signal:
• Main clock oscillation circuit
• Sub clock oscillation circuit
• On-chip oscillator
• PLL frequency synthesizer
Table 8.1 lists specifications of the clock generation circuit. Figure 8.1 shows a block diagram of the clock
generation circuit. Figures 8.2 to 8.8 show registers controlling the clock.
Table 8.1 Clock Generation Circuit Specifications
Item
Main Clock
Oscillation Circuit
Sub Clock
Oscillation Circuit
PLL Frequency
Synthesizer
On-chip Oscillator
Use
CPU clock source,
Peripheral function
clock source
CPU clock source,
Timer A and B clock
source
CPU clock source,
Peripheral function
clock source
CPU clock source,
Peripheral function
clock source
Clock Frequency
Up to 32 MHz
32.768 kHz
Approx. 1 MHz
Up to 32 MHz
(See Table 8.3)
Connectable
Osillator or
Additional Circuit
Ceramic resonator
Crystal oscillator
Crystal oscillator
---
---
Pins for Oscillator
or for Additional
Circuit
XIN, XOUT
XCIN, XCOUT
---
---
Oscillation Stop /
Restart Function
Available
Available
Available
Available
Oscillator State
after Reset
Oscillating
Stopped
Stopped
Stopped
Externally generated
clock can be applied.
Externally generated
clock can be applied.
When the main clock
stops oscillating, the
on-chip oscillator
starts oscillating automatically and
becomes clock source
for the CPU and
peripheral function.
---
Other
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Rev. 1.00 Nov. 01, 2005 Page 57
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Figure 8.1 Clock Generation Circuit
of 330
01
CLKOUT
a
PM21
PM22
S Q
R
S Q
R
CM02
CM00, CM01, CM02, CM04, CM05, CM07: Bits in the CM0 register
CM10, CM17: Bits in the CM1 register
CM20, CM21: Bits in the CM2 register
CM10=1 (Stop Mode)
Output signal to determine
interrupt priority request level
NMI
RESET
Software Reset
WAIT Instruction (Wait Mode)
CM01 and CM00
11
10
PM21
Clock Edge Detect
/Charge and
Discharge
Circuit Control
Charge and
Discharge
Circuit
On-Chip Oscillator
Watchdog Timer
Interrupt Request
Circuit to Generate
Oscillation Stop
Detection Interrupt
Request
On-Chip Oscillator and Main Clock Stop Detection
fC
f8
f32
Pheripheral Function
Clock
Port P53 00
Wait Mode
CM02
CM21
CM10
CM20
XIN
XCIN
XCOUT
b
CM21 Switch
Signal
On-chip Oscillator
Clock f(ROC)
Interrupt
Request Signal
1
CM21
0
fC
fROC
CM21
1/32
CM07
1/2
fC32
1
0
Divider
Reset
CPSR=1
(Note 2)
1/m
1/2
1/2
CST
1/2
1/2n
1/2
fAD
Peripheral
Function
Clock
Peripheral Function Clock
BCLK
CPU Clock
f2n(1)
f32
f8
f1
Phase
Comparator
PLC12: Bit in the PLC1 register
Reference
Frequency Counter
Programmable
Counter
Charge
Pump
Voltage
Controlled
Oscillator
(VCO)
1/3
1/2
PLC12
PLL Clock
e
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. The MCD4 to MCD0 bits in the MCD register select divide-by-m (m=1,2,3,4,6,8,10,12,14,16 ).
PLL Frequency Synthesizer
c
1
b
CM17
0
Sub Clock
CM21
CM05
XIN Clock
Main Clock
On-chip
Oscillator
0scillating
Activated
Main Clock
Stop Detect
Detecting
Function
Activated
c PLL Frequency e
Synthesizer
a
Sub Clock Oscillation Circuit
XOUT
Main Clock Oscillation Circuit
PM21
PM21, PM22: Bits in the PM2 register
CST: Bit in the TCSPR register
CPSR: Bit in the CPSRF register
CM04
CM05
Wait Mode
CM02
M32C/80 Group
8. Clock Generation Circuit
8. Clock Generation Circuit
M32C/80 Group
System Clock Control Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CM0
Bit
Symbol
Address
000616
After Reset
0000 10002
Bit Name
Function
b1 b0
CM00
Clock Output Function
Select Bit(2)
CM01
0 0: I/O port P53
0 1: Outputs fC
1 0: Outputs f8
1 1: Outputs f32
RW
RW
RW
CM02
0: Peripheral clock does not stop in
In Wait Mode, Peripheral
wait mode
Function Clock Stop Bit(9) 1: Peripheral clock stops in wait
mode(3)
CM03
XCIN-XCOUT Drive
Capacity Select Bit(11)
0: Low
1: High
RW
CM04
Port XC Switch Bit
0: I/O port function
1: XCIN-XCOUT oscillation function(4)
RW
CM05
Main Clock (XIN-XOUT)
Stop Bit(5, 9)
0: Main clock oscillates
1: Main clock stops(6)
RW
CM06
Watchdog Timer
Function Select Bit
0: Watchdog timer interrupt
1: Reset(7)
RW
CM07
CPU Clock Select
Bit 0(8, 9, 10)
0: Clock selected by the CM21 bit
divided by MCD register setting
1: Sub clock
RW
RW
NOTES:
1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), set the CM01 and CM00 bits to
"002". When the PM15 and PM14 bits in the PM1 register are set to "012" (ALE output to P53), set the
CM01 and CM00 bits to "002". When the PM07 bit is set to "1" (function selected in the CM01 and
CM00 bits) in microprocessor or memory expansion mode, and the CM01 and CM00 bits are set to
"002", an "L" signal is output from port P53 (port P53 does not function as an I/O port).
3. fc32 does not stop running. When the CM02 bit is set to "1", the PLL clock cannot be used in wait
mode.
4. When setting the CM04 bit is set to "1", set the PD8_7 and PD8_6 bits in the PD8 register to "002"
(port P87 and P86 in input mode) and the PU25 bit in the PUR2 register to "0" (no pull-up).
5. When entering low-power consumption mode or on-chip oscillator low-power consumption mode, the
CM05 bit stops running the main clock. The CM05 bit cannot detect whether the main clock stops or
not. To stop running the main clock, set the CM05 bit to "1" after the CM07 bit is set to "1" with a stable
sub clock oscillation or after the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock).
When the CM05 bit is set to "1", the clock applied to XOUT becomes "H". The built-in feedback resistor
remains ON. XIN is pulled up to XOUT ("H" level) via the feedback resistor.
6. When the CM05 bit is set to "1", the MCD4 to MCD0 bits in the MCD register are set to "010002"
(divide-by-8 mode). In on-chip oscillation mode, the MCD4 to MCD0 bits are not set to "010002" even
if the CM05 bit terminates XIN-XOUT.
7. Once the CM06 bit is set to "1", it cannot be set to "0" by program.
8. After the CM04 bit is set to "1" with a stable sub clock oscillation, set the CM07 bit to "1" from "0".
After the CM05 bit is set to "0" with a stable main clock oscillation, set the CM07 bit to "0" from "1".
Do not set the CM07 bit and CM04 or CM05 bit simultaneously.
9. When the PM21 bit in the PM2 register is set to "1" (clock change disabled), the CM02, CM05 and
CM07 bits do not change even when written.
10. After the CM07 bit is set to "0", set the PM21 bit to "1".
11. When stop mode is entered, the CM03 bit is set to "1".
Figure 8.2 CM0 Register
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8. Clock Generation Circuit
M32C/80 Group
System Clock Control Register 1(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CM1
0 1 0 0 0 0
Bit
Symbol
CM10
(b4 - b1)
(b5)
(b6)
CM17
Address
000716
After Reset
0010 00002
Bit Name
Function
RW
All Clock Stop Control
Bit(2, 5)
0: Clock oscillates
1: All clocks stop (stop mode)(3)
RW
Reserved Bit
Set to "0"
RW
Reserved Bit
Set to "1"
RW
Reserved Bit
Set to "0"
RW
CPU Clock Select
Bit 1(4,5)
0: Main clock
1: PLL clock
RW
NOTES:
1. Rewrite the CM1 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
2. When the CM10 bit is set to "1", the clock applied to XOUT becomes "H" and the built-in feedback
resistor is disabled. XIN, XCIN and XCOUT are placed in high-impedance states.
3. When the CM10 bit is set to "1", the MCD4 to MCD0 bits in the MCD register are set to "010002"
(divide-by-8 mode). When the CM20 bit is set to "1" (oscillation stop detect function enabled) or the
CM21 bit to "1" (on-chip oscillator selected), do not set the CM10 bit to "1".
4. The CM17 bit setting is enabled only when the CM21 bit in the CM2 register is set to "0". Use the
procedure shown in Figure 8.12 to set the CM17 bit to "1".
5. If the PM21 bit in the PM2 register is set to "1" (clock change disabled), the CM10 and CM17 bits do
not change when written.
If the PM22 bit in the PM2 register is set to "1" (on-chip oscillator clock as watchdog timer count
source), the CM10 bit setting does not change when written.
Figure 8.3 CM1 Register
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8. Clock Generation Circuit
M32C/80 Group
Main Clock Division Register(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
MCD
Bit
Symbol
Address
000C16
After Reset
XXX0 10002
Bit Name
Function
RW
b4 b3 b2 b1 b0
MCD0
MCD1
MCD2
Main Clock Division
Select Bit(2)
MCD3
MCD4
(b7 - b5)
Reserved Bit
1 0 0 1 0: Divide-by-1(no division)
mode
0 0 0 1 0: Divide-by-2 mode
0 0 0 1 1: Divide-by-3 mode
0 0 1 0 0: Divide-by-4 mode
0 0 1 1 0: Divide-by-6 mode
0 1 0 0 0: Divide-by-8 mode
0 1 0 1 0: Divide-by-10 mode
0 1 1 0 0: Divide-by-12 mode
0 1 1 1 0: Divide-by-14 mode
0 0 0 0 0: Divide-by-16 mode
(Note 3)
When read,
its content is indeterminate
RW
RW
RW
RW
RW
RO
NOTES:
1. Rewrite the MCD register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
2. When the microcomputer enters stop mode or low-power consumption mode, the MCD4 to MCD0 bits
are set to "010002".
The MCD4 to MCD0 bits are not set to "010002" even if the CM05 bit in the CM0 register is set to "1"
(XIN-XOUT stopped) in on-chip oscillator mode.
3. Bit combinations cannot be set not listed above.
Figure 8.4 MCD Register
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8. Clock Generation Circuit
M32C/80 Group
Oscillation Stop Detection Register(1)
b7
b6
b5
b4
b3
b2
b1
0 0 0 0
b0
Symbol
CM2
Bit
Symbol
Address
000D16
After Reset
0016
Bit Name
Function
RW
CM20
Oscillation Stop Detection 0: Disables oscillation stop detect function
RW
1: Enables oscillation stop detect function
Enable Bit(2)
CM21
CPU Clock
Select Bit 2(3, 4)
CM22
Oscillation Stop Detection 0: Main clock does not stop
1: Detects a main clock stop
Flag(5)
CM23
Main Clock Monitor
Flag(6)
0: Main clock oscillates
1: Main clock stops
RO
Reserved Bit
Set to "0"
RW
(b7 - b4)
0: Clock selected by the CM17 bit
1: On-chip oscillator clock
RW
RW
NOTES:
1. Rewrite the CM2 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
2. If the PM21 bit in the PM2 register is set to "1" (clock change disabled), the CM20 bit setting does not
change when written.
3. When a main clock oscillation stop is detected while the CM20 bit is set to "1", the CM21 bit is set to "1".
Although the main clock starts oscillating, the CM21 bit is not set to "0". If the main clock is used as a
CPU clock source after the main clock resumes oscillating, set the CM21 bit to "0" by program.
4. When the CM20 bit is set to "1" and the CM22 bit is set to "1", do not set the CM21 bit to "0".
5. When a main clock stop is detected, the CM22 bit is set to "1". The CM22 bit can only be set to "0", not
"1", by program.
If the CM22 bit is set to "0" by program while the main clock stops, the CM22 bit cannot be set to "1"
until the next main clock stop is detected.
6. Determine the main clock state by reading the CM23 bit several times after the oscillation stop
detection interrupt is generated.
Figure 8.5 CM2 Register
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8. Clock Generation Circuit
M32C/80 Group
Count Source Prescaler Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TCSPR
Bit
Symbol
Address
035F16
Bit Name
After Reset(2)
0XXX 00002
Function
CNT0
RW
CNT1
Division Rate
Select Bit(1)
CNT2
If setting value is n, f2n is the
main clock, on-chip oscillator clock
or PLL clock divided by 2n.
When n is set to "0", no division is
selected.
CNT3
(b6 - b4)
CST
RW
RW
RW
RW
Reserved Bit
Operation Enable Bit
When read,
its content is indeterminate
0: Divider stops
1: Divider starts
RO
RW
NOTES:
1. Rewrite the CNT3 to CNT0 bits after the CST bit is set to "0".
2. Value of the TCSPR register is not reset by software reset or watchdog timer reset.
Clock Prescaler Reset Flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Bit
Symbol
Address
034116
Bit Name
After Reset
0XXX XXXX2
Function
RW
Nothing is assigned. When write, set to "0".
(b6 - b0) When read, its content is indeterminate.
CPSR
Clock Prescaler Reset
Flag
Figure 8.6 TCSPR and CPSRF Registers
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When the CPSR bit is set to "1", fC
divided by 32 is reset.
When read, its content is "0".
RW
8. Clock Generation Circuit
M32C/80 Group
PLL Control Register 0(1, 2, 5)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PLC0
1 0 1
Bit
Symbol
Address
002616
After Reset
0001 X0102
Function
Bit Name
RW
RW
PLC00
b2 b1 b0
PLC01
Programmable Counter
Select Bit(3)
0 1 1: Multiply-by-6
1 0 0: Multiply-by-8
Do not set to values other than the
above
PLC02
RW
Reserved Bit
(b3)
(b4)
(b5)
(b6)
PLC07
RW
When read,
its content is indeterminate
RO
Reserved Bit
Set to "1"
RW
Reserved Bit
Set to "0"
RW
Reserved Bit
Set to "1"
RW
Operation Enable Bit(4)
0: PLL is Off
1: PLL is On
RW
NOTES:
1. Rewrite the PLC0 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
2. If the PM21 bit in the PM2 register is set to "1" (clock change disabled), the PLC0 register setting does
not change when written.
3. Set the PLC02 to PLC00 bits when the PLC07 bit is set to "0". Once these bits are set, they cannot be
changed.
4. Set the CM17 bit in the CM1 register to "0" (main clock as CPU clock source) and the PLC07 bit to "0"
before entering wait or stop mode.
5. Set the PLC0 and PLC1 registers simultaneously in 16-bit units.
PLL Control Register 1(1, 2, 3, 4)
b7
b6
b5
0 0 0
b4
b3
b2
0
b1
b0
Symbol
PLC1
1 0
Bit
Symbol
(b0)
(b1)
PLC12
(b3)
(b4)
(b7 - b5)
Address
002716
After Reset
000X 00002
Bit Name
Function
RW
Reserved Bit
Set to "0"
RW
Reserved Bit
Set to "1"
RW
PLL Clock Division
Switch Bit
0: Divide-by-2
1: Divide-by-3
RW
Reserved Bit
Set to "0"
RW
Reserved Bit
Reserved Bit
When read,
its content is indeterminate
Set to "0"
RO
RW
NOTES:
1. Rewrite the PLC1 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
2. If the PM21 bit in the PM2 register is set to "1" (clock change disabled), the PLC1 register does not
change when written.
3. Set the PLC1 register when the PLC07 bit is set to "0" (PLL off).
4. Set the PLC0 and PLC1 registers simultaneously in 16-bit units.
Figure 8.7 PLC0 and PLC1 Registers
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8. Clock Generation Circuit
M32C/80 Group
Processor Mode Register 2(1)
b7
b6
b5
b4
b3
b2
b1
0 0 0 0 0
b0
0
Symbol
PM2
Bit
Symbol
Address
001316
After Reset
0016
Bit Name
Function
RW
Reserved Bit
Set to "0"
RW
PM21
System Clock Protect
Bit(2, 3)
0: Protects the clock by a PRCR
register setting
1: Disables a clock change
RW
PM22
WDT Count Source
Protect Bit(2, 4)
0: Selects BCLK as count source of
the watchdog timer
RW
1: Selects the on-chip oscillator clock
as count source of the watchdog
timer
Reserved Bit
Set to "0"
(b0)
(b7 - b3)
RW
NOTES:
1. Rewrite the PM2 register after the PRC1 bit in the PRCR register is set to "1" (write enabled).
2. Once the PM22 and PM21 bits are set to "1", they can not be set to "0" by program.
3. When the PM21 bit is set to "1",
the CPU clock keeps running when the WAIT instruction is executed;
nothing is changed even if following bits are set to either "0" or "1".
• the CM02 bit in the CM0 register (the peripheral function clock is not stopped in wait mode.)
• the CM05 bit in the CM0 register (the main clock is not stopped.)
• the CM07 bit in the CM0 register (a CPU clock source is not changed.)
• the CM10 bit in the CM1 register (the microcomputer does not enter stop mode.)
• the CM17 bit in the CM1 register (a CPU clock source is not changed.)
• the CM20 bit in the CM2 register (oscillation stop detect function settings are not changed.)
• all bits in the PLC0 and PLC1 registers (PLL frequency synthesizer function settings are not changed.)
4. When the PM22 bit is set to "1",
the on-chip oscillator clock becomes a count source of the watchdog timer after the on-chip oscillator starts;
write to the CM10 bit is disabled (the microcomputer does not enter stop mode.);
the watchdog timer keeps running when the microcomputer is in wait mode and hold state.
Figure 8.8 PM2 Register
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8. Clock Generation Circuit
M32C/80 Group
8.1.1 Main Clock
Main clock oscillation circuit generates the main clock. The main clock becomes clock source of the CPU
clock and peripheral function clock.
The main clock oscillation circuit is configured by connecting an oscillator or resonator between the XIN
and XOUT pins. The circuit has a built-in feedback resistor. The feedback resistor is separated from the
oscillation circuit in stop mode to reduce power consumption. An external clock can be applied to the XIN
pin in the main clock oscillation circuit. Figure 8.9 shows an example of a main clock circuit connection.
Circuit constants vary depending on each oscillator. Use the circuit constant recommended by each oscillator manufacturer.
The main clock divided-by-eight becomes a CPU clock source after reset.
To reduce power consumption, set the CM05 bit in the CM0 register to "1" (main clock stopped) after
switching the CPU clock source to the sub clock or on-chip oscillator clock. In this case, the clock applied
to XOUT becomes high ("H"). XIN is pulled up by XOUT via the feedback resistor which remains on. When
an external clock is applied to the XIN pin, do not set the CM05 bit to "1".
All clocks, including the main clock, stop in stop mode. Refer to 8.5 Power Consumption Control for
details.
Microcomputer
(Built-in Feedback Resistor)
Microcomputer
(Built-in Feedback Resistor)
CIN
XIN
External Clock
XIN
VCC
VSS
Oscillator
XOUT
Rd(1)
COUT
XOUT
VSS
Open
NOTE:
1. Place a damping resistor if required. Resistance values vary depending on the oscillator setting.
Use values recommended by each oscillator manufacturer.
Place a feedback resistor between XIN and XOUT if the oscillator manufacturer recommends
placing the resistor externally.
Figure 8.9 Main Clock Circuit Connection
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8. Clock Generation Circuit
M32C/80 Group
8.1.2 Sub Clock
Sub clock oscillation circuit generates the sub clock. The sub clock becomes clock source of the CPU
clock and for the timers A and B. The same frequency, fc, as the sub clock can be output from the
CLKOUT pin.
The sub clock oscillation circuit is configured by connecting a crystal oscillator between the XCIN and
XCOUT pins. The circuit has a built-in feedback resistor. The feedback resistor is separated from the
oscillation circuit in stop mode to reduce power consumption. An external clock can be applied to the XCIN
pin. Figure 8.10 shows an example of a sub clock circuit connection. Circuit constants vary depending on
each oscillator. Use the circuit constant recommended by each oscillator manufacturer.
The sub clock stops after reset. The feedback resistor is separated from the oscillation circuit. When the
PD8_6 and PD8_7 bits in the PD8 register are set to "0" (input mode) and the PU25 bit in the PUR2
register is set to "0" (no pull-up), set the CM04 bit in the CM0 register to "1" (XCIN-XCOUT oscillation
function). The sub clock oscillation circuit starts oscillating. To apply an external clock to the XCIN pin, set
the CM04 bit to "1" when the PD8_7 bit is set to "0" and the PU25 bit to "0". The clock applied to the XCIN
pin becomes a clock source of the sub clock.
When the CM07 bit in the CM0 register is set to "1" (sub clock) after the sub clock oscillation has stabilized, the sub clock becomes a CPU clock source.
All clocks, including the sub clock, stop in stop mode. Refer to 8.5 Power Consumption Control for
details.
Microcomputer
(Built-in Feedback Resistor)
Microcomputer
(Built-in Feedback Resistor)
CCIN
XCIN
External Clock
XCIN
VCC
VSS
Oscillator
XCOUT
RCd(1)
CCOUT
XCOUT
VSS
Open
NOTE:
1. Place a damping resistor if required. Resistance values vary depending on the oscillator setting.
Use values recommended by each oscillator manufacturer.
Place a feedback resistor between XCIN and XCOUT if the oscillator manufacturer recommends
placing the resistor externally.
Figure 8.10 Sub Clock Circuit Connection
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8.1.3 On-Chip Oscillator Clock
On-chip oscillator generates the on-chip oscillator clock. The 1-MHz on-chip oscillator clock becomes a
clock source of the CPU clock and peripheral function clock.
The on-chip oscillator clock stops after reset. When the CM21 bit in the CM2 register is set to "1" (on-chip
oscillator clock), the on-chip oscillator starts oscillating. Instead of the main clock, the on-chip oscillator
clock becomes clock source of the CPU clock and peripheral function clock.
Table 8.2 shows bit settings for on-chip oscillator start condition.
Table 8.2 Bit Settings for On-Chip Oscillator Start Condition
CM2 Register
PM2 Register
CM21 Bit
PM22 Bit
1
0
CPU clock source or peripheral function clock source
0
1
Watchdog timer operating clock source
(The clock keeps running when entering stop mode.)
Used as
8.1.3.1 Oscillation Stop Detect Function
When the main clock is terminated by external source, the on-chip oscillator automatically starts oscillating to generate another clock.
When the CM 20 bit in the CM2 registser is set to "1" (oscillation stop detect function enabled), an oscillation stop detection interrupt request is generated as soon as the main clock stops. Simultaneously, the onchip oscillator starts oscillating. Instead of the main clock, the on-chip oscillator clock becomes clock
source for the CPU clock and peripheral function clock. Associated bits are set as follows:
• The CM21 bit is set to "1" (on-chip oscillator clock becomes a clock source of the CPU clock.)
• The CM22 bit is set to "1" (main clock stop is detected.)
• The CM23 bit is set to "1" (main clock stops.) (See Figure 8.14)
8.1.3.2 How to Use Oscillation Stop Detect Function
• The oscillation stop detection interrupt shares vectors with the watchdog timer interrupt and the low
voltage detection interrupt. When these interrupts are used simultaneously, read the CM22 bit with
an interrupt routine to determine if an oscillation stop detection interrupt request has been generated.
• When the main clock resumes running after an oscillation stop is detected, set the main clock as
clock source of the CPU clock and peripheral function clock. Figure 8.11 shows the procedure to
switch the on-chip oscillator clock to the main clock.
• In low-speed mode, when the main clock is stopped by setting the CM20 bit to "1", the oscillation
stop detection interrupt request is generated. Simultaneously, the on-chip oscillator starts oscillating. The sub clock remains the CPU clock source. The on-chip oscillator clock becomes a clock
source for the peripheral function clock.
• When the peripheral function clock stops running, the oscillation stop detect function is also disabled. To enter wait mode while the oscillation stop detect function is in use, set the CM02 bit in the
CM0 register to "0" (peripheral clock does not stop in wait mode).
• The oscillation stop detect function is provided to handle main clock stop caused by external source.
Set the CM20 bit to "0" (oscillation stop detect function disabled) when the main clock is terminated
by program, i.e., entering stop mode or setting the CM05 bit to "1" (main clock oscillation stop).
• When the main clock frequency is 2 MHz or less, the oscillation stop detect function is not available.
Set the CM20 bit to "0".
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Switch to the main clock
Determine several times whether
the CM23 bit is set to "0"
(main clock oscillates)
No
Yes
Set the MCD4 to MCD0 bits
to "010002" (divide-by-8 mode)
Set the CM22 bit to "0"
(main clock does not stop)
Set the CM21 bit to "0"
(main clock as CPU clock source)
End
MCD4 to MCD0: Bits in the MCD Register
CM23 to CM21: Bits in the CM2 Register
Figure 8.11 Switching Procedure from On-chip Oscillator Clock to Main Clock
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8.1.4 PLL Clock
The PLL frequency synthesizer generates the PLL clock based on the main clock. The PLL clock can be
used as clock source for the CPU clock and peripheral function clock.
The PLL frequency synthesizer stops after reset. When the PLC07 bit is set to "1" (PLL on), the PLL
frequency synthesizer starts operating. Wait tsu(PLL) ms for the PLL clock to stabilize.
The PLL clock can either be the clock output from the voltage controlled oscillator (VCO) divided-by-2 or
divided-by-3. When the PLL clock is used as a clock source for the CPU clock or peripheral function
clock, set each bit as is shown in Table 8.3. Figure 8.12 shows the procedure to use the PLL clock as the
CPU clock source.
To enter wait or stop mode, set the CM17 bit to "0" (main clock as CPU clock source), set the PLC07 bit
in the PLC0 register to "0" (PLL off) and then enter wait or stop mode.
Table 8.3 Bit Settings to Use PLL Clock as CPU Clock Source
PLC0 Register
PLC1 Register
f(XIN)
10 MHz
8 MHz
PLL Clock
PLC02 Bit
PLC01 Bit
PLC00 Bit
0
1
1
1
0
PLC12 Bit
0
30 MHz
1
20 MHz
0
32 MHz
1
21.3 MHz
0
Use PLL clock as CPU clock source
Set the PLC0 and the PLC1 registers
(Set the PLC07 bit to "0")
Set the PLC07 bit to "1"
(PLL on)
Wait tsu(PLL)ms
Set the CM17 bit to "1"
(PLL clock as CPU clock source)
End
PLC07: Bit in the PLC0 Register
CM17: Bit in the CM1 Register
Figure 8.12 Procedure to Use PLL Clock as CPU Clock Source
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8.2 CPU Clock and BCLK
The CPU operating clock is referred to as the CPU clock. The CPU clock is also a count source for the
watchdog timer. After reset, the CPU clock is the main clock divided-by-8 . In memory expansion or microprocessor mode, the clock having the same frequency as the CPU clock can be output from the BCLK pin
as BCLK. Refer to 8.4 Clock Output Function for details.
The main clock, sub clock, on-chip oscillator clock or PLL clock can be selected as a clock source for the
CPU clock. Table 8.4 shows CPU clock source and bit settings.
When the main clock, on-chip oscillator clock or PLL clock is selected as a clock source of the CPU clock,
the selected clock divided-by-1 (no division), -2, -3, -4, -6, -8, -10, -12, -14 or -16 becomes the CPU clock.
The MCD4 to MCD0 bits in the MCD register select the clock division.
When the microcomputer enters stop mode or low-power consumption mode (except when the on-chip
oscillator clock is the CPU clock), the MCD4 to MCD0 bits are set to "010002" (divide-by-8 mode). Therefore, when the main clock starts running, the CPU clock enters medium-speed mode (divide-by-8).
Table 8.4 CPU Clock Source and Bit Settings
CM0 Register
CM1 Register
CM2 Register
CM07 Bit
CM17 Bit
CM21 Bit
Main Clock
0
0
0
Sub Clock
1
0
0
On-Chip Oscillator Clock
0
0
1
PLL Clock
0
1
0
CPU Clock Source
8.3 Peripheral Function Clock
The peripheral function clock becomes an operating clock or count source for peripheral functions excluding the watchdog timer.
8.3.1 f1, f8, f32 and f2n
f1, f8 and f32 are the peripheral function clock, selected by the CM21 bit, divided-by-1, -8, or -32. The
PM27 and PM26 bits in the PM2 register selects a f2n count source from the peripheral clock, XIN clock,
and the on-chip oscillator clock. The CNT3 to CNT0 bits in the TCSPR register selects a f2n division. (n=0
to 15. No division when n=0.)
f1, f8, f32 and f2n stop when the CM02 bit in the CM0 register to "1" (peripheral function stops in wait mode)
to enter wait mode or when in low-power consumption mode.
f1, f8 and f2n are used as an operating clock of the serial I/O and count source of the timers A and B. f1 is
also used as an operating clock for the intelligent I/O.
The CLKOUT pin outputs f8 and f32 . Refer to 8.4 Clock Output Function for details.
8.3.2 fAD
fAD is an operating clock for the A/D converter and has the same frequency as either the main clock(1) or
the on-chip oscillator clock. The CM21 bit determines which clock is selected.
If the CM02 bit is set to "1" (peripheral function stop in wait mode) to enter wait mode, fAD stops. fAD also
stops in low-power consumption mode.
NOTE:
1. The PLL clock, instead of the main clock, when the CM17 bit is set to "1" (PLL clock).
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8.3.3 fC32
fC32 is the sub clock divided by 32. fC32 is used as a count source for the timers A and B. fC32 is available
when the sub clock is running.
8.4 Clock Output Function
The CLKOUT pin outputs fC, f8 or f32.
In memory expansion mode or microprocessor mode, a clock having the same frequency as the CPU clock
can be output from the BCLK pin as BCLK.
Table 8.5 lists CLKOUT pin function in single-chip mode. Table 8.6 lists CLKOUT pin function in memory
expansion mode and microprocessor mode.
Table 8.5 CLKOUT Pin in Single-Chip Mode
PM0 Register (1)
PM07 Bit
CM0 Register (2)
CM01 Bit
CLKOUT Pin Function
0
CM00 Bit
0
1
0
1
Outputs fc
1
1
0
Outputs f8
1
1
1
Outputs f32
P53 I/O port
- : Can be set to either "0" or "1"
NOTES:
1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1" (write enabled).
2. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
Table 8.6 CLKOUT Pin in Memory Expansion Mode and Microprocessor Mode
PM1 Register(1)
PM15 Bit
PM0 Register(1)
PM14 Bit
002, 102, 112,
0
PM07 Bit
0
CM0 Register(2)
CM01 Bit
0 (3)
CM00 Bit
0 (3)
CLKOUT Pin Function
Outputs BCLK
1
0
0
Outputs "L" (not P53)
1
0
1
Outputs fc
1
1
0
Outputs f8
1
1
1
Outputs f32
0 (3)
0 (3)
Outputs ALE
1
- : Can be set to either "0" or "1"
NOTES:
1. Rewrite the PM1 and PM0 registers after the PRC1 bit in the PRCR register is set to "1" (write enabled).
2. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
3. When the PM07 bit is set to "0" (selected in the CM01 and CM00 bits) or the PM15 and PM14 bits are
set to "012" (P53/BCLK), set the CM01 and CM00 bits to "002" (I/O port P53).
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8.5 Power Consumption Control
Normal operating mode, wait mode and stop mode are provided as the power consumption control.
All mode states, except wait mode and stop mode, are called normal operating mode in this section. Figure
8.13 shows a block diagram of status transition in wait mode and stop mode. Figure 8.14 shows a block
diagram of status transition in all modes.
8.5.1 Normal Operating Mode
The normal operating mode is further separated into six modes.
In normal operating mode, the CPU clock and peripheral function clock are supplied to operate the CPU
and peripheral function. The power consumption control is enabled by controlling a CPU clock frequency. The higher the CPU clock frequency is, the more processing power increases. The lower the
CPU clock frequency is, the more power consumption decreases. When unnecessary oscillation circuit
stops, power consumption is further reduced.
8.5.1.1 High-Speed Mode
The main clock(1) becomes the CPU clock and a clock source of the peripheral function clock. When
the sub clock runs, fC32 can be used as a count source for the timers A and B.
8.5.1.2 Medium-Speed Mode
The main clock(1) divided-by-2, -3, -4, -6, -8, -10, -12, -14, or -16 becomes the CPU clock. The main
clock(1) is a clock source for the peripheral function clock. When the sub clock runs, fC32 can be used
as a count source for the timers A and B.
8.5.1.3 Low-Speed Mode
The sub clock becomes the CPU clock . The main clock(1) is a clock source for the peripheral function
clock. fC32 can be used as a count source for the timers A and B.
8.5.1.4 Low-Power Consumption Mode
The microcomputer enters low-power consumption mode when the main clock stops in low-speed
mode. The sub clock becomes the CPU clock. Only fC32 can be used as a count source for the timers
A and B and the peripheral function clock. In low-power consumption mode, the MCD4 to MCD0 bits
in the MCD register are set to "010002" (divide-by-8 mode). Therefore, when the main clock resumes
running, the microcomputer is in midium-speed mode (divide-by-8 mode).
8.5.1.5 On-Chip Oscillator Mode
The on-chip oscillator clock divided-by-1 (no division), -2, -3, 4-, -6, -8, -10, -12, -14, or -16 becomes
the CPU clock. The on-chip oscillator clock is a clock source for the peripheral function clock. When
the sub clock runs, fC32 can be used as a count source for the timers A and B.
8.5.1.6 On-Chip Oscillator Low-Power Consumption Mode
The microcomputer enters on-chip oscillator low-power consumption mode when the main clock stops
in on-chip oscillator mode . The on-chip oscillator clock divided-by-1 (no division), -2, -3, -4, -6, -8, -10, 12, -14, or -16 becomes the CPU clock. The on-chip oscillator clock is a clock source for the peripheral
function clock. When the sub clock runs, fC32 can be used as a count source for the timers A and B.
NOTE:
1. The PLL clock, instead of the main clock, when the CM17 bit is set to "1" (PLL clock).
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Switch the CPU clock after the clock to be switched to stabilize. Sub clock oscillation will take longer(2) to
stabilize. Wait, by program, until the clock stabilizes directly after turning the microcomputer on or exiting
stop mode.
To switch the on-chip oscillator clock to the main clock, enter medium-speed mode (divide-by-8) after the
main clock is divided by eight in on-chip oscillator mode (the MCD4 to MCD0 bits in the MCD register are
set to "010002").
Do not enter on-chip oscillator mode or on-chip oscillator low-power consumption mode from low-speed
mode or low-power consumption mode and vice versa.
NOTE:
2. Contact your oscillator manufacturer for oscillation stabilization time.
8.5.2 Wait Mode
In wait mode, the CPU clock stops running. The CPU and watchdog timer, operated by the CPU clock,
also stop. When the PM22 bit in the PM2 register is set to "1" (on-chip oscillator clock as watchdog timer
count source), the watchdog timer continues operating. Because the main clock, sub clock and on-chip
oscillator clock continue running, peripheral functions using these clocks also continue operating.
8.5.2.1 Peripheral Function Clock Stop Function
If the CM02 bit in the CM0 register is set to "1" (peripheral function clock stops in wait mode), f1, f8, f32,
f2n (when peripheral clock is selected as a count source), and fAD stop in wait mode. Power consumption can be reduced. f2n, when XIN clock or on-chip oscillator clock is selected as a count source, and
fC32 do not stop running.
8.5.2.2 Entering Wait Mode
If wait mode is entered after setting the CM02 bit to "1", set the MCD4 to MCD0 bits in the MCD
register to be the 10-MHz or less CPU clock flequency after dividing the main clock.
Enter wait mode after setting the followings.
• Initial Setting
Set each interrupt priority level after setting the exit priority level required to exit wait mode, controlled by the RLVL2 to RLVL0 bits in the RLVL register, to "7".
• Before Entering Wait Mode
(1) Set the I flag to "0"
(2) Set the interrupt priority level of the interrupt being used to exit wait mode
(3) Set the interrupt priority levels of the interrupts, not being used to exit wait mode, to "0"
(4) Set IPL in the FLG register. Then set the exit priority level to the same level as IPL
Interrupt priority level of the interrupt used to exit wait mode > IPL = the exit priority level
(5) Set the PRC0 bit in the PRCR register to "1"
(6) If the CPU clock source is the PLL clock, set the CM17 bit in the CM1 register to "0" (main clock)
and PLC07 bit in the PLC0 register to "0" (PLL off)
(7) Set the I flag to "1"
(8) Execute the WAIT instruction
• After Exiting Wait Mode
Set the exit priority level to "7" as soon as exiting wait mode.
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8.5.2.3 Pin Status in Wait Mode
Table 8.7 lists pin states in wait mode.
Table 8.7 Pin States in Wait Mode
Pin
Memory Expansion Mode
Single-Chip Mode
Microprocessor Mode
_______
_______
Address Bus, Data Bus, CS0 to CS3,
Maintains state immediately
________
BHE
_____
______
before entering wait mode
________
_________
RD, WR, WRL, WRH
"H"
__________
HLDA, BCLK
"H"
ALE
"L"
Ports
Maintains state immediately before entering wait mode
CLKOUT
When fC is selected
Outputs clock
When f8, f32 are selected
Outputs the clock when the CM02 bit in the CM0 register is set to "0"
(peripheral function clock does not stop in wait mode).
Maintains state immediately before entering wait mode when the CM02
bit is set to "1" (peripheral function clock stops in wait mode).
8.5.2.4 Exiting Wait Mode
_______
Wait mode is exited by the hardware reset, NMI interrupt or peripheral function interrupts.
_______
When the hardware reset or NMI interrupt, but not the peripheral function interrupts, is used to exit wait
mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to "0002" (interrupt disabled)
before executing the WAIT instruction.
CM02 bit setting affects the peripheral function interrupts. When the CM02 bit in the CM0 register is
set to "0" (peripheral function clock does not stop in wait mode), all peripheral function interrupts can
be used to exit wait mode. When the CM02 bit is set to "1" (peripheral function clock stops in wait
mode), peripheral functions using the peripheral function clock stop. Therefore, the peripheral function
interrupts cannot be used to exit wait mode. However, the peripheral function interrupts caused by an
external clock, fC32, or f2n whose count source is the XIN clock or on-chip oscillator clock, can be used
to exit wait mode.
_______
The CPU clock used when exiting wait mode by the peripheral function interrupts or NMI interrupt is
the same CPU clock used when the WAIT instruction is executed.
Table 8.8 shows interrupts to be used to exit wait mode and usage conditions.
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Table 8.8 Interrupts to Exit Wait Mode
Interrupt
When CM02=0
When CM02=1
NMI Interrupt
Available
Available
Serial I/O Interrupt
Available when the internal and
external clocks are used
Available when the external clock or f2n
(when XIN clock or on-chip oscillator is
selected) is used
Key Input Interrupt
Available
Available
A/D Conversion Interrupt
Available in single or single-sweep
mode
Do not use
Timer A Interrupt
Timer B Interrupt
Available in all modes
Available in event counter mode or when
count source is fC32 or f2n (when XIN clock or
on-chip oscillator is selected)
INT Interrupt
Available
Available
Intelligent I/O Interrupt
Available
Do not use
8.5.3 Stop Mode
In stop mode, all oscillators and resonators stop. The CPU clock and peripheral function clock, as well as
the CPU and peripheral functions operated by these clocks, also stop. The least power required to
operate the microcomputer is in stop mode. The internal RAM holds its data when the voltage applied to
the VCC1 and VCC2 pins is VRAM or more. If the voltage applied to the VCC1 and VCC2 pins is 2.7 V or less,
the voltage must be Vcc1 ≥ Vcc2 ≥ VRAM.
The following interrupts can be used to exit stop mode:
_______
• NMI interrupt
• Key Input Interrupt
______
• INT interrupt
• Timer A and B interrupt (Available when the timer counts external pulse, having its 100 Hz or less
frequency, in event counter mode)
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8.5.3.1 Entering Stop Mode
Stop mode is entered when setting the CM10 bit in the CM1 register to "1" (all clocks stops). The
MCD4 to MCD0 bits in the MCD register become set to "010002" (divide-by-8 mode).
Enter stop mode after setting the followings.
• Initial Setting
Set each interrupt priority level after setting the exit priority level required to exit stop mode, controlled by the RLVL2 to RLVL0 bits in the RLVL register, to "7".
• Before Entering stop mode
(1) Set the I flag to "0"
(2) Set the interrupt priority level of the interrupt being used to exit stop mode
(3) Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to "0"
(4) Set IPL in the FLG register. Then set the exit priority level to the same level as IPL
Interrupt priority level of the interrupt used to exit stop mode > IPL = the exit priority level
(5) Set the PRC0 bit in the PRCR register to "1" (write enabled)
(6) Select the main clock as the CPU clock
• When the CPU clock source is the sub clock,
(a) set the CM05 bit in the CM0 register to "0" (main clock oscillates)
(b) set the CM07 bit in the CM0 register to "0" (clock selected by the CM21 bit divided by MCD
register setting)
• When the CPU clock source is the PLL clock,
(a) set the CM17 bit in the CM1 register to "0" (main clock)
(b) set the PLC07 bit in the PLC0 register to "0" (PLL off)
• When the CPU clock source is the on-chip oscillator clock,
(a) set MCD4 to MCD0 bits to "010002" (divide-by-8 mode)
(b) set the CM05 bit to "0" (main clock oscillates)
(c) set the CM21 bit in the CM2 register to "0" (clock selected by the CM17 bit)
(7) The oscillation stop detect function is used, set the CM20 bit in the CM2 register to "0" (oscillation stop detect fucntion disabled)
(8) Set the I flag to "1"
(9) Set the CM10 bit to "1" (all clocks stops)
• After Exiting Stop Mode
Set the exit priority level to "7" as soon as exiting stop mode.
8.5.3.2 Exiting Stop Mode
_______
Stop mode is exited by the hardware reset, NMI interrupt or peripheral function interrupts (key input
______
interrupt and INT interrupt).
_______
When the hardware reset or NMI interrupt, but not the peripheral function interrupts, is used to exit wait
mode, set all ILVL2 to ILVL0 bits in the interrupt control registers for the peripheral function interrupt to
"0002" (interrupt disabled) before setting the CM10 bit to "1" (all clocks stops).
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8.5.3.3 Pin Status in Stop Mode
Table 8.9 lists pin status in stop mode.
Table 8.9 Pin Status in Stop Mode
Pin
Memory Expansion Mode
Single-Chip Mode
Microprocessor Mode
_______
_______
_______
Address Bus, Data Bus, CS0 to CS3, BHE
Maintains state immediately before
entering stop mode
_____
______
________
_________
RD, WR, WRL, WRH
"H"
__________
HLDA, BCLK
"H"
ALE
"H"
Ports
Maintains state immediately before entering stop mode
CLKOUT
When fC selected
"H"
When f8, f32 selected
Maintains state immediately before entering stop mode
XIN
Placed in a high-impedance state
XOUT
"H"
XCIN, XCOUT
Placed in a high-impedance state
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Reset
All oscillation is stopped
CPU operation is stopped
CM10=1
(Note 2)
Stop Mode
Interrupt
Inter
Stop Mode
Middle-Speed Mode
(divide-by-8 mode)
(Note 2)
WAIT Instruction
Interrupt
Wait Mode
(Note 1)
rupt
(Note 2)
High-Speed /
Middle-Speed Mode
CM10=1
(Note 2)
(Note 1)
WAIT Instruction
Wait Mode
Interrupt
(Note 3)
Low-Speed/ Low-Power
Consumption Mode
On-Chip Oscillator / OnChip Oscillator Low-Power
Consumption Mode
WAIT Instruction
Wait Mode
Interrupt
WAIT Instruction
Interrupt
Wait Mode
Normal Operating Mode
NOTES:
1. See Figure 8.14.
2. When the CM17 bit is set to "1" (PLL clock as CPU clock source), set the CM17 bit to "0"(main clock as CPU clock source)
and the PLC07 bit is set to "0" (PLL off). Then enter wait mode or stop mode.
3. When the CM17 bit is set to "1" (PLL clock as CPU clock source), set the CM17 bit to "0"(main clock as CPU clock source)
and the PLC07 bit is set to "0" (PLL off). Then enter low-speed or low-power consumption mode.
Figure 8.13 Status Transition in Wait Mode and Stop Mode
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Figure 8.14 Status Transition
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CM17=0
PLC07=0
PLC07=1
NOTES:
1. Switch the clock after main clock oscillation is fully stabilized.
2. Switch the clock after sub clock oscillation is fully stabilized.
3. The MCD4 to MCD0 bits in the MCD register are set to "010002" (devide-by-8
mode) automatically.
4. The CM05 bit is not set to "1" when the microcomputer detects a main clock
oscillation stop through the oscillation stop detection circuit.
5. The on-chip oscillator clock runs when setting the PM22 bit to "1" (on-chip
oscillator clock as watchdog timer count source).
(Note 5)
Main clock stop
is detected when
CM20=1
Medium-Speed Mode
CPU clock: f(XIN)/n
(n=2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=0
CM05=0 CM04=0 PLC07=1
CM17=0
: An arrow shows mode can be changed.
Do not change mode to another mode when no arrow is shown.
MCD=XX16: Set the MCD4 to MCD0 bits in the MCD register to the desired division.
Medium-Speed Mode
CPU clock: f(XPLL)/n
(n=2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=0
CM05=0 CM04=0 PLC07=1
CM17=1
CPU clock: f(XIN)
CM07=0 MCD=1216 CM21=0
CM05=0 CM04=0 PLC07=1
CM17=0
High-Speed Mode
CM17=1
High-Speed Mode
CPU clock: f(XPLL)
CM07=0 MCD=1216 CM21=0
CM05=0 CM04=0 PLC07=1
CM17=1
Main Clock Oscillation
Sub Clock Stop
On-Chip Oscillator Clock Stop
PLL Clock Oscillation
Main Clock Oscillation
Sub Clock Stop
On-Chip Oscillator Clock Stop
PLL Clock Oscillation
CM05=1
On-Chip Oscillator Low-Power
Consumption Mode
Main Clock Stop
Sub Clock Stop
CM04=0
On-Chip Oscillator Clock Oscillation
PLL Clock Stop
CPU Clock: On-Chip Oscillator Clock /n
(n=1,2,3,4,6,8,10,12,14,16)
CM04=1
CM07=0 MCD=XX16 CM21=1
CM05=1 CM04=0 PLC07=0
CM17=0
CM05=0
(Note 4)
CM05=1
CM07=1 (Note 2)
CM07=0 (Note 1)
Medium-Speed Mode
CPU clock: f(XIN)/n
(n=2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=0
CM05=0 CM04=1 PLC07=1
CM17=0
CM21=0
CM05=0
(Note 3)
Main Clock Stop
Sub Clock Oscillation
On-Chip Oscillator Clock Oscillation
PLL Clock Stop
CPU Clock: f(XCIN)
CM07=1 MCD=0816 CM21=1
CM05=1 CM04=1 PLC07=0
CM17=0
CM05=0
Main Clock Stop
Sub Clock Oscillation
On-Chip Oscillator Clock Stop
PLL Clock Stop
CPU Clock: f(XCIN)
CM07=1 MCD=0816 CM21=0
CM05=1 CM04=1 PLC07=0
CM17=0
Low-Power Consumption Mode
CM05=1
CM21=1
(Note 1)
Main Clock Oscillation
Sub Clock Oscillation
On-Chip Oscillator Clock Stop
PLL Clock Stop
CPU clock: f(XCIN)
CM07=1 CM21=0 CM05=0
CM04=1 PLC07=0
CM17=0
Main Clock Oscillation
Sub Clock Oscillation
On-Chip Oscillator Clock Oscillation
PLL Clock Stop
CPU Clock: f(XCIN)
CM07=1 CM21=1 CM05=0
CM04=1 PLC07=0
CM17=0
Low-Power Consumption Mode
CM07=1
(Note 2)
CM07=0
Low-Speed Mode
(Note 3)
CM05=1
Medium-Speed Mode
CPU clock: f(XPLL)/n
(n=2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=0
CM05=0 CM04=1 PLC07=1
CM17=1
Low-Speed Mode
CM17=1
CPU clock: f(XPLL)
CM07=0 MCD=1216 CM21=0
CM05=0 CM04=1 PLC07=1
CM17=1
High-Speed Mode
CM17=0
High-Speed Mode
CPU clock: f(XIN)
CM07=0 MCD=1216 CM21=0
CM05=0 CM04=1 PLC07=1
CM17=0
Main Clock Oscillation
Sub Clock Oscillation
On-Chip Oscillator Clock Stop
PLL Clock Oscillation
Main Clock Oscillation
Sub Clock Oscillation
On-Chip Oscillator Clock stop
PLL Clock Oscillation
Main clock stop
is detected when
CM20=1
PLC07=1
PLC07=0
CM21=1
Main Clock Stop
Sub Clock Oscillation
On-Chip Oscillator Clock Oscillation
PLL Clock Stop
CPU Clock: On-Chip Oscillator Clock /n
(n=1,2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=1
CM05=1 CM04=1 PLC07=0
CM17=0
CM05=0
On-Chip Oscillator Low-Power
Consumption Mode
Main Clock Oscillation
Sub Clock Oscillation
On-Chip Oscillator Clock Oscillation
PLL Clock Stop
CPU Clock: On-Chip Oscillator Clock /n
(n=1,2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=1
CM05=0 CM04=1 PLC07=0
CM17=0
Main Clock Oscillation
Sub Clock Stop
On-Chip Oscillator Clock Oscillation
CM04=0
PLL Clock Stop
CPU Clock: On-Chip Oscillator Clock /n
(n=1,2,3,4,6,8,10,12,14,16)
CM04=1
CM07=0 MCD=XX16 CM21=1
CM05=0 CM04=0 PLC07=0
CM17=0
(Note 1) CM21=0
Medium-Speed Mode
CPU clock: f(XIN)/n
(n=2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=0
CM05=0 CM04=1 PLC07=0
CM17=0
On-Chip Oscillator Mode
CM21=1
CM04=1
On-Chip Oscillator Mode
(Note 1) CM21=0
Medium-Speed Mode
CPU clock: f(XIN)/n
(n=2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=0
CM05=0 CM04=0 PLC07=0
CM17=0
CPU clock :f(XIN)
CM07=0 MCD=1216 CM21=0
CM05=0 CM04=1 PLC07=0
CM17=0
High-Speed Mode
High-Speed Mode
CPU clock: f(XIN)
CM07=0 MCD=1216 CM21=0
CM05=0 CM04=0 PLC07=0
CM17=0
Main Clock Oscillation
Sub Clock Oscillation
On-Chip Oscillator Clock Stop
PLL Clock Stop
CM04=1 (Note 1)
Main Clock Oscillation
Sub Clock Stop
On-Chip Oscillator Clock Stop
PLL Clock Stop
CM04=0
MCD=XX16 (Note 1)
Main Clock Oscillation
Sub Clock Stop
On-Chip Oscillator Clock Stop
PLL Clock Stop
CPU Clock: f(XIN)/8
CM07=0 MCD=0816 CM21=0
CM05=0 CM04=0 PLC07=0
CM17=0
After reset,
Medium-Speed Mode (Divide-by-8)
M32C/80 Group
8. Clock Generation Circuit
8. Clock Generation Circuit
M32C/80 Group
8.6 System Clock Protect Function
The system clock protect function prohibits the CPU clock from changing clock sources when the main
clock is selected as the CPU clock source. This prevents the CPU clock from stopping the program crash.
When the PM21 bit in the PM2 register is set to "1" (clock change disabled), the following bits cannot be
written to:
• The CM02 bit, CM05 bit and CM07 bit in the CM0 register
• The CM10 bit and CM17 bit in the CM1 register
• The CM20 bit in the CM2 register
• All bits in the PLC0 and PLC1 registers
The CPU clock continues running when the WAIT instruction is executed.
To use the system clock protect function, set the CM05 bit in the CM0 register to "0" (main clock oscillation)
and CM07 bit to "0" (main clock as BCLK clock source) and follow the procedure below.
(1) Set the PRC1 bit in the PRCR register to "1" (write enabled).
(2) Set the PM21 bit in the PM2 register to "1" (protects the clock).
(3) Set the PRC1 bit in the PRCR register to "0" (write disabled).
When the PM21 bit is set to "1", do not execute the WAIT instruction.
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9. Protection
M32C/80 Group
9. Protection
The protection function protects important registers from being easily overwritten when a program runs out of
control.
Figure 9.1 shows the PRCR register. Each bit in the PRCR register protects the following registers:
• The PRC0 bit protects the CM0, CM1, CM2, MCD, PLC0 and PLC1 registers;
• The PRC1 bit protects the PM0, PM1, PM2, INVC0 and INVC1 registers;
• The PRC2 bit protects the PD9 and PS3 registers;
The PRC2 bit is set to "0" (write disabled) when data is written to a desired address after setting the PRC2
bit to "1" (write enabled). Set the PD9 and PS3 registers immediately after setting the PRC2 bit in the
PRCR register to "1" (write enabled). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the following instruction. The PRC1 and PRC0 bits are not set to "0"
even if data is written to desired addresses. Set the PRC1 and PRC0 bits to "0" by program.
Protect Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PRCR
Bit
Symbol
Address
000A16
After Reset
XXXX 00002
Bit Name
Function
PRC0
Protect Bit 0
Enables writing to CM0, CM1, CM2,
MCD, PLC0, PLC1 registers
0: Write disabled
1: Write enabled
PRC1
Protect Bit 1
Enables writing to PM0, PM1, PM2,
INVC0, INVC1 registers
0: Write disabled
1: Write enabled
RW
PRC2
Protect Bit 2(1)
Enables writing to PD9, PS3 registers
0: Write disabled
1: Write enabled
RW
Reserved Bit
Set to "0"
RW
(b3)
Nothing is assigned. When write, set to "0".
(b7 - b4) When read, its content is indeterminate.
NOTE:
1. The PRC2 bit is set to "0" by writing into a desired address after the PRC2 bit is set to "1".
The PRC1 and PRC0 bits are not automatically set to "0". Set them to "0" by program.
Figure 9.1 PRCR Register
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RW
10. Interrupts
M32C/80 Group
10. Interrupts
10.1 Types of Interrupts
Figure 10.1 shows types of interrupts.










Hardware
Special
(Non-Maskable Interrupt)















Interrupt
Software
(Non-Maskable Interrupt)
Undefined Instruction (UND Instruction)
Overflow (INTO Instruction)
BRK Instruction
BRK2 Instruction(2)
INT Instruction
_______
NMI
Watchdog Timer
Oscillation Stop Detection
Single-Step(2)
Address Match
DMACII
Peripheral Function(1)
(Maskable Interrupt)
NOTES:
1. The peripheral functions in the microcomputer are used to generate the peripheral interrupt.
2. Do not use this interrupt. For development support tools only.
Figure 10.1 Interrupts
• Maskable Interrupt
The I flag enables or disables an interrupt.
The interrupt priority order based on interrupt priority level can be changed.
• Non-Maskable Interrupt
The I flag does not enable nor disable an interrupt .
The interrupt priority order based on interrupt priority level cannot be changed.
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10. Interrupts
M32C/80 Group
10.2 Software Interrupts
Software interrupt occurs when an instruction is executed. The software interrupts are non-maskable interrupts.
10.2.1 Undefined Instruction Interrupt
The undefined instruction interrupt occurs when the UND instruction is executed.
10.2.2 Overflow Interrupt
The overflow interrupt occurs when the O flag in the FLG register is set to "1" (overflow of arithmetic
operation) and the INTO instruction is executed.
Instructions to set the O flag are :
ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA, SUB, SUBX
10.2.3 BRK Interrupt
The BRK interrupt occurs when the BRK instruction is executed.
10.2.4 BRK2 Interrupt
The BRK2 interrupt occurs when the BRK2 instruction is executed.
Do not use this interrupt. For development support tools only.
10.2.5 INT Instruction Interrupt
The INT instruction interrupt occurs when the INT instruction is executed. The INT instruction can select
software interrupt numbers 0 to 63. Software interrupt numbers 8 to 48 are assigned to the vector table
used for the peripheral function interrupt. Therefore, the microcomputer executes the same interrupt routine when the INT instruction is executed as when a peripheral function interrupt occurs.
When the INT instruction is executed, the FLG register and PC are saved to the stack. PC also stores the
relocatable vector of specified software interrupt numbers. Where the stack is saved varies depending
on a software interrupt number. ISP is selected as the stack for software interrupt numbers 0 to 31
(setting the U flag to "0"). SP, which is set before the INT instruction is executed, is selected as the stack
for software interrupt numbers 32 to 63 (the U flag is not changed).
With the peripheral function interrupt, the FLG register is saved and the U flag is set to "0" (ISP select)
when an interrupt request is acknowledged. With software interrupt numbers 32 to 48, SP to be used
varies depending on whether the interrupt is generated by the peripheral function interrupt request or by
the INT instruction.
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10. Interrupts
M32C/80 Group
10.3 Hardware Interrupts
Special interrupts and peripheral function interrupts are available as hardware interrupts.
10.3.1 Special Interrupts
Special interrupts are non-maskable interrupts.
______
10.3.1.1 NMI Interrupt
______
______
The NMI interrupt occurs when a signal applied to the NMI pin changes from a high-level ("H") signal
______
to a low-level ("L") signal. Refer to 10.8 NMI Interrupt for details.
10.3.1.2 Watchdog Timer Interrupt
The watchdog timer interrupt occurs when a count source of the watchdog timer underflows. Refer to
11. Watchdog Timer for details.
10.3.1.3 Oscillation Stop Detection Interrupt
The oscillation stop detection interrupt occurs when the microcomputer detects a main clock oscillation stop. Refer to 8. Clock Generation Circuit for details.
10.3.1.4 Single-Step Interrupt
Do not use the single-step interrupt. For development support tool only.
10.3.1.5 Address Match Interrupt
The address match interrupt occurs immediately before executing an instruction that is stored into an
address indicated by the RMADi register (i=0 to 7) when the AIERi bit in the AIER register is set to "1"
(address match interrupt enabled). Set the starting address of the instruction in the RMADi register.
The address match interrupt does not occur when a table data or addresses of the instruction other
than the starting address, if the instruction has multiple addresses, is set. Refer to 10.10 Address
Match Interrupt for details.
10.3.2 Peripheral Function Interrupt
The peripheral function interrupt occurs when a request from the peripheral functions in the microcomputer is acknowledged. The peripheral function interrupts and software interrupt numbers 8 to 48 for
the INT instruction use the same interrupt vector table. The peripheral function interrupt is a maskable
interrupt.
See Table 10.2 about how the peripheral function interrupt occurs. Refer to the descriptions of each
function for details.
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10. Interrupts
M32C/80 Group
10.4 High-Speed Interrupt
The high-speed interrupt executes an interrupt sequence in five cycles and returns from the interrupt in
three cycles.
When the FSIT bit in the RLVL register is set to "1" (interrupt priority level 7 available for the high-speed
interrupt), the ILVL2 to ILVL0 bits in the interrupt control registers can be set to "1112" (level 7) to use the
high-speed interrupt.
Only one interrupt can be set as the high-speed interrupt. When using the high-speed interrupt, do not set
multiple interrupts to interrupt priority level 7. Set the DMAII bit in the RLVL register to "0" (interrupt priority
level 7 available for interrupts).
Set the starting address of the high-speed interrupt routine in the VCT register.
When the high-speed interrupt is acknowledged, the FLG register is saved into the SVF register and PC is
saved into the SVP register. The program is executed from an address indicated by the VCT register.
Execute the FREIT instruction to return from the high-speed interrupt routine.
The values saved into the SVF and SVP registers are restored to the FLG register and PC by executing the
FREIT instruction.
The high-speed interrupt and the DMA2 and DMA3 use the same register. When using the high-speed
interrupt, neither DMA2 nor DMA3 is available. DMA0 and DMA1 can be used.
10.5 Interrupts and Interrupt Vectors
There are four bytes in one vector. Set the starting address of interrupt routine in each vector table. When
an interrupt request is acknowledged, the interrupt routine is executed from the address set in the interrupt
vectors.
Figure 10.2 shows the interrupt vector.
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
MSB
LSB
Vector Address + 0
Low-order bits of an address
Vector Address + 1
Middle-order bits of an address
Vector Address + 2
High-order bits of an address
Vector Address + 3
0016
Figure 10.2 Interrupt Vector
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10. Interrupts
M32C/80 Group
10.5.1 Fixed Vector Tables
The fixed vector tables are allocated addresses FFFFDC16 to FFFFFF16. Table 10.1 lists the fixed vector
tables.
Table 10.1 Fixed Vector Table
Interrupt
Generated by
Vector Addresses
Low address to High address
Remarks
Undefined
Instruction
FFFFDC16 to FFFFDF16
Overflow
FFFFE016 to FFFFE316
BRK Instruction
FFFFE416 to FFFFE716
Address Match
FFFFE816 to FFFFEB16
-
FFFFEC16 to FFFFEF16
Reserved space
Watchdog Timer
FFFFF016 to FFFFF316
These addresses are used for the
watchdog timer interrupt and
oscillation stop detection interrupt
-
FFFFF416 to FFFFF716
Reserved space
NMI
FFFFF816 to FFFFFB16
Reset
FFFFFC16 to FFFFFF16
Reference
M32C/80 Series Software
Manual
If the content of address FFFFE716
is FF16, a program is executed
from the address stored into
software interrupt number 0 in the
relocatable vector table
Reset,
Clock Generation Circuit,
Watchdog Timer
Reset
10.5.2 Relocatable Vector Tables
The relocatable vector tables occupy 256 bytes from the starting address set in the INTB register. Table
10.2 lists the relocatable vector tables.
Set an even address as the starting address of the vector table set in the INTB register to increase
interrupt sequence execution rate.
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10. Interrupts
M32C/80 Group
Table 10.2 Relocatable Vector Tables
Interrupt Generated by
Vector Table Address
Address(L) to Address(H)(1)
Software
Reference
Interrupt Number
BRK Instruction(2)
+0 to +3 (000016 to 000316)
0
M32C/80 Series
Reserved Space
+4 to +31 (000416 to 001F16)
1 to 7
Software Manual
DMA0
+32 to +35 (002016 to 002316)
8
DMAC
DMA1
+36 to +39 (002416 to 002716)
9
DMA2
+40 to +43 (002816 to 002B16)
10
DMA3
+44 to +47 (002C16 to 002F16)
11
Timer A0
+48 to +51 (003016 to 003316)
12
Timer A1
+52 to +55 (003416 to 003716)
13
Timer A2
+56 to +59 (003816 to 003B16)
14
Timer A3
+60 to +63 (003C16 to 003F16)
15
+64 to +67 (004016 to 004316)
16
+68 to +71 (004416 to 004716)
17
+72 to +75 (004816 to 004B16)
18
+76 to +79 (004C16 to 004F16)
19
UART1 Reception, ACK (3)
+80 to +83 (005016 to 005316)
20
Timer B0
+84 to +87 (005416 to 005716)
21
Timer B1
+88 to +91 (005816 to 005B16)
22
Timer B2
+92 to +95 (005C16 to 005F16)
23
Timer B3
+96 to +99 (006016 to 006316)
24
Timer B4
+100 to +103 (006416 to 006716)
25
Timer A4
UART0 Transmission,
NACK(3)
UART0 Reception, ACK(3)
UART1 Transmission,
NACK(3)
Timer A
Serial I/O
Timer B
________
INT5
+104 to +107 (006816 to 006B16) 26
Interrupt
________
INT4
+108 to +111 (006C16 to 006F16) 27
________
INT3
+112 to +115 (007016 to 007316)
28
+116 to +119 (007416 to 007716)
29
________
INT2
________
INT1
+120 to +123 (007816 to 007B16) 30
_______
INT0
+124 to +127 (007C16 to 007F16) 31
Timer B5
UART2 Transmission,
NACK(3)
UART2 Reception, ACK(3)
UART3 Transmission,
Timer B
+132 to +135 (008416 to 008716)
33
Serial I/O
+140 to +143 (008C16 to 008F16) 35
NACK(3)
UART4 Reception, ACK(3)
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32
+136 to +139 (008816 to 008B16) 34
NACK(3)
UART3 Reception, ACK(3)
UART4 Transmission,
+128 to +131 (008016 to 008316)
+144 to +147 (009016 to 009316)
36
+148 to +151 (009416 to 009716)
37
+152 to +155 (009816 to 009B16) 38
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10. Interrupts
M32C/80 Group
Table 10.2 Relocatable Vector Tables (Continued)
Interrupt Generated by
Vector Table Address
Address(L) to Address(H)(1)
Software
Interrupt Number
Bus Conflict Detect, Start Condition Detect, +156 to +159 (009C16 to 009F16) 39
Reference
Serial I/O
Stop Condition Detect (UART2)(3),
Bus Conflict Detect, Start Condition Detect, +160 to +163 (00A016 to 00A316) 40
Stop Condition Detect (UART3/UART0)(4)
Bus Conflict Detect, Start Condition Detect, +164 to +167 (00A416 to 00A716) 41
Stop Condition Detect (UART4/UART1)(4)
A/D0
+168 to +171 (00A816 to 00AB16) 42
A/D Converter
Key Input
+172 to +175 (00AC16 to 00AF16) 43
Interrupts
Intelligent I/O Interrupt 0
+176 to +179 (00B016 to 00B316) 44
Intelligent I/O
Intelligent I/O Interrupt 1
+180 to +183 (00B416 to 00B716) 45
Intelligent I/O Interrupt 2
+184 to +187 (00B816 to 00BB16) 46
Intelligent I/O Interrupt 3
+188 to +191 (00BC16 to 00BF16) 47
Intelligent I/O Interrupt 4
+192 to +195 (00C016 to 00C316) 48
INT Instruction(2)
+0 to +3 (000016 to 000316) to
0 to 63
Interrupts
+252 to +255 (00FC16 to 00FF16)
NOTES:
1. These addresses are relative to those in the INTB register.
2. The I flag does not disable interrupts.
3. In I2C mode, NACK, ACK or start/stop condition detection causes interrupts to be generated.
4. The IFSR6 bit in the IFSR register determines whether these addresses are used for an interrupt in UART0 or in
UART3.
The IFSR7 bit in the IFSR register determines whether these addresses are used for an interrupt in UART1 or in
UART4.
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10. Interrupts
M32C/80 Group
10.6 Interrupt Request Acknowledgement
Software interrupts and special interrupts occur when conditions to generate an interrupt are met.
The peripheral function interrupts are acknowledged when all conditions below are met.
• I flag
= "1"
• IR bit
= "1"
• ILVL2 to ILVL0 bits
> IPL
The I flag, IPL, IR bit and ILVL2 to ILVL0 bits are independent of each other. The I flag and IPL are in the
FLG register. The IR bit and ILVL2 to ILVL0 bits are in the interrupt control register.
10.6.1 I Flag and IPL
The I flag enables or disables maskable interrupts. When the I flag is set to "1" (enable), all maskable
interrupts are enabled; when the I flag is set to "0" (disable), they are disabled. The I flag is automatically
set to "0" after reset.
IPL, consisting of three bits, indicates the interrupt priority level from level 0 to level 7.
If a requested interrupt has higher priority level than indicated by IPL, the interrupt is acknowledged.
Table 10.3 lists interrupt priority levels associated with IPL.
Table 10.3 Interrupt Priority Levels
IPL2
IPL1
IPL0
Interrupt Priority Levels
0
0
0
Level 1 and above
0
0
1
Level 2 and above
0
1
0
Level 3 and above
0
1
1
Level 4 and above
1
0
0
Level 5 and above
1
0
1
Level 6 and above
1
1
0
Level 7 and above
1
1
1
All maskable interrupts are disabled
10.6.2 Interrupt Control Register and RLVL Register
The peripheral function interrupts use interrupt control registers to control each interrupt. Figures 10.3
and 10.4 show the interrupt control register. Figure 10.5 shows the RLVL register.
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10. Interrupts
M32C/80 Group
Interrupt Control Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TA0IC to TA4IC
Address
006C16, 008C16, 006E16, 008E16, 007016
009416, 007616, 009616, 007816, 009816, 006916
TB0IC to TB5IC
S0TIC to S4TIC
S0RIC to S4RIC
BCN0IC to BCN4IC
DM0IC to DM3IC
AD0IC
KUPIC
IIO0IC to IIO4IC
Bit
Symbol
009016, 009216, 008916, 008B16, 008D16
007216, 007416, 006B16, 006D16, 006F16
007116, 009116, 008F16, 007116(1), 009116(2)
006816, 008816, 006A16, 008A16
007316
009316
007516, 009516, 007716, 009716, 007916
Bit Name
After Reset
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
Function
RW
b2b1b0
ILVL0
ILVL1
Interrupt Priority Level
Select Bit
ILVL2
IR
Interrupt Request Bit
0 0 0: Level 0 (interrupt disabled)
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
1 0 1: Level 5
1 1 0: Level 6
1 1 1: Level 7
0: No interrupt requested
1: Interrupt requested(3)
Nothing is assigned. When write, set to "0".
(b7 - b4) When read, its content is indeterminate.
NOTES:
1. The BCN0IC register shares an address with the BCN3IC register.
2. The BCN1IC register shares an address with the BCN4IC register.
3. The IR bit can be set to "0" only (do not set to "1").
Figure 10.3 Interrupt Control Register (1)
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RW
RW
RW
RW
10. Interrupts
M32C/80 Group
Interrupt Control Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
INT0IC to INT2IC
Address
009E16, 007E16, 009C16
After Reset
XX00 X0002
INT3IC to INT5IC(1)
007C16, 009A16, 007A16
XX00 X0002
Bit
Symbol
Bit Name
Function
RW
b2b1b0
ILVL0
ILVL1
Interrupt Priority Level
Select Bit
ILVL2
0 0 0: Level 0 (interrupt disabled)
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
1 0 1: Level 5
1 1 0: Level 6
1 1 1: Level 7
RW
RW
RW
Interrupt Request Bit
0: Requests no interrupt
1: Requests an interrupt(2)
RW
POL
Polarity Switch Bit
0: Selects falling edge or "L"(3)
1: Selects rising edge or "H"
RW
LVS
Level Sensitive/Edge
Sensitive Switch Bit
0: Edge sensitive
1: Level sensitive(4)
RW
IR
Nothing is assigned. When write, set to "0".
(b7 - b6) When read, its content is indeterminate.
NOTES:
1. When a 16-bit data bus is used in microprocessor or memory expansion mode, each INT3 to INT5
pin is used as the data bus. Set the ILVL2 to ILVL0 bits in the INT3IC, INT4IC and INT5IC registers
to "0002".
2. The IR bit can be set to "0" only (do not set to "1").
3. Set the POL bit to "0" when a corresponding bit in the IFSR register is set to "1" (both edges).
4. When setting the LVS bit to "1" , set a corresponding bit in the IFSR register to "0" (one edge).
Figure 10.4 Interrupt Control Register (2)
10.6.2.1 ILVL2 to ILVL0 Bits
The ILVL2 to ILVL0 bits determines an interrupt priority level. The higher the interrupt priority level is,
the higher interrupt priority is.
When an interrupt request is generated, its interrupt priority level is compared to IPL. This interrupt is
acknowledged only when its interrupt priority level is higher than IPL. When the ILVL2 to ILVL0 bits
are set to "0002" (level 0), its interrupt is ignored.
10.6.2.2 IR Bit
The IR bit is automatically set to "1" (interrupt requested) when an interrupt request is generated. The
IR bit is automatically set to "0" (no interrupt requested) after an interrupt request is acknowledged and
an interrupt routine in the corresponding interrupt vector is executed.
The IR bit can be set to "0" by program. Do not set to "1".
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10. Interrupts
M32C/80 Group
Exit Priority Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
RLVL
Bit
Symbol
Address
009F16
Bit Name
Function
b2b1b0
RLVL0
RLVL1
After Reset
XXXX 00002
Stop/Wait Mode Exit
Minimum Interrupt
Priority Level Control
Bit(1)
RLVL2
0 0 0: Level 0
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
1 0 1: Level 5
1 1 0: Level 6
1 1 1: Level 7
0: Interrupt priority level 7 is used
for normal interrupt
1: Interrupt priority level 7 is used
for high-speed interrupt
FSIT
High-speed Interrupt
Set Bit(2)
(b4)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
DMAII
DMA II Select
Bit(4)
0: Interrupt priority level 7 is used
for interrupt
1: Interrupt priority level 7 is used
for DMA II transfer(3)
RW
RW
RW
RW
RW
RW
Nothing is assigned. When write, set to "0".
(b7 - b6) When read, its content is indeterminate.
NOTES:
1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than
the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in
the FLG register.
2. When the FSIT bit is set to "1", an interrupt having the interrupt priority level 7 becomes the high-speed
interrupt. In this case, set only one interrupt to the interrupt priority level 7 and the DMAII bit to "0".
3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1".
Do not change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0"
when the DMAII bit to "1".
4. The DMAII bit becomes indeterminate after reset. To use the DMAII bit for an interrupt setting, set it
to "0" before setting the interrupt control register.
Figure 10.5 RLVL Register
10.6.2.3 RLVL2 to RLVL0 Bits
When using an interrupt to exit stop or wait mode, refer to 8.5.2 Wait Mode and 8.5.3 Stop Mode for
details.
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10. Interrupts
M32C/80 Group
10.6.3 Interrupt Sequence
The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine
execution.
When an interrupt request is generated while an instruction is executed, the CPU determines its interrupt
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following
cycle. However, in regards to the SCMPU, SIN, SMOVB, SMOVF, SMOVU, SSTR, SOUT or RMPA
instruction, if an interrupt request is generated while executing the instruction, the microcomputer suspends the instruction to start the interrupt sequence.
The interrupt sequence is performed as follows:
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading
address 00000016 (address 00000216 for the high-speed interrupt). Then, the IR bit applicable to
the interrupt information is set to "0" (interrupt requested).
(2) The FLG register, prior to an interrupt sequence, is saved to a temporary register(1) within the CPU.
(3) Each bit in the FLG register is set as follows:
• The I flag is set to "0" (interrupt disabled)
• The D flag is set to "0" (single-step disabled)
• The U flag is set to "0" (ISP selected)
(4) A temporary register within the CPU is saved to the stack; or to the SVF register for the high-speed
interrupt.
(5) PC is saved to the stack; or to the SVP register for the high-speed interrupt.
(6) The interrupt priority level of the acknowledged interrupt is set in IPL .
(7) A relocatable vector corresponding to the acknowledged interrupt is stored into PC.
After the interrupt sequence is completed, an instruction is executed from the starting address of the
interrupt routine.
NOTE:
1. Temporary register cannot be modified by users.
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10. Interrupts
M32C/80 Group
10.6.4 Interrupt Response Time
Figure 10.6 shows an interrupt response time. Interrupt response time is the period between an interrupt
generation and the execution of the first instruction in an interrupt routine. Interrupt response time includes the period between an interrupt request generation and the completed execution of an instruction
((a) on Figure 10.6) and the period required to perform an interrupt sequence ((b) on Figure 10.6).
Interrupt request is generated
Interrupt request is acknowledged
Time
Instruction
(a)
Interrupt sequence
Instruction in
interrupt routine
(b)
Interrupt response time
(a) Period between an interrupt request generation and the completed execution of an instruction.
(b) Period required to perform an interrupt sequence.
Figure 10.6 Interrupt Response Time
Time (a) varies depending on an instruction being executed. The DIV, DIVX and DIVU instructions
require the longest time (a); 42 cycles when an immediate value or register is set as the divisor.
When the divisor is a value in the memory, the following value is added.
• Normal addressing
:2+X
• Index addressing
:3+X
• Indirect addressing
: 5 + X + 2Y
• Indirect index addressing
: 6 + X + 2Y
X is the number of wait states for a divisor space. Y is the number of wait states for the space that stores
indirect addresses. If X and Y are in an odd address or in 8-bit bus space, the X and Y value must be
doubled.
Table 10.4 lists time (b), shown Figure 10.6.
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10. Interrupts
M32C/80 Group
Table 10.4 Interrupt Sequence Execution Time
Interrupt
Interrupt Vector Address
Peripheral Function
16-Bit Bus
8-Bit Bus
Even address
14 cycles
16 cycles
Odd address(1)
16 cycles
16 cycles
Even address
12 cycles
14 cycles
Odd address(1)
14 cycles
14 cycles
Even address(2)
13 cycles
15 cycles
Overflow
Even address(2)
14 cycles
16 cycles
BRK Instruction (relocatable vector table)
Even address
17 cycles
19 cycles
Odd address(1)
19 cycles
19 cycles
BRK Instruction (fixed vector table)
Even address(2)
19 cycles
21 cycles
High-speed Interrupt
Vector table is internal register
5 cycles
INT Instruction
_______
NMI
Watchdog Timer
Undefined Instruction
Address Match
NOTES:
1. Allocate interrupt vectors in even addresses.
2. Vectors are fixed to even addresses.
10.6.5 IPL Change when Interrupt Request is Acknowledged
When a peripheral function interrupt request is acknowledged, IPL sets the priority level for the acknowledged interrupt.
Software interrupts and special interrupts have no interrupt priority level. If an interrupt request that has
no interrupt priority level is acknowledged, the value shown in Table 10.5 is set in IPL as the interrupt
priority level.
Table 10.5 Interrupts without Interrupt Priority Levels and IPL
Interrupt Source
Level Set to IPL
_______
Watchdog Timer, NMI, Oscillation Stop Detection
7
Reset
0
Software, Address Match
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10. Interrupts
M32C/80 Group
10.6.6 Saving a Register
In the interrupt sequence, the FLG register and PC are saved to the stack.
After the FLG register is saved to the stack, 16 high-order bits and 16 low-order bits of PC, extended to 32
bits, are saved to the stack. Figure 10.7 shows stack states before and after an interrupt request is
acknowledged.
Other important registers are saved by program at the beginning of an interrupt routine. The PUSHM
instruction can save several registers(1) in the register bank used.
Refer to 10.4 High-Speed Interrupt for the high-speed interrupt.
NOTE:
1. Can be selected from the R0, R1, R2, R3, A0, A1, SB and FB registers.
Address
The Stack
Address
LSB
MSB
m-6
The Stack
MSB
m-6
LSB
PCL
PCM
m-5
m-5
m–4
m–4
PCH
m–3
m–3
00 16
m–2
m–2
FLG L
m–1
m–1
m
Content of
previous stack
m+1
Content of
previous stack
[SP]
SP value before
an interrupt is
generated
m
m+1
Stack state before an interrupt request is acknowledged
[SP]
New SP value
FLGH
Content of
previous stack
Content of
previous stack
Stack state after an interrupt request is acknowledged
Figure 10.7 Stack States
10.6.7 Restoration from Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC before the
interrupt sequence is performed, which have been saved to the stack, are automatically restored. The program, executed before an interrupt request was acknowledged, starts running again. Refer to 10.4 HighSpeed Interrupt for the high-speed interrupt.
Restore registers saved by program in an interrupt routine by the POPM instruction or others before the
REIT and FREIT instructions. Register bank is switched back to the bank used prior to the interrupt
sequence by the REIT or FREIT instruction.
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10. Interrupts
M32C/80 Group
10.6.8 Interrupt Priority
If two or more interrupt requests are sampled at the same sampling points (a timing to detect whether an
interrupt request is generated or not), the interrupt with the highest priority is acknowledged.
Set the ILVL2 to ILVL0 bits to select the desired priority level for maskable interrupts (peripheral function
interrupt).
Priority levels of special interrupts such as reset (reset has the highest priority) and watchdog timer are
set by hardware. Figure 10.8 shows priority levels of hardware interrupts.
The interrupt priority does not affect software interrupts. Executing instruction causes the microcomputer
to execute an interrupt routine.
_______
Reset > NMI > Oscillation Stop Detection > Peripheral Function > Address Match
Watchdog
Figure 10.8 Interrupt Priority
10.6.9 Interrupt Priority Level Select Circuit
The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt
requests are sampled at the same sampling point.
Figure 10.9 shows the interrupt priority level select circuit.
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10. Interrupts
M32C/80 Group
High
Each Interrupt Priority Level
Level 0 (Initial Value)
DMA0
DMA1
DMA2
DMA3
Timer A0
Each Interrupt Priority Level
Timer A1
A/D0
Timer A2
Key Input Interrupt
Timer A3
Intelligent I/O Interrupt 0
Timer A4
Intelligent I/O Interrupt 1
UART0 Transmission/NACK
Intelligent I/O Interrupt 2
UART0 Reception/ACK
Intelligent I/O Interrupt 3
UART1 Transmission/NACK
Intelligent I/O Interrupt 4
UART1 Reception/ACK
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
INT5
RLVL2 to RLVL0 Bits
INT4
Interrupt request priority
detection results output
(to the clock generation
circuit)
INT3
INT2
IPL
INT1
INT0
I Flag
Timer B5
Address Match
Watchdog Timer,
Oscillation Stop Detection
UART2 Transmission/NACK
NMI
UART2 Reception/ACK
DMAC II
UART3 Transmission/NACK
UART3 Reception/ACK
UART4 Transmission/NACK
UART4 Reception/ACK
Bus Conflict/Start, Stop
Condition(UART2)
Bus Conflict/Start, Stop Condition
(UART0, UART3)
Bus Conflict/Start, Stop Condition
(UART1, UART4)
Low
Peripheral Function Interrupt Priority
(if priority levels are the same)
Figure 10.9 Interrupt Priority Level Select Circuit
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Interrupt request
acknowledged
(to CPU)
10. Interrupts
M32C/80 Group
______
10.7 INT Interrupt
______
External input generates the INTi interrupt (i = 0 to 5). The LVS bit in the INTiIC register selects either edge
sensitive triggering to generate an interrupt on any edge or level sensitive triggering to generate an interrupt at an applied signal level. The POL bit in the INTiIC register determines the polarity.
For edge sensitive, when the IFSRi bit in the IFSR register is set to "1", an interrupt occurs on both rising
and falling edges of the external input. If the IFSRi bit is set to "1", set the POL bit in the corresponding
register to "0" (falling edge).
_______
For level sensitive, set the IFSRi bit to "0" (single edge). When the INTi pin input level reaches the level set
_______
in the POL bit, the IR bit in the INTiIC register is set to "1". The IR bit remains unchanged even if the INTi
_______
pin level is changed. The IR bit is set to "0" when the INTi interrupt is acknowledged or when the IR bit is
written to "0" by program.
Figure 10.10 shows the IFSR register.
External Interrupt Request Source Select Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IFSR
Bit
Symbol
Address
031F16
Bit Name
After Reset
0016
Function
IFSR0
INT0 Interrupt Polarity
Select Bit(1)
0: One edge
1 : Both edges
RW
IFSR1
INT1 Interrupt Polarity
Select Bit(1)
0: One edge
1: Both edges
RW
IFSR2
INT2 Interrupt Polarity
Select Bit(1)
0: One edge
1: Both edges
RW
IFSR3
INT3 Interrupt Polarity
Select Bit(1)
0: One edge
1: Both edges
RW
IFSR4
INT4 Interrupt Polarity
select bit(1)
0: One edge
1: Both edges
RW
IFSR5
INT5 Interrupt Polarity
Select Bit(1)
0: One edge
1: Both edges
RW
IFSR6
UART0, UART3
Interrupt Source
Select Bit
0: UART3 bus conflict, start condition
detect, stop condition detect
RW
1: UART0 bus conflict, start condition
detect, stop condition detect
IFSR7
UART1, UART4
Interrupt Source
Select Bit
0: UART4 bus conflict, start condition
detect, stop condition detect
RW
1: UART1 bus conflict, start condition
detect, stop condition detect
NOTE:
1. Set this bit to "0" to select a level-sensitive triggering.
When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge).
Figure 10.10 IFSR Register
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10. Interrupts
M32C/80 Group
______
10.8 NMI Interrupt
______
______
The NMI interrupt(1) occurs when a signal applied to the NMI pin changes from a high-level ("H") signal to a
______
______
low-level ("L") signal. The NMI interrupt is a non-maskable interrupt. Although the P85/NMI pin is used as
______
the NMI interrupt input pin, the P8_5 bit in the P8 register indicates the input level for this pin.
NOTE:
______
______
______
1. When the NMI interrupt is not used, connect the NMI pin to VCC1 via a resistor. Because the NMI
interrupt cannot be ignored, the pin must be connected.
10.9 Key Input Interrupt
Key input interrupt request is generated when one of the signals applied to the P104 to P107 pins in input
mode is on the falling edge. The key input interrupt can be also used as key-on wake-up function to exit wait
or stop mode. To use the key input interrupt, do not use P104 to P107 as A/D input ports. Figure 10.11
shows a block diagram of the key input interrupt. When an "L" signal is applied to any pins in input mode,
signals applied to other pins are not detected as an interrupt request signal.
When the PSC_7 bit in the PSC register(2) is set to "1" (key input interrupt disabled), no key input interrupt
occurs regardless of interrupt control register settings. When the PSC_7 bit is set to "1", no input from a
port pin is available even when in input mode.
NOTE:
2. Refer to 22. Programmable I/O Ports about the PSC register.
PU31 Bit in the
PUR3 Register
Pull-up
Transistor
PD10_7 Bit
PSC_7 Bit
KUPIC Register
PD10_7 Bit
P107/KI3
Pull-up
Transistor
PD10_6 Bit
Interrupt Control
Circuit
P106/KI2
Pull-up
Transistor
Key Input Interrupt
Request
PD10_5 Bit
P105/KI1
Pull-up
Transistor
PD10_4 Bit
P104/KI0
Figure 10.11 Key Input Interrupt
To use the intelligent I/O interrupt as a source to activate DMAC II, set the IRLT bit in the IIOiIE register to
"0" (interrupt request is used for DMAC, DMAC II) and enable an interrupt request source for the IIOiIE
register.
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10. Interrupts
M32C/80 Group
10.10 Address Match Interrupt
The address match interrupt occurs immediately before executing an instruction that is stored into an address indicated by the RMADi register (i=0 to 7). The address match interrupt can be set in eight addresses. The AIERi bit in the AIER register determines whether the interrupt is enabled or disabled. The I
flag and IPL do not affect the address match interrupt.
Figure 10.12 shows registers associated with the address match interrupt.
The starting address of an instruction must be set in the RMADi register. The address match interrupt does
not occur when a table data or addresses other than the starting address of the instruction is set.
Address Match Interrupt Enable Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AIER
Bit
Symbol
Address
000916
After Reset
0016
Function
Bit Name
RW
AIER0
Address Match
Interrupt 0 Enable Bit
0: Disables the interrupt
1: Enables the interrupt
RW
AIER1
Address Match
Interrupt 1 Enable Bit
0: Disables the interrupt
1: Enables the interrupt
RW
AIER2
Address Match
Interrupt 2 Enable Bit
0: Disables the interrupt
1: Enables the interrupt
RW
AIER3
Address Match
Interrupt 3 Enable Bit
0: Disables the interrupt
1: Enables the interrupt
RW
AIER4
Address Match
Interrupt 4 Enable Bit
0: Disables the interrupt
1: Enables the interrupt
RW
AIER5
Address Match
Interrupt 5 Enable Bit
0: Disables the interrupt
1: Enables the interrupt
RW
AIER6
Address Match
Interrupt 6 Enable Bit
0: Disables the interrupt
1: Enables the interrupt
RW
AIER7
Address Match
Interrupt 7 Enable Bit
0: Disables the interrupt
1: Enables the interrupt
RW
Address Match Interrupt Register i (i=0 to 7)
b23
b16 b15
b8 b7
b0
Symbol
RMAD0
RMAD1
RMAD2
RMAD3
RMAD4
RMAD5
RMAD6
RMAD7
Address
001216 - 001016
001616 - 001416
001A16 - 001816
001E16 - 001C16
002A16 - 002816
002E16 - 002C16
003A16 - 003816
003E16 - 003C16
Function
Addressing register for the address match interrupt
Figure 10.12 AIER Register and RMAD0 to RMAD7 Registers
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After Reset
00000016
00000016
00000016
00000016
00000016
00000016
00000016
00000016
Setting Range
RW
00000016 to FFFFFF16
RW
10. Interrupts
M32C/80 Group
10.11 Intelligent I/O Interrupt
The intelligent I/O interrupt is assigned to software interrupt numbers 44 to 48.
When using the intelligent I/O interrupt, set the IRLT bit in the IIOiIE register (i = 0 to 4) to "1" (interrupt
request for interrupt used).
Various interrupt requests cause the intelligent I/O interrupt to occur. When an interrupt request is generated with each intelligent I/O or CAN functions, the corresponding bit in the IIOiIR register is set to "1"
(interrupt requested). When the corresponding bit in the IIOiIE register is set to "1" (interrupt enabled),
the IR bit in the corresponding IIOiIC register is set to "1" (interrupt requested).
After the IR bit setting changes "0" to "1", the IR bit remains set to "1" when a bit in the IIOiIR register is
set to "1" by another interrupt request and the corresponding bit in the IIOiIE register is set to "1".
Bits in the IIOiIR register are not set to "0" automatically, even if an interrupt is acknowledged. Set each
bit to "0" by program. If these bit settings are left "1", all generated interrupt requests are ignored.
Figure 10.13 shows a block diagram of the intelligent I/O interrupt. Figure 10.14 shows the IIOiIR
register. Figure 10.15 shows the IIOiIE register.
IIOiIR Register(2)
IRLT Bit in the
IIOiIE Register
0
Bit 1
Interrupt Request(1)
1
Intelligent I/O Interrupt i Request
0
Bit 2
Interrupt Request(1)
1
0
Bit 7
Interrupt Request(1)
1
IIOiIE Register(3)
Bit 1
Bit 2
Bit 7
NOTES:
1. See Figures 10.14 and 10.15 about bits 7 to 1 in the
IIOiIR register and bits 1 to 7 in the IIOiIE register.
2. Bits 7 to 1 in the IIOiIR register are not set to "0"
automatically even if an interrupt request is
generated. Set to "0" by program.
3. Do not change the IRLT bit and the interrupt enable bit
in the IIOiIE register simultaneously.
i= 0 to 4
Figure 10.13 Intelligent I/O Interrupt
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10. Interrupts
M32C/80 Group
Interrupt Request Register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0
Symbol
IIO0IR to IIO4IR
Bit
Symbol
(b0)
Address
After Reset
See below
0000 000X2
RW
Function
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Reserved bit. Set to "0".
When read, its content is indeterminate.
RW
(Note 1)
0: Requests no interrupt
1: Requests an interrupt(2)
RW
(Note 1)
0: Requests no interrupt
1: Requests an interrupt(2)
RW
(Note 1)
0: Requests no interrupt
1: Requests an interrupt(2)
RW
(Note 1)
0: Requests no interrupt
1: Requests an interrupt(2)
RW
(b3 - b1)
NOTES:
1. See table below for bit symbols.
2. Only "0" can be set (nothing is changed even if "1" is set).
Bit Symbols for the Interrupt Request Register
Symbol
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IIO0IR
00A016
-
-
SIO0RR
G0RIR
-
-
-
-
IIO1IR
00A116
-
-
SIO0TR
G0TOR
-
-
-
-
IIO2IR
00A216
-
-
SIO1RR
G1RIR
-
-
-
-
IIO3IR
00A316
-
-
SIO1TR
G1TOR
-
-
-
-
IIO4IR
00A416
SRT0R
SRT1R
-
-
-
-
-
-
SIOiRR: Intelligent I/O Communication Unit i Receive Interrupt Request
SIOiTR: Intelligent I/O Communication Unit i Transmit Interrupt Request
GiTOR: Intelligent I/O Communication Unit i HDLC Data Processing Function Interrupt Request (TO: Output to Transmit)
GiRIR: Intelligent I/O Communication Unit i HDLC Data Processing Function Interrupt Request (RI: Input to Receive)
SRTiR: Intelligent I/O Special Communication Function Interrupt Request
-: Reserved Bit. Set to "0"
Figure 10.14 IIO0IR to IIO4IR Registers
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i=0, 1
10. Interrupts
M32C/80 Group
Interrupt Enable Register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0
Symbol
IIO0IE to IIO4IE
Address
After Reset
See below
0016
Bit
Symbol
Bit Name
IRLT
Interrupt Request
Select Bit(2)
0: Interrupt request is used for DMAC, DMAC II
1: Interrupt request is used for interrupt
RW
Reserved Bit
Set to "0"
RW
0: Disables an interrupt by bit 4 in IIOiIR register
1: Enables an interrupt by bit 4 in IIOiIR register
RW
(b3 - b1)
RW
Function
(Note 1)
0: Disables an interrupt by bit 5 in IIOiIR register
(Note 1)
1: Enables an interrupt by bit 5 in IIOiIR register
0: Disables an interrupt by bit 6 in IIOiIR register
(Note 1)
1: Enables an interrupt by bit 6 in IIOiIR register
0: Disables an interrupt by bit 7 in IIOiIR register
1: Enables an interrupt by bit 7 in IIOiIR register
(Note 1)
RW
RW
RW
NOTES:
1. See table below for bit symbols.
2. If an interrupt request is used for interrupt, set bit 1, 2, 4 to 7 to "1" after the IRLT bit is set to "1".
Bit Symbols for the Interrupt Enable Register
Symbol
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IIO0IE
00B016
-
-
SIO0RE
G0RIE
-
-
-
IRLT
IIO1IE
00B116
-
-
SIO0TE
G0TOE
-
-
-
IRLT
IIO2IE
00B216
-
-
SIO1RE
G1RIE
-
-
-
IRLT
IIO3IE
00B316
-
-
SIO1TE
G1TOE
-
-
-
IRLT
IIO4IE
00B416
SRT0E
SRT1E
-
-
-
-
-
IRLT
SIOiRE: Intelligent I/O Communication Unit i Receive Interrupt Enabled
SIOiTE: Intelligent I/O Communication Unit i Transmit Interrupt Enabled
GiTOE: Intelligent I/O Communication Unit i HDLC Data Processing Function Interrupt Enabled (TO: Output to Transmit)
GiRIE: Intelligent I/O Communication Unit i HDLC Data Processing Function Interrupt Enabled (RI: Input to Receive)
SRTiE: Intelligent I/O Special Communication Function Interrupt Enabled
i=0, 1
-: Reserved Bit. Set to "0".
Figure 10.15 IIO0IE to IIO4IE Registers
Rev. 1.00 Nov. 01, 2005 Page 104 of 330
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11. Watchdog Timer
M32C/80 Group
11. Watchdog Timer
The watchdog timer monitors the program executions and detects defective program. It allows the microcomputer to trigger a reset or to generate an interrupt if the program error occurs. The watchdog timer
contains a 15-bit counter, which is decremented by the CPU clock that the prescaler divides. The CM06 bit
in the CM0 register determines whether a watchdog timer interrupt request or reset is generated if the
watchdog timer underflows. Once the CM06 bit is set to "1", it cannot be changed to "0" ( watchdog timer
interrupt) by program. The CM06 bit is set to "0" only after reset.
When the main clock, on-chip oscillator clock, or PLL clock runs as the CPU clock, the WDC7 bit in the
WDC register determine whether the prescaler divides the clock by 16 or by 128. When the sub clock runs
as the CPU clock, the prescaler divides the clock by 2 regardless of the WDC7 bit setting. Watchdog timer
cycle is calculated as follows. Marginal errors, due to the prescaler, may occur in watchdog timer cycle.
When the main clock, on-chip oscillator clock, or PLL clock is selected as the CPU clock,
Watchdog timer cycle =
Divide-by-16 or -128 prescaler x counter value of watchdog timer (32768)
CPU clock
When the sub clock is selected as the CPU clock,
Watchdog timer cycle =
Divide-by-2 prescaler x counter value of watchdog timer (32768)
CPU clock
For example, if the CPU clock frequency is 30MHz and the prescaler divides it by 16, the watchdog timer
cycle is approximately 17.5 ms.
The watchdog timer is reset when the WDTS register is set and when a watchdog timer interrupt request is
generated. The prescaler is reset only when the microcomputer is reset. Both watchdog timer and prescaler
stop after reset. They begin counting when the WDTS register is set.
The watchdog timer and prescaler stop in stop mode, wait mode and hold state. They resume counting
from the value held when the mode or state is exited.
Figure 11.1 shows a block diagram of the watchdog timer. Figure 11.2 shows registers associated with the
watchdog timer.
Prescaler
1/16
CPU Clock
1/128
CM07 = 0
WDC7 = 0
CM07 = 0
WDC7 = 1
PM22 = 0
CM06 = 0
HOLD Signal
Watchdog Timer
Interrupt Request
CM07 = 1
Watchdog Timer
1/2
Reset
CM06 = 1
On-chip Oscillator Clock
Write to WDTS Register
Internal Reset Signal
CM06, CM07: Bits in the CM0 Register
WDC7: Bit in the WDC Register
PM22: Bit in the PM2 Register
Figure 11.1 Watchdog Timer Block Diagram
Rev. 1.00 Nov. 01, 2005 Page 105 of 330
REJ09B0271-0100
PM22 = 1
Set to
7FFF16
11. Watchdog Timer
M32C/80 Group
Watchdog Timer Control Register
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
WDC
Address
000F16
Bit
Symbol
(b4 - b0)
(b5)
(b6)
WDC7
After Reset
000X XXXX2
Bit Name
Function
RW
RO
High-Order Bit of the Watchdog Timer
Reserved Bit
When read,
its content is inderterminate
RW
Reserved Bit
Set to "0"
RW
Prescaler Select Bit
0: Divide-by-16
1: Divide-by-128
RW
Watchdog Timer Start Register(1)
b7
b0
Symbol
WDTS
Address
000E16
After Reset
Indeterminate
Function
The watchdog timer is reset to start counting by a write instruction to the
WDTS register. Default value of the watchdog timer is always set to
"7FFF16" regardless of the value written.
NOTE:
1. Write the WDTS register after the watchdog timer interrupt is generated.
Figure 11.2 WDC Register and WDTS Register
Rev. 1.00 Nov. 01, 2005 Page 106 of 330
REJ09B0271-0100
RW
WO
11. Watchdog Timer
M32C/80 Group
System Clock Control Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CM0
Bit
Symbol
Address
000616
After Reset
0000 10002
Bit Name
Function
b1 b0
CM00
Clock Output Function
Select Bit(2)
CM01
0 0: I/O port P53
0 1: Outputs fC
1 0: Outputs f8
1 1: Outputs f32
RW
RW
RW
CM02
0: Peripheral clock does not stop in
In Wait Mode, Peripheral
wait mode
Function Clock Stop Bit(9) 1: Peripheral clock stops in wait
mode(3)
CM03
XCIN-XCOUT Drive
Capacity Select Bit(11)
0: Low
1: High
RW
CM04
Port XC Switch Bit
0: I/O port function
1: XCIN-XCOUT oscillation function(4)
RW
CM05
Main Clock (XIN-XOUT)
Stop Bit(5, 9)
0: Main clock oscillates
1: Main clock stops(6)
RW
CM06
Watchdog Timer
Function Select Bit
0: Watchdog timer interrupt
1: Reset(7)
RW
CM07
CPU Clock Select
Bit 0(8, 9, 10)
0: Clock selected by the CM21 bit
divided by MCD register setting
1: Sub clock
RW
RW
NOTES:
1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), set the CM01 and CM00 bits to
"002". When the PM15 and PM14 bits in the PM1 register are set to "012" (ALE output to P53), set the
CM01 and CM00 bits to "002". When the PM07 bit is set to "1" (function selected in the CM01 and
CM00 bits) in microprocessor or memory expansion mode, and the CM01 and CM00 bits are set to
"002", an "L" signal is output from port P53 (port P53 does not function as an I/O port).
3. fc32 does not stop running. When the CM02 bit is set to "1", the PLL clock cannot be used in wait
mode.
4. When setting the CM04 bit is set to "1", set the PD8_7 and PD8_6 bits in the PD8 register to "002"
(port P87 and P86 in input mode) and the PU25 bit in the PUR2 register to "0" (no pull-up).
5. When entering low-power consumption mode or on-chip oscillator low-power consumption mode, the
CM05 bit stops running the main clock. The CM05 bit cannot detect whether the main clock stops or
not. To stop running the main clock, set the CM05 bit to "1" after the CM07 bit is set to "1" with a stable
sub clock oscillation or after the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock).
When the CM05 bit is set to "1", the clock applied to XOUT becomes "H". The built-in feedback resistor
remains ON. XIN is pulled up to XOUT ("H" level) via the feedback resistor.
6. When the CM05 bit is set to "1", the MCD4 to MCD0 bits in the MCD register are set to "010002"
(divide-by-8 mode). In on-chip oscillation mode, the MCD4 to MCD0 bits are not set to "010002" even
if the CM05 bit terminates XIN-XOUT.
7. Once the CM06 bit is set to "1", it cannot be set to "0" by program.
8. After the CM04 bit is set to "1" with a stable sub clock oscillation, set the CM07 bit to "1" from "0".
After the CM05 bit is set to "0" with a stable main clock oscillation, set the CM07 bit to "0" from "1".
Do not set the CM07 bit and CM04 or CM05 bit simultaneously.
9. When the PM21 bit in the PM2 register is set to "1" (clock change disabled), the CM02, CM05 and
CM07 bits do not change even when written.
10. After the CM07 bit is set to "0", set the PM21 bit to "1".
11. When stop mode is entered, the CM03 bit is set to "1".
Figure 11.3 CM0 Register
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11. Watchdog Timer
M32C/80 Group
11.1 Count Source Protection Mode
In count source protection mode, the on-chip oscillator clock is used as a count source for the watchdog
timer. The count source protection mode allows the on-chip oscillator clock to run continuously, maintaining watchdog timer operation even if the program error occurs and the CPU clock stops running.
Follow the procedures below when using this mode.
(1) Set the PRC0 bit in the PRCR register to "1" (write to CM0 register enabled)
(2) Set the PRC1 bit in the PRCR register to "1" (write to PM2 register enabled)
(3) Set the CM06 bit in the CM0 register to "1" (reset when the watchdog timer overflows)
(4) Set the PM22 bit in the PM2 register to "1" (the on-chip oscillator clock as a count source of the watchdog timer)
(5) Set the PRC0 bit to "0" (write to CM0 register disabled)
(6) Set the PRC1 bit to "0" (write to PM2 register disabled)
(7) Write to the WDTS register (the watchdog timer starts counting)
The followings will occur when the PM22 bit is set to "1".
• The on-chip oscillator starts oscillating and the on-chip oscillator clock becomes a count source for
the watchdog timer.
Watchdog timer cycle =
Counter value of watchdog timer (32768)
On-chip oscillator clock
• Write to the CM10 bit in the CM1 register is disabled. (The bit setting remains unchanged even if set
it to "1". The microcomputer does not enter stop mode.)
• In wait mode or hold state, the watchdog timer continues running. However, the watchdog timer
interrupt cannot be used to exit wait mode.
Rev. 1.00 Nov. 01, 2005 Page 108 of 330
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12. DMAC
M32C/80 Group
12. DMAC
This microcomputer contains four DMAC (direct memory access controller) channels that allow data to be
sent to memory without using the CPU. DMAC transmits a 8- or 16-bit data from a source address to a
destination address whenever a transmit request occurs. DMA0 and DMA1 must be prioritized if using
DMAC. DMA2 and DMA3 share registers required for high-speed interrupts. High-speed interrupts cannot
be used when using three or more DMAC channels.
The CPU and DMAC use the same data bus, but DMAC has a higher bus access privilege than the CPU.
The cycle-steal method employed on DMAC enables high-speed operation between a transfer request and
the complete transmission of 16-bit (word) or 8-bit (byte) data. Figure 12.1 shows a mapping of registers to
be used for DMAC. Table 12.1 lists specifications of DMAC. Figures 12.2 to 12.5 show registers associated with DMAC.
Because the registers shown in Figure 12.1 are allocated in the CPU, use the LDC instruction to write to the
registers. To set the DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3 registers, set the B flag to "1" (register
bank 1) and set the R0 to R3, A0, A1 registers with the MOV instruction.
To set the DSA2 and DSA3 registers, set the B flag to "1" and set the SB and FB registers with the LDC
instruction. To set the DRA2 and DRA3 registers, set the SVP and VCT registers with the LDC instruction.
DMAC-associated Registers
DMD0
DMA Mode Register 0
DMD1
DMA Mode Register 1
DCT0
DMA 0 Transfer Count Register
DCT1
DMA 1 Transfer Count Register
DRC0
DMA 0 Transfer Count Reload Register(1)
DRC1
DMA 1 Transfer Count Reload Register(1)
DMA0
DMA 0 Memory Address Register
DMA1
DMA 1 Memory Address Register
DSA0
DMA 0 SFR Address Register
DSA1
DMA 1 SFR Address Register
DRA0
DMA 0 Memory Address Reload Register(1)
DRA1
DMA 1 Memory Address Reload Register(1)
When Three or More DMAC Channels are Used,
the Register Bank 1 is Used as DMAC Registers
When Three or More DMAC Channels are Used,
the High-speed Interrupt Register is Used as DMAC
Registers
Flag Save Register
DCT2 (R0)
DMA2 Transfer Count Register
SVF
DCT3 (R1)
DMA3 Transfer Count Register
DRA2 (SVP)
DMA2 Memory Address Reload Register(1)
DRC2 (R2)
DMA2 Transfer Count Reload Register(1)
DRA1 (VCT)
DMA3 Memory Address Reload Register(1)
DRC3 (R3)
DMA3 Transfer Count Reload Register(1)
DMA2 (A0)
DMA2 Memory Address Register
DMA3 (A1)
DMA3 Memory Address Register
DSA2 (SB)
DMA2 SFR Address Register
DSA3 (FB)
DMA3 SFR Address Register
NOTE:
1. Registers are used for repeat transfer, not for single transfer.
Figure 12.1 Register Mapping for DMAC
Rev. 1.00 Nov. 01, 2005 Page 109 of 330
REJ09B0271-0100
When using DMA2 and DMA3, use the CPU registers shown in parentheses ().
M32C/80 Group
12. DMAC
DMAC starts a data transfer by setting the DSR bit in the DMiSL register (i=0 to 3) or by using an interrupt
request, generated by the functions determined by the DSEL 4 to DSEL0 bits in the DMiSL register, as a
DMA request. Unlike interrupt requests, the I flag and interrupt control register do not affect DMA. Therefore, a DMA request can be acknowledged even if an interrupt is disabled and cannot be acknowledged. In
addition, the IR bit in the interrupt control register does not change when a DMA request is acknowledged.
Table 12.1 DMAC Specifications
Item
Specification
Channels
4 channels (cycle-steal method)
Transfer Memory Space
• From a desired address in a 16-Mbyte space to a fixed address in a
16-Mbyte space
• From a fixed address in a 16-Mbyte space to a desired address in a
16-Mbyte space
Maximum Bytes Transferred
128 Kbytes (when a 16-bit data is transferred) or 64 Kbytes (with an 8bit data is transferred)
________
________
DMA Request Source(1)
Falling edge or both edges of signals applied to the INT0 to INT3 pins
Timers A0 to A4 interrupt requests
Timers B0 to B5 interrupt requests
UART0 to UART4 transmit and receive interrupt requests
A/D0 conversion interrupt request
Intelligent I/O interrupt request
Software trigger
Channel Priority
DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has highest priority)
Transfer Unit
8 bits, 16 bits
Destination Address
Forward/fixed (forward and fixed directions cannot be specified when
specifying source and destination addresses simultaneously)
Transfer Mode Single Transfer Transfer is completed when the DCTi register (i = 0 to 3) is set to "000016"
Repeat Transfer When the DCTi register is set to "000016", the value of the DRCi register
is reloaded into the DCTi register and the DMA transfer is continued
DMA Interrupt Request Generation Timing When the DCTi register changes "000116" to "000016"
DMA Startup
Single Transfer DMA starts when a DMA request is generated after the DCTi register is
set to "000116" or more and the MDi1 and MD0 bits in the DMDj register
(j = 0,1) are set to "012" (single transfer)
Repeat Transfer DMA starts when a DMA request is generated after the DCTi register is
set to "000116" or more and the MDi1 and MDi0 bits are set to "112"
(repeat transfer)
DMA Stop
Single Transfer DMA stops when the MDi1 and MDi0 bits are set to "002" (DMA disabled) and the DCTi register is set to "000016" (0 DMA transfer) by DMA
transfer or write
Repeat Transfer DMA stops when the MDi1 and MDi0 bits are set to "002" and the DCTi
register is set to "000016" and the DRCi register set to "000016"
Reload Timing to the DCTi
When the DCTi register is set to "000016" from "000116" in repeat transor DMAi Register
fer mode
DMA Transfer Cycles
Minimum 3 cycles between SFRs and internal RAM
NOTE:
1. The IR bit in the interrupt control register does not change when a DMA request is acknowledged.
Rev. 1.00 Nov. 01, 2005 Page 110 of 330
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12. DMAC
M32C/80 Group
DMAi Request Source Select Register (i=0 to 3)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
DM0SL to DM3SL 037816, 037916, 037A16, 037B16
Bit
Symbol
Bit Name
After Reset
0X00 00002
Function
RW
DSEL0
RW
DSEL1
RW
DSEL2
DMA Request Source
Select Bit(1)
See Table 12.2 for the DMiSL
register (i=0 to 3) function
RW
DSEL3
RW
DSEL4
RW
DSR
Software DMA
Request Bit(2)
When a software trigger is selected,
a DMA request is generated by
RW
setting this bit to "1" (When read, its
content is always "0")
Reserved Bit
When read,
its content is indeterminate
RO
DMA Request Bit(2, 3)
0: Not requested
1: Requested
RW
(b6)
DRQ
NOTES:
1. Change the DSEL4 to DSEL0 bit settings while the MDi1 and MDi0 bits in the DMD0 and DMD1
registers are set to "002" (DMA disabled). Also, set the DRQ bit to "1" simultaneously when the
DSEL4 to DSEL0 bit settings are changed.
e.g., MOV.B #083h, DMiSL ; Set timer A0
2. When the DSR bit is set to "1", set the DRQ bit to "1" simultaneously.
e.g., OR.B #0A0h, DMiSL
3. Do not set the DRQ bit to "0".
Figure 12.2 DM0SL to DM3SL Registers
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12. DMAC
M32C/80 Group
Table 12.2 DMiSL Register (i=0 to 3) Function
Setting Value
b4 b3 b2 b1 b0
DMA Request Source
DMA0
DMA1
DMA2
DMA3
Software trigger
0 0 0 0 0
0 0 0 0 1
Falling Edge of INT0
Falling Edge of INT1
Falling Edge of INT2
Falling Edge of INT3(1)
(Note 2)
0 0 0 1 0
Both Edges of INT0
Both Edges of INT1
Both Edges of INT2
Both Edges of INT3(1)
(Note 2)
0 0 0 1 1
Timer A0 Interrupt Request
0 0 1 0 0
Timer A1 Interrupt Request
0 0 1 0 1
Timer A2 Interrupt Request
0 0 1 1 0
Timer A3 Interrupt Request
0 0 1 1 1
Timer A4 Interrupt Request
0 1 0 0 0
Timer B0 Interrupt Request
0 1 0 0 1
Timer B1 Interrupt Request
0 1 0 1 0
Timer B2 Interrupt Request
0 1 0 1 1
Timer B3 Interrupt Request
0 1 1 0 0
Timer B4 Interrupt Request
0 1 1 0 1
Timer B5 Interrupt Request
0 1 1 1 0
UART0 Transmit Interrupt Request
0 1 1 1 1
UART0 Receive or ACK Interrupt Request(3)
1 0 0 0 0
UART1 Transmit Interrupt Request
1 0 0 0 1
UART1 Receive or ACK Interrupt Request(3)
1 0 0 1 0
UART2 Transmit Interrupt Request
1 0 0 1 1
UART2 Receive or ACK Interrupt Request(3)
1 0 1 0 0
UART3 Transmit Interrupt Request
1 0 1 0 1
UART3 Receive or ACK Interrupt Request(3)
1 0 1 1 0
UART4 Transmit Interrupt Request
1 0 1 1 1
UART4 Receive or ACK Interrupt Request(3)
1 1 0 0 0
A/D0 Interrupt Request
1 1 0 0 1
Intelligent I/O
Interrupt 0 Request
Intelligent I/O
Interrupt 2 Request
1 1 0 1 0
Intelligent I/O
Interrupt 1 Request
Intelligent I/O
Interrupt 3 Request
1 1 0 1 1
Intelligent I/O
Interrupt 2 Request
Intelligent I/O
Interrupt 4 Request
1 1 1 0 0
Intelligent I/O
Interrupt 3 Request
Intelligent I/O
Interrupt 0 Request
1 1 1 0 1
Intelligent I/O
Interrupt 4 Request
Intelligent I/O
Interrupt 1 Request
1 1 1 1 0
Intelligent I/O
Interrupt 0 Request
Intelligent I/O
Interrupt 2 Request
1 1 1 1 1
Intelligent I/O
Interrupt 1 Request
Intelligent I/O
Interrupt 3 Request
NOTES:
1. If the INT3 pin is used for data bus in memory expansion mode or microprocessor mode, a DMA3 interrupt request
cannot be generated by a signal applied to the INT3 pin.
2. The falling edge and both edges of signals applied to the INTj pin (j=0 to 3) cause a DMA request generation. The
INT interrupt (the POL bit in the INTjlC register, the LVS bit, the IFSR register) is not affected and vice versa.
3. Use the UkSMR register and UkSMR2 register (k=0 to 4) to switch between the UARTk receive and ACK interrupt
as a DMA request source.
To use the ACK interrupt for a DMA reqest, set the IICM bit in the UkSMR register to "1" and the IICM2 bit in the
UkSMR2 register to "0".
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12. DMAC
M32C/80 Group
DMA Mode Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DMD0
Bit
Symbol
Address
(CPU Internal Register)
Bit Name
After Reset
0016
Function
RW
b1 b0
MD00
Channel 0 Transfer
Mode Select Bit
MD01
0 0: DMA disabled
0 1: Single transfer
1 0: Do not set to this value
1 1: Repeat transfer
RW
RW
BW0
Channel 0 Transfer
Unit Select Bit
0: 8 bits
1: 16 bits
RW0
Channel 0 Transfer
Direction Select Bit
0: Fixed address to memory (forward direction)
RW
1: Memory (forward direction) to fixed address
RW
b5 b4
MD10
Channel 1 Transfer
Mode Select Bit
MD11
0 0: DMA disabled
0 1: Single transfer
1 0: Do not set to this value
1 1: Repeat transfer
RW
RW
BW1
Channel 1 Transfer
Unit Select Bit
0: 8 bits
1: 16 bits
RW1
Channel 1 Transfer
Direction Select Bit
0: Fixed address to memory (forward direction)
RW
1: Memory (forward direction) to fixed address
RW
NOTE:
1. Use the LDC instruction to set the DMD0 register.
DMA Mode Register 1(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DMD1
Bit
Symbol
Address
(CPU internal register)
Bit Name
After Reset
0016
Function
RW
b1 b0
MD20
MD21
0 0: DMA disabled
Channel 2 Transfer 0 1: Single transfer
Mode Select Bit
1 0: Do not set to this value
1 1: Repeat transfer
RW
RW
BW2
Channel 2 Transfer 0: 8 bits
1: 16 bits
Unit Select Bit
RW2
Channel 2 Transfer 0: Fixed address to memory (forward direction)
RW
Direction Select Bit 1: Memory (forward direction) to fixed address
MD30
MD31
b5 b4
0 0 : DMA disabled
Channel 3 Transfer 0 1 : Single transfer
Mode Select Bit
1 0 : Do not set to this value
1 1 : Repeat transfer
RW
RW
RW
BW3
Channel 3 Transfer 0: 8 bits
Unit Select Bit
1: 16 bits
RW3
Channel 3 Transfer 0: Fixed address to memory (forward direction)
RW
Direction Select Bit 1: Memory (forward direction) to fixed address
NOTE:
1. Use the LDC instruction to set the DMD1 register.
Figure 12.3 DMD0 and DMD1 Registers
Rev. 1.00 Nov. 01, 2005 Page 113 of 330
REJ09B0271-0100
RW
12. DMAC
M32C/80 Group
DMAi Transfer Count Register (i=0 to 3)
b15
b8 b7
b0
Symbol
DCT0(2)
DCT1(2)
DCT2(bank1;R0)(3)
DCT3(bank1;R1)(4)
Address
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
Function
Set the number of transfers
After Reset
XXXX16
XXXX16
000016
000016
Setting Range
RW
000016 to FFFF16(1)
RW
NOTES:
1. When the DCTi register is set to "000016", no data transfer occurs regardless of a DMA request.
2. Use the LDC instruction to set the DCT0 and DCT1 registers.
3. To set the DCT2 register, set the B flag in the FLG register to "1" (register bank 1) and set the R0
register. Use the MOV instruction to set the R0 register.
4. To set the DCT3 register, set the B flag to "1" and set R1 register. Use the MOV instruction to
set the R1 register.
DMAi Transfer Count Reload Register (i=0 to 3)
b15
b8 b7
b0
Symbol
DRC0(1)
DRC1(1)
DRC2(bank1;R2)(2)
DRC3(bank1;R3)(3)
Address
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
Function
Set the number of transfers
After Reset
XXXX16
XXXX16
000016
000016
Setting Range
RW
000016 to FFFF16
RW
NOTES:
1. Use the LDC instruction to set the DRC0 and DRC1 registers.
2. To set the DRC2 register, set the B flag in the FLG register to "1" (register bank 1) and set the R2
register. Use the MOV instruction to set the R2 register.
3. To set the DRC3 register, set the B flag to "1" and set R3 register. Use the MOV instruction to set the
R3 register.
Figure 12.4 DCT0 to DCT3 Registers and DRC0 to DRC3 Registers
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12. DMAC
M32C/80 Group
DMAi Memory Address Register (i=0 to 3)
b23
b16 b15
b8 b7
b0
Symbol
DMA0(2)
DMA1(2)
DMA2(bank1;A0)(3)
DMA3(bank1;A1)(4)
Address
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
Function
Set a source memory address or destination
memory address(1)
After Reset
XXXXXX16
XXXXXX16
00000016
00000016
Setting Range
RW
00000016 to FFFFFF16
(16-Mbyte space)
RW
NOTES:
1. When the RWk bit (k=0 to 3) in the DMDj register (j=0, 1)is set to "0" (fixed address to memory), a
destination address is selected. When the RWk bit is set to "1" (memory to fixed address), a source
address is selected.
2. Use the LDC instruction to set the DMA0 and DMA1 registers.
3. To set the DMA2 register, set the B flag in the FLG register to "1" (register bank 1) and set the A0
register. Use the MOV instruction to set the A0 register.
4. To set the DMA3 register, set the B flag to "1" and set the A1 register. Use the MOV instruction to set
the A1 register.
DMAi SFR Address Register (i=0 to 3)
b23
b16 b15
b8 b7
b0
Symbol
DSA0(2)
DSA1(2)
DSA2(bank1;SB)(3)
DSA3(bank1;FB)(4)
Address
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
Function
Set a source fixed address or destination fixed
address(1)
After Reset
XXXXXX16
XXXXXX16
00000016
00000016
Setting Range
RW
00000016 to FFFFFF16
(16-Mbyte space)
RW
NOTES:
1. When the RWk bit (k=0 to 3) in the DMDj register (j=0, 1)is set to "0" (fixed address to memory), a
source address is selected. When the RWk bit is set to "1" (memory to fixed address), a destination
address is selected.
2. Use the LDC instruction to set the DSA0 and DSA1 registers.
3. To set the DSA2 register, set the B flag in the FLG register to "1" (register bank 1) and the set the SB
register. Use the LDC instruction to set the SB register.
4. To set the DSA3 register, set the B flag to "1" and set the FB register. Use the LDC instruction to set
the PB register.
DMAi Memory Address Reload Register(1) (i=0 to 3)
b23
b16 b15
b8 b7
b0
Symbol
DRA0
DRA1
DRA2(SVP)(2)
DRA3(VCT)(3)
Address
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
Function
Set a source memory address or destination
memory address(1)
After Reset
XXXXXX16
XXXXXX16
XXXXXX16
XXXXXX16
Setting Range
RW
00000016 to FFFFFF16
(16-Mbyte space)
RW
NOTES:
1. Use the LDC instruction to set the DRA0 and DRA1 registers.
2. To set the DRA2 register, set the SVP register.
3. To set the DRA3 register, set the VCT register.
Figure 12.5 DMA0 to DMA3 Registers, DSA0 to DSA3 Registers and DRA0 to DRA3 Registers
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12.1 Transfer Cycle
Transfer cycle contains a bus cycle to read data from a memory or the SFR area (source read) and a bus
cycle to write data to a memory space or the SFR area (destination write). The number of read and write
bus cycles depends on source and destination addresses. In memory expansion mode and microprocessor
mode, the number of read and write bus cycles also depends on DS register setting. Software wait state
________
insertion and the RDY signal make a bus cycle longer.
12.1.1 Effect of Source and Destination Addresses
When a 16-bit data is transferred with a 16-bit data bus and a source address starting with an odd
address, source read cycle is incremented by one bus cycle, compared to a source address starting with
an even address.
When a 16-bit data is transferred with a 16-bit data bus and a destination address starting with an odd
address, a destination write cycle is incremented by one bus cycle, compared to a destination address
starting with an even address.
12.1.2 Effect of the DS Register
In an external space in memory expansion or microprocessor mode, transfer cycle varies depending on
the data bus used at the source and destination addresses. See Figure 8.1 for details about the DS
register.
• When an 8-bit data bus (the DSi bit in the DS register is set to "0" (i=0 to 3)), accessing both source
address and destination address, is used to transfer a 16-bit data, 8-bit data is transferred twice.
Therefore, two bus cycles are required to read the data and another two bus cycles to write the data.
• When an 8-bit data bus (the DSi bit in the DS register is set to "0" (i=0 to 3)), accessing source
address, and a 16-bit data bus, accessing destination address, are used to transfer a 16-bit data, 8bit data is read twice but is written once as 16-bit data. Therefore, two bus cycles are required for
reading and one bus cycle is for writing.
• When a 16-bit data bus, accessing source address, and an 8-bit data bus, accessing destination
address, are used to transfer a 16-bit data, 16-bit data is read once and 8-bit data is written twice.
Therefore, one bus cycle is required for reading and two bus cycles is for writing.
12.1.3 Effect of Software Wait State
When the SFR area or memory space with software wait states is accessed, the number of CPU clock
cycles is incremented by software wait states.
Figure 12.6 shows an example of a transfer cycle for the source-read bus cycle. In Figure 12.6, the
number of source-read bus cycles is illustrated under different conditions, provided that the destination
address is an address of an external space with the destination-write cycle as two CPU clock cycles
(=one bus cycle). In effect, the destination-write bus cycle is also affected by each condition and the
transfer cycles change accordingly. To calculate a transfer cycle, apply respective conditions to both
destination-write bus cycle and source-read bus cycle. As shown in example (2) of Figure 12.6, when an
8-bit data bus, accessing both source and destination addresses, is used to transfer a 16-bit data, two
bus cycles each are required for the source-read bus cycle and destination-write bus cycle.
________
12.1.4 Effect of RDY Signal
________
In memory expansion or microprocessor mode, the RDY signal affects a bus cycle if a source address or
_______
destination address is allocated address in an external space. Refer to 7.2.6 RDY Signal for details.
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(1) When 8-bit data is transferred
or when 16-bit data is transferred with a 16-bit data bus from an even source address
CPU Clock
Address
Bus
CPU Use
Source
Destination
CPU Use
RD Signal
WR Signal
Data bus
CPU Use
Destination
Source
CPU Use
(2) When 16-bit data is transferred from an odd source address
or when 16-bit data is transferred and 8-bit bus is used to access a source address
CPU
CPUClock
Clock
Address
Bus
CPU Use
Source
Source + 1
CPU Use
Destination
RD Signal
WR Signal
Data Bus
CPU Use
Source
Source + 1
CPU Use
Destination
(3) When one wait state is inserted into the source-read bus cycle under the conditions in (1)
CPU Clock
Address
Bus
CPU Use
Source
Destination
CPU Use
RD Signal
WR Signal
Data Bus
CPU Use
Source
CPU Use
Destination
(4) When one wait state is inserted into the source-read bus cycle under the conditions in (2)
CPU Clock
Address
Bus
CPU Use
Source
Source + 1
Destination
CPU Use
RD Signal
WR Signal
Data Bus
CPU Use
Source
Source + 1
Destination
CPU Use
NOTE:
1. The above applies when the destination-write bus cycle is 2 CPU clock cycles (=1 bus cycle).
However, if the destination-write bus cycle is pleaced under these conditions, it will change to
the same timing as the source-read cycle illustrated above.
Figure 12.6 Transfer Cycle Examples with the Source-Read Bus Cycle
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12.2 DMAC Transfer Cycle
The number of DMAC transfer cycle can be calculated as follows.
Any combination of even or odd transfer read and write addresses are possible. Table 12.3 lists the number
of DMAC transfer cycles. Table 12.4 lists coefficient j, k.
Transfer cycles per transfer = Number of read cycle x j + Number of write cycle x k
Table 12.3 DMAC Transfer Cycles
Single-Chip Mode
Transfer Unit
Bus Width Access Address
16-bit
8-bit transfers
(BWi bit in the DMDp
register = 0)
8-bit
16-bit
16-bit transfers
(BWi bit = 1)
8-bit
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Read
Cycle
1
1
—
—
1
2
—
—
Write
Cycle
1
1
—
—
1
2
—
—
Memory Expansion Mode
Microprocessor Mode
Read
Write
Cycle
Cycle
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
i= 0 to 3, p = 0, 1
Table 12.4 Coefficient j, k
Internal Space
Internal RAM
Internal RAM
SFR
with no wait state with a wait state area
j=1
j=2
j=2
k=1
k=2
k=2
j, k=2 to 9
External Space
j and k BCLK cycles shown in Table 7.5.
Add one cycle to j or k cycles when inserting a recovery cycle.
12.3 Channel Priority and DMA Transfer Timing
When multiple DMA requests are generated in the same sampling period, between the falling edge of the
CPU clock and the next falling edge, the DRQ bit in the DMiSL register (i=0 to 3) is set to "1" (requested)
simultaneously. Channel priority in this case is: DMA0 > DMA1 > DMA2 > DMA3.
Figure 12.7 shows an example of the DMA transfer by external source.
In Figure 12.7, the DMA0 request having highest priority is received first to start a transfer when a DMA0
request and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, the bus
privilege is returned to the CPU. When the CPU has completed one bus access, the DMA1 transfer starts.
After one DMA1 transfer is completed, the privilege is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DRQ bit. Therefore, when
DMA requests, as DMA1 in Figure 12.7, occur more than once before receiving bus privilege, the DRQ bit
is set to "0" as soon as privilege is acquired. The bus privilege is returned to the CPU when one transfer is
completed.
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When DMA transfer request signals by external source are applied to INT0 and
INT1 simultaneously and a DMA transfer with minimum cycle occurs
CPU Clock
DMA0
DMA1
CPU
INT0
AAA
AAA
AAA
AAA
AAAAAAAA AAA
AA
A
AAA
AA
AA
A
AAA
AA
DRQ Bit in the
DMA0 Register
INT1
DRQ Bit in the
DMA1 Register
Figure 12.7 DMA Transfer by External Source
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Bus
privilege
acquired
M32C/80 Group
13. DMACII
13. DMAC II
DMAC II performs memory-to-memory transfer, immediate data transfer and calculation transfer, which
transfers the sum of two data added by an interrupt request from any peripheral functions.
Table 13.1 lists specifications of DMAC II.
Table 13.1 DMAC II Specifications
Item
DMAC II Request Source
Specification
Interrupt requests generated by all peripheral functions when the ILVL2 to
ILVL0 bits are set to "1112"
Transfer Data
• Data in memory is transferred to memory (memory-to-memory transfer)
• Immediate data is transferred to memory (immediate data transfer)
• Data in memory (or immediate data) + data in memory are transferred to
memory (calculation transfer)
Transfer Block
8 bits or 16 bits
Transfer Space
64-Kbyte space in addresses 0000016 to 0FFFF16(1, 2)
Transfer Direction
Fixed or forward address
Selected separately for each source address and destination address
Transfer Mode
Single transfer, burst transfer
Chained Transfer Function Parameters (transfer count, transfer address and other information) are
switched when transfer counter reaches zero
End-of-Transfer Interrupt
Interrupt occurs when a transfer counter reaches zero
Multiple Transfer Function Multiple data can be transferred by a generated request for one DMAC II transfer
NOTES:
1. When transferring a 16-bit data to destination address 0FFFF16, it is transferred to 0FFFF16 and
1000016. The same transfer occurs when the source address is 0FFFF16.
2. The actual space where transfer can occurs is limited due to internal RAM capacity.
13.1 DMAC II Settings
DMAC II can be made available by setting up the following registers and tables.
• RLVL register
• DMAC II Index
• Interrupt control register of the peripheral function causing a DMAC II request
• The relocatable vector table of the peripheral function causing a DMAC II request
• IRLT bit in the IIOiIE register (i=0 to 4) to use the intelligent I/O
Refer to 10. Interrupts for details on the IIOiIE register.
13.1.1 RLVL Register
When the DMAII bit is set to "1" (DMAC II transfer) and the FSIT bit to "0" (normal interrupt), DMAC II is
activated by an interrupt request from any peripheral function with the ILVL2 to ILVL0 bits in the interrupt
control register set to "1112" (level 7).
Figure 13.1 shows the RLVL register.
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Exit Priority Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
RLVL
Bit
Symbol
Address
009F16
Bit Name
Function
b2b1b0
RLVL0
RLVL1
After Reset
XXXX 00002
Stop/Wait Mode Exit
Minimum Interrupt
Priority Level Control
Bit(1)
RLVL2
0 0 0: Level 0
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
1 0 1: Level 5
1 1 0: Level 6
1 1 1: Level 7
0: Interrupt priority level 7 is used
for normal interrupt
1: Interrupt priority level 7 is used
for high-speed interrupt
FSIT
High-speed Interrupt
Set Bit(2)
(b4)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
DMAII
DMA II Select
Bit(4)
0: Interrupt priority level 7 is used
for interrupt
1: Interrupt priority level 7 is used
for DMA II transfer(3)
RW
RW
RW
RW
RW
RW
Nothing is assigned. When write, set to "0".
(b7 - b6) When read, its content is indeterminate.
NOTES:
1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than
the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in
the FLG register.
2. When the FSIT bit is set to "1", an interrupt having the interrupt priority level 7 becomes the high-speed
interrupt. In this case, set only one interrupt to the interrupt priority level 7 and the DMAII bit to "0".
3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1".
Do not change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0"
when the DMAII bit to "1".
4. The DMAII bit becomes indeterminate after reset. To use the DMAII bit for an interrupt setting, set it
to "0" before setting the interrupt control register.
Figure 13.1 RLVL Register
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13.1.2 DMAC II Index
The DMAC II index is a data table which comprises 8 to 18 bytes (maximum 32 bytes when the multiple
transfer function is selected). The DMAC II index stores parameters for transfer mode, transfer counter,
source address (or immediate data), operation address as an address to be calculated, destination address, chained transfer address, and end-of-transfer interrupt address.
This DMAC II index must be located on the RAM area.
Figure 13.2 shows a configuration of the DMAC II index. Table 13.2 lists a configuration of the DMAC II
index in transfer mode.
Memory-to-Memory Transfer, Immediate Transfer,
Calculation Transfer
DMAC II Index
Starting Address
(BASE)
BASE + 2
Multiple Transfer
16 bits
16 bits
Transfer Mode
(MOD)
BASE
Transfer Mode
(MOD)
Transfer Counter
(COUNT)
BASE + 2
Transfer Counter
(COUNT)
(SADR1)
BASE + 4
Transfer Source Address (or immediate data) (SADR)
BASE + 4
Transfer Source Address
BASE + 6
Operation Address(1)
(OADR)
BASE + 6
Transfer Destination Address
(DADR1)
BASE + 8
Transfer Destination Address
(DADR)
BASE + 8
Transfer Source Address
(SADR2)
BASE + 10
Chained Transfer Address(2)
(CADR0)
BASE + 10 Transfer Destination Address
(DADR2)
BASE + 12
Chained Transfer Address(2)
(CADR1)
BASE + 14
End-of-Transfer Interrupt Address(3)
(IADR0)
BASE + 28 Transfer Source Address
(SADR7)
BASE + 16
End-of-Transfer Interrupt Address(3)
(IADR1)
BASE + 30 Transfer Destination Address
(DADR7)
NOTES:
1. This data is not required when not using the calculation transfer function.
2. This data is not required when not using the chained transfer function.
3. This data is not required when not using the end-of-transfer interrupt.
The DMAC II index must be located on the RAM. Necessary data is set front-aligned. For example, if not using a calculation
transfer function, set destination address to BASE+6. (See Table 13.2)
Starting address of the DMAC II index must be set in the interrupt vector for the peripheral function interrupt causing a DMAC II request.
Figure 13.2 DMAC II Index
The followings are details of the DMAC II index. Set these parameters in the specified order listed in
Table 13.2, according to DMAC II transfer mode.
• Transfer mode (MOD)
Two-byte data is required to set transfer mode. Figure 13.3 shows a configuration for transfer mode.
• Transfer counter (COUNT)
Two-byte data is required to set the number of transfer.
• Transfer source address (SADR)
Two-byte data is required to set the source memory address or immediate data.
• Operation address (OADR)
Two-byte data is required to set a memory address to be calculated. Set this data only when using
the calculation transfer function.
• Transfer destination address (DADR)
Two-byte data is required to set the destination memory address.
• Chained transfer address (CADR)
Four-byte data is required to set the starting address of the DMAC II index for the next transfer. Set
this data only when using the chained transfer function.
• End-of-transfer interrupt address (IADR)
Four-byte data is required to set a jump address for end-of-transfer interrupt processing. Set this
data only when using the end-of-transfer interrupt.
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Table 13.2 DMAC II Index Configuration in Transfer Mode
Memory-to-Memory Transfer
/Immediate Data Transfer
Transfer Data
Calculation Transfer
Multiple Transfer
Chained Transfer Not Used
Used
Not Used
Used
Not Used
Used
Not Used
Used
Not Available
End-of-Transfer Not Used
Interrupt
Not Used
Used
Used
Not Used
Not Used
Used
Used
Not Available
DMAC II
Index
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
COUNT
COUNT
COUNT
COUNT
COUNT
COUNT
COUNT
COUNT
COUNT
SADR
SADR
SADR
SADR
SADR
SADR
SADR
SADR
SADR1
DADR
DADR
DADR
DADR
OADR
OADR
OADR
OADR
DADR1
CADR0
IADR0
CADR0
DADR
DADR
DADR
DADR
CADR1
IADR1
CADR1
10 bytes
CADR0
IADR0
CADR0
CADR1
IADR1
CADR1
SADRi
IADR0
DADRi
IADR1
i=1 to 7
max. 32 bytes
(when i=7)
8 bytes
12 bytes
12 bytes
IADR0
IADR1
14 bytes
14 bytes
16 bytes
18 bytes
Transfer Mode (MOD)(1)
b15
b8 b7
b0
Bit
Symbol
Bit Name
Function
(MULT=0)
SIZE
Transfer Unit
Select Bit
0: 8 bits
1: 16 bits
IMM
Transfer Data
Select Bit
0: Immediate data
1: Memory
Function
(MULT=1)
RW
RW
Set to "1"
RW
UPDS
Transfer Source
0: Fixed address
Direction Select Bit 1: Forward address
RW
UPDD
Transfer Destination 0: Fixed address
Direction Select Bit 1: Forward address
RW
OPER/ Calculation Transfer 0: Not used
CNT0(2) Function Select Bit 1: Used
BRST/ Burst Transfer
CNT1(2) Select Bit
0: Single transfer
1: Burst transfer
INTE/ End-of-Transfer
CNT2(2) Interrupt Select Bit
0: Interrupt not used
1: Use interrupt
CHAIN
Chained Transfer
Select Bit
b6 b5 b4
0 0 0: Do not set
to this value
0 0 1: Once
0 1 0: Twice
:
:
1 1 0: 6 times
1 1 1: 7 times
0: Chained transfer not used
Set to "0"
1: Use chained transfer
RW
RW
RW
RW
Nothing is assigned. When write, set to "0".
(b14 - b8) When read, its content is indeterminate.
MULT
Multiple Transfer
Select Bit
0: Multiple
transfer not used
1: Use multiple
transfer
RW
NOTES:
1. MOD must be located on the RAM.
2. When the MULT bit is set to "0" (no multiple transfer), bits 6 to 4 becomes the INTE, OPER and BRST
bits. When the MULT bit is set to "1" (multiple transfer), bits 6 to 4 becomes the CNT2 to CNT0 bits.
Figure 13.3 MOD
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13. DMACII
13.1.3 Interrupt Control Register for the Peripheral Function
For the peripheral function interrupt activating DMAC II, set the ILVL2 to ILVL0 bits to "1112" (level 7).
13.1.4 Relocatable Vector Table for the Peripheral Function
Set the starting address of the DMAC II index in the interrupt vector for the peripheral function interrupt
activating DMAC II.
When using the chained transfer, the relocatable vector table must be located in the RAM.
13.1.5 IRLT Bit in the IIOiIE Register (i=0 to 4)
When the intelligent I/O interrupt or CAN interrupt is used to activate DMAC II, set the IRLT bit in the IIOiIE
register of the interrupt to "0".
13.2 DMAC II Performance
Function to activate DMAC II is selected by setting the DMA II bit to "1" (DMAC II transfer). DMAC II is
activated by all peripheral function interrupts with the ILVL2 to ILVL0 bits set to "1112" (level 7). These
peripheral function interrupt request signals become DMAC II transfer request signals and the peripheral
function interrupt cannot be used.
When an interrupt request is generated by setting the ILVL2 to ILVL0 bits to "1112" (level 7), DMAC II is
activated regardless of what state the I flag and IPL are in.
13.3 Transfer Data
DMAC II transfers 8-bit or 16-bit data.
• Memory-to-memory transfer : Data is transferred from a desired memory location in a 64-Kbyte space
(Addresses 0000016 to 0FFFF16) to another desired memory location in the same space.
• Immediate data transfer : Immediate data is transferred to a desired memory location in a 64-Kbyte space.
• Calculation transfer : Two 8-bit or16-bit data are added together and the result is transferred to a desired
memory location in a 64-Kbyte space.
When a 16-bit data is transferred to the destination address 0FFFF16, it is transferred to 0FFFF16 and
1000016. The same transfer occurs when the source address is 0FFFF16. Actual transferable space varies
depending on the internal RAM capacity.
13.3.1 Memory-to-memory Transfer
Data transfer between any two memory locations can be:
• a transfer from a fixed address to another fixed address
• a transfer from a fixed address to a relocatable address
• a transfer from a relocatable address to a fixed address
• a transfer from a relocatable address to another relocatable address
When a relocatable address is selected, the address is incremented, after a transfer, for the next transfer.
In a 8-bit transfer, the transfer address is incremented by one. In a 16-bit transfer, the transfer address is
incremented by two.
When a source or destination address exceeds address 0FFFF16 as a result of address incrementation,
the source or destination address returns to address 0000016 and continues incrementation. Maintain
source and destination address at address 0FFFF16 or below.
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13. DMACII
13.3.2 Immediate Data Transfer
DMAC II transfers immediate data to any memory location. A fixed or relocatable address can be selected as the destination address. Store the immediate data into SADR. To transfer an 8-bit immediate
data, write the data in the low-order byte of SADR (high-order byte is ignored).
13.3.3 Calculation Transfer
After two memory data or an immediate data and memory data are added together, DMAC II transfers
calculated result to any memory location. SADR must have one memory location address to be calculated or immediate data and OADR must have the other memory location address to be calculated. Fixed
or relocatable address can be selected as source and destination addresses when using a memory +
memory calculation transfer. If the transfer source address is relocatable, the operation address also
becomes relocatable. Fixed or relocatable address can be selected as the transfer destination address
when using an immediate data + memory calculation transfer.
13.4 Transfer Modes
Single and burst transfers are available. The BRST bit in MOD selects transfer method, either single transfer or burst transfer. COUNT determines how many transfers occur. No transfer occurs when COUNT is set
to "000016".
13.4.1 Single Transfer
For every transfer request source, DMAC II transfers one transfer unit of 8-bit or 16-bit data once. When
the source or destination address is relocatable, the address is incremented, after a transfer, for the next
transfer.
COUNT is decremented every time a transfer occurs. When using the end-of-transfer interrupt, the interrupt is acknowledged when COUNT reaches "0".
13.4.2 Burst Transfer
For every transfer request source, DMAC II continuously transfers data the number of times determined
by COUNT. COUNT is decremented every time a transfer occurs. The burst transfer ends when COUNT
reaches "0". The end-of-transfer interrupt is acknowledged when the burst transfer ends if using the endof-transfer interrupt. All interrupts are ignored while the burst transfer is in progress.
13.5 Multiple Transfer
The MULT bit in MOD selects the multiple transfer. When using the multiple transfer, select the memory-tomemory transfer. One transfer request source initiates multiple transfers. The CNT2 to CNT0 bits in MOD
selects the number of transfers from "0012" (once) to "1112" (7 times). Do not set the CNT2 to CNT0 bits to
"0002".
The transfer source and destination addresses for each transfer must be allocated alternately in addresses
following MOD and COUNT. When the multiple transfer is selected, the calculation transfer, burst transfer,
end-of-transfer interrupt and chained transfer cannot be used.
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13.6 Chained Transfer
The CHAIN bit in MOD selects the chained transfer.
The following process initiates the chained transfer.
(1) Transfer, caused by a transfer request source, occurs according to the content of the DMAC II index.
The vectors of the request source indicates where the DMAC II index is allocated. For each request, the
BRST bit selects either single or burst transfer.
(2) When COUNT reaches "0", the contents of CADR1 and CADR0 are written to the vector of the request
source. When the INTE bit in MOD is set to "1", the end-of-transfer interrupt is generated simultaneously.
(3) When the next DMAC II transfer request is generated, transfer occurs according to the contents of the
DMAC II index indicated by the peripheral function interrupt vector rewritten in (2).
Figure 13.4 shows the relocatable vector and DMACII index when the chained transfer is in progress.
For the chained transfer, the relocatable vector table must be located in the RAM.
RAM
INTB
Relocatable Vector
Peripheral I/O interrupt vector causing DMAC II request
Default value of DMAC II is BASE(1).
BASE(1)
DMAC II
Index(1)
(CADR1 and
CADR0)
BASE(2)
The above vector is rewritten to BASE(2)
when a transfer is completed.
Starts at BASE(2) when next request conditions
are met.
Transferred according to the DMAC II Index.
BASE(2)
DMAC II
Index(2)
(CADR1 and
CADR0)
BASE(3)
The above vector is rewritten to BASE(3)
when a transfer is completed.
Figure 13.4 Relocatable Vector and DMAC II Index
13.7 End-of-Transfer Interrupt
The INTE bit in MOD selects the end-of-transfer interrupt. Set the starting address of the end-of-transfer
interrupt routine in IADR1 and IADR0. The end-of-transfer interrupt is generated when COUNT reaches "0."
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13.8 Execution Time
DMAC II execution cycle is calculated by the following equations:
Multiple transfers: t = 21+ (11 + b + c) x k cycles
Other than multiple transfers: t = 6 + (26 + a + b + c + d) x m + (4 + e) x n cycles
a: If IMM = 0 (source of transfer is immediate data), a = 0;
if IMM = 1 (source of transfer is memory), a = –1
b: If UPDS = 1 (source transfer address is a relocatable address), b = 0;
if UPDS = 0 (source transfer address is a fixed address), b = 1
c: If UPDD = 1 (destination transfer address is a relocatable address), c = 0;
if UPDD = 0 (destination transfer address is a fixed address), c = 1
d: If OPER = 0 (calculation function is not selected), d = 0;
if OPER = 1 (calculation function is selected) and UPDS = 0 (source of transfer is immediate data or fixed
address memory), d = 7;
if OPER = 1 (calculation function is selected) and UPDS = 1 (source of transfer is relocatable address
memory), d = 8
e: If CHAIN = 0 (chained transfer is not selected), e = 0; if CHAIN = 1 (chained transfer is selected), e = 4
m: BRST = 0 (single transfer), m = 1; BRST = 1 (burst transfer), m = the value set in transfer counter
n: If COUNT = 1, n = 0; if COUNT = 2 or more, n = 1
k: Number of transfers set in the CNT2 to CNT0 bits
The equations above are approximations. The number of cycles may vary depending on CPU state, bus
wait state, and DMAC II index allocation.
The first instruction from the end-of-transfer interrupt routine is executed in the eighth cycle after the DMAC
II transfer is completed.
If the end-of-transfer interrupt (transfer counter = 2) occurs with no chained transfer function
after a memory-to-memory transfer occurs with a relocatable source address, fixed destination address,
single transfer and double transfer:
a=-1
b=0
c=1
d=0
e=0
m=1
First DMAC II transfer
t=6+26x1+4x1=36 cycles
Second DMAC II transfer t=6+26x1+4x0=32 cycles
DMAC II transfer request
Program
DMAC II transfer
(First time)
DMAC II transfer request
Program
36 cycles
Transfer counter = 2
Processing the end-of-transfer
interrupt
DMAC II transfer
(Second time)
32 cycles
7 cycles
Transfer counter = 1
Decrement a transfer counter
Transfer counter = 1
Decrement a transfer counter
Transfer counter = 0
Figure 13.5 Transfer Cycle
When an interrupt
request as a DMAC II transfer request source and another interrupt request with higher
_______
priority (e.g., NMI or watchdog timer) are generated simultaneously, the interrupt with higher priority takes
precedence over the DMAC II transfer. The pending DMAC II transfer starts after the interrupt sequence
has been completed.
Rev. 1.00 Nov. 01, 2005 Page 127 of 330
REJ09B0271-0100
14. Timer
M32C/80 Group
14. Timer
The microcomputer has eleven 16-bit timers. Five timers A and six timers B have different functions. Each
timer functions independently. The count source for each timer becomes the clock for timer operations
including counting and reloading, etc. Figures 14.1 and 14.2 show block diagrams of timer A and timer B
configuration.
Clock prescaler
1/32
XCIN
fC32
Reset
Set the CPSR bit in the
CPSRF register to "1"
f1 f8 f2n fC32
00
01
10
11
TCK1 and TCK0
TMOD1 and TMOD0
10
Noise
filter
TA0IN
00: Timer mode
10: One-shot timer mode
11: PWM mode
Timer A0 interrupt
Timer A0
01
00
01: Event counter mode
11 TA0TGH and TA0TGL
00
01
10
11
TCK1 and TCK0
TCK1 and TCK0
00
01
10
11
Noise
filter
Timer A1 interrupt
Timer A1
01
00
11
TA2IN
TMOD1 and TMOD0
10
Noise
filter
TA1IN
00: Timer mode
10: One-shot tiemr mode
11: PWM mode
01: Event counter mode
TA1TGH and TA1TGL
00: Timer mode
10: One-shot timer mode
11: PWM mode
TMOD1 and TMOD0
10
01
00
Timer A2 interrupt
Timer A2
01: Event counter mode
11 TA2TGH and TA2TGL
00TCK1 and TCK0
01
10
11
Noise
filter
TA3IN
00: Timer mode
10: One-shot timer mode
11: PWM mode
TMOD1 and TMOD0
10
01
00
Timer A3 interrupt
Timer A3
01: Event counter mode
11 TA3TGH and TA3TGL
00
01
10
11
TA4IN
TCK1 and TCK0
00: Timer mode
10: One-shot timer mode
11: PWM mode
TMOD1 and TMOD0
10
Noise
filter
Timer A4
01
00
01: Event counter mode
11 TA4TGH and TA4TGL
Timer B2 overflow
or underflow signal
CST: Bit in the TCSPR Register
TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TAiMR Register (i=0 to 4)
TAiTGH and TAiTGL: Bits in the ONSF Register or TRGSR Register
Figure 14.1 Timer A Configuration
Rev. 1.00 Nov. 01, 2005 Page 128 of 330
REJ09B0271-0100
Timer A4 interrupt
14. Timer
M32C/80 Group
Clock prescaler
1/32
XCIN
fC32
Reset
Set the CPSR bit in the
CPSRF register to "1"
f1 f8 f2n fC32
00
01
10
11
Timer B2 overflow or underflow signal
(to a count source of Timer A)
TCK1 to TCK0
00: Timer mode
10: Pulse width measurement mode
TMOD1 and TMOD0
TB0IN
Noise
filter
00
01
10
11
TB1IN
Timer B0
TCK1
1
01:Event counter mode
TMOD1 and TMOD0
0
TCK1
01:Event counter mode
TCK1 and TCK0
00: Timer mode
10: Pulse width measurement mode
1
TMOD1 and TMOD0
0
01:Event counter mode
TCK1 and TCK0
00: Timer mode
10: Pulse width measurement mode
TMOD1 and TMOD0
Noise
filter
00
01
10
11
00
01
10
11
TB5IN
0
Timer B3
TCK1
TCK1 and TCK0
Timer B3 interrupt
01:Event counter mode
00: Timer mode
10: Pulse width measurement mode
1
Noise
filter
TB4IN
Timer B2 interrupt
Timer B2
1
TB3IN
Timer B1 interrupt
Timer B1
TCK1
00
01
10
11
Timer B0 interrupt
00: Timer mode
10: Pulse width measurement mode
Noise
filter
TB2IN
0
TCK1 and TCK0
Noise
filter
00
01
10
11
1
TMOD1 and TMOD0
Timer B4
0
TCK1
TCK1 and TCK0
Timer B4 interrupt
01:Event counter mode
00: Timer mode
10: Pulse width measurement mode
1
Noise
filter
TMOD1 and TMOD0
Timer B5
0
TCK1
01:Event counter mode
CST: Bit in the TCSPR Register
TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TBiMR Register (i=0 to 5)
Figure 14.2 Timer B Configuration
Rev. 1.00 Nov. 01, 2005 Page 129 of 330
REJ09B0271-0100
Timer B5 interrupt
14. Timer (Timer A)
M32C/80 Group
14.1 Timer A
Figure 14.3 shows a block diagram of the timer A. Figures 14.4 to 14.7 show registers associated with the
timer A.
The timer A supports the following four modes. Except in event counter mode, all timers A0 to A4 have the
same function. The TMOD1 and TMOD0 bits in the TAiMR register (i=0 to 4) determine which mode is
used.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts an external pulse or an overflow and underflow of other timers.
• One-shot timer mode: The timer outputs one valid pulse until a counter value reaches "000016".
• Pulse width modulation mode: The timer continuously outputs desired pulse widths.
Table 14.1 lists TAiOUT pin settings when used as an output. Table 14.2 lists TAiIN and TAiOUT pin settings
when used as an input.
Select clock
High-Order Bits of Data Bus
Select Count Source
f1
f8
f2n(1)
fC32
TAiIN
00
01
10
11
TCK1 and
TCK0
• Timer Mode
:TMOD1 and TMOD0=00, MR2=0
• One-Shot Timer Mode :TMOD1 and TMOD0=10
• Pulse Width Modulation Mode
:TMOD1 and TMOD0=11 TMOD1 and TMOD0,
MR2
• Timer Mode (gate function):
TMOD1 and TMOD0=00, MR2=1
• Event Counter Mode:TMOD1 and TMOD0=01
Polarity
Selector
Low-Order Bits of Data Bus
8 loworder
bits
Reload Register
A
A
Counter
Increment / decrement
Always decrement except
in event counter mode
TAiS
00
01
TB2 Overflow(2)
10
TAj Overflow(2)
11
(2)
TAk Overflow
Decrement
00
01
11
01
TAiTGH and TAiTGL
TAiUD
TMOD1 and TMOD0
0
1
Pulse Output
MR2
TAiOUT
Toggle Flip Flop
i=0 to 4
j=i-1, except j=4 if i=0
k=i+1, except k=0 if i=4
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select
no division (n=0) or divide-by-2n (n=1 to 15).
2. Overflow or underflow signal
TAi
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Addresses
034716 034616
034916 034816
034B16 034A16
034D16 034C16
034F16 034E16
TCK1 and TCK0, TMOD1 and TMOD0, MR2 and MR1: Bits in the TAiMR register
TAiTGH and TAiTGL: Bits in the ONSF register if i=0 or bits in the TRGSR register if i=1 to 4
TAiS: Bits in the TABSR register
TAiUD: Bits in the UDF register
Figure 14.3 Timer A Block Diagram
Rev. 1.00 Nov. 01, 2005 Page 130 of 330
REJ09B0271-0100
8 highorder
bits
TAj
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
TAk
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
14. Timer (Timer A)
M32C/80 Group
Timer Ai Register (i=0 to 4)(1)
b15
b8 b7
b0
Symbol
TA0 to TA2
TA3, TA4
Address
034716-034616, 034916-034816, 034B16-034A16
034D16-034C16, 034F16-034E16
Mode
Function
After Reset
Indeterminate
Indeterminate
Setting Range
RW
Timer Mode
If setting value is n, count source
is divided by n+1.
000016 to FFFF16 RW
Event Counter
Mode(2)
If setting value is n, count source
is divided by FFFF16 - n+1 when
the counter is incremented
and by n+1 when the counter is
decremented.
000016 to FFFF16 RW
One-Shot Timer
Mode(4)
If setting value is n, count source
is divided by n, then stops.
000016 to FFFF16(3) WO
If count source frequency is fj
Pulse Width
and setting value of the TAi
Modulation Mode(5) register is n,
PWM cycle: (216-1) / fj
(16-Bit PWM)
"H" width of PWM pulse: n / fj
Pulse Width
Modulation Mode(5)
(8-Bit PWM)
If count source frequency is fj,
setting value of high-order bits in
the TAi register is n and setting
value of low-order bits in the TAi
register is m,
PWM cycle: (28-1)x(m+1) / fj
"H" width of PWM pulse: (m+1)n / fj
000016 to FFFE16(3) WO
0016 to FE16(3)
(High-order
address bits)
0016 to FF16(3)
(Low-order
address bits)
WO
fj : f1, f8, f2n, fC32
NOTES:
1. Use 16-bit data for reading and writing.
2. The TAi register counts how many pulse inputs are provided externally or how many times another
timer counter overflows and underflows.
3. Use the MOV instruction to set the TAi register.
4. When the TAi register is set to "000016", the timer counter does not start and the timer Ai interrupt
request is not generated.
5. When the TAi register is set to "000016", the pulse width modulator does not operate and the TAiOUT
pin is held "L". The TAi interrupt request is also not generated. The same situation occurs in 8-bit
pulse width modulator mode if the 8 high-order bits in the TAi register are set to "0016".
Figure 14.4 TA0 to TA4 Registers
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14. Timer (Timer A)
M32C/80 Group
Timer Ai Mode Register (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
TA0MR to TA4MR
Bit
Symbol
Address
035616, 035716, 035816, 035916, 035A16
Bit Name
After Reset
0016
Function
RW
b1b0
0 0: Timer mode
0 1: Event counter mode
1 0: One-shot timer mode
1 1: Pulse width modulation
(PWM) mode
RW
Operating Mode
Select Bit
Reserved Bit
Set to "0"
RW
TMOD0
TMOD1
(b3)
MR1
RW
RW
Function varies depending on
operating mode
MR2
MR3
RW
RW
TCK0
Count Source
Select Bit
Function varies depending on
operating mode
TCK1
RW
RW
Count Start Flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Bit
Symbol
Address
034016
After Reset
0016
Bit Name
Function
RW
TA0S
Timer A0 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TA1S
Timer A1 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TA2S
Timer A2 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TA3S
Timer A3 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TA4S
Timer A4 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TB0S
Timer B0 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TB1S
Timer B1 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TB2S
Timer B2 Count
Start Flag
0: Stops counting
1: Starts counting
RW
Figure 14.5 TA0MR to TA4MR Registers and TABSR Register
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14. Timer (Timer A)
M32C/80 Group
Up/Down Flag(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UDF
Address
034416
After Reset
0016
Bit
Symbol
Bit Name
TA0UD
Timer A0
Up/Down Flag(2)
0: Decrement
1: Increment
RW
TA1UD
Timer A1
Up/Down Flag(2)
0: Decrement
1: Increment
RW
TA2UD
Timer A2
Up/Down Flag(2)
0: Decrement
1: Increment
RW
TA3UD
Timer A3
Up/Down Flag(2)
0: Decrement
1: Increment
RW
TA4UD
Timer A4
Up/Down Flag(2)
0: Decrement
1: Increment
RW
Function
0: Disables two-phase pulse signal
Timer A2 Two-Phase
processing function
Pulse Signal Processing
1: Enables two-phase pulse signal
Function Select Bit(3)
processing function
0: Disables two-phase pulse signal
Timer A3 Two-Phase
processing function
Pulse Signal Processing 1: Enables
two-phase pulse signal
(3)
Function Select Bit
processing function
0: Disables two-phase pulse signal
Timer A4 Two-Phase
processing function
Pulse Signal Processing
1: Enables two-phase pulse signal
Function Select Bit(3)
processing function
TA2P
TA3P
TA4P
RW
WO
WO
WO
NOTES:
1. Use the MOV instruction to set the UDF register.
2. This bit is enabled when the MR2 bit in the TAiMR register (i=0 to 4) is set to "0" (the UDF register
causes increment/decrement switching) in event counter mode.
3. Set this bit to "0" when not using the two-phase pulse signal processing function.
One-Shot Start Flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
ONSF
Bit
Symbol
Address
034216
After Reset
0016
Bit Name
Function
RW
TA0OS
Timer A0 One-Shot
Start Flag(1)
0: In an idle state
1: Starts the timer
RW
TA1OS
Timer A1 One-Shot
Start Flag(1)
0: In an idle state
1: Starts the timer
RW
TA2OS
Timer A2 One-Shot
Start Flag(1)
0: In an idle state
1: Starts the timer
RW
TA3OS
Timer A3 One-Shot
Start Flag(1)
0: In an idle state
1: Starts the timer
RW
TA4OS
Timer A4 One-Shot
Start Flag(1)
0: In an idle state
1: Starts the timer
RW
TAZIE
Z-Phase Input Enable
Bit
0: Disables Z-phase input
1: Enables Z-phase input
RW
b7b6
TA0TGL
Timer A0 Event/Trigger
Select Bit
TA0TGH
NOTES:
1. When read, this bit is set to "0".
2. Overflow or underflow.
Figure 14.6 UDF Register and ONSF Register
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REJ09B0271-0100
0 0: Selects an input to the TA0IN pin RW
0 1: Selects the TB2 overflows(2)
1 0: Selects the TA4 overflows(2)
RW
1 1: Selects the TA1 overflows(2)
14. Timer (Timer A)
M32C/80 Group
Trigger Select Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
TRGSR
034316
0016
Bit
Symbol
Function
RW
0 0: Selects an input to the TA1IN pin
0 1: Selects the TB2 overflows(1)
1 0: Selects the TA0 overflows(1)
1 1: Selects the TA2 overflows(1)
RW
Bit Name
b1 b0
TA1TGL
Timer A1 Event/Trigger
Select Bit
TA1TGH
RW
b3 b2
TA2TGL
Timer A2 Event/Trigger
Select Bit
TA2TGH
0 0: Selects an input to the TA2IN pin
0 1: Selects the TB2 overflows(1)
1 0: Selects the TA1 overflows(1)
1 1: Selects the TA3 overflows(1)
RW
RW
b5 b4
TA3TGL
Timer A3 Event/Trigger
Select Bit
TA3TGH
0 0: Selects an input to the TA3IN pin
0 1: Selects the TB2 overflows(1)
1 0: Selects the TA2 overflows(1)
1 1: Selects the TA4 overflows(1)
RW
RW
b7 b6
TA4TGL
Timer A4 Event/Trigger
Select Bit
TA4TGH
0 0: Selects an input to the TA4IN pin
0 1: Selects the TB2 overflows(1)
1 0: Selects the TA3 overflows(1)
1 1: Selects the TA0 overflows(1)
RW
RW
NOTE:
1. Overflow or underflow
Count Source Prescaler Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TCSPR
Bit
Symbol
Address
035F16
Bit Name
After Reset(2)
0XXX 00002
Function
RW
CNT0
CNT1
Divide Ratio Select Bit(1)
CNT2
If setting value is n, f2n is the
main clock, on-chip oscillator or
PLL clock divided by 2n.
Not divided if n=0.
CST
RW
RW
RW
CNT3
(b6 - b4)
RW
Reserved Bit
Operation Enable Bit
When read,
its content is indeterminate
0: Stops a divider
1: Starts a divider
RO
RW
NOTES:
1. Set the CST bit to "0" before the CNT3 to CNT0 bits are rewritten.
2. The TCSPR register maintains values set before reset, even after software reset or watchdog timer
reset has performed.
Figure 14.7 TRGSR Register and TCSPR Register
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REJ09B0271-0100
14. Timer (Timer A)
M32C/80 Group
Table 14.1 Pin Settings for Output from TAiOUT Pin (i=0 to 4)
Pin
Setting
PS1, PS2 Registers
PSL1, PSL2 Registers
PSC Register
P70/TA0OUT(1)
PS1_0= 1
PSL1_0=1
PSC_0= 0
P72/TA1OUT
PS1_2= 1
PSL1_2=1
PSC_2= 0
P74/TA2OUT
PS1_4= 1
PSL1_4=0
PSC_4= 0
P76/TA3OUT
PS1_6= 1
PSL1_6=1
PSC_6= 0
P80/TA4OUT
PS2_0= 1
PSL2_0=0
–
NOTE:
1. P70/TA0OUT is a port for the N-channel open drain output.
Table 14.2 Pin Settings for Input to TAiIN and TAiOUT Pins (i=0 to 4)
Pin
Setting
PS1, PS2 Registers
PD7, PD8 Registers
P70/TA0OUT
PS1_0=0
PD7_0=0
P71/TA0IN
PS1_1=0
PD7_1=0
P72/TA1OUT
PS1_2=0
PD7_2=0
P73/TA1IN
PS1_3=0
PD7_3=0
P74TA2OUT
PS1_4=0
PD7_4=0
P75/TA2IN
PS1_5=0
PD7_5=0
P76TA3OUT
PS1_6=0
PD7_6=0
P77/TA3IN
PS1_7=0
PD7_7=0
P80/TA4OUT
PS2_0=0
PD8_0=0
P81/TA4IN
PS2_1=0
PD8_1=0
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REJ09B0271-0100
14. Timer (Timer A)
M32C/80 Group
14.1.1 Timer Mode
In timer mode, the timer counts an internally generated count source (see Table 14.3). Figure 14.8
shows the TAiMR register (i=0 to 4) in timer mode.
Table 14.3 Timer Mode Specifications
Item
Specification
Count Source
f1, f8, f2n(1), fC32
Counting Operation
• The timer decrements a counter value
When the timer counter underflows, content of the reload register is reloaded into the
count register and counting resumes.
Divide Ratio
1/(n+1)
n: setting value of the TAi register (i=0 to 4)
000016 to FFFF16
Counter Start Condition
The TAiS bit in the TABSR register is set to "1" (starts counting)
Counter Stop Condition
The TAiS bit is set to "0" (stops counting)
Interrupt Request Generation Timing The timer counter underflows
TAiIN Pin Function
Programmable I/O port or gate input
TAiOUT Pin Function
Programmable I/O port or pulse output
Read from Timer
The TAi register indicates counter value
Write to Timer
• While the timer counter stops, the value written to the TAi register is also written to
both reload register and counter
• While counting, the value written to the TAi register is written to the reload register
(It is transferred to the counter at the next reload timing)
Selectable Function
• Gate function
Input signal to the TAiIN pin determines whether the timer counter starts or stops counting
• Pulse output function
The polarity of the TAiOUT pin is inversed whenever the timer counter underflows
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
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14. Timer (Timer A)
M32C/80 Group
Timer Ai Mode Register (i=0 to 4) (Timer Mode)
b7
b6
b5
0
b4
b3
b2
b1
b0
0 0 0
Symbol
TA0MR to TA4MR
Bit
Symbol
Address
035616, 035716, 035816, 035916, 035A16
Bit Name
TMOD0
Operating Mode
Select Bit
Function
b1b0
RW
RW
0 0: Timer mode
TMOD1
(b2)
After Reset
0016
RW
Reserved Bit
Set to "0"
RW
b4b3
MR1
Gate Function
Select Bit
MR2
MR3
0 X: Gate function disabled(1)
RW
(TAiIN pin is a programmable I/O pin)
1 0: Timer counts only while the
TAiIN pin is held "L"
RW
1 1: Timer counts only while the
TAiIN pin is held "H"
Set to "0" in timer mode
RW
b7b6
TCK0
Count Source
Select Bit
TCK1
0 0: f1
0 1: f8
1 0: f2n(2)
1 1: fC32
RW
RW
NOTES:
1. X can be set to either "0" or "1".
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.8 TA0MR to TA4MR Registers
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14. Timer (Timer A)
M32C/80 Group
14.1.2 Event Counter Mode
In event counter mode, the timer counts how many external signals are applied or how many times
another timer counter overflows and underflows. The timers A2, A3 and A4 can count externally generated two-phase signals. Table 14.4 lists specifications in event counter mode (when not handling a twophase pulse signal). Table 14.5 lists specifications in event counter mode (when handling a two-phase
pulse signal with the timers A2, A3 and A4). Figure 14.9 shows the TAiMR register (i=0 to 4) in event
counter mode.
Table 14.4 Event Counter Mode Specifications (When Not Processing Two-phase Pulse Signal)
Item
Count Source
Specification
• External signal applied to the TAiIN pin (i = 0 to 4) (valid edge can be selected by program)
• Timer B2 overflow or underflow signal, timer Aj overflow or underflow signal (j=i-1,
except j=4 if i=0) and timer Ak overflow or underflow signal (k=i+1, except k=0 if i=4)
Counting Operation
• External signal and program can determine whether the timer increments or decrements a counter value
• When the timer counter underflows or overflows, content of the reload register is
reloaded into the count register and counting resumes. When the free-running count
function is selected, the timer counter continues running without reloading.
Divide Ratio
• 1/(FFFF16 - n + 1) for counter increment
Counter Start Condition
The TAiS bit in the TABSR register is set to "1" (starts counting)
Counter Stop Condition
The TAiS bit is set to "0" (stops counting)
• 1/(n + 1) for counter decrement
n : setting value of the TAi register 0000 16 to FFFF16
Interrupt Request Generation Timing The timer counter overflows or underflows
TAiIN Pin Function
Programmable I/O port or count source input
TAiOUT Pin Function
Programmable I/O port, pulse output or input selecting a counter increment or decrement
Read from Timer
The TAi register indicates counter value
Write to Timer
• When the timer counter stops, the value written to the TAi register is also written to
both reload register and counter
• While counting, the value written to the TAi register is written to the reload register
(It is transferred to the counter at the next reload timing)
Selectable Function
• Free-running count function
Content of the reload register is not reloaded even if the timer counter overflows or
underflows
• Pulse output function
The polarity of the TAiOUT pin is inversed whenever the timer counter overflows or
underflows
Rev. 1.00 Nov. 01, 2005 Page 138 of 330
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14. Timer (Timer A)
M32C/80 Group
Table 14.5 Event Counter Mode Specifications (When Processing Two-phase Pulse Signal on
Timer A2, A3 and A4)
Item
Specification
Count Source
Two-phase pulse signal applied to the TAiIN and TAiOUT pins (i = 2 to 4)
Counting Operation
• Two-phase pulse signal determines whether the timer increments or decrements a
counter value
• When the timer counter overflows or underflows, content of the reload register is
reloaded into the count register and counting resumes. With the free-running count
function, the timer counter continues running without reloading.
Divide Ratio
• 1/ (FFFF16 - n + 1) for counter increment
• 1/ (n + 1) for counter decrement
n : setting value of the TAi register 000016 to FFFF16
Counter Start Condition
The TAiS bit in the TABSR register is set to "1" (starts counting)
Counter Stop Condition
The TAiS bit is set to "0" (stops counting)
Interrupt Request Generation Timing The timer counter overflows or underflows
TAiIN Pin Function
Two-phase pulse signal is applied
TAiOUT Pin Function
Two-phase pulse signal is applied
Read from Timer
The TAi register indicates the counter value
Write to Timer
• When the timer counter stops, the value written to the TAi register is also written to
both reload register and counter
• While counting, the value written to the TAi register is written to the reload register
(It is transferred to the counter at the next reload timing)
Selectable
Function(1)
• Normal processing operation (the timer A2 and timer A3)
While a high-level ("H") signal is applied to the TAjOUT pin (j = 2 or 3), the timer
increments a counter value on the rising edge of the TAjIN pin or decrements a
counter on the falling edge.
TAjOUT
TAjIN
Increment Increment Increment Decrement Decrement Decrement
• Multiply-by-4 processing operation (the timer A3 and timer A4)
While an "H" signal is applied to the TAkOUT pin (k = 3 or 4) on the rising edge of the
TAkIN pin, the timer increments a counter value on the rising and falling edges of the
TAkOUT and TAkIN pins.
While an "H" signal is applied to the TAkOUT pin on the falling edge of the TAkIN pin, the
timer decrements a counter value on the rising and falling edges of the TAkOUT and
TAkIN pins.
TAkOUT
TAkIN
Increment on all edges
Decrement on all edges
NOTE:
1. Only timer A3 operation can be selected. The timer A2 is for the normal processing operation. The timer A4 is
for the multiply-by-4 operation.
Rev. 1.00 Nov. 01, 2005 Page 139 of 330
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14. Timer (Timer A)
M32C/80 Group
Timer Ai Mode Register (i=0 to 4) (Event Counter Mode)
b7
b6
b5
0
b4
b3
b2
b1
b0
0 0 1
Symbol
TA0MR to TA4MR
Bit
Symbol
Address
035616, 035716, 035816, 035916, 035A16
Bit Name
TMOD0
Operating Mode
Select Bit
After Reset
0016
Function
Function
(When not processing
two-phase pulse signal)
(When processing
two-phase pulse signal)
RW
RW
b1b0
0 1: Event counter mode(1)
RW
TMOD1
Reserved Bit
Set to "0"
RW
MR1
Count Polarity
Select Bit(2)
0: Counts falling edges
of an external signal
Set to "0"
1: Counts rising edges
of an external signal
RW
MR2
Increment/Decrement 0: UDF registser
setting
Switching Source
1: Input signal to
Select Bit
TAiOUT pin(3)
(b2)
Set to "1"
RW
MR3
Set to "0" in event counter mode
RW
TCK0
Count Operation
Type Select Bit
RW
TCK1
Two-Phase Pulse
Set to "0"
Signal Processing
Operation Select Bit(4,5)
0: Reloading
1: Free running
0: Normal processing
operation
RW
1: Multiply-by-4
processing operation
NOTES:
1. The TAiTGH and TAiTGL bits in the ONSF or TRGSR register determine the count source in the event
counter mode.
2. MR1 bit setting is enabled only when counting how many times external signals are applied.
3. The timer decrements a counter value when an "L" signal is applied to the TAiOUT pin and the timer
increments a counter value when an "H" signal is applied to the TAiOUT pin.
4. The TCK1 bit is enabled only in the TA3MR register.
5. For two-phase pulse signal processing, set the TAjP bit in the UDF register (j=2 to 4) to "1" (twophase pulse signal processing function enabled). Also, set the TAjTGH and TAjTGL bits to "002"
(input to the TAjIN pin).
Figure 14.9 TA0MR to TA4MR Registers
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14. Timer (Timer A)
M32C/80 Group
14.1.2.1 Counter Reset by Two-Phase Pulse Signal Processing
Z-phase input resets the timer counter when processing a two-phase pulse signal.
This function can be used in timer A3 event counter mode, two-phase pulse signal processing, free_______
running count operation type or multiply-by-4 processing. The Z-phase signal is applied to the INT2 pin.
When the TAZIE bit in the ONSF register is set to "1" (Z-phase input enabled), Z-phase input can
reset the timer counter. To reset the counter by a Z-phase input, set the TA3 register to "000016"
beforehand.
_______
Z-phase input is enabled when the edge of the signal applied to the INT2 pin is detected. The POL bit
in the INT2IC register can determine edge polarity. The Z-phase must have a pulse width of one timer
A3 count source cycle or more . Figure 14.10 shows two-phase pulses (A-phase and B-phase) and
the Z-phase.
Z-phase input resets the timer counter in the next count source following Z-phase input. Figure 14.11
shows the counter reset timing.
Timer A3 interrupt request is generated twice continuously when a timer A3 overflow or underflow,
_______
and a counter reset by INT2 input occur at the same time. Do not use the timer A3 interrupt request
when this function is used.
TA3OUT
(A-phase)
TA3IN
(B-phase)
Count source
INT2 (1)
(Z-phase)
Pulse width of one count source cycle
or more is required
NOTE:
1. When the rising edge of INT2 is selected.
Figure 14.10 Two-Phase Pulse (A-phase and B-phase) and Z-phase
TA3OUT
(A-phase)
TA3IN
(B-phase)
Count source
INT2 (1)
(Z-phase)
Counter value
m
m+1
1
Timer counter is reset
at this timing
Figure 14.11 Counter Reset Timing
Rev. 1.00 Nov. 01, 2005 Page 141 of 330
REJ09B0271-0100
2
3
4
5
NOTE:
1. When the rising edge of INT2 is selected.
14. Timer (Timer A)
M32C/80 Group
14.1.3 One-Shot Timer Mode
In one-shot timer mode, the timer operates only once for each trigger (see Table 14.6). Once a trigger
occurs, the timer starts and continues operating for a desired period. Figure 14.12 shows the TAiMR
register (i=0 to 4) in one-shot timer mode.
Table 14.6 One-Shot Timer Mode Specifications
Item
Specification
Count Source
f1, f8, f2n(1), fC32
Counting Operation
• The timer decrements a counter value
When the timer counter reaches "000016", it stops counting after reloading.
If a trigger occurs while counting, content of the reload register is reloaded into the
count register and counting resumes.
Divide Ratio
1/n
n : setting value of the TAi register (i=0 to 4) 000016 to FFFF16,
Counter Start Condition
The TAiS bit in the TABSR register is set to "1" (starts counting) and following triggers
but the timer counter does not run if n=000016
occur:
• External trigger input is provided
• Timer counter overflows or underflows
• The TAiOS bit in the ONSF register is set to "1" (timer started)
Counter Stop Condition
• After the timer counter has reached "000016" and is reloaded
• When the TAiS bit is set to "0" (stops counting)
Interrupt Request Generation Timing The timer counter reaches "000016"
TAiIN Pin Function
Programmable I/O port or trigger input
TAiOUT Pin Function
Programmable I/O port or pulse output
Read from Timer
The value in the TAi register is indeterminate when read
Write to Timer
• When the timer counter stops, the value written to the TAi register is also written to
both reload register and counter
• While counting, the value written to the TAi register is written to the reload register
(It is transferred to the counter at the next reload timing)
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
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14. Timer (Timer A)
M32C/80 Group
Timer Ai Mode Register (i=0 to 4) (One-Shot Timer Mode)
b7
b6
b5
0
b4
b3
b2
b1
b0
Symbol
0 1 0
TA0MR to TA4MR
Bit
Symbol
Address
035616, 035716, 035816, 035916, 035A16
Bit Name
TMOD0
Operating Mode
Select Bit
After Reset
0016
Function
b1b0
RW
1 0: One-shot timer mode
RW
TMOD1
(b2)
RW
Reserved Bit
Set to "0"
MR1
External Trigger Select 0: Falling edge of input signal to TAiIN pin
RW
Bit(1)
1: Rising edge of input signal to TAiIN pin
MR2
Trigger Select Bit
MR3
Set to "0" in the one-shot timer mode
0: The TAiOS bit is enabled
1: Selected by the TAiTGH and
TAiTGL bits
b7b6
TCK0
Count Source
Select Bit
TCK1
0 0: f1
0 1: f8
1 0: f2n(2)
1 1: fC32
RW
RW
RW
RW
NOTES:
1. The MR1 bit setting is enabled only when the TAiTGH and TAiTGL bits in the TRGSR register are set
to "002" (input to the TAiIN pin). The MR1 bit can be set to either "0" or "1" when the TAiTGH and
TAiTGL bits are set to "012" (TB2 overflow and underflow), "102" (TAi overflow and underflow), or
"112" (TAi overflow and underflow).
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.12 TA0MR to TA4MR Registers
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14. Timer (Timer A)
M32C/80 Group
14.1.4 Pulse Width Modulation Mode
In pulse width modulation mode, the timer outputs pulse of desired width continuously (see Table 14.7).
The timer counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure
14.13 shows the TAiMR register (i=0 to 4) in pulse width modulation mode. Figures 14.14 and 14.15
show examples of how a 16-bit pulse width modulator operates and of how an 8-bit pulse width modulator
operates.
Table 14.7 Pulse Width Modulation Mode Specifications
Item
Specification
Count Source
f1, f8, f2n(1), fC32
Counting Operation
• The timer decrements a counter value
(The counter functions as an 8-bit or a 16-bit pulse width modulator)
Content of the reload register is reloaded on the rising edge of PWM pulse and counting continues.
The timer is not affected by a trigger that is generated during counting.
16-Bit PWM
• "H" width = n / fj
n : setting value of the TAi register
000016 to FFFE16
fj : count source frequency
• Cycle = (216-1) / fj fixed
8-Bit PWM
• "H" width = n x (m+1) / fj
• Cycles = (28-1) x (m+1) / fj
m : setting value of low-order bit address of the TAi register
n : setting value of high-order bit address of the TAi register
Counter Start Condition
0016 to FF16
0016 to FE16
• External trigger input is provided
• Timer counter overflows or underflows
• The TAiS bit in the TABSR register is set to "1" (starts counting)
Counter Stop Condition
The TAiS bit is set to "0" (stops counting)
Interrupt Request Generation Timing On the falling edge of the PWM pulse
TAiIN Pin Function
Programmable I/O port or trigger input
TAiOUT Pin Function
Pulse output
Read from Timer
The value in the TAi register is indeterminate when read
Write to Timer
• When the timer counter stops, the value written to the TAi register is also written to
both reload register and counter
• While counting, the value written to the TAi register is written to the reload register
(It is transferred to the counter at the next reload timing)
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Rev. 1.00 Nov. 01, 2005 Page 144 of 330
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14. Timer (Timer A)
M32C/80 Group
Timer Ai Mode Register (i=0 to 4) (Pulse Width Modulator Mode)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TA0MR to TA4MR
0 1 1
Bit
Symbol
Address
035616, 035716, 035816, 035916, 035A16
Bit Name
TMOD0
Operating Mode
Select Bit
TMOD1
After Reset
0016
Function
b1b0
1 1: Pulse width modulation (PWM)
mode
RW
RW
Reserved Bit
Set to "0"
External Trigger Select
Bit(1)
0: Falling edge of input signal to TAiIN pin
RW
1: Rising edge of input signal to TAiIN pin
(b2)
MR1
RW
RW
MR2
Trigger Select Bit
0: The TAiS bit is enabled
1: Selected by the TAiTGH and TAiTGL
bits
MR3
16/8-Bit PWM Mode
Select Bit
0: Functions as a 16-bit pulse width modulator
RW
1: Functions as an 8-bit pulse width modulator
b7b6
TCK0
Count Source
Select Bit
TCK1
0 0: f1
0 1: f8
1 0: f2n(2)
1 1: fC32
RW
RW
RW
NOTES:
1. MR1 bit setting is enabled only when the TAiTGH and TAiTGL bits in the TRGSR register are set to
"002" (input to the TAiIN pin). The MR1 bit can be set to either "0" or "1" when the TAiTGH and
TAiTGL bits are set to "012" (TB2 overflow and underflow), "102" (TAi overflow and underflow) or
"112" (TAi overflow and underflow).
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.13 TA0MR to TA4MR Registers
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14. Timer (Timer A)
M32C/80 Group
When the reload register is set to "000316" and an external trigger (on rising edge
of a signal applied to the TAiIN pin) is selected
1 / fj X (216 – 1)
Count source
“H”
Signal applied
to TAiIN pin
“L”
No trigger occurs by this signal
1 / fi X n
“H”
PWM pulse output
from TAiOUT pin
“L”
“1”
IR bit in TAiIC register
“0”
fj : Count source frequency
(f1, f8, f2n(1), fC32)
Set to "0" by an interrupt request acknowledgement or by program
n=000016 to FFFE16
i=0 to 4
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.14 16-bit Pulse Width Modulator Operation
When 8 high-order bits of the reload register are set to "0216", 8 low-order bits of
the reload register are set to "0216" and an external trigger (on falling edge of a
signal applied to the TAiIN pin) is selected
1 / fj X (m + 1) X (28 – 1)
Count source(1)
Signal applied to
TAiIN pin
“H”
“L”
AAAAAAAAAAAAAAA
1 / fj X (m + 1)
Underflow signal of
8-bit prescaler(2)
“H”
“L”
1 / fj X (m + 1) X n
PWM pulse output
from TAiOUT pin
“H”
“L”
“1”
IR bit in TAiIC register
“0”
fj : Count source frequency
(f1, f8, f2n(3), fC32)
Set to "0" by an interrupt request
acknowledgement or by program
m=0016 to FF16, n=0016 to FE16
i=0 to 4
NOTES:
1. 8-bit prescaler counts a count source.
2. 8-bit pulse width modulator counts underflow signals of the 8-bit prescaler.
3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.15 8-bit Pulse Width Modulator Operation
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14. Timer (Timer B)
M32C/80 Group
14.2 Timer B
Figure 14.16 shows a block diagram of the timer B. Figures 14.17 to 14.19 show registers associated with
the timer B. The timer B supports the following three modes. The TMOD1 and TMOD0 bits in the TBiMR
register (i=0 to 5) determine which mode is used.
• Timer mode : The timer counts an internal count source.
• Event counter mode : The timer counts pulses from an external source or overflow and underflow of
another timer.
• Pulse period/pulse width measurement mode : The timer measures pulse period or pulse width of an
external signal.
Table 14.8 lists TBiIN pin settings.
High-order Bits of Data Bus
Select Clock Source
Low-order Bits of Data Bus
TCK1 and
TCK0
00
00: Timer Mode
f1
TMOD1 and
01: Pulse Period/Pulse Width TMOD0
01
f8
Measurement Mode
f2n(1) 10
fc32 11
01: Event
TCK1
Counter Mode
TBj Overflow
1
Signal(2,3)
8 highorder
bits
Reload Register
Counter
TBiS
0
Polarity Switching
and Edge Pulse
TBiIN
8 low-order
bits
Counter Reset Circuit
i=0 to 5
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no
division (n=0) or divide-by-2n (n=1 to 15).
2. Overflow signal or underflow signal.
3. j=i-1, except j=2 when i=0 j=5 when i=3
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
Address
035116 035016
035316 035216
035516 035416
031116 031016
031316 031216
031516 031416
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TBiMR Register
TBiS: Bits in the TABSR and the TBSR Register
Figure 14.16 Timer B Block Diagram
Timer Bi Register(1) (i=0 to 5)
b15
b8 b7
b0
Symbol
TB0 to TB2
TB3 to TB5
Mode
Address
035116 - 035016, 035316 - 035216, 035516 - 035416
After Reset
Indeterminate
031116 - 031016, 031316 - 031216, 031516 - 031416
Indeterminate
Function
Setting Range
RW
Timer Mode
If setting value is n, a count source 000016 to FFFF16 RW
is divided by n+1
Event Counter
Mode
If setting value is n, a count source 000016 to FFFF16 RW
is divided by n+1(2)
Pulse Period/Pulse A count source is incremented
Width Measurement between one valid edge and
Mode
another valid edge of TBiIN pulse
RO
NOTES:
1. Use 16-bit data for reading and writing.
2. The TBi register counts how many pulse inputs are provided externally or how many times another
timer counter overflows and underflows.
Figure 14.17 TB0 to TB5 Registers
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14. Timer (Timer B)
M32C/80 Group
Timer Bi Mode Register (i=0 to 5)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TB0MR to TB5MR
Bit
Symbol
Address
After Reset
035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002
Bit Name
Function
RW
b1b0
TMOD0
Operating Mode
Select Bit
TMOD1
0 0: Timer mode
RW
0 1: Event counter mode
1 0: Pulse period measurement mode,
pulse width measurement mode
RW
1 1: Do not set to this value
MR0
RW
MR1
Function varies depending on
operating mode (1, 2)
MR2
MR3
RW
RW
RW
TCK0
RW
Count Source
Select Bit
Function varies depending on
operating mode
TCK1
RW
NOTES:
1. Only MR2 bits in the TB0MR and TB3MR registers are enabled.
2. Nothing is assigned in the MR2 bit in the TB1MR, TB2MR, TB4MR and TB5MR registers.
When write, set to "0". When read, its content is indeterminate.
Count Start Flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Bit
Symbol
Address
034016
After Reset
0016
Bit Name
Function
RW
TA0S
Timer A0 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TA1S
Timer A1 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TA2S
Timer A2 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TA3S
Timer A3 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TA4S
Timer A4 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TB0S
Timer B0 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TB1S
Timer B1 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TB2S
Timer B2 Count
Start Flag
0: Stops counting
1: Starts counting
RW
Figure 14.18 TB0MR to TB5MR Registers, TABSR Register
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14. Timer (Timer B)
M32C/80 Group
Timer B3, B4,B5 Count Start Flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TBSR
Bit
Symbol
Address
030016
After Reset
000X XXXX2
Bit Name
Function
RW
Nothing is assigned. When write, set to "0".
(b4 - b0) When read, its content is indeterminate.
TB3S
Timer B3 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TB4S
Timer B4 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TB5S
Timer B5 Count
Start Flag
0: Stops counting
1: Starts counting
RW
Figure 14.19 TBSR Register
Table 14.8 Settings for the TBiIN Pins (i=0 to 5)
Port Name
Function
Setting
PS1, PS3(1) Registers
PD7, PD9(1) Registers
P90
TB0IN
PS3_0=0
PD9_0=0
P91
TB1IN
PS3_1=0
PD9_1=0
P92
TB2IN
PS3_2=0
PD9_2=0
P93
TB3IN
PS3_3=0
PD9_3=0
P94
TB4IN
PS3_4=0
PD9_4=0
P71
TB5IN
PS1_1=0
PD7_1=0
NOTE:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (
write enabled). Do not generate an interrupt or a DMA transfer between the instruction to set the
PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers.
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14. Timer (Timer B)
M32C/80 Group
14.2.1 Timer Mode
In timer mode, the timer counts an internally generated count source (see Table 14.9). Figure 14.20
shows the TBiMR register (i=0 to 5) in timer mode.
Table 14.9 Timer Mode Specifications
Item
Specification
Count Source
f1, f8, f2n(1), fC32
Counting Operation
• The timer decrements a counter value
When the timer counter underflows, content of the reload register is reloaded into the
count register and counting resumes
Divide Ratio
1/(n+1)
n: setting value of the TBi register (i=0 to 5)
Counter Start Condition
The TBiS bits in the TABSR and TBSR registers are set to "1" (starts counting)
Counter Stop Condition
The TBiS bit is set to "0" (stops counting)
000016 to FFFF16
Interrupt Request Generation Timing Timer counter underflows
TBiIN Pin Function
Programmable I/O port
Read from Timer
The TBi register indicates counter value
Write to Timer
• When the timer counter stops, the value written to the TBi register is also written to
both reload register and counter
• While counting, the value written to the TBi register is written to the reload register
(It is transferred to the counter at the next reload timing)
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Timer Bi Mode Register (i=0 to 5) (Timer Mode)
b7
b6
b5
0
b4
b3
b2
b1
b0
0 0
Symbol
Address
After reset
TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002
Bit
Symbol
Bit Name
TMOD0
Operating Mode
Select Bit
Function
b1b0
MR1
RW
0 0: Timer mode
TMOD1
MR0
RW
RW
RW
Disabled in timer mode.
Can be set to "0" or "1".
RW
TB0MR, TB3MR registers:
Set to "0" in timer mode
MR2
TB1MR, TB2MR TB4MR, TB5MR registers:
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
MR3
Set to "0" in timer mode
RW
RW
b7 b6
TCK0
Count Source
Select Bit
TCK1
0 0: f1
0 1: f8
1 0: f2n(1)
1 1: fC32
RW
RW
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.20 TB0MR to TB5MR Registers
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REJ09B0271-0100
14. Timer (Timer B)
M32C/80 Group
14.2.2 Event Counter Mode
In event counter mode, the timer counts how many external signals are applied or how many times
another timer overflows and underflows. (See Table 14.10) Figure 14.21 shows the TBiMR register (i=0
to 5) in event counter mode.
Table 14.10 Event Counter Mode Specifications
Item
Count Source
Specification
• External signal applied to the TBiIN pin (i = 0 to 5) (valid edge can be selected by
program)
• TBj overflow or underflow signal (j=i-1, except j=2 when i=0, j=5 when i=3)
Counting Operation
• The timer decrements a counter value
When the timer counter underflows, content of the reload register is reloaded into the
count register to continue counting
Divide Ratio
1/(n+1)
n : setting value of the TBi register
Counter Start Condition
The TBiS bits in the TABSR and TBSR register are set to "1" (starts counting)
Counter Stop Condition
The TBiS bit is set to "0" (stops counting)
000016 to FFFF16
Interrupt Request Generation Timing The timer counter underflows
TBiIN Pin Function
Programmable I/O port or count source input
Read from Timer
The TBi register indicates counter value
Write to Timer
• When the timer counter stops, the value written to the TBi register is also written to
both reload register and counter
• While counting, the value written to the TBi register is written to the reload register
(It is transferred to the counter at the next reload timing)
Rev. 1.00 Nov. 01, 2005 Page 151 of 330
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14. Timer (Timer B)
M32C/80 Group
Timer Bi Mode Register (i=0 to 5) (Event Counter Mode)
b7
b6
b5
0
b4
b3
b2
b1
b0
0 1
Symbol
Address
After reset
TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002
Bit
Symbol
TMOD0
TMOD1
Bit Name
Operating Mode
Select Bit
Function
b1b0
0 1: Event counter mode
RW
RW
RW
b3b2
MR0
Count Polarity Select
Bit(1)
MR1
0 0: Counts falling edges of external signal RW
0 1: Counts rising edges of external signal
1 0: Counts falling and rising edges of
external signal
RW
1 1: Do not set to this value
TB0MR and TB3MR registers:
Set to "0" in event counter mode
MR2
RW
TB1MR, TB2MR, TB4MR and TB5MR registers:
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
MR3
Disabled in event counter mode. When write, set to "0".
When read, its content is indeterminate.
TCK0
Disabled in event counter mode.
Can be set to "0" or "1".
TCK1
Event Clock
Select Bit
0: Input signal from the TBiIN pin
1: TBj overflows or underflows(2)
RW
RW
NOTES:
1. MR0 and MR1 bit settings are enabled when the TCK1 bit is set to "0". The MR1 bit can be set to
either "0" or "1", when the TCK1 bit is set to "1".
2. j=i-1, except j=2 when i=0 and j=5 when i=3.
Figure 14.21 TB0MR to TB5MR Registers
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REJ09B0271-0100
14. Timer (Timer B)
M32C/80 Group
14.2.3 Pulse Period/Pulse Width Measurement Mode
In pulse period/pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal. (See Table 14.11) Figure 14.22 shows the TBiMR register (i=0 to 5) in pulse period/pulse
width measurement mode. Figure 14.23 shows an operation example in pulse period measurement
mode. Figure 14.24 shows an operation example in the pulse width measurement mode.
Table 14.11 Pulse Period/Pulse Width Measurement Mode Specifications
Item
Specification
Count Source
f1, f8, f2n(3), fC32
Counting Operation
• The timer increments a counter value
Counter value is transferred to the reload register on the valid edge of a pulse to be
measured. It is set to "000016" and the timer continues counting
Counter Start Condition
The TBiS bits (i=0 to 5) in the TABSR and TBSR register are set to "1" (starts counting)
Counter Stop Condition
The TBiS bit is set to "0" (stops counting)
Interrupt Request Generation Timing • On the valid edge of a pulse to be measured(1)
• The timer counter overflows
The MR3 bit in the TBiMR register is set to "1" (overflow) simultaneously. When the
TBiS bit is set to "1" (start counting) and the next count source is counted after setting
the MR3 bit to "1" (overflow), the MR3 bit can be set to "0" (no overflow) by writing to
the TBiMR register.
TBiIN Pin Function
Input for a pulse to be measured
Read from Timer
The TBi register indicates reload register values (measurement results)(2)
Write to Timer
Value written to the TBi register can be written to neither reload register nor counter
NOTES:
1. No interrupt request is generated when the pulse to be measured is on the first valid edge after the
timer has started counting.
2. The TBi register is in an indeterminate state until the pulse to be measured is on the second valid
edge after the timer has started counting.
3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Rev. 1.00 Nov. 01, 2005 Page 153 of 330
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14. Timer (Timer B)
M32C/80 Group
Timer Bi Mode Register (i=0 to 5)
(Pulse Period / Pulse Width Measurement Mode)
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Symbol
Address
After reset
TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002
Bit
Symbol
TMOD0
TMOD1
Bit Name
Operating Mode
Select Bit
Function
RW
b1b0
RW
1 0: Pulse period measurement mode,
Pulse width measurement mode RW
b3b2
MR0
Measurement Mode
Select Bit(1)
MR1
0 0: Pulse period measurement 1
0 1: Pulse period measurement 2
1 0: Pulse width measurement
1 1: Do not set to this value
TB0MR, TB3MR registers:
Set to "0" in pulse period/pulse width measurement mode
MR2
MR3
RW
RW
RW
TB1MR, TB2MR TB4MR, TB5MR registers:
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
0: No overflow
Timer Bi Overflow Flag(2) 1: Overflow
RO
b7b6
TCK0
Count Source
Select Bit
TCK1
0 0: f1
0 1: f8
1 0: f2n(3)
1 1: fC32
RW
RW
NOTES:
1. The MR1 and MR0 bits selects the following measurements.
Pulse period measurement 1 (the MR1 and MR0 bits are set to "002"):
Measures between the falling edge and the next falling edge of a pulse to be measured
Pulse period measurement 2 (the MR1 and MR0 bits are set to "012"):
Measures between the rising edge and the next rising edge of a pulse to be measured
Pulse width measurement (the MR1 and MR0 bits are set to "102"):
Measures between a falling edge and the next rising edge of a pulse to be measured and
between the rising edge and the next falling edge of a pulse to be measured
2. The MR3 bit is indeterminate when reset.
To set the MR3 bit to "0", se the TBiMR register after the MR3 bit is set to "1" and one or more cycles
of the count source are counted, while the TBiS bits in the TABSR and TBSR registers are set to "1"
(starts counting).
The MR3 bit cannot be set to "1" by program.
3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.22 TB0MR to TB5MR Registers
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REJ09B0271-0100
14. Timer (Timer B)
M32C/80 Group
Count source
Pulse to be measured
"H"
"L"
Transferred
(indeterminate value)
Timing to transfer value
from counter to reload
register
Transferred
(measured value)
(Note 1)
(Note 1)
(Note 2)
Timing that the counter
reaches "000016"
TBiS bits in the
TABSR and TBSR
registers
"1"
IR bit in the TBilC
register
"1"
MR3 bit in the TBiMR
register
"1"
"0"
"0"
Set to "0" by an interrupt request acknowledgement or by program
"0"
i=0 to 5
NOTES:
1. The counter is reset when a measurement is completed.
2. The timer counter overflows.
Figure 14.23 Operation Example in Pulse Period Measurement Mode
Count source
"H"
Pulse to be measured
"L"
Timing to transfer value
from counter to reload
register
Transferred
(indeterminate
value)
(Note 1)
Transferred
(measured value)
(Note 1)
Transferred
(measured
value)
(Note 1)
Transferred
(measured value)
(Note 1)
(Note 2)
Timing that the counter
reaches "000016"
TBiS bits in the
TABSR and TBSR
registers
IR bit in the TBilC
register
"1"
"0"
"1"
"0"
Set to "0" by an interrupt request acknowledgement or by program.
MR3 bit in the TBiMR
register
“1”
“0”
i=0 to 5
NOTES:
1. The counter is reset when a measurement is completed.
2. The timer counter overflows.
Figure 14.24 Operation Example in Pulse Width Measurement Mode
Rev. 1.00 Nov. 01, 2005 Page 155 of 330
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15. Three-Phase Motor Control Timer Functions
M32C/80 Group
15. Three-Phase Motor Control Timer Functions
Three-phase motor driving waveform can be output by using the timers A1, A2, A4 and B2. Table 15.1 lists
specifications of the three-phase motor control timer functions. Table 15.2 lists pin settings. Figure 15.1
shows a block diagram. Figures 15.2 to 15.7 show registers associated with the three-phase motor control
timer functions.
Table 15.1 Three-Phase Motor Control Timer Functions Specification
Item
Specification
___
___
___
Three-Phase Waveform Output Pin Six pins (U, U, V, V, W, W)
_______
Forced Cutoff(1)
Apply a low-level ("L") signal to the NMI pin
Timers to be Used
Timer A4, A1, A2 (used in one-shot timer mode):
___
Timer A4: U- and U-phase waveform control
___
Timer A1: V- and V-phase waveform control
___
Timer A2: W- and W-phase waveform control
Timer B2 (used in timer mode):
Carrier wave cycle control
Dead time timer (three 8-bit timers share reload register):
Dead time control
Output Waveform
Triangular wave modulation, Sawtooth wave modulation
Can output a high-level waveform or a low-level waveform for one cycle;
Can set positive-phase level and negative-phase level separately
Carrier Wave Cycle
Triangular wave modulation: count source x (m+1) x 2
Sawtooth wave modulation: count source x (m+1)
m: setting value of the TB2 register, 000016 to FFFF16
Count source: f1, f8, f2n(2), fc32
Three-Phase PWM Output Width
Triangular wave modulation: count source x n x 2
Sawtooth wave modulation: count source x n
n : setting value of the TA4, TA1 and TA2 register (of the TA4, TA41, TA1, TA11,
TA2 and TA21 registers when setting the INV11 bit to "1"), 000116 to FFFF16
Count source: f1, f8, f2n(2), fc32
Dead Time
Count source x p, or no dead time
p: setting value of the DTT register, 0116 to FF16
Count source: f1, or f1 divided by 2
Active Level
Selected from a high level ("H") or low level ("L")
Positive- and Negative-Phase Con- Positive and negative-phases concurrent active disable function
current Active Disable Function
Positive and negative-phases concurrent active detect function
Interrupt Frequency
For the timer B2 interrupt, one carrier wave cycle-to-cycle basis through 15
time- carrier wave cycle-to-cycle basis can be selected
NOTES:
_______
1. Forced cutoff by the signal applied to the NMI pin is available when the INV02 bit is set to "1" (threephase motor control timer functions) and the INV03 bit is set to "1" (three-phase motor control timer
output enabled).
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Rev. 1.00 Nov. 01, 2005 Page 156 of 330
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15. Three-Phase Motor Control Timer Functions
M32C/80 Group
Table 15.2 Pin Settings
Setting
Pin
PS1, PS2 Registers(1)
PSL1, PSL2 Registers
PSC Register
P72/V
PS1_2 =1
PSL1_2 =0
PSC_2 =1
P73/V
PS1_3 =1
PSL1_3 =1
PSC_3 =0
P74/W
PS1_4 =1
PSL1_4 =1
PSC_4 =0
P75/W
PS1_5 =1
PSL1_5 =0
P80/U
PS2_0 =1
PSL2_0 =1
P81/U
PS2_1 =1
PSL2_1 =0
NOTE:
1. Set the PS1_5 to PS1_2 bits and PS2_1 and PS2_0 bits in the PS1 and PS2 registers to "1"
after the INV02 bit is set to "1".
Rev. 1.00 Nov. 01, 2005 Page 157 of 330
REJ09B0271-0100
(Timer Mode)
Timer B2
Rev. 1.00 Nov. 01, 2005 Page 158 of 330
REJ09B0271-0100
TA41 Register
T Q
INV11
(One-Shot Timer Mode)
Timer A4 Counter
Reload
TA11 Register
T Q
INV11
(One-Shot Timer Mode)
Timer A1 Counter
Reload
Figure 15.1 Three-Phase Motor Control Timer Functions Block Diagram
TA21 Register
(One-Shot Timer Mode)
INV11
T Q
Timer A2 Counter
Reload
When setting the TA2S bit to "0", signal is
set to "0"
Trigger
TA2 Register
When setting the TA1S bit to "0", signal is
set to "0"
Trigger
TA1 Register
When setting the TA4S bit to "0", signal is
set to "0"
Trigger
TA4 Register
INV07
INV00
Reload Control Signal for
Timer A4
Start Trigger Signal for
Timers A1, A2, A4
Write Signal
to Timer B2
INV10
Timer B2 Underflow
INV07 to INV00: Bits in INVC0 Register
INV15 to INV10: Bits in INVC1 Register
DUi, DUBi: Bits in IDBi Register (i=0,1)
TA4S to TA1S: Bits in TABSR Register
1/2
0
1
INV06
INV06
Timer A4
One-Shot
Pulse
Transfer
Trigger(1)
INV06
f1
INV12
INV01
INV11
0
1
T
Q
T
Q
T
Q
D
T
Q
DUB0
bit
D
DU0
bit
W-Phase Output Signal
W-Phase Output Signal
Dead Time Timer
n = 1 to 255
V-Phase Output Signal
V-Phase Output Signal
Dead Time Timer
n = 1 to 255
U-Phase Output Signal
Three-Phase Output
Shift Register
(U Phase)
U-Phase Output Signal
T
D Q
D Q
T
D Q
T
D Q
T
T
D Q
D Q
T
INV05
INV04
RESET
NMI
Value to be written
to INV03 bit
Write signal to
INV03 bit
R
Inverse
Control
Inverse
Control
Inverse
Control
Inverse
Control
Inverse
Control
Inverse
Control
INV14
INV02
T
D Q
INV03
Switching to P80, P81 and P72 to P75 is not shown in this diagram.
NOTES:
1. Transfer trigger is generated only when the IDB0 and IDB1 registers are set and the first timer B2 counter
underflows, if the INV06 bit is set to "0" (triangular wave modulation mode).
W-Phase Output
Control Circuit
Trigger
Trigger
V-Phase Output
Control Circuit
Trigger
Trigger
D
DUB1
bit
D
DU1
bit
Reload Register
n = 1 to 255
ICTB2 Counter
n=1 to 15
Timer B2
Interrupt Request Bit
ICTB2 Register n=1 to 15
Dead Time Timer
n = 1 to 255
U-Phase Output
Control Circuit
Trigger
Trigger
A
PWCON
INV13
Circuit to set Interrupt
Generating Frequency
W
W
V
V
U
U
M32C/80 Group
15. Three-Phase Motor Control Timer Functions
15. Three-Phase Motor Control Timer Functions
M32C/80 Group
Three-Phase PWM Control Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
INVC0
030816
Bit
Symbol
After Reset
0016
Bit Name
Function
RW
INV00
Interrupt Enable Output
Polarity Select Bit(3)
0: The ICTB2 counter is incremented by one on the
rising edge of the timer A1 reload control signal
1: The ICTB2 counter is incremented by one on the
falling edge of the timer A1 reload control signal
RW
INV01
Interrupt Enable Output
Specification Bit(2, 3)
0: ICTB2 counter is incremented by one when
timer B2 counter underflows
1: Selected by the INV00 bit
RW
INV02 Mode Select Bit(4, 5, 6)
0: Three-phase control timer function not used
1: Three-phase control timer function used
(6, 7)
INV03 Output Control Bit
0: Disables three-phase control timer output
1: Enables three-phase control timer output
RW
Positive and NegativeINV04 Phases Concurrent Active
Disable Function Enable Bit
Positive and NegativeINV05 Phases Concurrent Active
Output Detect Flag(8)
0: Enables concurrent active output
1: Disables concurrent active output
RW
0: Not detected
1: Detected
RW
Modulation Mode
Select Bit(9, 10)
0: Triangular wave modulation mode
1: Sawtooth wave modulation mode
RW
Transfer trigger is generated when the
INV07 bit is set to "1". Trigger to the dead
time timer is also generated when setting the
INV06 bit to "1". Its value is "0" when read.
RW
INV06
Software Trigger Select
INV07
Bit
RW
NOTES:
1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
Rewrite the INV02 to INV00 and INV06 bits when the timers A1,A2, A4 and B2 stop.
2. Set the INV01 bit to "1" after setting the ICTB2 register.
3. The INV01 and INV00 bit settings are enabled only when the INV11 bit in the INVC1 register is set to "1"
(three-phase mode 1). The ICTB2 counter is incremented by one every time the timer B2 counter
underflows, regardless of INV01 and INV00bit settings, when the INV11 bit is set to "0" (three-phase mode).
When setting the INV01 bit to "1", set the timer A1 count start flag before the first timer B2 counter underflows.
When the INV00 bit is set to "1", the first interrupt is generated when the timer B2 counter underflows n-1
times, if n is the value set in the ICTB2 counter. Subsequent interrupts are generated every n times the
timer B2 counter underflows.
4. Set the INV02 bit to "1" to operate the dead time timer, U-, V-and W-phase output control circuits and ICTB2
counter.
5. Set pins after the INV02 bit is set to "1". See Table 16.2 for pin settings.
6. When the INV02 bit is set to "1" and the INV03 bit to "0", the U, U, V, V, W and W pins, including pins
shared with other output functions, are all placed in high-impedance states.
7. The INV03 bit is set to "0" when the followings occurs :
- Reset
- A concurrent active state occurs while the INV04 bit is set to "1"
- The INV03 bit is set to "0" by program
- An "H" signal applied to the NMI pin changes to an "L" signal
8. The INV05 bit can not be set to "1" by program. Set the INV04 bit to "0", as well, when setting the INV05 bit
to "0".
9. The following table describes how the INV06 bit setting works.
Item
Mode
INV06 = 0
Triangular wave modulation mode
Timing to Transfer from the IDB0 Transferred once by generating a
and IDB1 Registers to Threetransfer trigger after setting the IDB0
Phase Output Shift Register
and IDB1 registers
INV06 = 1
Sawtooth wave modulation mode
Transferred every time a transfer trigger
is generated
Timing to Trigger the Dead Time On the falling edge of a one-shot pulse By a transfer trigger, or the falling edge of
Timer when the INV16 Bit=0
a one-shot pulse of the timer A1, A2 or A4
of the timer A1, A2 or A4
INV13 Bit
Enabled when the INV11 bit=1 and the Disabled
INV06 bit=0
Transfer trigger: Timer B2 counter underflows and write to the INV07 bit, or write to the TB2 register when INV10 = 1
10. When the INV06 bit is set to "1", set the INV11 bit to "0" (three-phase mode 0) and the PWCON bit in the
TB2SC register to "0" (timer B2 counter underflows).
Figure 15.2 INVC0 Register
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15. Three-Phase Motor Control Timer Functions
M32C/80 Group
Three-Phase PWM Control Register 1(1)
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
INVC1
Bit
Symbol
Address
030916
After Reset
0016
Bit Name
Function
RW
INV10
Timer A1, A2 and A4
Start Trigger Select Bit
0: Timer B2 counter underflows
1: Timer B2 counter underflows and
write to the TB2 register
INV11
Timer A1-1, A2-1 and
A4-1 Control Bit(2, 3)
0: Three-phase mode 0
1: Three-phase mode 1
INV12
Dead Time Timer
0: f1
Count Source Select Bit 1: f1 divided-by-2
INV13
Carrier Wave Detect Flag(4)
0: Timer A1 reload control signal is "0"
RO
1: Timer A1 reload control signal is "1"
INV14
Output Polarity Control Bit
0: High active of an output waveform
RW
1: Low active of an output waveform
INV15
Dead Time Disable Bit
0: Enables dead time
1: Disables dead time
INV16
0: Falling edge of a one-shot pulse of
Dead Time Timer Trigger the timer A1, A2 and A4(5)
RW
1: Rising edge of the three-phase output
Select Bit
shift register (U-, V-, W-phase)
Reserved Bit
RW
RW
RW
Set to "0"
RW
RW
(b7)
NOTES:
1. Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
The timers A1, A2, A4, and B2 must be stopped during rewrite.
2. The following table lists how the INV11 bit setting works.
Item
Mode
INV11 = 0
Three-phase mode 0
TA11, TA21 and TA41 Registers Not used
INV11 = 1
Three-phase mode 1
Used
INV01 and INV00 Bit
in the INVC0 Register
Disabled. The ICTB2 counter is
incremented whenever the timer B2
counter underflows
Enabled
INV13 Bit
Disabled
Enabled when INV11=1 and INV06=0
3. When the INV06 bit in the INVC0 registser is set to "1" (sawtooth wave modulation mode), set the
INV11 bit to "0". Also, when the INV11 bit is set to "0", set the PWCON bit in the TB2SC register to
"0" (Timer B2 counter underflows).
4. The INV13 bit setting is enabled only when the INV06 bit is set to "0" (Triangular wave modulation
mode) and the INV11 bit to "1".
5. If the following conditions are all met, set the INV16 bit to "1":
• The INV15 bit is set to "0"
• The Dij bit (i=U, V or W, j=0, 1) and DiBj bit always have different values when the INV03 bit in
the INVC0 register is set to "1". (The positive-phase and negative-phase outputs always provide
opposite level signals.)
If the above conditions are not met, set the INV16 bit to "0".
Figure 15.3 INVC1 Register
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15. Three-Phase Motor Control Timer Functions
M32C/80 Group
Three-Phase Output Buffer Register i(1) (i=0, 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
IDB0, IDB1
030A16, 030B16
XX11 11112
Bit
Symbol
DUi
DUBi
DVi
DVBi
DWi
DWBi
Bit Name
Function
RW
U-Phase Output Buffer i Write output level
U-Phase Output Buffer i 0: Active level
1: Inactive level
V-Phase Output Buffer i
RW
V-Phase Output Buffer i
When read, the value of the threeW-Phase Output Buffer i phase shift register is read.
RW
W-Phase Output Buffer i
RW
Reserved Bit
(b7 - b6)
RW
RW
When read,
its content is indeterminate
RW
RO
NOTE:
1. Values of the IDB0 and IDB1 registers are transferred to the three-phase output shift register by a
transfer trigger.
After the transfer trigger occurs, the values written in the IDB0 register determine each phase output
signal level first. Then the value written in the IDB1 register on the falling edge of the timers A1, A2
and A4 one-shot pulse determines each phase output signal level.
Dead Time Timer(1, 2)
b7
b0
Symbol
DTT
Address
030C16
Function
If setting value is n, the timer stops when counting
n times a count source selected by the INV12 bit
after start trigger occurs. Positive or negative
phase, which changes from inactive level to active
level, shifts when the dead time timer stops.
After Reset
Indeterminate
Setting Range
RW
1 to 255
WO
NOTES:
1. Use the MOV instruction to set the DTT register.
2. The DTT register setting is enabled when the INV15 bit in the INVC1 register is set to "0" (dead time
enabled). No dead time can be set when the INV15 bit is set to "1" (dead time disabled). The INV06
bit in the INVC0 register determines start trigger of the DTT register.
Figure 15.4 IDB0 and IDB1 registers, DTT Register
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15. Three-Phase Motor Control Timer Functions
M32C/80 Group
Timer B2 Interrupt Generation Frequency Set Counter(1, 2, 3)
b7
b0
Symbol
Address
After Reset
ICTB2
030D16
Indeterminate
Setting Range
Function
When the INV01 bit is set to "0" (the ICTB2 counter
increments whenever the timer B2 counter underflows) and
the setting value is n, the timer B2 interrupt is generated
every nth time timer B2 counter underflow occurs.
When the INV01 bit is set to "1" (the INV00 bit selects
count timing of the ICTB2 counter) and setting value is
n, the timer B2 interrupt is generated every nth time
timer B2 counter underflow meeting the condition
selected in the INV00 bit occurs.
1 to 15
RW
WO
Nothing is assigned. When write, set to "0".
NOTES:
1. Use the MOV instruction to set the ICTB2 register.
2. If the INV01 bit in the INVC0 register is set to "1", set the ICTB2 register in the TABSR register when
the TB2S bit is set to "0" (timer B2 counter stopped).
If the INV01 bit is set to "0" and the TB2S bit to "1" (timer B2 counter start), do not set the ICTB2
register when the timer B2 counter underflows.
3. If the INV00 bit in the INVC0 register is set to "1", the first interrupt is generated when the timer B2
counter underflows n-1 times, n being the value set in the ICTB2 counter. Subsequent interrupts are
generated every n times the timer B2 counter underflows.
Timer Ai, Ai-1 Register (i=1, 2, 4)(1, 2, 3, 4, 5, 6)
b15
b8 b7
b0
Symbol
TA1, TA2, TA4
TA11, TA21, TA41
Address
After Reset
034916 - 034816, 034B16 - 034A16, 034F16 - 034E16 Indeterminate
030316 - 030216, 030516 - 030416, 030716 - 030616 Indeterminate
Function
If setting value is n, the timer stops when the nth count
source is counted after a start trigger is generated.
Positive phase changes to negative phase, and vice
versa, when the timers A1, A2 and A4 stop.
Setting Range
RW
000016 to FFFF16
WO
NOTES:
1. Use a 16-bit data for read and write.
2. If the TAi or TAi1 register is set to "000016", no counter starts and no timer Ai interrupt is generated.
3. Use the MOV instruction to set the TAi and TAi1 registers.
4. When the INV15 bit in the INVC1 register is set to "0" (dead timer enabled), phase switches from an
inactive level to an active level when the dead time timer stops.
5. When the INV11 bit in the INVC1 register is set to "0" (three-phase mode 0), the value of the TAi
register is transferred to the reload register by a timer Ai start trigger.
When the INV11 bit is set to "1" (three-phase mode 1), the value of the TAi1 register is first
transferred to the reload register by a timer Ai start trigger. Then, the value of the TAi register is
transferred by the next trigger. The values of the TAi1 and TAi registers are transferred alternately to
the reload register with every timer Ai start trigger.
6. Do not write to these registers when the timer B2 counter underflows.
Timer B2 Special Mode Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
TB2SC
035E16
XXXX XXX02
Bit
Symbol
PWCON
Bit Name
Timer B2 Reload Timing
Switching Bit(1)
Function
0: Timer B2 counter underflows
1: Timer A output in odd-number
times
RW
RW
Nothing is assigned. When write, set to "0".
When read, its content is "0."
NOTE:
1. Set the PWCON bit to "0" when setting the INV11 bit to "0" (three-phase mode 0) or the INV06 bit to
"1" (sawtooth wave modulation mode).
Figure 15.5 ICTB2 Register, TA1, TA2, TA4, TA11, TA21 and TA41 Registers, TB2SC Register
Rev. 1.00 Nov. 01, 2005 Page 162 of 330
REJ09B0271-0100
15. Three-Phase Motor Control Timer Functions
M32C/80 Group
Timer B2 Register(1)
b15
b8 b7
b0
Symbol
Address
After Reset
TB2
035516 - 035416
Indeterminate
Setting Range
RW
000016 to FFFF16
RW
Function
If setting value is n, count source is divided by n+1.
The timers A1, A2 and A4 start every time an underflow occurs.
NOTE:
1. Use a 16-bit data for read and write.
Trigger Select Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
TRGSR
034316
0016
Bit
Symbol
TA1TGL
TA1TGH
TA2TGL
TA2TGH
Bit Name
Function
RW
Timer A1 Event/Trigger
Select Bit
RW
Set to "012" (TB2 underflow) before
using the V-phase output control circuit RW
Timer A2 Event/Trigger
Select Bit
RW
Set to "012" (TB2 underflow) before
using the W-phase output control circuit RW
b5 b4
Timer A3 Event/Trigger
Select Bit
0 0: Selects an input to the TA3IN pin RW
0 1: Selects TB2 overflow(1)
1 0: Selects TA2 overflow(1)
RW
1 1: Selects TA4 overflow(1)
Timer A4 Event/Trigger
Select Bit
RW
Set to "012" (TB2 underflow) before
using the U-phase output control circuit RW
TA3TGL
TA3TGH
TA4TGL
TA4TGH
NOTE:
1. Overflow or underflow.
Count Start Flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
TABSR
034016
0016
Bit
Symbol
Bit Name
Function
RW
TA0S
Timer A0 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TA1S
Timer A1 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TA2S
Timer A2 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TA3S
Timer A3 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TA4S
Timer A4 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TB0S
Timer B0 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TB1S
Timer B1 Count
Start Flag
0: Stops counting
1: Starts counting
RW
TB2S
Timer B2 Count
Start Flag
0: Stops counting
1: Starts counting
RW
Figure 15.6 TB2, TRGSR and TABSR Registers
Rev. 1.00 Nov. 01, 2005 Page 163 of 330
REJ09B0271-0100
15. Three-Phase Motor Control Timer Functions
M32C/80 Group
Timer Ai Mode Register (i=1, 2, 4)
b7
b6
b5
b4
b2
b1
b0
Symbol
Address
After Reset
0
1 0 0
1
0
TA1MR, TA2MR, TA4MR
035716, 035816, 035A16
0016
b3
Bit
Symbol
Bit Name
Function
RW
Operating Mode
Select Bit
Set to "102" (one-shot timer
mode) when using the three-phase
motor control timer function
RW
MR0
Reserved Bit
Set to "0"
RW
MR1
External Trigger Select
Bit
Set to "0" when using the three-phase RW
motor control timer function
MR2
Trigger Select Bit
Set to "1" (selected by the TRGSR
register) when using the threephase motor control timer function
MR3
Set to "0" with the three-phase motor control timer function
TMOD0
TMOD1
RW
RW
b7 b6
TCK0
TCK1
RW
0 0: f1
Count Source Select Bit 0 1: f8
1 0: f2n(1)
1 1: fC32
RW
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Timer B2 Mode Register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0
Symbol
Address
After Reset
TB2MR
035D16
00XX 00002
Bit
Symbol
Bit Name
Function
RW
MR1
Set to "002" (timer mode) when using
Operating Mode
RW
the
three-phase motor control timer
Select Bit
function
Disabled when using the three-phase motor control timer function.
When write, set to "0".
When read, its content is indeterminate.
MR2
Set to "0" when using three-phase motor control timer function RW
MR3
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
TMOD0
TMOD1
MR0
RW
b7 b6
TCK0
TCK1
0 0: f1
Count Source Select Bit 0 1: f8
1 0: f2n(1)
1 1: fC32
RW
RW
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 15.7 TA1MR, TA2MR and TA4MR Registers, TB2MR Register
Rev. 1.00 Nov. 01, 2005 Page 164 of 330
REJ09B0271-0100
15. Three-Phase Motor Control Timer Functions
M32C/80 Group
The three-phase motor control timer function is available by setting the INV02 bit in the INVC0 register to
"1". The timer B2 is used for carrier wave control and the timers A1, A2, A4 for three-phase PWM output
__
__
___
(U, U, V, V, W, W) control. An exclusive dead time timer controls dead time. Figure 15.8 shows an
example of the triangular modulation waveform. Figure 15.9 shows an example of the sawtooth modulation waveform.
Triangular waveform as a Carrier Wave
Triangular Wave
Signal Wave
TB2S Bit in the
TABSR Register
Timer B2
Timer A1
Reload Control Signal(1)
Timer A4
Start Trigger Signal(1)
TA4 Register(2)
m
n
p
q
r
TA4-1 Register(2)
m
n
p
q
r
Reload
Register(2)
m
Timer A4
One-Shot Pulse(1)
m
m
n
m
n
n
n
p
p
n
q
q
p
p
q
r
q
Rewrite the IDB0 and IDB1 registers
U-Phase
Output Signal(1)
Transfer the values
to the three-phase
shift register
U-Phase
Output Signal(1)
U-Phase
INV14 = 0
("L" active)
U-Phase
Dead time
INV14 = 1
("H" active)
U-Phase
Dead time
U-Phase
INV00, INV01: Bits in the INVC0 register
INV11, INV14: Bits in the INVC1 register
NOTES:
1. Internal signals. See Figure 15.1.
2. Applies only when the INV11 bit is set to "1" (three-phase mode).
The above applies when INVC0 = 00XX11XX2 and INVC1 = 010XXXX02 (X varies depending on each system.)
Examples of PWM output change are
(b) When INV11=0 (three-phase mode 0)
(a) When INV11=1 (three-phase mode 1)
- INV01=0, ICTB2=116 (The timer B2 interrupt is generated
- INV01=0 and ICTB2=216 (The timer B2 interrupt is
whenever the timer B2 underflows)
generated with every second timer B2 underflow) or
- Default value of the timer: TA4=m
INV01=1, INV00=1and ICTB2=116 (The timer B2 interrupt is
The TA4 register is changed whenever the timer B2
generated on the falling edge of the timer A reload control
interrupt is generated.
signal)
First time: TA4=m. Second time: TA4=n.
- Default value of the timer: TA41=m, TA4=m
Third time: TA4=n. Fourth time: TA=p.
The TA4 and TA41 registers are changed whenever the
Fifth time: TA4=p.
timer B2 interrupt is generated.
- Default value of the IDB0 and IDB1 registers:
First time: TA41=n, TA4:=n.
DU0=1, DUB0=0, DU1=0, DUB1=1
Second time: TA41=p, TA4=p.
They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0 by
- Default value of the IDB0 and IDB1 registers
the sixth timer B2 interrupt.
DU0=1, DUB0=0, DU1=0, DUB1=1
They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0
by the third timer B2 interrupt.
Figure 15.8 Triangular Wave Modulation Operation
Rev. 1.00 Nov. 01, 2005 Page 165 of 330
REJ09B0271-0100
15. Three-Phase Motor Control Timer Functions
M32C/80 Group
Sawtooth Waveform as a Carrier Wave
Sawtooth Wave
Signal Wave
Timer B2
Timer A4 Start
Trigger Signal(1)
Timer A4
One-Shot Pulse(1)
Rewrite the IDB0 and IDB1 registers
Transfer the register values to
the three-phase shift register
U-Phase
(1)
Output Signal
U-Phase
(1)
Output Signal
U-Phase
INV14 = 0
("L" active)
Dead time
U-Phase
U-Phase
INV14 = 1
("H" active)
Dead time
U-Phase
INV14: Bits in the INVC1 register
NOTE:
1. Internal signals. See Figure 15.1.
The above applies when INVC0 = 01XX110X2 and INVC1 = 000XXX002 (X varies depending on each system.)
The examples of PWM output change are
- Default value of the IDB0 and IDB1 registers: DU0=0, DUB0=1, DU1=1, DUB1=1
They are changed to DU0=1, DUB0=0, DU1=1, DUB1=1 by the timer B2 interrupt.
Figure 15.9 Sawtooth Wave Modulation Operation
Rev. 1.00 Nov. 01, 2005 Page 166 of 330
REJ09B0271-0100
M32C/80 Group
16. Serial I/O
16. Serial I/O
Serial I/O consists of five channels (UART0 to UART4).
Each UARTi (i=0 to 4) has an exclusive timer to generate the transfer clock and operates independently.
Figure 16.1 shows a UARTi block diagram.
UARTi supports the following modes :
- Clock synchronous serial I/O mode
- Clock asynchronous serial I/O mode (UART mode)
- Special mode 1 (I2C mode)
- Special mode 2
- Special mode 3 (Clock-divided synchronous function, GCI mode)
- Special mode 4 (Bus conflict detect function, IE mode)
- Special mode 5 (SIM mode)
Figures 16.2 to 16.9 show registers associated with UARTi.
Refer to the tables listing each mode for register and pin settings.
Rev. 1.00 Nov. 01, 2005 Page 167 of 330
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16. Serial I/O
M32C/80 Group
RxD Polarity
Switching Circuit
RxDi
Selecting Clock Source
00
CKDIR
f1
Internal
01
0
f8
10
f2n(2)
CLK1 and 1
CLK0
External
Clock Asynchronous
Receive
SMD2 to SMD0
010, 100, 101, 110
1/16
Receive
001
Control Circuit
Clock Synchronous
UiBRG
Register
Receive
Clock
Clock Asynchronous
Transmit
1 / (m+1)
1/16
Transmit/
Receive
Unit
TxDi
(Note 1)
Transmit
Clock
Transmit
Control Circuit
010, 100, 101, 110
Clock Synchronous
001
Clock Synchronous (when
internal clock is selected)
TxD
Polarity
Switching
Circuit
1/2
0
1
Clock
Synchronous
Clock Synchronous
CKDIR
(when internal clock is selected) (when external clock is
selected)
CKPOL
CLKi
CLK
Polarity
Switching
Circuit
CTS/RTS
selected
1
CTSi / RTSi
CTS/RTS disabled
CRD
RTSi
CRS 0
0
1
CRD CTS/RTS disabled
CTSi
m: setting value of the UiBRG register
VSS
IOPOL
No inverse
0
RxD Data
Inverse Circuit
RxDi
NOTES:
1. P70 and P71 are ports for the N-channel open drain output, but
not for the CMOS output.
2. The CNT3 to CNT0 bits in the TCSPR register select no division
(n=0) or divide-by-2n (n=1 to 15).
1
Inverse
Clock
Synchronous
7-bit Clock
Asynchronous
8-bit Clock
Asynchronous
PRYE
PAR
Clock
disabled Synchronous
0
STPS
1SP
0
SP
SP
7-bit Clock
Asynchronous
UARTi Receive Register
0
0
PAR
Clock
1
Asynchronous
PAR
enabled SMD2 to SMD0
1
2SP
1
9-bit Clock
Asynchronous
Type
Clock 1
Synchronous
8-bit Clock
Asynchronous
9-bit Clock
Asynchronous
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiRB Register
Logic Inverse Circuit + MSB/LSB Conversion Circuit
High-order bits of data bus
Low-order bits of data bus
Logic Inverse Circuit + MSB/LSB Conversion Circuit
D8
STPS
2SP
1
SP
SP
PRYE
SMD2 to SMD0
PAR
enabled
1
Clock
Asynchronous
1
9-bit Clock
Asynchronous
1
D7
D6
D5
D4
D3
D2
D1
D0
UiTB Register
8-bit Clock
Asynchronous
9-bit Clock
Asynchronous
Clock
Synchronous
1
PAR
0
1SP
0
Clock
PAR
Synchronous
disabled
0
0
7-bit Clock
Asynchronous
8-bit Clock
Asynchronous
Clock
Synchronous
0 7-bit Clock
Asynchronous
UARTi Transmit Register
Error Signal Output
disable
0
SP: Stop bit
PAR: Parity bit
i=0 to 4
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in the UiMR register
CLK1 and CLK0, CKPOL, CRD, CRS: Bits in the UiC0 register
UiERE: Bit in the UiC1 register
Figure 16.1 UARTi Block Diagram
Rev. 1.00 Nov. 01, 2005 Page 168 of 330
REJ09B0271-0100
Error Signal
Output Circuit
1
Error Signal Output
enable
UiERE
IOPOL
0
1
Inverse
No inverse
TxD Data
Inverse Circuit
TxDi
16. Serial I/O
M32C/80 Group
UARTi Transmit Buffer Register (i=0 to 4)(1)
b15
b8 b7
b0
Symbol
Address
U0TB to U2TB 036B16-036A16, 02EB16-02EA16, 033B16-033A16
U3TB, U4TB
032B16-032A16, 02FB16-02FA16
Bit
Symbol
After Reset
Indeterminate
Indeterminate
RW
Function
(b7 - b0) Transmit data (D7 to D0)
(b8)
WO
Transmit data (D8)
WO
Nothing is assigned.
When write, set to "0".
(b15 - b9) When read, its content is indeterminate.
NOTE:
1. Use the MOV instruction to set the UiTB register.
UARTi Receive Buffer Register (i=0 to 4)
b15
b8 b7
b0
Symbol
Address
U0RB to U2RB 036F16 - 036E16, 02EF16 - 02EE16, 033F16 - 033E16
U3RB, U4RB
032F16 - 032E16, 02FF16 - 02FE16
Bit
Symbol
Bit Name
Function
Indeterminate
Indeterminate
RW
Received data (D7 to D0)
RO
Received data (D8)
RO
(b7 - b0)
(b8)
After Reset
Nothing is assigned. When write, set to "0".
(b10 - b9) When read, its content is indeterminate.
ABT
Arbitration Lost
Detect Flag(1)
OER
0: No overrun error occurs
Overrun Error Flag(2) 1: Overrun error occurs
RO
FER
Framing Error
Flag(2, 3)
0: No framing error occurs
1: Framing error occurs
RO
PER
Parity Error Flag(2, 3)
0: No parity error occurs
1: Parity error occurs
RO
SUM
Error Sum Flag(2, 3)
0: No error occurs
1: Error occurs
RO
0: Not detected (win)
1: Detected (lose)
RW
NOTES:
1. The ABT bit can be set to "0" only.
2. When the SMD2 to SMD0 bits in the UiMR register are set to "0002" (serial I/O disable) or the RE bit in
the UiC1 register is set to "0" (receive disable), the OER, FER, PER and SUM bits are set to "0".
When all OER, FER and PER bits are set to "0", the SUM bit is set to "0".
Also, the FER and PER bits are set to "0" by reading low-order bits in the UiRB register.
3. These error flags are disabled when the SMD2 to SMD0 bits are set to "0012" (clock synchronous serial
I/O mode) or to "0102" (I2C mode). When read, the contents are indeterminate.
Figure 16.2 U0TB to U4TB Registers and U0RB to U4RB Registers
Rev. 1.00 Nov. 01, 2005 Page 169 of 330
REJ09B0271-0100
16. Serial I/O
M32C/80 Group
UARTi Bit Rate Register (i=0 to 4)(1, 2, 3)
b7
b0
Symbol
Address
U0BRG to U4BRG 036916, 02E916, 033916, 032916, 02F916
Function
After Reset
Indeterminate
Setting Range
If the setting value is m, the UiBRG register
divides a count source by m+1
0016 to FF16
RW
WO
NOTES:
1. Use the MOV instruction to set the UiBRG register.
2. Set the UiBRG register while no data transfer occurs.
3. Set the CLK1 and CLK0 bits in the UiC0 register, and then the UiBRG register.
UARTi Transmit/Receive Mode Register (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0MR to U4MR
Bit
Symbol
Address
036816, 02E816, 033816, 032816, 02F816
Bit Name
Function
After Reset
0016
RW
b2 b1 b0
SMD0
SMD1
SMD2
0 0 0: Serial I/O disabled
RW
0 0 1: Clock synchronous serial I/O mode
2
Serial I/O Mode Select 0 1 0: I C mode
1
0
0:
UART
mode, 7-bit transfer data RW
Bit
1 0 1: UART mode, 8-bit transfer data
1 1 0: UART mode, 9-bit transfer data
RW
Do not set value other than the above
CKDIR
Internal/External Clock 0: Internal clock
Select Bit
1: External clock
RW
STPS
Stop Bit Length Select 0: 1 stop bit
Bit
1: 2 stop bits
RW
PRY
Odd/Even Parity Select Enables when PRYE = 1
0: Odd parity
Bit
1: Even parity
RW
0: Disables a parity
1: Enables a parity
PRYE
Parity Enable Bit
IOPOL
TxD,RxD Input/Output 0: Not inversed
Polarity Switch Bit
1: Inverse
Figure 16.3 U0BRG to U4BRG Registers and U0MR to U4MR Registers
Rev. 1.00 Nov. 01, 2005 Page 170 of 330
REJ09B0271-0100
RW
RW
16. Serial I/O
M32C/80 Group
UARTi Transmit/Receive Control Register 0 (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0C0 to U4C0
Bit
Symbol
Address
036C16, 02EC16, 033C16, 032C16, 02FC16
Bit Name
After Reset
0000 10002
Function
RW
b1 b0
CLK0
CLK1
CRS
0 0: Selects f1
UiBRG Count
0 1: Selects f8
Source Select Bit(4)
1 0: Selects f2n(2)
1 1: Do not set to this value
CST/RTS Function Enabled when CRD=0
0: Selects CTS function
Select Bit
1: Selects RTS function
RW
RW
RW
TXEPT
Transmit Register
Empty Flag
0: Data in the transmit register
(during transmission)
1: No data in the transmit register
(transmission is completed)
RO
CRD
CTS/RTS Disable
Bit
0: Enables CTS/RTS function
1: Disables CTS/RTS function
RW
0: TxDi/SDAi and SCLi are ports for the
Data Output Select
CMOS output
RW
Bit(1)
1: TxDi/SDAi and SCLi are ports for the
N-channel open drain output
0: Data is transmitted on the falling edge of
the transfer clock and data is received
on the rising edge
CLK Polarity
CKPOL
RW
1: Data is transmitted on the rising edge of
Select Bit
the transfer clock and data is received
on the falling edge
NCH
UFORM
Transfer Format
Select Bit(3)
0: LSB first
1: MSB first
RW
NOTES:
1. P70/TxD2 and P71/SCL2 are ports for the N-channel open drain output, but not for the CMOS output.
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
3. The UFORM bit setting is enabled when the SMD2 to SMD0 bits in the UiMR register are set to
"0012" (clock syncronous serial I/O mode) or "1012" (UART mode, 8-bit transfer data).
Set the UFORM bit to "1" when setting the SMD2 to SMD0 bits to"0102" (I2C mode), or to "0" when
setting them to "1002" (UART mode, 7-bit transfer data) or "1102" (UART mode, 9-bit transfer data).
4. Set the UiBRG register after the CLK1 and CLK0 bit settings are changed.
Figure 16.4 U0C0 to U4C0 Registers
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16. Serial I/O
M32C/80 Group
UARTi Transmit/Receive Control Register 1 (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0C1 to U4C1
Bit
Symbol
Address
036D16, 02ED16, 033D16, 032D16, 02FD16
After Reset
0000 00102
Function
Bit Name
RW
0: Transmit disabled
1: Transmit enabled
TE
Transmit
Enable Bit
TI
Transmit Buffer 0: Data in the UiTB register
1: No data in the UiTB register
Empty Flag
RE
Receive
Enable Bit
0: Receive disabled
1: Receive enabled
RW
RI
Receive
Complete Flag
0: No data in the UiRB register
1: Data in the UiRB register
RO
UiIRS
RW
RO
UARTi Transmit 0: No data in the UiTB register (TI = 1)
Interrupt Cause
1: Transmission is completed (TXEPT = 1)
Select Bit
RW
UiRRM
UARTi
Continuous
Receive Mode
Enable Bit
0: Disables continuous receive mode to be entered
RW
1: Enables continuous receive mode to be entered
UiLCH
Data Logic
Select Bit(2)
0: Not inversed
1: Inverse
Clock-Divided
Synchronous Stop
SCLKSTPB Bit /
/UiERE
Error Signal
Output Enable
Bit(1)
RW
Clock-divided synchronous stop bit (special mode 3)
0: Stops synchronizing
1: Starts synchronizing
RW
Error signal output enable bit (special mode 5)
0: Not output
1: Output
NOTES:
1. Set the SCLKSTPB/UiERE bit after setting the SMD2 to SMD0 bits in the UiMR register.
2. The UiLCH bit setting is enabled when setting the SMD2 to SMD0 bits to "0012" (clock syncronous
serial I/O mode), "1002" (UART mode, 7-bit transfer data) or "1012" (UART mode, 8-bit transfer data).
Set the UiLCH bit to "0" when setting the SMD2 to SMD0 bits to"0102" (I2C mode) or "1102" (UART
mode, 9-bit transfer data).
UARTi Special Mode Register (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0SMR to U4SMR
Bit
Symbol
Address
036716, 02E716, 033716, 032716, 02F716
After Reset
0016
Function
Bit Name
0: Except I2C mode
1: I2C mode
IICM
I2C Mode Select Bit
ABC
Arbitration Lost Detect 0: Update per bit
Flag Control Bit
1: Update per byte
BBS
Bus Busy Flag
0: Stop condition detected
1: Start condition detected (Busy)
SCLL Sync Output
Enable Bit
0: Disabled
1: Enabled
LSYN
Bus Conflict Detect
0: Rising edge of transfer clock
ABSCS Sampling Clock Select Bit
1: Timer Aj underflow(j=0 to 4)(2)
ACSE
SSS
SCLKDIV
RW
RW
RW(1)
RW
RW
Auto Clear Function Select 0: No auto clear function
Bit for Transmit Enable Bit 1: Auto clear at bus conflict
RW
Transmit Start
Condition Select Bit
0: Not related to RxDi
1: Synchronized with RxDi
RW
Clock Divide
Synchronous Bit
(Note 3)
RW
NOTES:
1. The BBS bit is set to "0" by program. It is unchanged if set to "1".
2. UART0: timer A3 underflow signal, UART1: timer A4 underflow signal,
UART2: timer A0 underflow signal, UART3: timer A3 underflow signal,
UART4: timer A4 underflow signal.
3. Refer to notes for the SU1HIM bit in the UiSMR2 register.
Figure 16.5 U0C1 to U4C1 Registers and U0SMR to U4SMR Registers
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RW
16. Serial I/O
M32C/80 Group
UARTi Special Mode Register 2 (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0SMR2 to U4SMR2
Address
036616, 02E616, 033616, 032616, 02F616
After Reset
0016
Bit
Symbol
Bit Name
IICM2
I2C Mode Select Bit 2
(Note 1)
RW
CSC
Clock Synchronous Bit
0: Disabled
1: Enabled
RW
SWC
SCL Wait Output Bit
0: Disabled
1: Enabled
RW
ALS
SDA Output Stop Bit
0: Output
1: No output
RW
STC
UARTi Initialize Bit
0: Disabled
1: Enabled
RW
SWC2
SCL Wait Output Bit 2
0: Transfer clock
1: "L" output
RW
SDHI
SDA Output Inhibit Bit
0: Output
1: No output (high-impedance)
RW
External Clock
Synchronous Enable Bit
(Note 2)
RW
SU1HIM
Function
NOTES:
1. Refer to Table 16.14.
2. The external clock synchronous function can be selected by combining the SU1HIM bit and the
SCLKDIV bit in the UiSMR register.
SCLKDIV bit in the
UiSMR Register
SU1HIM bit in the
UiSMR2 Register
0
0
0
1
1
0 or 1
Figure 16.6 U0SMR2 to U4SMR2 Registers
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External Clock Synchronous Function
Selection
No synchronization
Same division as the external clock
External clock divided by 2
RW
16. Serial I/O
M32C/80 Group
UARTi Special Mode Register 3 (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0SMR3 to U4SMR3
Bit
Symbol
Address
036516, 02E516, 033516, 032516, 02F516
0016
Function
RW
SS Pin Function
Enable Bit(1)
0: Disables SS pin function
1: Enables SS pin function
RW
CKPH
Clock Phase
Set Bit
0: No clock delay
1: Clock delay
RW
DINC
Serial Input Port
Set Bit
0: Selects the TxDi and RxDi pins
(master mode)
1: Selects the STxDi and SRxDi pins
(slave mode)
RW
NODC
Clock Output
Select Bit
0: CMOS output
1: N-channel open drain output
RW
Fault Error Flag(2)
0: No error
1: Error
RW
SSE
ERR
Bit Name
After Reset
b7 b6 b5
DL0
DL1
DL2
0 0 0: No delay
0 0 1: 1-to-2 cycles of BRG count source
0 1 0: 2-to-3 cycles of BRG count source
SDAi Digital Delay 0 1 1: 3-to-4 cycles of BRG count source
(3,
4)
Time Set Bit
1 0 0: 4-to-5 cycles of BRG count source
1 0 1: 5-to-6 cycles of BRG count source
1 1 0: 6-to-7 cycles of BRG count source
1 1 1: 7-to-8 cycles of BRG count source
NOTES:
1. Set the SS pin after the CRD bit in the UiC0 register is set to "1" (CTS/RTS function disabled).
2. The ERR bit is set to "0" by program. It is unchanged if set to "1".
3. Digital delay is generated from a SDAi output by the DL2 to DL0 bits in I2C mode. Set these bits to
"0002" (no delay) except in the I2C mode.
4. When the external clock is selected, approximately 100ns delay is added.
Figure 16.7 U0SMR3 to U4SMR3 Registers
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RW
RW
RW
16. Serial I/O
M32C/80 Group
UARTi Special Mode Register 4 (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0SMR4 to U4SMR4
Bit
Symbol
Address
036416, 02E416, 033416, 032416, 02F416
Bit Name
After Reset
0016
Function
RW
STAREQ
Start Condition
Generate Bit(1)
0: Clear
1: Start
RW
RSTAREQ
Restart Condition
Generate Bit(1)
0: Clear
1: Start
RW
STPREQ
Stop Condition
Generate Bit(1)
0: Clear
1: Start
RW
STSPSEL
SCL, SDA Output
Select Bit
0: Selects the serial I/O circuit
1: Selects the start/stop condition
generation circuit
RW
ACKD
ACK Data Bit
0: ACK
1: NACK
RW
ACKC
ACK Data Output
Enable Bit
0: Serial I/O data output
1: ACK data output
RW
SCLHI
SCL Output Stop
Enable Bit
0: Disabled
1: Enabled
RW
SWC9
SCL Wait Output Bit 3
0: SCL "L" hold disabled
1: SCL "L" hold enabled
RW
NOTE:
1. When each condition is generated, the STAREQ, RSTAREQ or STPREQ bit is set to "0".
When a condition generation is incomplete, the bit remains unchanged as "1".
Figure 16.8 U0SMR4 to U4SMR4 Registers
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16. Serial I/O
M32C/80 Group
External Interrupt Request Source Select Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IFSR
Bit
Symbol
Address
031F16
Bit Name
After Reset
0016
Function
RW
IFSR0
INT0 Interrupt Polarity
Select Bit(1)
0: One edge
1 : Both edges
RW
IFSR1
INT1 Interrupt Polarity
Select Bit(1)
0: One edge
1: Both edges
RW
IFSR2
INT2 Interrupt Polarity
Select Bit(1)
0: One edge
1: Both edges
RW
IFSR3
INT3 Interrupt Polarity
Select Bit(1)
0: One edge
1: Both edges
RW
IFSR4
INT4 Interrupt Polarity
select bit(1)
0: One edge
1: Both edges
RW
IFSR5
INT5 Interrupt Polarity
Select Bit(1)
0: One edge
1: Both edges
RW
IFSR6
UART0, UART3
Interrupt Source
Select Bit
0: UART3 bus conflict, start condition
detect, stop condition detect
RW
1: UART0 bus conflict, start condition
detect, stop condition detect
IFSR7
UART1, UART4
Interrupt Source
Select Bit
0: UART4 bus conflict, start condition
detect, stop condition detect
RW
1: UART1 bus conflict, start condition
detect, stop condition detect
NOTE:
1. Set this bit to "0" to select a level-sensitive triggering.
When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge).
Figure 16.9 IFSR Register
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16. Serial I/O (Clock Synchronous Serial I/O)
M32C/80 Group
16.1 Clock Synchronous Serial I/O Mode
In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. Table 16.1
lists specifications of clock synchronous serial I/O mode. Table 16.2 lists register settings. Tables 16.3 to
16.5 list pin settings. When UARTi (i=0 to 4) operating mode is selected, the TxDi pin outputs a high-level
("H") signal before transfer starts (the TxDi pin is in a high-impedance state when the N-channel open drain
output is selected). Figure 16.10 shows transmit and receive timings in clock synchronous serial I/O mode.
Table 16.1 Clock Synchronous Serial I/O Mode Specifications
Item
Transfer Data Format
Transfer Clock
Specification
Transfer data : 8 bits long
• The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected):
fj
fj=f1, f8, f2n(1) m :setting value of the UiBRG register, 0016 to FF16
2(m+1)
Transmit/Receive Control
Transmit Start Condition
• The CKDIR bit is set to "1" (external clock selected) : an input from the CLKi pin
_______
_______
_______ _______
Selected from the CTS function, RTS function or CTS/RTS function disabled
To start transmitting, the following requirements must be met(2):
- Set the TE bit in the UiC1 register to "1" (transmit enabled)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
________
_______
- Apply a low-level ("L") signal to the CTSi pin when the CTS function is selected
Receive Start Condition
To start receiving, the following requirements must be met(2):
- Set the RE bit in the UiC1 register to "1" (receive enabled)
- Set the TE bit to "1" (transmit enabled)
- Set the TI bit to "0" (data in the UiTB register)
Interrupt Request Generation Timing • While transmitting, the following conditions can be selected:
- The UiIRS bit in the UiC1 register is set to "0" (no data in the transmit buffer):
when data is transferred from the UiTB register to the UARTi transmit register (transfer started)
- The UiIRS bit is set to "1" (transmission completed):
when a data transfer from the UARTi transmit register is completed
• While receiving
Error Detect
When data is transferred from the UARTi receive register to the UiRB register (reception completed)
Overrun error(3)
This error occurs when the seventh bit of the next received data is read before reading
the UiRB register
Selectable Function
• CLK polarity
Selectable from the rising edge or falling edge of the transfer clock at transferred data
output or input timing
• LSB first or MSB first
Selectable from data transmission or reception in either bit 0 or in bit 7
• Continuous receive mode
Data can be received simultaneously by reading the UiRB register
• Serial data logic inverse
This function inverses transmitted/received data logically
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL
bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received
on the rising edge) and the CLKi pin is held "H", or when the CKPOL bit is set to "1" (data is transmitted on the rising
edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held "L".
3. If an overrun error occurs, the UiRB register is indeterminate. The IR bit setting in the SiRIC register does not
change to "1" (interrupt requested).
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16. Serial I/O (Clock Synchronous Serial I/O)
M32C/80 Group
Table 16.2 Register Settings in Clock Synchronous Serial I/O Mode
Register
UiTB
UiRB
Bit
Function
7 to 0
Set transmit data
7 to 0
Received data can be read
OER
Overrun error flag
UiBRG
7 to 0
Set bit rate
UiMR
SMD2 to SMD0
Set to "0012"
CKDIR
Select the internal clock or external clock
UiC0
IOPOL
Set to "0"
CLK1, CLK0
Select count source for the UiBRG register
CRS
Select CTS or RTS when using either
TXEPT
Transmit register empty flag
CRD
Enables or disables the CTS or RTS function
NCH
Select output format of the TxDi pin
_______
_______
_______
UiC1
_______
CKPOL
Select transmit clock polarity
UFORM
Select either LSB first or MSB first
TE
Set to "1" to enable data transmission and reception
TI
Transmit buffer empty flag
RE
Set to "1" to enable data reception
RI
Reception complete flag
UiIRS
Select what causes the UARTi transmit interrupt to be generated
UiRRM
Set to "1" when using continuous receive mode
UiLCH
Set to "1" when using data logic inverse
SCLKSTPB
Set to "0"
UiSMR
UiSMR2
7 to 0
7 to 0
Set to "0016"
Set to "0016"
UiSMR3
2 to 0
Set to "0002"
UiSMR4
NODC
Select clock output format
7 to 4
Set to "00002"
7 to 0
Set to "0016"
i=0 to 4
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16. Serial I/O (Clock Synchronous Serial I/O)
M32C/80 Group
Table 16.3 Pin Settings in Clock Synchronous Serial I/O Mode (1)
Port
Function
Setting
PS0 Register
PSL0 Register
PD6 Register
PS0_0=0
-
PD6_0=0
__________
P60
CTS0 input
__________
P61
P62
P63
RTS0 output
PS0_0=1
-
-
CLK0 input
PS0_1=0
-
PD6_1=0
CLK0 output
PS0_1=1
-
-
RxD0 input
PS0_2=0
-
PD6_2=0
TxD0 output
PS0_3=1
-
-
PS0_4=0
-
PD6_4=0
__________
P64
CTS1 input
_________
P65
RTS1 output
PS0_4=1
PSL0_4=0
-
CLK1 input
PS0_5=0
-
PD6_5=0
CLK1 output
PS0_5=1
-
-
P66
RxD1 input
PS0_6=0
-
PD6_6=0
P67
TxD1 output
PS0_7=1
-
-
Table 16.4 Pin Settings (2)
Port
Function
P70(1)
TxD2 output
P71(1)
P72
Setting
PS1 Register
PSL1 Register
PSC Register
PD7 Register
PS1_0=1
PSL1_0=0
PSC_0=0
-
RxD2 input
PS1_1=0
-
-
PD7_1=0
CLK2 input
PS1_2=0
-
-
PD7_2=0
CLK2 output
PS1_2=1
PSL1_2=0
PSC_2=0
-
PS1_3=0
-
-
PD7_3=0
PS1_3=1
PSL1_3=0
PSC_3=0
-
__________
P73
CTS2 input
__________
RTS2 output
NOTE:
1. P70 and P71 are ports for the N-channel open drain output.
Table 16.5 Pin Settings (3)
Port
Function
Setting
PS3 Register(1)
PSL3 Register
PSC3 Register
PD9 Register(1)
CLK3 input
PS3_0=0
-
-
PD9_0=0
CLK3 output
PS3_0=1
-
-
-
P91
RxD3 input
PS3_1=0
-
-
PD9_1=0
P92
TxD3 output
PS3_2=1
PSL3_2=0
-
-
PS3_3=0
PSL3_3=0
-
PD9_3=0
PS3_3=1
-
-
-
P90
__________
P93
CTS3 input
__________
RTS3 output
__________
P94
CTS4 input
PS3_4=0
PSL3_4=0
-
PD9_4=0
RTS4 output
PS3_4=1
-
-
-
CLK4 input
PS3_5=0
PSL3_5=0
-
PD9_5=0
CLK4 output
PS3_5=1
-
-
-
__________
P95
P96
TxD4 output
PS3_6=1
-
PSC3_6=0
-
P97
RxD4 input
PS3_7=0
-
-
PD9_7=0
NOTE:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enabled). Do
not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the instruction to
set the PD9 and PS3 registers.
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16. Serial I/O (Clock Synchronous Serial I/O)
M32C/80 Group
(1) Transmit Timing (Internal clock selected)
Tc
Transfer Clock
"1"
TE bit in the UiC1
"0"
register
TI bit in the UiC1
register
Data is set in the UiTB register
"1"
"0"
Data is transferred from the UiTB register to the UARTi transmit register
"H"
CTSi
TCLK
"L"
Pulse stops because an "H"
signal is applied to CTSi
Pulse stops because the TE bit is set to "0"
CLKi
TxDi
TXEPT bit in
the UiC0 register
D0 D 1 D2 D3 D4 D5 D6 D7
D0 D 1 D2 D3 D4 D5 D 6 D7
D 0 D1 D2 D 3 D 4 D 5 D6 D7
"1"
"0"
IR bit in the SiTIC "1"
register
"0"
Set to "0" by an interrupt request acknowledgement or by program
The above applies under the following conditions:
TC=TCLK=2(m+1)/fj
• The CKDIR bit in the UiMR register is set to "0" (internal clock selected)
fj: Count source frequency set in the UiBRG register (f1, f8, f2n(1))
• The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled)
m: Setting value of the UiBRG register
The CRS bit is set to "0" (CTS function selected)
i = 0 to 4
• The CKPOL bit the in UiC0 register is set to "0" (data transmitted on the
NOTE:
falling edge of the transfer clock)
1. The CNT3 to CNT0 bits in the TCSPR register select no division (
• The UiIRS bit in the UiC1 register is set to "0" (no data in the UiTB register)
n=0) or divide-by-2n (n=1 to 15).
(2) Receive Timing (External clock selected)
RE bit in the UiC1
register
"1"
TE bit in the UiC1
register
"1"
TI bit in the UiC1
register
"1"
"0"
Dummy data is set in the UiTB register
"0"
"0"
Data is transferred from the UiTB register to the UARTi transmit register
RTSi
"H"
An "L" signal is applied when
the UiRB register is read
"L"
1 / fEXT
CLKi
Received data is taken in
RxDi
D0 D 1 D2 D3 D4 D 5 D6 D7
RI bit in the UiC1
register
"1"
IR bit in the SiRIC
register
"1"
OER bit in the
UiRB register
"1"
D 0 D1 D2 D3 D 4 D 5
D6
D7
D0 D1 D2 D 3 D4 D 5 D6
Read by the UiRB register
Date is transferred from the UARTi
receive register to the UiRB register
"0"
"0"
Set to "0" by an interrupt request acknowledgement or by program
"0"
The above applies under the following conditions:
• The CKDIR bit in the UiMR register is set to "1" (external clock selected)
• The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled)
The CRS bit is set to "1" (RTS function selected)
• The CKPOL bit in the UiC0 register is set to "0"
(Data is received on the rising edge of the transfer clock)
fEXT: External clock frequency
i=0 to 4
Figure 16.10 Transmit and Receive Operation
Rev. 1.00 Nov. 01, 2005 Page 180 of 330
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Meet the following conditions while an "H" signal is applied to
the CLKi pin before receiving data:
• Set the TE bit in the UiC1 register to "1" (transmit enable)
• Set the RE bit in the UiC1 register to "1" (receive enable)
• Write dummy data to the UiTB register
16. Serial I/O (Clock Synchronous Serial I/O)
M32C/80 Group
16.1.1 Selecting CLK Polarity Selecting
As shown in Figure 16.11, the CKPOL bit in the UiC0 register (i=0 to 4) determines the polarity of the
transfer clock.
(1) When the CKPOL bit in the UiC0 register (i=0 to 4) is set to "0"
(Data is transmitted on the falling edge of the transfer clock and data is received on the rising edge)
"H"
CLKi "L"
"H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
"H"
RXDi "L"
D0
D1
D2
D3
D4
D5
D6
D7
TXDi
NOTES:
1. The CLKi pin is held high ("H") when no data is transferred.
2. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first)
and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
(2) When the CKPOL bit in the UiC0 register is set to "1"
(Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge)
CLKi
"H"
"L"
TXDi "H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
RXDi "H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
NOTES:
3. The CLKi pin is held low ("L") when no data is transferred.
4. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first)
and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
Figure 16.11 Transfer Clock Polarity
16.1.2 Selecting LSB First or MSB First
As shown in Figure 16.12, the UFORM bit in the UiC0 register (i=0 to 4) determines a data transfer format.
(1) When the UFORM bit in the UiC0 register (i=0 to 4) is set to "0"
(LSB first)
"H"
CLKi "L"
"H"
TXDi "L"
D0
D1
D2
D3
D4
D5
D6
D7
"H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
NOTE:
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
transmitted on the falling edge of the transfer clock and received on the rising
edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
(2) When the UFORM bit in the UiC0 register is set to "1" (MSB first)
"H"
CLKi "L"
"H"
"L"
D7
D6
D5
D4
D3
D2
D1
D0
"H"
RXDi "L"
D7
D6
D5
D4
D3
D2
D1
D0
TXDi
NOTE:
2. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
transmitted on the falling edge of the transfer clock and received on the rising
edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
Figure 16.12 Transfer Format
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16. Serial I/O (Clock Synchronous Serial I/O)
M32C/80 Group
16.1.3 Continuous Receive Mode
When the UiRRM bit in the UiC1 register (i=0 to 4) is set to "1" (continuous receive mode), the TI bit is set
to "0" (data in the UiTB register) by reading the UiRB register. When the UiRRM bit is set to "1", do not set
dummy data in the UiTB register by program.
16.1.4 Serial Data Logic Inverse
When the UiLCH bit (i=0 to 4) in the UiC1 register is set to "1" (inverse), data logic written in the UiTB
register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB
register. Figure 16.13 shows a switching example of the serial data logic.
(1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (not inversed)
Transfer clock
"H"
"L"
TxDi
"H"
(no inverse) "L"
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UiLCH bit in the UiC1 register is set to "1" (inverse)
Transfer clock
"H"
"L"
TxDi
"H"
(inverse) "L"
D0
D1
D2
D3
D4
D5
D6
D7
NOTE:
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on
the falling edge) and the UFORM bit in the UiC0 register is set to "0" (LSB first).
Figure 16.13 Serial Data Logic Inverse
Rev. 1.00 Nov. 01, 2005 Page 182 of 330
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16. Serial I/O (UART)
M32C/80 Group
16.2 Clock Asynchronous Serial I/O (UART) Mode
In UART mode, data is transmitted and received after setting a desired bit rate and data transfer format.
Table 16.6 lists specifications of UART mode.
Table 16.6 UART Mode Specifications
Item
Transfer Data Format
Specification
• Character bit (transfer data) : selected from 7 bits, 8 bits, or 9 bits long
• Start bit: 1 bit long
• Parity bit: selected from odd, even, or none
Transfer Clock
• Stop bit: selected from 1 bit or 2 bits long
• The CKDIR bit in the UiMR register is set to "0" (internal clock selected):
fj/16(m+1) fj = f1, f8, f2n(1) m: setting value of the UiBRG register , 0016 to FF16
• The CKDIR bit is set to "1" (external clock selected):
Transmit/Receive Control
Transmit Start Condition
fEXT/16(m+1)
fEXT: clock applied to the CLKi pin
_______
_______
_______ _______
Select from CTS function, RTS function or CTS/RTS function disabled
To start transmitting, the following requirements must be met:
- Set the TE bit in the UiC1 register to "1" (transmit enabled)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
_______
_______
- Apply a low-velel ("L") signal to the CTSi pin when the CTS function is selected
Receive Start Condition
Interrupt Request
Generation Timing
To start receiving, the following requirements must be met:
- Set the RE bit in the UiC1 register to "1" (receive enabled)
- The start bit is detected
While transmitting, the following condition can be selected:
- The UiIRS bit in the UiC1 register is set to "0" (no data in the UiTB register):
when data is transferred from the UiTB register to the UARTi transmit register (transfer started)
- The UiIRS bit is set to "1" (transmission completed):
when data transmission from the UARTi transfer register is completed
While receiving
Error Detect
when data is transferred from the UARTi receive register to the UiRB register (reception completed)
• Overrun error(2)
This error occurs when the bit before the last stop bit of the next received data is read
prior to reading the UiRB register (the first stop bit when selecting 2 stop bits)
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
When parity is enabled, this error occurs when the number of "1" in parity and character bits does not match the number of "1" set
• Error sum flag
Selectable Function
This flag is set to "1" when any of an overrun, framing or parity errors occur
• LSB first or MSB first
Selectable from data transmission or reception in either bit 0 or in bit 7
•Serial data logic inverse
Logic values of data to be transmitted and received data are inversed. The start bit
and stop bit are not inversed
•TxD and RxD I/O polarity Inverse
TxD pin output and RxD pin input are inversed. All I/O data levels are also inversed
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. If an overrun error occurs, the UiRB register is indeterminate. The IR bit setting in the SiRIC register does not
change to "1" (interrupt requested).
Rev. 1.00 Nov. 01, 2005 Page 183 of 330
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16. Serial I/O (UART)
M32C/80 Group
Table 16.7 lists register settings. Tables 16.8 to 16.10 list pin settings. When UARTi (i=0 to 4) operating
mode is selected, the TxDi pin outputs a high-level ("H") signal before transfer is started (the TxDi pin is in
a high-impedance state when the N-channel open drain output is selected). Figure 16.14 shows an example of a transmit operation in UART mode. Figure 16.15 shows an example of a receive operation in
UART mode.
Table 16.7 Register Settings in UART Mode
Register
Bit
Function
UiTB
8 to 0
Set transmit data(1)
UiRB
8 to 0
Received data can be read(1)
OER, FER,
Error flags
PER, SUM
UiBRG
7 to 0
UiMR
SMD2 to SMD0
Set bit rate
Set to "1002" when transfer data is 7 bits long
Set to "1012" when transfer data is 8 bits long
Set to "1102" when transfer data is 9 bits long
CKDIR
UiC0
Select the internal clock or external clock
STPS
Select stop bit length
PRY, PRYE
Select parity enabled or disabled, odd or even
IOPOL
Select TxD and RxD I/O polarity
CLK1, CLK0
Select count source for the UiBRG register
CRS
Select either CTS or RTS when using either
TXEPT
Transfer register empty flag
CRD
Select the CTS or RTS function enabled or disabled
NCH
Select output format of the TxDi pin
_______
________
_______
_______
CKPOL
Set to "0"
UFORM
Select the LSB first or MSB first when a transfer data is 8 bits long
Set to "0" when transfer data is 7 bits or 9 bits long
UiC1
TE
Set to "1" to enable data transmission
TI
Transfer buffer empty flag
RE
Set to "1" to enable data reception
RI
Reception complete flag
UiIRS
Select what causes the UARTi transmit interrupt to be generated
UiRRM
Set to "0"
UiLCH
Select whether data logic is inversed or not inversed when a transfer data is
UiERE
Set to either "0" or "1"
UiSMR
7 to 0
Set to "0016"
UiSMR2
7 to 0
Set to "0016"
UiSMR3
7 to 0
Set to "0016"
UiSMR4
7 to 0
Set to "0016"
7 bits or 8 bits long. Set to "0" when transfer data is 9 bits long
NOTE:
1. Use bits 0 to 6 when transfer data is 7 bits long, bits 0 to 7 when 8 bits long, bits 0 to 8 when 9 bits long.
Rev. 1.00 Nov. 01, 2005 Page 184 of 330
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16. Serial I/O (UART)
M32C/80 Group
Table 16.8 Pin Settings in UART Mode (1)
Port
Function
Setting
PS0 Register
PSL0 Register
PD6 Register
PS0_0=0
–
PD6_0=0
__________
P60
CTS0 input
__________
RTS0 output
PS0_0=1
–
–
P61
CLK0 input
PS0_1=0
–
PD6_1=0
P62
RxD0 input
PS0_2=0
–
PD6_2=0
P63
TxD0 output
PS0_3=1
–
–
__________
P64
CTS1 input
PS0_4=0
–
PD6_4=0
RTS1 output
PS0_4=1
PSL0_4=0
–
P65
CLK1 input
PS0_5=0
–
PD6_5=0
P66
RxD1 input
PS0_6=0
–
PD6_6=0
P67
TxD1 output
PS0_7=1
–
–
__________
Table 16.9 Pin Settings (2)
Port
Function
Setting
PS1 Register
PSL1 Register
PSC Register
PD7 Register
PS1_0=1
PSL1_0=0
PSC_0=0
–
RxD2 input
PS1_1=0
–
–
PD7_1=0
CLK2 input
PS1_2=0
–
–
PD7_2=0
PS1_3=0
–
–
PD7_3=0
PS1_3=1
PSL1_3=0
PSC_3=0
–
PSL3 Register
PSC3 Register
PD9 Register(1)
PD9_0=0
P70(1)
TxD2 output
P71(1)
P72
__________
P73
CTS2 input
__________
RTS2 output
NOTE:
1. P70 and P71 are ports for the N-channel open drain output.
Table 16.10 Pin Settings (3)
Port
Function
Setting
PS3
Register(1)
P90
CLK3 input
PS3_0=0
–
–
P91
RxD3 input
PS3_1=0
–
–
PD9_1=0
P92
TxD3 output
PS3_2=1
PSL3_2=0
–
–
PS3_3=0
PSL3_3=0
–
PD9_3=0
PS3_3=1
–
–
–
PS3_4=0
PSL3_4=0
–
PD9_4=0
PS3_4=1
–
–
–
__________
P93
CTS3 input
__________
RTS3 output
__________
P94
CTS4 input
__________
RTS4 output
P95
CLK4 input
PS3_5=0
PSL3_5=0
–
PD9_5=0
P96
TxD4 output
PS3_6=1
–
PSC3_6=0
–
P97
RxD4 input
PS3_7=0
–
–
PD9_7=0
NOTE:
1. Set the PD9 and PS3 registers set immediately after the PRC2 bit in the PRCR register is set to "1" (write enabled).
Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the
instruction to set the PD9 and PS3 registers.
Rev. 1.00 Nov. 01, 2005 Page 185 of 330
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16. Serial I/O (UART)
M32C/80 Group
(1) 8-bit Data Transmit Timing (with a parity and 1 stop bit)
Tc
The transfer clock stops momentarily, because an "H" signal is applied to the CTS pin,
when the stop bit state is verified.
The transfer clock resumes running as soon as an "L" signal is applied to the CTS pin
Transfer Clock
TE bit in UiC1
register
"1"
TI bit in UiC1
register
"1"
"0"
Data is set in the UiTB register
"0"
Data is transferred from the UiTB register to the UARTi transmit register
"H"
CTSi
"L"
Parity
bit
Start
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
TxDi
P
Stop
bit
Pulse stops because the TE bit is set to "0"
ST D0 D1 D2 D3 D4 D5 D6 D7
SP
P
ST D0 D1
SP
TXEPT bit in UiC0 "1"
register
"0"
IR bit in SiTIC
register
"1"
"0"
Set to "0" by an interrupt request acknowledgement or by program
i=0 to 4
The above timing applies under the following conditions:
• The PRYE bit in the UiMR register is set to "1" (parity enabled)
• The STPS bit in the UiMR register is set to "0" (1 stop bit)
• The CRD bit in the UiC0 register is set to "0" and the CRS bit is set
to "0" (CTS function selected)
• The UilRS bit in the UiC1 register is set to "1"
(transmission completed)
Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT
fj: count source frequency set in the UiBRG register (f1, f8, f2n(1))
fEXT: count source frequency set in the UiBRG register (external
clock)
m: setting value of the UiBRG register
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0)
or divide-by-2n (n=1 to 15).
(2) 9-bit Data Transmit Timing (with no parity and 2 stop bits)
Tc
Transfer Clock
TE bit in UiC1
register
TI bit in UiC1
register
"1"
Data is set in the UiTB register
"0"
"1"
"0"
Data is transferred from the UiTB register to the UARTi transmit register
Stop
Stop
bit
bit
Start
bit
TxDi
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8
SP SP
ST D0 D1
"1"
TXEPT bit in UiC0
register
"0"
IR bit in SiTIC
register
"1"
"0"
Set to "0" by an interrupt request acknowledgement or by program
i=0 to 4
The above timing applies under the following conditions:
• The PRYE bit in the UiMR register is set to "0" (parity disabled)
• The STPS bit in the UiMR register is set to "1" (2 stop bits)
• The CRD bit in the UiC0 register is set to "1" (CTS function
disabled)
• The UilRS bit in the UiC1 register is set to "0" (no data in the
transmit buffer)
Figure 16.14 Transmit Operation
Rev. 1.00 Nov. 01, 2005 Page 186 of 330
REJ09B0271-0100
Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT
fj: count source frequency set in the UiBRG register (f1, f8, f2n(1))
fEXT: count source frequency set in the UiBRG register (external
clock)
m: setting value of the UiBRG register
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division
(n=0) or divide-by-2n (n=1 to 15).
16. Serial I/O (UART)
M32C/80 Group
8-bit Data Receive Timing (with no parity and 1 stop bit)
UiBRG register
setting output
RE bit in the
UiC1 register
"1"
"0"
Stop bit
Start bit
RxDi
D1
D0
Verify if an "L"
signal is applied
D7
Capture a received data
Transfer Clock
RI bit in the UiC1
register
RTSi
Data is transferred from the UARTi receive
Start receiving when the transfer clock is
"1" generated on the falling edge of the start bit register to the UiRB register
"0"
"H"
"L"
Change to "L" by reading the UiRB register
IR bit in the SiRIC "1"
register
"0"
Set to "0" by an interrupt request acknowledgement or by program
i=0 to 4
NOTE:
1. The above applies when the PRYE bit in the UiMR register is set to "0" (parity disabled),
the STPS bit in the UiMR register is set to "0" (1 stop bit) and the CRS bit in the UiC0 register is set
to "1" (RTS function selected).
Figure 16.15 Receive Operation
16.2.1 Bit Rate
In UART mode, bit rate is clock frequency which is divided by a setting value of the UiBRG (i=0 to 4)
register and again divided by 16. Table 16.11 lists an example of bit rate setting.
Table 16.11 Bit Rate
Bit Rate
(bps)
Count
Source
of
UiBRG
Peripheral Function Clock:
16MHz
Setting Value
of UiBRG: n
Actual Bit Rate
(bps)
Peripheral Function Clock:
24MHz
Setting Value
of UiBRG: n
Actual Bit Rate
(bps)
Peripheral Function Clock:
32MHz
Setting Value
of UiBRG: n
Actual Bit Rate
(bps)
1200
f8
103 (67h)
1202
155 (96h)
1202
207 (CFh)
1202
2400
f8
51 (33h)
2404
77 (46h)
2404
103 (67h)
2404
4800
f8
25 (19h)
4808
38 (26h)
4808
51 (33h)
4808
9600
f1
103 (67h)
9615
155 (96h)
9615
207 (CFh)
9615
14400
f1
68 (44h)
14493
103 (67h)
14423
138 (8Ah)
14388
19200
f1
51 (33h)
19231
77 (46h)
19231
103 (67h)
19231
28800
f1
34 (22h)
28571
51 (33h)
28846
68 (44h)
28986
31250
f1
31 (1Fh)
31250
47 (2Fh)
31250
63 (3Fh)
31250
38400
f1
25 (19h)
38462
38 (26h)
38462
51 (33h)
38462
51200
f1
19 (13h)
50000
28 (1Ch)
51724
38 (26h)
51282
Rev. 1.00 Nov. 01, 2005 Page 187 of 330
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16. Serial I/O (UART)
M32C/80 Group
16.2.2 Selecting LSB First or MSB First
As shown in Figure 16.16, the UFORM bit in the UiC0 register (i=0 to 4) determines data transfer format.
This function is available for 8-bit transfer data.
(1) When the UFORM Bit in the UiC0 Register (i=0 to 4) is set to "0" (LSB first)
CLKi
"H"
"L"
TxDi
"H"
"L"
RxDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
"H"
"L"
(2) When the UFORM Bit in the UiC0 Register is set to "1" (MSB first)
CLKi
"H"
"L"
TxDi "H"
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
"H"
"L"
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
"L"
RxDi
NOTE:
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
transmitted on the falling edge of the transfer clock and received on the rising edge)
and the UiLCH bit in the UiC1 register is set to "0" (no inverse).
ST: Start bit
P: Parity bit
SP: Stop bit
Figure 16.16 Transfer Format
16.2.3 Serial Data Logic Inverse
When the UiLCH bit (i=0 to 4) in the UiC1 register is set to "1" (inverse), data logic written in the UiTB
register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB
register. Figure 16.17 shows a switching example of the serial data logic.
(1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (no inverse)
Transfer Clock
"H"
"L"
TxDi
"H"
(no inverse)
"L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
D7
P
SP
(2) When the UiLCH bit in the UiC1 register is set to "1" (inverse)
Transfer Clock
"H"
"L"
TxDi
"H"
(inverse) "L"
ST
D0
D1
D2
D3
D4
D5
D6
NOTE:
1. The above applies when the UFORM bit in the UiC0 register is set to "0" (
LSB first), the STPS bit in the UiMR register is set to "0" (1 stop bit) and the
PRYE bit is set to "1" (parity enabled).
Figure 16.17 Serial Data Logic Inverse
Rev. 1.00 Nov. 01, 2005 Page 188 of 330
REJ09B0271-0100
ST: Start bit
P: Parity bit
SP: Stop bit
16. Serial I/O (UART)
M32C/80 Group
16.2.4 TxD and RxD I/O Polarity Inverse
TxD pin output and RxD pin input are inversed. All I/O data level, including the start bit, stop bit and parity
bit, are inversed. Figure 16.18 shows TxD and RxD I/O polarity inverse.
(1) When the IOPOL bit in the UiMR register (i=0 to 4) is set to "0" (no inverse)
Transfer Clock
"H"
"L"
TxDi
"H"
(no inverse)
"L"
RxDi
"H"
(no inverse)
"L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When the IOPOL bit in the UiMR register is set to "1" (inverse)
Transfer Clock
"H"
TxDi
"H"
"L"
(inverse) "L"
RxDi
"H"
(inverse)
"L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
NOTE:
1. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB
first), the STPS bit in the UiMR bit is set to "0" (1 stop bit) and the PRYE bit is
set to "1" (parity enabled).
Figure 16.18 TxD and RxD I/O Polarity Inverse
Rev. 1.00 Nov. 01, 2005 Page 189 of 330
REJ09B0271-0100
ST: Start bit
P: Even parity
SP: Stop bit
16. Serial I/O (Special Function)
M32C/80 Group
16.3 Special Mode 1 (I2C Mode)
I2C mode is a mode to communicate with external devices with a simplified I2C. Table 16.12 lists specifications of I2C mode. Table 16.13 lists register settings, Table 16.14 lists each function. Figure 16.19 shows
a block diagram of I2C mode. Figure 16.20 shows timings for transfer to the UiRB register (i=0 to 4) and
interrupts. Tables 16.15 to 16.17 list pin settings.
As shown in Table 16.12, I2C mode is entered when the SMD2 to SMD0 bits in the UiMR register is set to
"0102" and the IICM bit in the UiSMR register is set to "1". Output signal from the SDAi pin changes after
the SCLi pin level becomes low ("L") and stabilizes due to a SDAi transmit output via the delay circuit.
Table 16.12 I2C Mode Specifications
Item
Interrupt
Specifications
Start condition detect, stop condition detect, no acknowledgment detect, acknowledgment
detect
Selectable Function
• Arbitration lost
Selectable from update timing of the ABT bit in the UiRB register.
Refer to 16.3.3 Arbitration
• SDAi digital delay
Selectable from no digital delay or 2 to 8 cycle delay of the count source of of the
UiBRG register. Refer to 16.3.5 SDA Output
• Clock phase setting
Selectable from clock delay or no clock delay. Refer to 16.3.4 Transfer Clock
Rev. 1.00 Nov. 01, 2005 Page 190 of 330
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16. Serial I/O (Special Function)
M32C/80 Group
SDAi
(Note1)
Timer
To DMA
I/O
UARTi
IICM 1
Delay Circuit
0
SDHI
D
Q
IICM=1 and
IICM2=0
To DMA
Arbitration
1
0
IICM=0 or
IICM2=1
IICM
Receive Register
UARTi
S
Detects Stop Condition
Falling edge
detect
SCLi
Noise
Filter
Q
Bus
busy
NACK
D Q
T
LSYN bit
D Q
T
R
I/O
Data Register
ACK
9th Pulse
Internal Clock
UARTi
Noise
Filter
R
IICM=1
1 IICM
UARTi Reception
ACK Interrupt Request
DMA Request
IICM=1 and
IICM2=0
Detects Start Condition
(Note 1)
UARTi Transmission
NACK Interrupt
Request
UARTi
ALS
T
Noise
Filter
IICM=0 or IICM2=1
Transmit Register
Bus Conflict
SWC2 CLK
Detect
Control
UARTi
External Clock
1
0
IICM
0
QR
S
Falling Edge of 9th Pulse
SWC
Port reading
(Note 1)
CLKi
UARTi
IICM=0
I/O
Timer
i=0 to 4
NOTE:
1. Set the PSj (j=0,1,3), PSLj or PSC register to determine.
IICM: Bit in the UiSMR register
IICM2: Bit in the UiSMR2 register
Figure 16.19 I2C Mode Block Diagram
Rev. 1.00 Nov. 01, 2005 Page 191 of 330
REJ09B0271-0100
* When the IICM bit is set to "1", port pin can be read
regardless of the direction register being set to "1" (output).
Bus Conflict
Start Condition Detect
Stop Condition Detect
Interrupt Request
16. Serial I/O (Special Function)
M32C/80 Group
Table 16.13 Register Settings in I2C Mode
Register
Bit
Function
Master
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
IFSR
i=0 to 4
Slave
7 to 0
7 to 0
8
ABT
OER
7 to 0
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD, NCH
CKPOL
UFORM
TE
TI
RE
RI
UiRRM, UiLCH,
UiERE
IICM
ABC
BBS
7 to 3
IICM2
CSC
SWC
Set transmit data
Received data can be read
ACK or NACK bit can be read
Arbitration lost detect flag
Overrun error flag
Set bit rate
Set to "0102"
Set to "0"
Set to "0"
Select count source of the UiBRG register
Disabled because the CRD bit is set to "1"
Transfer register empty flag
Set to "1"
Set to "0"
Set to "1"
Set to "1" to enable data transmission
Transfer buffer empty flag
Set to "1" to enable data reception
Reception complete flag
Set to "0"
STSPSEL
ACKD
ACKC
SCLHI
Set to "1" when using a condition generating function
Select ACK or NACK
Set to "1" for ACK data output
Set to "1" to enable SCL output stop when
Not used. Set to "0"
SWC9
detecting stop condition
Not used. Set to "0"
IFSR6, IFSR7
Set to "1"
Disabled
Disabled
Set to "1"
Disabled
Set to "1"
Select an arbitration lost detect timing
Disabled
Bus busy flag
Set to "000002"
See Table 16.14
Set to "1" to enable clock synchronization
Set to "0"
Set to "1" to fix an "L" signal output from SCLi on the falling edge of the ninth bit
of the transfer clock
ALS
Set to "1" to terminate SDAi output when
Not used. Set to "0"
detecting the arbitration lost
STC
Not used. Set to "0"
Set to "1" to reset UARTi
by detecting the start condition
SWC2
Set to "1" for an "L" signal output from SCL forcibly
SDHI
Set to "1" to disable SDA output
SU1HIM
Set to "0"
SSE
Set to "0"
CKPH
See Table 16.14
DINC, NODC, ERR Set to "0"
DL2 to DL0
Set digital delay value for SDAi
STAREQ
Set to "1" when generating a start condition
Not used. Set to "0"
RSTAREQ
Set to "1" when generating a restart condition
STPREQ
Set to "1" when generating a stop condition
Rev. 1.00 Nov. 01, 2005 Page 192 of 330
REJ09B0271-0100
Set to "1" to fix an "L" signal output
from SCLi on the falling edge of the
ninth bit of the transfer clock
16. Serial I/O (Special Function)
M32C/80 Group
Table 16.14 I2C Mode Functions
I2 C Mode (SMD2 to SMD0=0102, IICM=1)
Function
Clock Synchronous
Serial I/O Mode
(SMD2 to SMD0=0012,
IICM=0)
IICM2=0
(NACK/ACK interrupt)
IICM2=1
(UART transmit / UART receive interrupt)
CKPH=0
(No clock delay)
CKPH=0
(No clock delay)
CKPH=1
(Clock delay)
CKPH=1
(Clock delay)
Source for Interrupt
Numbers 39 to 41( 1 )
(See Figure 16.20)
-
Start condition or stop condition detect (See Table 16.18)
Source for Interrupt
Number 17, 19, 33, 35
and 37( 1 )
(See Figure 16.20)
UARTi Transmission Transmission started or
completed (selected by
the UiIRS register)
No Acknowledgement
Detection (NACK) Rising edge of 9th bit of SCLi
UARTi
Transmission Rising edge of
9th bit of SCLi
Source for Interrupt
Numbers 18, 20, 34, 36
and 38( 1 )
(See Figure 16.20)
UARTi Reception Receiving at 8th bit
CKPOL=0(rising edge)
CKPOL=1(falling edge)
Acknowledgement Detection
(ACK) Rising edge of 9th bit of SCLi
UARTi Reception Falling edge of 9th bit of SCLi
Data Transfer Timing from
the UART Receive Shift
Register to the UiRB Register
CKPOL=0(rising edge)
CKPOL=1(falling edge)
Rising edge of 9th bit of SCLi
Falling edge of
9th bit of SCLi
UARTi Transmit Output
Delay
No delay
Delay
P63, P67, P70, P92, P96
Pin Functions
TxDi output
SDAi input and output
P62, P66, P71, P91, P97
Pin Functions
RxDi input
SCLi input and output
P61, P65, P72, P90, P95
Pin Functions
Select CLKi input or
output
– (Not used in I2 C mode)
Noise Filter Width
15 ns
200 ns
Reading RxDi and SCLi
Pin Levels
Can be read if port
direction bit is set to "0"
Can be read regardless of the port direction bit
Default Value of TxDi,
SDAi Output
CKPOL=0 (H)
CKPOL=1 (L)
Values set in the port register before entering I2 C mode( 2 )
SCLi Default and End
Value
–
H
Source for DMA
(See Figure 16.20)
UARTi reception
Acknowledgement detection
(ACK)
Store Received Data
Reading Received Data
1st to 8th bits of the
received data are stored
into bits 7 to 0 in the
UiRB register
L
1st to 8th bits of the received
data are stored into bits 7 to 0
in the UiRB register
The UiRB register status is read
H
UARTi Transmission Next falling edge after the
9th bit of SCLi
Falling edge and rising edge
of 9th bit of SCLi
L
UARTi Reception Falling edge of 9th bit of SCLi
1st to 7th bits of the received data are stored
into bits 6 to 0 in the UiRB register. 8th bit is
stored into bit 8 in the UiRB register.
1st to 8th bits are stored into
bits 7 to 0 in the UiRB
register(3 )
Bits 6 to 0 in the UiRB
registerts( 4 ) are read as bit 7
to 1. Bit 8 in the UiRB
register is read as bit 0
i=0 to 4
NOTES:
1. Use the following procedure to change what causes an interrupt to be generated.
(a) Disable interrupt of corresponding interrupt number.
(b) Change what causes an interrupt to be generated.
(c) Set the IR bit of a corresponding interrupt number to "0" (no interrupt requested).
(d) Set the ILVL2 to ILVL0 bits of a corresponding interrupt number.
2. Set default value of the SDAi output when the SMD2 to SMD0 bits in the UiMR register are set to "0002"
(serial I/O disabled).
3. Second data transfer to the UiRB register (on the rising edge of the ninth bit of SCLi).
4. First data transfer to the UiRB register (on the falling edge of the ninth bit of SCLi).
Rev. 1.00 Nov. 01, 2005 Page 193 of 330
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16. Serial I/O (Special Function)
M32C/80 Group
(1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (no clock delay)
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK or NACK)
ACK interrupt (DMA
request) or NACK interrupt
b15
Data is transferred to the UiRB register
b9
b8
b7
b0
D8 D7 D 6 D 5 D4 D3 D2 D1 D 0
•••
Contents of the UiRB register
(2) When the IICM2 bit is set to "0" and the CKPH bit is set to "1" (clock delay)
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK or NACK)
ACK interrupt (DMA
request) or NACK interrupt
b15
Data is transferred to the UiRB register
b9
•••
b8
b7
b0
D8 D7 D6 D 5 D 4 D3 D2 D1 D0
Contents of the UiRB register
(3) When the IICM2 bit is set to "1" (UART transmit or receive interrupt) and the CKPH bit is set to "0"
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D8 (ACK or NACK)
D0
Receive interrupt
(DMA request)
Transmit interrupt
b15
Data is transferred to the UiRB register
b9
b8
b7
D0
•••
b0
D7 D6 D5 D4 D 3 D 2 D 1
Contents of the UiRB register
(4) When the IICM2 bit is set to "1" and the CKPH bit is set to "1"
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK or NACK)
Receive interrupt
(DMA request)
Data is transferred to the UiRB register
b15
b9
•••
i=0 to 4
IICM2: Bit in the UiSMR2 register
CKPH: Bit in the UiSMR3 regiser
b8
b7
D0
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D7 D6 D 5 D 4 D3 D2 D1
Contents of the UiRB register
The above applies under the following condition:
• The CKDIR bit in the UiMR register is set to "1" (slave)
Figure 16.20 SCLi Timing
b0
Transmit interrupt
Data is transferred to the UiRB register
b15
b9
•••
b8
b7
b0
D 8 D7 D6 D5 D 4 D 3 D2 D 1 D0
Contents of the UiRB register
16. Serial I/O (Special Function)
M32C/80 Group
Table 16.15 Pin Settings in I2C Mode (1)
Port
Function
Setting
PS0 Register
P62
P63
P66
P67
PSL0 Register
PD6 Register
SCL0 output
PS0_2=1
PSL0_2=0
-
SCL0 input
PS0_2=0
-
PD6_2=0
SDA0 output
PS0_3=1
-
-
SDA0 input
PS0_3=0
-
PD6_3=0
SCL1 output
PS0_6=1
PSL0_6=0
-
SCL1 input
PS0_6=0
-
PD6_6=0
SDA1 output
PS0_7=1
-
-
SDA1 input
PS0_7=0
-
PD6_7=0
Table 16.16 Pin Settings (2)
Setting
Port
Function
PS1 Register
PSL1 Register PSC Register PD7 Register
SDA2 output
PS1_0=1
PSL1_0=0
PSC_0=0
–
SDA2 input
PS1_0=0
–
–
PD7_0=0
SCL2 output
PS1_1=1
PSL1_1=1
PSC_1=0
–
SCL2 input
PS1_1=0
–
–
PD7_1=0
P70( 1 )
P71( 1 )
NOTE:
1. P70 and P71 are ports for the N-channel open drain output.
Table 16.17 Pin Settings (3)
Port
Function
Setting
PS3
P91
P92
P96
P97
Register(1)
PSL3 Register
PSC3 Register
PD9 Register(1)
SCL3 output
PS3_1=1
PSL3_1=0
-
-
SCL3 input
PS3_1=0
-
-
PD9_1=0
SDA3 output
PS3_2=1
PSL3_2=0
-
-
SDA3 input
PS3_2=0
-
-
PD9_2=0
SDA4 output
PS3_6=1
-
PSC3_6=0
-
SDA4 input
PS3_6=0
-
-
PD9_6=0
SCL4 output
PS3_7=1
PSL3_7=0
-
-
SCL4 input
PS3_7=0
-
-
PD9_7=0
NOTE:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enabled).
Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the
instruction to set the PD9 and PS3 registers.
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16. Serial I/O (Special Function)
M32C/80 Group
16.3.1 Detecting Start Condition and Stop Condition
The microcomputer detects either a start condition or stop condition. The start condition detect interrupt
is generated when the SCLi (i=0 to 4) pin level is held high ("H") and the SDAi pin level changes "H" to low
("L"). The stop condition detect interrupt is generated when the SCLi pin level is held "H" and the SDAi pin
level changes "L" to "H". The start condition detect interrupt shares interrupt control registers and vectors
with the stop condition detect interrupt. The BBS bit in the UiSMR register determines which interrupt is
requested.
3 to 6 cycles < setup time(1)
3 to 6 cycles < hold time(1)
Setup time
Hold time
SCLi
SDAi
(Start condition)
SDAi
(Stop condition)
i=0 to 4
NOTE:
1. These cycles are main clock generation frequency cycles f(XIN).
Figure 16.21 Start Condition or Stop Condition Detecting
16.3.2 Start Condition or Stop Condition Output
The start condition is generated when the STAREQ bit in the UiSMR4 register (i=0 to 4) is set to "1"
(start). The restart condition is generated when the RSTAREQ bit in the UiSMR4 register is set to "1"
(start). The stop condition is generated the STPREQ bit in the UiSMR4 is set to "1" (start).
The start condition is output when the STAREQ bit is set to "1" and the STSPSEL bit in the UiSMR4
register is set to "1" (start or stop condition generating circuit selected). The restart condition output is
provided when the RSTAREQ bit and STSPSEL bit are set to "1". The stop condition output is provided
when the STPREQ bit and the STSPSEL bit are set to "1".
When the start condition, stop condition or restart condition is output, do not generate an interrupt between the instruction to set the STAREQ bit, STPREQ bit or RSTAREQ bit to "1" and the instruction to set
the STSPSEL bit to "1". When the start condition is output, set the STAREQ bit to "1" before the
STSPSEL bit is set to "1".
Table 16.18 lists function of the STSPSEL bit. Figure 16.22 shows functions of the STSPSEL bit.
Rev. 1.00 Nov. 01, 2005 Page 196 of 330
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16. Serial I/O (Special Function)
M32C/80 Group
Table 16.18 STSPSEL Bit Function
Function
STSPSEL = 0
STSPSEL = 1
Start condition and stop
condition output
Program with ports determines how the
start condition or stop condition output
is provided
The STAREQ bit, RSTAREQ bit and
STPREQ bit determine how the start
condition or stop condition output is
provided
Timing to generate start
condition and stop condition
interrupt requests
The start condition and stop condition
are detected
Start condition and stop condition
generation are completed
(1) In slave mode,
The CKDIR bit is set to "1" (external clock)
The STSPSEL bit is set to "0" (no start condition and stop condition output)
SCLi
SDAi
Start condition detect
interrupt
Stop condition detect
interrupt
(2) In master mode,
The CKDIR bit is set to "0" (internal clock)
The STSPSEL bit is set to "1" (start condition and stop condition output)
Setting value of
the STSPEL bit
0
1
0
1
0
SCLi
SDAi
The STPREQ
bit is set to "1"
(start)
Start condition detect
interrupt
i=0 to 4
Figure 16.22 STSPSEL Bit Function
Rev. 1.00 Nov. 01, 2005 Page 197 of 330
REJ09B0271-0100
The STPREQ
bit is set to "1"
(start)
Stop condition detect
interrupt
M32C/80 Group
16. Serial I/O (Special Function)
16.3.3 Arbitration
The ABC bit in the UiSMR register (i=0 to 4) determines an update timing for the ABT bit in the UiRB
register. On the rising edge of the SCLi pin, the microcomputer determines whether a transmit data
matches data input to the SDAi pin.
When the ABC bit is set to "0" (update per bit), the ABT bit is set to "1" (detected-arbitration is lost) as
soon as a data discrepancy is detected. The ABT bit is set to "0" (not detected-arbitration is won) if not
detected. When the ABC bit is set to "1" (update per byte), the ABT bit is set to "1" on the falling edge of
the ninth bit of the transfer clock if any discrepancy is detected. When the ABT bit is updated per byte, set
the ABT bit to "0" between an ACK detection in the first byte data and the next byte data to be transferred.
When the ALS bit in the UiSMR2 register is set to "1" (SDA output stop enabled), the arbitration lost
occurs. As soon as the ABT bit is set to "1", the SDAi pin is placed in a high-impedance state.
16.3.4 Transfer Clock
The transfer clock transmits and receives data as is shown in Figure 16.20.
The CSC bit in the UiSMR2 register (i=0 to 4) synchronizes an internally generated clock (internal SCLi)
with the external clock applied to the SCLi pin. When the CSC bit is set to "1" (clock synchronous enabled) and the internal SCLi is held high ("H"), the internal SCLi become low ("L") if signal applied to the
SCLi pin is on the falling edge. Value of the UiBRG register is reloaded to start counting for low level. A
counter stops when the SCLi pin is held "L" and then the internal SCLi changes "L" to "H". Counting is
resumed when the SCLi pin become "H". The transfer clock of UARTi is equivalent to the AND for signals
from the internal SCLi and the SCLi pin.
The transfer clock is synchronized between a half cycle before the falling edge of first bit of the internal
SCLi and the rising edge of the ninth bit. Select the internal clock as the transfer clock while the CSC bit
is set to "1".
The SWC bit in the UiSMR2 register determines whether the SCLi pin is fixed to be an "L" signal output on
the falling edge of the ninth cycle of the transfer clock or not.
When the SCLHI bit in the UiSMR4 register is set to "1" (enabled), a SCLi output stops when a stop
condition is detected (high-impedance).
When the SWC2 bit in the UiSMR2 register is set to "1" (0 output), the SCLi pin focibly outputs an "L" signal
while transmitting and receiving. The fixed "L" signal applied to the SCLi pin is cancelled by setting the
SWC2 bit to "0" (transfer clock) and the transfer clock input to and output from the SCLi pin are provided.
When the CKPH bit in the UiSMR3 register is set to "1" and the SWC9 bit in the UiSMR4 register is set to
"1" (SCL "L" hold enabled), the SCLi pin is fixed to be an "L" signal output on the next falling edge after the
ninth bit of the clock. The fixed "L" signal applied to the SCLi pin is cancelled by setting the SWC9 bit to
"0" (SCL "L" hold disabled).
16.3.5 SDA Output
Values output set in bits 7 to 0 (D7 to D0) in the UiTB register (i=0 to 4) are provided in descending order
from D7. The ninth bit (D8) is ACK or NACK.
Set the default value of SDAi transmit output when the IICM bit is set to "1" (I2C mode) and the SMD2 to
SMD0 bits in the UiMR register are set to "0002" (serial I/O disabled).
The DL2 to DL0 bits in the UiSMR3 register determine no delay in the SDAi output or a delay of 2 to 8
UiBRG register count source cycles.
When the SDHI bit in the UiSMR2 register is set to "1" (SDA output disabled), the SDAi pin is forcibly
placed in a high-impedance state. Do not set the SDHI bit on the rising edge of the UARTi transfer clock.
The ABT bit in the UiRB register may be set to "1" (detected).
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M32C/80 Group
16. Serial I/O (Special Function)
16.3.6 SDA Input
When the IICM2 bit in the UiSMR2 register (i=0 to 4) is set to "0", the first eight bits of received data are
stored into bits 7 to 0 (D7 to D0) in the UiRB register. The ninth bit (D8) is ACK or NACK.
When the IICM2 bit is set to "1", the first seven bits (D7 to D1) of received data are stored into bits 6 to 0
in the UiRB register. Store the eighth bit (D0) into bit 8 in the UiRB register.
If the IICM2 bit is set to "1" and the CKPH bit in the UiSMR3 register is set to "1", the same data as that of
when setting the IICM2 bit to "0" can be read. To read the data, read the UiRB register after the rising
edge of the ninth bit of the transfer clock.
16.3.7 ACK, NACK
When the STSPSEL bit in the UiSMR4 register (i=0 to 4) is set to "0" (serial I/O circuit selected) and the
ACKC bit in the UiSMR4 register is set to "1" (ACK data output), the SDAi pin provides the value output
set in the ACKD bit in the UiSMR4 register.
If the IICM2 bit is set to "0", the NACK interrupt request is generated when the SDAi pin is held high ("H")
on the rising edge of the ninth bit of the transfer clock. The ACK interrupt request is generated when the
SDAi pin is held low ("L") on the rising edge of the ninth bit of the transfer clock.
When ACK is selected to generate a DMA request, the DMA transfer is activated by an ACK detection.
16.3.8 Transmit and Receive Reset
When the STC bit in the UiSMR2 register (i=0 to 4) is set to "1" (UARTi initialization enabled) and a start
condition is detected,
- the transmit shift register is reset and the content of the UiTB register is transferred to the transmit shift
register. The first bit starts transmitting when the next clock is input. UARTi output value remains
unchanged between when the clock is applied and when the first bit data output is provided. The value
remains the same as when start condition was detected.
- the receive shift register is reset and the first bit start receiving when the next clock is applied.
- the SWC bit is set to "1" (SCL wait output enabled). The SCLi pin becomes "L" on the falling edge of the
ninth bit of the transfer clock.
If UARTi transmission and reception are started with this function, the TI bit in the UiC1 register remains
unchanged. Select the external clock as the transfer clock when using this function.
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16. Serial I/O (Special Function)
M32C/80 Group
16.4 Special Mode 2
In special
mode 2, serial communication between one or multiple masters and multiple slaves is available.
_____
The SSi input pin (i=0 to 4) controls the serial bus communication. Table 16.19 lists specifications of special
mode 2. Table 16.20 lists register settings. Tables 16.21 to 16.23 list pin settings.
Table 16.19 Special Mode 2 Specifications
Item
Transfer Data Format
Transfer Clock
Specification
Transfer data : 8 bits long
• The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected):
fj/2(m+1) fj = f1, f8, f2n(1)
m : setting value of the UiBRG register, 0016 to FF16
• The CKDIR bit to "1" (external clock selected) : input from the CLKi pin
______
Transmit/Receive Control SSi input pin function
Transmit Start Condition To start transmitting, the following requirements must be met(2):
- Set the TE bit in the UiC1 register to "1" (transmit enabled)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
Receive Start Condition To start receiving, the following requirement must be met(2):
- Set the RE bit in the UiC1 register to "1" (receive enabled)
- Set the TE bit in the UiC1 register to "1" (transmit enabled)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
Interrupt Request
• While transmitting, the following conditions can be selected:
Generation Timing
- The UiIRS bit in the UiC1 register is set to "0" (no data in a transmit buffer) :
when data is transferred from the UiTB register to the UARTi transmit register (transmission started)
- The UiIRS register is set to "1" (transmission completed):
when data transmission from UARTi transfer register is completed
• While receiving
When data is transferred from the UARTi receive register to the UiRB register (reception completed)
Error Detection
• Overrun error(3)
This error occurs when the seventh bit of the next received data is read before reading
the UiRB register
• Fault error
______
In master mode, the fault error occurs an "L" signal is applied to the SSi pin
Selectable Function
• CLK polarity
Selectable from the rising edge or falling edge of the transfer clock at transferred data
output or input timing
• LSB first or MSB first
Selectable from data transmission or reception in either bit 0 or in bit 7
• Continuous receive mode
Data reception is enabled simultaneously by reading the UiRB register
• Serial data logic inverse
This function inverses transmitted or received data logically
• TxD and RxD I/O polarity inverse
TxD pin output and RxD pin input are inversed. All I/O data levels are also inversed
• Clock phase
Selectable from one of 4 combinations of transfer data polarity and phases
_____
• SSi input pin function
Output pin is placed in a high-impedance state to avoid data conflict between master
and other masters or slaves
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. To start transmission/reception when selecting the external clock, these conditions must be met after the
CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data
is received on the rising edge) and the CLKi pin is held high ("H"), or when the CKPOL bit is set to "1" (Data is
transmitted on the rising edge of the transfer clock and data is received on the falling edge) and the CLKi pin is
held low ("L").
3. If an overrun error occurs, the UiRB register is in an indeterminate state. The IR bit setting in the SiRIC register
does not change to "1" (interrupt requested).
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16. Serial I/O (Special Function)
M32C/80 Group
Table 16.20 Register Settings in Special Mode 2
Register
Bit
Function
UiTB
7 to 0
Set transmit data
UiRB
7 to 0
Received data can be read
OER
Overrun error flag
UiBRG
7 to 0
Set bit rate
UiMR
UiC0
SMD2 to SMD0
Set to "0012"
CKDIR
Set to "0" in master mode or "1" in slave mode
IOPOL
Set to "0"
CLK1, CLK0
Select count source for the UiBRG register
CRS
Disabled because the CRD bit is set to "1"
TXEPT
Transfer register empty flag
CRD
Set to "1"
NCH
Select the output format of the TxDi pin
CKPOL
Clock phase can be set by the combination of the CKPOL bit and the CKPH bit in
the UiSMR3 register
UiC1
UFORM
Select either LSB first or MSB first
TE
Set to "1" to enable data transmission and reception
TI
Transfer buffer empty flag
RE
Set to "1" to enable data reception
RI
Reception complete flag
UiIRS
Select what causes the UARTi transmit interrupt to be generated
UiRRM
Set to "1" to enable continuous receive mode
UiLCH, SCLKSTPB Set to "0"
UiSMR
7 to 0
Set to "0016"
UiSMR2
7 to 0
Set to "0016"
SSE
Set to "1"
CKPH
Clock phase can be set by the combination of the CKPH bit and the CKPOL bit
UiSMR3
in the UiC0 register
DINC
UiSMR4
Set to "0" in master mode or "1" in slave mode
NODC
Set to "0"
ERR
Fault error flag
7 to 5
Set to "0002"
7 to 0
Set to "0016"
i=0 to 4
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16. Serial I/O (Special Function)
M32C/80 Group
Table 16.21 Pin Settings in Special Mode 2 (1)
Port
Function
______
P60
P61
SS0 input
CLK0 input (slave)
CLK0 output (master)
RxD0 input (master)
STxD0 output (slave)
TxD0 output (master)
SRxD0 input (slave)
______
SS1 input
CLK1 input (slave)
CLK1 output (master)
RxD1 input (master)
STxD1 output (slave)
TxD1 output (master)
SRxD1 input (slave)
P62
P63
P64
P65
P66
P67
PS0 Register
PS0_0=0
PS0_1=0
PS0_1=1
PS0_2=0
PS0_2=1
PS0_3=1
PS0_3=0
PS0_4=0
PS0_5=0
PS0_5=1
PS0_6=0
PS0_6=1
PS0_7=1
PS0_7=0
Setting
PSL0 Register
–
–
–
–
PSL0_2=1
–
–
–
–
–
–
PSL0_6=1
–
–
PS1 Register
PS1_0=1
PS1_0=0
PS1_1=0
PS1_1=1
PS1_2=0
PS1_2=1
PS1_3=0
Setting
PSL1 Register
PSC Register
PSL1_0=0
PSC_0=0
–
–
–
–
PSL1_1=1
PSC_1=0
–
–
PSL1_2=0
PSC_2=0
–
–
PD7 Register
–
PD7_0=0
PD7_1=0
–
PD7_2=0
–
PD7_3=0
PS3 Register(1)
PS3_0=0
PS3_0=1
PS3_1=0
PS3_1=1
PS3_2=1
PS3_2=0
PS3_3=0
PS3_4=0
PS3_5=0
PS3_5=1
PS3_6=1
PS3_6=0
PS3_7=0
PS3_7=1
Setting
PSL3 Register
–
–
–
PSL3_1=1
PSL3_2=0
–
PSL3_3=0
PSL3_4=0
PSL3_5=0
–
–
PSL3_6=0
–
PSL3_7=1
PD9 Register(1)
PD9_0=0
–
PD9_1=0
–
–
PD9_2=0
PD9_3=0
PD9_4=0
PD9_5=0
–
–
PD9_6=0
PD9_7=0
–
PD6 Register
PD6_0=0
PD6_1=0
–
PD6_2=0
–
–
PD6_3=0
PD6_4=0
PD6_5=0
–
PD6_6=0
–
–
PD6_7=0
Table 16.22 Pin Settings (2)
Port
P70(1)
P71(1)
P72
Function
TxD2 output (master)
SRxD2 input (slave)
RxD2 input (master)
STxD2 output (slave)
CLK2 input (slave)
CLK2 output (master)
______
SS2 input
P73
NOTE:
1. P70 and P71 are ports for the N-channel open drain output.
Table 16.23 Pin Settings (3)
Port
P90
P91
P92
P93
P94
P95
P96
P97
Function
CLK3 input (slave)
CLK3 output (master)
RxD3 input (master)
STxD3 output (slave)
TxD3 output (master)
SRxD3 input (slave)
______
SS3 input
_______
SS4 input
CLK4 input (slave)
CLK4 output (master)
TxD4 output (master)
SRxD4 input (slave)
RxD4 input (master)
STxD4 output (slave)
PSC3 Register
–
–
–
–
–
–
–
–
–
–
PSC3_6=0
–
–
–
NOTE:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enabled). Do
not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to
set the PD9 and PS3 registers.
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16. Serial I/O (Special Function)
M32C/80 Group
______
16.4.1 SSi Input Pin Function (i=0 to 4)
____
When the SSE bit in the UiSMR3 register is set to "1" (SS function enabled), the special mode 2 is
selected, activating the pin function.
The DINC bit in the UiSMR3 register determines which microcomputer performs as master or slave.
______
When multiple microcomputers perform as the masters (multi-master system), the SSi pin setting determines which master microcomputer is active and when.
16.4.1.1 When Setting the DINC Bit to "1" (Slave Mode)
_____
When a high-level ("H") signal is applied to the SSi pin, the STxDi and SRxDi pins are placed in a highimpedance state and the transfer clock applied to the CLKi pin is ignored. When a low-level ("L") signal
_____
is applied to the SSi input pin, the transfer clock input is valid and serial communication is enabled.
16.4.1.2 When Setting the DINC Bit to "0" (Master Mode)
______
When using the SSi pin functin in master mode, set the UiIRS bit in the UiC1 register to "1" (transmission completed).
_____
When an "H" signal is applied to the SSi pin, serial communication is available due to transmission
_____
privilege. The master provides the transfer clock output. When an "L" signal is applied to the SSi pin,
it indicates that another master is active. The TxDi and CLKi pins are placed in high-impedance states
and the ERR bit in the UiSMR3 register is set to "1" (fault error) Use the transmit complete interrupt
routine to verify the ERR bit state.
To resume the serial communication after the fault error occurs, set the ERR bit to "0" while applying
______
the "H" signal to the SSi pin. The TxDi and CLKi pins become ready for signal outputs.
Microcomputer
Microcomputer
P13
P12
P93(SS3)
P93(SS3)
P90(CLK3)
P90(CLK3)
P91(RxD3)
P91(STxD3)
P92(TxD3)
P92(SRxD3)
Master
Slave
Microcomputer
P93(SS3)
P90(CLK3)
P91(STxD3)
P92(SRxD3)
Slave
____
Figure 16.23 Serial Bus Communication Control with SS Pin
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16. Serial I/O (Special Function)
M32C/80 Group
16.4.2 Clock Phase Setting Function
The CKPH bit in the UiSMR3 register (i=0 to 4) and the CKPOL bit in the UiC0 register select one of four
combinations of transfer clock polarity and phases.
The transfer clock phase and polarity must be the same between the master and the slave involved in the
transfer.
16.4.2.1 When setting the DINC Bit to "0" (Master (Internal Clock))
Figure 16.24 shows transmit and receive timing.
16.4.2.2 When Setting the DINC Bit to "1" (Slave (External Clock))
_____
When the CKPH bit is set to "0" (no clock delay) and the SSi input pin is held high ("H"), the STxDi pin
_____
is placed in a high-impedance state. When the SSi input pin becomes low ("L"), conditions to start a
serial transfer are met, but output is indeterminate. The serial transmission is synchronized with the
transfer clock. Figure 16.25 shows the transmit and receive timing.
_____
When the CKPH bit is set to "1" (clock delay) and the SSi input pin is held high, the STxDi pin is placed
_____
in a high-impedance state. When the SSi pin becomes low, the first data is output. The serial transmission is synchronized with the transfer clock. Figure 16.26 shows the transmit and receive timing.
Signal Applied to
the SS Pin
"H"
"L"
Clock Output
"H"
(CKPOL=0, CKPH=0) "L"
Clock Output
"H"
(CKPOL=1, CKPH=0) "L"
Clock Output
"H"
(CKPOL=0, CKPH=1) "L"
Clock Output
"H"
(CKPOL=1, CKPH=1) "L"
Data Output Timing
"H"
"L"
D0
D1
D2
D3
D4
D5
Data Input Timing
Figure 16.24 Transmit and Receive Timing in Master Mode (Internal Clock)
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D6
D7
16. Serial I/O (Special Function)
M32C/80 Group
Signal Applied to
the SS Pin
"H"
"L"
"H"
Clock Input
(CKPOL=0, CKPH=0) "L"
"H"
Clock Input
(CKPOL=1, CKPH=0) "L"
Data Output Timing(1)
"H"
"L"
Data Input Timing
D0
D1
D2
D3
D4
D5
D6
D7
Highimpedance
Highimpedance
Indeterminate
NOTE:
1. P70 and P71 are ports for the N-channel open drain output and must be pulled up externally
for data output.
Figure 16.25 Transmit and Receive Timing in Slave Mode (External Clock) (CKPH=0)
"H"
Signal Applied to
the SS Pin
"L"
"H"
Clock Input
(CKPOL=0, CKPH=0) "L"
"H"
Clock Input
(CKPOL=1, CKPH=1) "L"
Data Output Timing(1) "H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
Highimpedance
Data Input Timing
NOTE:
1. P70 and P71 are ports for the N-channel open drain output and must be pulled up externally
for data output.
Figure 16.26 Transmit and Receive Timing in Slave Mode (External Clock) (CKPH=1)
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Highimpedance
16. Serial I/O (Special Function)
M32C/80 Group
16.5 Special Mode 3 (GCI Mode)
In GCI mode, the external clock is synchronized with the transfer clock used in the clock synchronous serial
I/O mode.
Table 16.24 lists specifications of GCI mode. Table 16.25 lists registers settings. Tables 16.26 to 16.28 list
pin settings.
Table16.24 GCI Mode Specifications
Item
Specification
Transfer Data Format
Transfer data : 8 bits long
Transfer Clock
The CKDIR bit in the UiMR register (i=0 to 4) is set to "1" (external clock selected):
input from the CLKi pin
________
Clock Synchronization Function Trigger signal input from the CTSi pin
Transmit/Receive Start
To start data transmission and reception, meet the following conditions and then apply a
Condition
trigger signal to the CTSi pin:
________
- Set the TE bit in the UiC1 register to "1" (transmit enabled)
- Set the RE bit in the UiC1 register to "1" (receive enabled)
- Set the TI bit in the UiC1 register to "0" (Data in the UiTB register)
Interrupt Request
• While transmitting, the following condition can be selected:
Generation Timing
- The UiIRS bit in the UiC1 register is set to "0" (UiTB register empty):
when data is transferred from the UiTB register to the UARTi transmit register (transmission started)
- The UiIRS bit is set to "1" (Transmit completed):
when a data transmission from the UARTi transfer register is completed
• While receiving,
when data is transferred from the UARTi receive register to the UiRB register (reception
completed)
Error Detection
Overrun error(1)
This error occurs when the seventh bit of the next received data is read before reading the
UiRB register.
NOTE:
1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit setting in the SiRIC register does not
change to "1" (interrupt requested).
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16. Serial I/O (Special Function)
M32C/80 Group
Table 16.25 Register Settings in GCI Mode
Register
Bit
Function
UiTB
7 to 0
Set transmit data
UiRB
7 to 0
Received data
OER
Overrun error flag
UiBRG
7 to 0
Set to "0016"
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
SMD2 to SMD0
Set to "0012"
CKDIR
Set to "1"
IOPOL
Set to "0"
CLK1, CLK0
Set to "002"
CRS
Disabled because the CRD bit is set to "1"
TXEPT
Transfer register empty flag
CRD
Set to "1"
NCH
Select the output format of the TxDi pin
CKPOL
Set to "0"
UFORM
Set to "0"
TE
Set to "1" to enable data transmission and reception
TI
Transfer buffer empty flag
RE
Set to "1" to enable data reception
RI
Reception complete flag
UiIRS
Select what causes the UARTi transmit interrupt to be generated
UiRRM, UiLCH
Set to "0"
SCLKSTPB
Set to "0"
6 to 0
Set to "00000002"
SCLKDIV
See Table 16.29
6 to 0
Set to "00000002"
SU1HIM
See Table 16.29
2 to 0
Set to "0002"
NODC
Set to "0"
7 to 4
Set to "00002"
7 to 0
Set to "0016"
i=0 to 4
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16. Serial I/O (Special Function)
M32C/80 Group
Table 16.26 Pin Settings in GCI Mode (1)
Port
Function
Setting
PS0 Register
PD6 Register
P60
CTS0 input(1)
PS0_0=0
PD6_0=0
P61
CLK0 input
PS0_1=0
PD6_1=0
P62
RxD0 input
PS0_2=0
PD6_2=0
TxD0 output
__________
P63
PS0_3=1
–
P64
CTS1 input(1)
PS0_4=0
PD6_4=0
P65
CLK1 input
PS0_5=0
PD6_5=0
P66
RxD1 input
PS0_6=0
PD6_6=0
P67
TxD1 output
PS0_7=1
–
__________
NOTE:
_______
1. CTS input is used as a trigger siganl input.
Table 16.27 Pin Settings (2)
Port
Function
Setting
PS1 Register
PSL1 Register
PSC Register
PD7 Register
P70(1)
TxD2 output
PS1_0=1
PSL1_0=0
PSC_0=0
–
P71(1)
RxD2 input
PS1_1=0
–
–
PD7_1=0
CLK2 input
PS1_2=0
–
–
PD7_2=0
PS1_3=0
–
–
PD7_3=0
P72
__________
CTS2 input(2)
P73
NOTES:
1. P70 and P71 are ports for the N-channel open drain output.
_______
2. CTS input is used as a trigger siganl input.
Table 16.28 Pin Settings (3)
Port
Function
Setting
PS3 Register(1)
PSL3 Register
PSL3 Register
PD9 Register(1)
P90
CLK3 input
PS3_0=0
–
–
PD9_0=0
P91
RxD3 input
PS3_1=0
–
–
PD9_1=0
TxD3 output
PS3_2=1
PSL3_2=0
–
–
PS3_3=0
PSL3_3=0
–
PD9_3=0
PS3_4=0
PSL3_4=0
–
PD9_4=0
PS3_5=0
PSL3_5=0
–
PD9_5=0
P92
__________
P93
CTS3 input(2)
__________
input(2)
P94
CTS4
P95
CLK4 input
P96
TxD4 output
PS3_6=1
PSL3_6=0
PSL3_6=0
–
P97
RxD4 input
PS3_7=0
–
–
PD9_7=0
NOTES:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enabled). Do
not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to
set the PD9 and PS3 registers.
_______
2. CTS input is used for a trigger siganl input.
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16. Serial I/O (Special Function)
M32C/80 Group
To generate the internal clock synchronized with the external clock, set the SU1HIM bit in the UiSMR2
register (i=0 to 4) and the SCLKDIV bit in the UiSMR register to values shown in Table 16.29. Then apply
________
a trigger signal to the CTSi pin. Either the same clock cycle as the external clock or external clock divided
by two can be selected as the transfer clock. The SCLKSTPB bit in the UiC1 register controls the transfer
clock. Set the SCLKSTPB bit accordingly, to start or stop the transfer clock during an external clock
operation. Figure 16.27 shows an example of the clock-divided synchronous function.
Table 16.29 Clock-Divided Synchronous Function Select
SCLKDIV Bit in
SU1HIM Bit in
Clock-Divided Synchronous Function
UiSMR Register
UiSMR2 Register
Example of Waveform
0
0
Not synchronized
-
0
1
Same division as the external clock
A in Figure 16.27
1
0 or 1
Same division as the external clock
B in Figure 16.27
divided by 2
i=0 to 4
External Clock
from the CLKi Pin
Trigger Signal
from the CTSi Pin
1
2
3
4
5
6
7
8
Transfer Clock
The SCLKSTPB bit in the UiC1 register
stops the clock
A
TxDi
1
2
3
4
5
6
7
8
Transfer Clock
B
TxDi
1
2
3
i=0 to 4
A, B: See Table 16.29.
Figure 16.27 Clock-Divided Synchronous Function
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4
5
6
7
8
16. Serial I/O (Special Function)
M32C/80 Group
16.6 Special Mode 4 (IE Mode)
In IE mode, devices connected with the IEBus can communicate in UART mode.
Table 16.30 lists register settings. Tables 16.31 to 16.33 list pin settings.
Table 16.30 Register Settings in IE Mode
Register
Bit
Function
UiTB
8 to 0
Set transmit data
UiRB
8 to 0
Received data can be read
OER, FER,
Error flags
PER, SUM
UiBRG
7 to 0
Set bit rate
UiMR
SMD2 to SMD0
Set to "1102"
CKDIR
Select the internal clock or external clock
STPS
Set to "0"
PRY
Disabled because the PRYE bit is set to "0"
PRYE
Set to "0"
UiC0
UiC1
IOPOL
Select TxD and RxD I/O polarity
CLK1, CLK0
Select count source for the UiBRG register
CRS
Disabled because the CRD bit is set to "1"
TXEPT
Transfer register empty flag
CRD
Set to "1"
NCH
Select output format of the TxDi pin
CKPOL
Set to "0"
UFORM
Set to "0"
TE
Set to "1" to enable data transmission
TI
Transfer buffer empty flag
RE
Set to "1" te enable data reception
RI
Reception complete flag
UiIRS
Select what causes the UARTi transmit interrupt to be generated
UiRRM, UiLCH,
Set to "0"
SCLKSTPB
UiSMR
3 to 0
Set to "00002"
ABSCS
Select bus conflict detect sampling timing
ACSE
Set to "1" to automatically clear the transmit enable bit
SSS
Select transmit start condition
SCLKDIV
Set to "0"
UiSMR2
7 to 0
Set to "0016"
UiSMR3
7 to 0
Set to "0016"
UiSMR4
7 to 0
Set to "0016"
IFSR
IFSR6, IFSR7
Select how the bus conflict interrupt occurs
i=0 to 4
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16. Serial I/O (Special Function)
M32C/80 Group
Table 16.31 Pin Settings in IE Mode (1)
Port
Function
Setting
PS0 Register
P61
PD6 Register
CLK0 input
PS0_1=0
PD6_1=0
CLK0 output
PS0_1=1
–
P62
RxD0 input
PS0_2=0
PD6_2=0
P63
TxD0 output
PS0_3=1
–
P65
CLK1 input
PS0_5=0
PD6_5=0
CLK1 output
PS0_5=1
–
P66
RxD1 input
PS0_6=0
PD6_6=0
P67
TxD1 output
PS0_7=1
–
Table 16.32 Pin Settings (2)
Port
Function
Setting
PS1 Register
P70(1)
TxD2 output
P71(1)
P72
PSL1 Register
PSC Register
PD7 Register
PS1_0=1
PSL1_0=0
PSC_0=0
–
RxD2 input
PS1_1=0
–
–
PD7_1=0
CLK2 input
PS1_2=0
–
–
PD7_2=0
CLK2 output
PS1_2=1
PSL1_2=0
PSC_2=0
–
NOTE:
1. P70 and P71 are ports for the N-channel open drain output.
Table 16.33 Pin Settings (3)
Port
Function
Setting
PS3
P90
Register(1)
PSL3 Register
PSC3 Register
PD9 Register(1)
CLK3 input
PS3_0=0
–
–
PD9_0=0
CLK3 output
PS3_0=1
–
–
–
P91
RxD3 input
PS3_1=0
–
–
PD9_1=0
P92
TxD3 output
PS3_2=1
PSL3_2=0
–
–
P95
CLK4 input
PS3_5=0
PSL3_5=0
–
PD9_5=0
CLK4 output
PS3_5=1
–
–
–
P96
TxD4 output
PS3_6=1
–
PSC3_6=0
–
P97
RxD4 input
PS3_7=0
–
–
PD9_7=0
NOTE:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enabled).
Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction
to set the PD9 and PS3 registers.
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M32C/80 Group
16. Serial I/O (Special Function)
If the output signal level of the TxDi pin (i=0 to 4) differs from the input signal level of the RxDi pin, an
interrupt request is generated.
UART0 and UART3 are assigned software interrupt number 40. UART1 and UART4 are assigned number
41. When using the bus conflict detect function of UART0 or UART3, of UART1 or UART4, set the IFSR6
bit and the IFSR7 bit in the IFSR register accordingly.
When the ABSCS bit in the UiSMR register is set to "0" (rising edge of the transfer clock), it is determined,
on the rising edge of the transfer clock, if the output level of the TxD pin and the input level of the RxD pin
match. When the ABSCS bit is set to "1" (timer Aj underflow), it is determined when the timer Aj (timer A3
in UART0, timer A4 in UART1, timer A0 in UART2, timer A3 in UART3, the timer A4 in UART4) counter
overflows. Use the timer Aj in one-shot timer mode.
When the ACSE bit in the UiSMR register is set to "1" (automatic clear at bus conflict) and the IR bit in the
BCNiIC register to "1" (discrepancy detected), the TE bit in the UiC1 register is set to "0" (transmit disabled).
When the SSS bit in the UiSMR register is set to "1" (synchronized with RxDi), data is transmitted from the
TxDi pin on the falling edge of the RxDi pin. Figure 16.28 shows bits associated with the bus conflict detect
function.
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16. Serial I/O (Special Function)
M32C/80 Group
(1) The ABSCS Bit in the UiSMR Register (Bus conflict and sampling clock selected)
(i=0 to 4)
Bus conflict is detected on the rising edge of the transfer clock
when the ABSCS bit is set to "0"
Transfer Clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxDi
RxDi
Trigger signal is applied to the TAjIN pin
Timer Aj
When the ABSCS bit is set to "1", bus conflict is detected when the timer Aj
underflows (in the one-shot timer mode). An interrupt request is generated.
Timer Aj: timer A3 in UART0 or UART3, timer A4 in UART1 or UART4, timer A0 in UART2
(2) The ACSE Bit in the UiSMR Register (Transmit enable bit is automatically cleared)
Transfer Clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxDi
RxDi
IR bit in
BCNilC register
TE bit in
UiC1 register
(3) The SSS bit in the UiSMR Register (Transmit start condition is selected)
When the SSS bit is set to "0", data is transmitted after one transfer clock cycle
if data transmission is enabled.
Transfer Clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
D7
D8
SP
TxDi
transmit enable conditons are met
When the SSS bit is set to "1", data is transmitted on the falling edge of RxDi(1)
CLKi
ST
TxDi
D0
D1
D2
D3
D4
D5
D6
(Note 2)
RxDi
NOTES:
1. Data is transmitted on the falling edge of a signal applied to the RxDi pin when the IOPOL bit is set to "0".
Data is transmitted on the rising edge of a signal applied to the RxDi pin when the IOPOL bit is set to "1".
2. Data transmission condition must be met before the falling edge of the RxDi pin.
Figure 16.28 Bit Function Related Bus Conflict Detection
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16. Serial I/O (Special Function)
M32C/80 Group
16.7 Special Mode 5 (SIM Mode)
In SIM mode, SIM interface devices can communicate in UART mode. Both direct and inverse formats are
available and a low-level ("L") signal output can be provided from the TxDi pin (i=0 to 4) when a parity error
is detected.
Table 16.34 lists specifications of SIM mode. Table 16.35 lists register settings. Tables 16.36 to 16.38 list
pin settings.
Table 16.34 SIM Mode Specifications
Item
Transfer Data Format
Transfer Clock
Specification
• Transfer data: 8-bit UART mode
• One stop bit
• In direct format
• In inverse format
Parity:
Even
Parity:
Odd
Data logic:
Direct
Data logic:
Inverse
Transfer format:
LSB first
Transfer format:
MSB first
• The CKDIR bit in the UiMR register (i=0 to 4) is "0" (internal clock selected):
fj/16(m+1)(1) fj = f1, f8, f2n(2) m : setting value of the UiBRG register, 0016 to FF16
Do not set the CKDIR bit to "1" (external clock selected)
_______
_______
Transmit/Receive Control The CRD bit in the UiC0 register is set to "1" (CTS, RTS function disabled)
Other Setting Items
The UiIRS bit in the UiC1 register is set to "1" (transmission completed)
Transmit Start Condition To start transmitting, the following requirements must be met:
- Set the TE bit in the UiC1 register to "1" (transmit enabled)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
Receive Start Condition To start receiving, the following requirements must be met:
- Set the RE bit in the UiC1 register to "1" (receive enabled)
- Detect the start bit
Interrupt Request
Generation Timing
• While transmitting,
-The UiIRS bit is set to "1" (transmission completed):
when data transmission from the UARTi transfer register is completed
• While receiving,
when data is transferred from the UARTi receive register to the UiRB register (reception completed)
Error Detection
• Overrun error(1)
This error occurs when the eighth bit of the next data is received before reading the
UiRB register
• Framing error
This error occurs when the number of the stop bit set is not detected
• Parity error
This error occurs when the number of "1" in parity bit and character bits differs from
the number set
• Error sum flag
The SUM bit is set to "1" when an overrun error, framing error or parity error occurs
NOTES:
1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit setting in the SiRIC register does not
change to "1" (interrupt requested).
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
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16. Serial I/O (Special Function)
M32C/80 Group
Table 16.35 Register Settings in SIM Mode
Register
UiTB
UiRB
Bit
Function
7 to 0
Set transmit data
7 to 0
Received data can be read
OER, FER,
Error flags
PER, SUM
UiBRG
UiMR
UiC0
UiC1
7 to 0
Set bit rate
SMD2 to SMD0
Set to "1012"
CKDIR
Set to "0"
STPS
Set to "0"
PRY
Set to "1" for direct format or "0" for inverse format
PRYE
Set to "1"
IOPOL
Set to "0"
CLK1, CLK0
Select count source for the UiBRG register
CRS
Disabled because the CRD bit is set to "1"
TXEPT
Transfer register empty flag
CRD
Set to "1"
NCH
Set to "1"
CKPOL
Set to "0"
UFORM
Set to "0" for direct format or "1" for inverse format
TE
Set to "1" to enable data transmission
TI
Transfer buffer empty flag
RE
Set to "1" to enable data reception
RI
Reception complete flag
UiIRS
Set to "1"
UiRRM
Set to "0"
UiLCH
Set to "0" for direct format or "1" for inverse format
UiERE
Set to "1"
UiSMR
7 to 0
Set to "0016"
UiSMR2
7 to 0
Set to "0016"
UiSMR3
7 to 0
Set to "0016"
UiSMR4
7 to 0
Set to "0016"
i=0 to 4
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16. Serial I/O (Special Function)
M32C/80 Group
Table 16.36 Pin Settings in SIM Mode (1)
Port
Function
Setting
PS0 Register
PD6 Register
P62
RxD0 input
PS0_2=0
PD6_2=0
P63
TxD0 output
PS0_3=1
–
P66
RxD1 input
PS0_6=0
PD6_6=0
P67
TxD1 output
PS0_7=1
–
PS1 Register
PSL1 Register
PSC Register
Table 16.37 Pin Settings (2)
Port
Function
Setting
PD7 Register
P70(1)
TxD2 output
PS1_0=1
PSL1_0=0
PSC_0=0
–
P71(1)
RxD2 input
PS1_1=0
–
–
PD7_1=0
PSC3 Register
PD9 Register(1)
NOTE:
1. P70 and P71 are ports for the N-channel open drain output.
Table 16.38 Pin Settings (3)
Port
Function
Setting
PS3
Register(1)
PS3_1=0
PSL3 Register
P91
RxD3 input
–
P92
TxD3 output
PS3_2=1
PSL3_2=0
P96
TxD4 output
PS3_6=1
–
P97
RxD4 input
PS3_7=0
–
PD9_1=0
–
PSC3_6=0
–
PD9_7=0
NOTE:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enabled).
Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction
to set the PD9 and PS3 registers.
Figure 16.29 shows an example of a SIM interface operation. Figure 16.30 shows an example of a SIM
interface connection. Connect the TxDi pin to the RxDi pin for a pull-up.
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16. Serial I/O (Special Function)
M32C/80 Group
(1) Transmit Timing
Tc
Transfer Clock
TE bit in the UiC1
register
TI bit in the UiC1
register
"1"
Data is written to
the UiTB register
"0"
"0"
Parity Stop
bit
bit
Start
bit
TxDi
ST D0 D1
D2 D3 D4 D5 D6 D7
P
Data is transferred from the UiTB
register to the UARTi transmit
register
ST D0 D1 D2 D3 D4 D5 D6 D7
SP
Parity Error Signal
returned from
Receiving End
P
SP
An "L" signal is applied from the SIM
card due to a parity error
Signal Line Level(2)
TXEPT bit in the
UiC0 register
(Note 1)
"1"
ST D0 D1 D2 D3 D4 D5 D6 D7
P
ST D0 D1 D2 D3 D4 D5 D6 D7
SP
An interrupt routine
detects "H" or "L"
"1"
SP
P
An interrupt routine detects
"H" or "L"
"0"
IR bit in the SiTIC
register
"1"
"0"
Set to "0" by an interrupt request acknowledgement or by program
i=0 to 4
The above applies under the following conditions:
• The PRYE bit in the UiMR register is set to "1" (parity enabled)
• The STPS bit in the UiMR register is set to "0" (1 stop bit)
• The UiIRS bit in the UiC1 register is set to "1" (interrupt request generated
when transmission completed)
Tc = 16(m+1) / fj
fj: count source frequency of the UiBRG register (f1, f8, f2n(4))
m: setting value of the UiBRG register
(2) Receive Timing
Transfer Clock
RE bit in the UiC1
register
"1"
"0"
Start
bit
Transmit Waveform
from the
Transmitting End
ST D0 D1 D2 D3 D4 D5 D6 D7
Parity Stop
bit
bit
P SP
TxDi
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
TxDi outputs "L" due to
a parity error
Signal Line Level(3)
ST D0 D1 D2 D3 D4 D5 D6 D7
RI bit in the UiC1
register
"1"
IR bit in the
SiRIC register
"1"
P SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
"0"
Read the UiRB register
"0"
Set to "0" by an interrupt request acknowledgement or by program
i=0 to 4
The above applies under the following conditions:
• The PRYE bit in the UiMR register is set to "1" (parity enabled)
• The STPS bit in the UiMR register is set to "0" (1 stop bit)
Tc = 16(m+1) / fj
fj: count source frequency of the UiBRG register (f1, f8, f2n(4))
m: setting value of the UiBRG register
NOTES:
1. Data transmission starts when BRG overflows after a value is set to the UiTB register on the rising edge of the TI bit.
2. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the TxDi
pin and parity error signal from the receiving end, is generated.
3. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the
transmitting end and parity error signal from the TxDi pin, is generated.
4. The CNT3 to CNT0 bits in the TCSPR register selects no division (n=0) or divide-by-2n (n=1 to 15).
Figure 16.29 SIM Interface Operation
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16. Serial I/O (Special Function)
M32C/80 Group
Microcomputer
SIM card
TxDi
RxDi
i=0 to 4
Figure 16.30 SIM Interface Connection
16.7.1 Parity Error Signal
16.7.1.1 Parity Error Signal Output Function
When the UiERE bit in the UiC1 register (i=0 to 4) is set to "1" (output), the parity error signal output
can be provided. The parity error signal output is provided when a parity error is detected upon
receiving data. A low-level ("L") signal output is provided from the TxDi pin in the timing shown in
Figure 16.31. When reading the UiRB register during a parity error output, the PER bit in the UiRB
register is set to "0" (no error occurs) and a high-level ("H") signal output is again provided simultaneously.
16.7.1.2 Parity Error Signal
To determine whether the parity error signal is output, the port that shares a pin with the RxDi pin is
read by using an end-of-transmit interrupt routine.
Transfer Clock
"H"
"L"
RxDi
"H"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
"L"
TxDi
"H"
Hi-Z
"L"
Recieve
Complete Flag
"1"
"0"
NOTE:
1. The above applies to direct format.
(The PRY bit is set to "1", the UFORM bit is set to "0",
and the UiLCH bit is set to "0").
Figure 16.31 Parity Error Signal Output Timing (LSB First)
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REJ09B0271-0100
ST: Start bit
P: Even parity
SP: Stop bit
i=0 to 4
16. Serial I/O (Special Function)
M32C/80 Group
16.7.2 Format
16.7.2.1 Direct Format
Set the PRYE bit in the UiMR register (i=0 to 4) to "1" (parity enabled), the PRY bit to "1" (even
parity), the UFORM bit in the UiC0 register to "0" (LSB first) and the UiLCH bit in the UiC1 register to
"0" (not inversed). When data are transmitted, data set in the UiTB register are transmitted with the
even-numbered parity, starting from D0. When data are received, received data are stored in the
UiRB register, starting from D0. The even-numbered parity determines whether a parity error occurs.
16.7.2.2 Inverse Format
Set the PRYE bit to "1", the PRY bit to "0" (odd parity), the UFORM bit to "1" (MSB first) and the
UiLCH bit to "1" (inversed). When data are transmitted, values set in the UiTB register are logically
inversed and are transmitted with the odd-numbered parity, starting from D7. When data are received, received data are logically inversed to be stored in the UiRB register, starting from D7. The
odd-numbered parity determines whether a parity error occurs.
(1) Direct Format
Transfer Clock
"H"
"L"
TxDi
"H"
D0
D1
D2
D3
D4
D5
D6
D7
D7
D6
D5
D4
D3
D2
D1
D0
"L"
P
P: Even parity
(2) Inverse Format
Transfer Clock
TxDi
"H"
"L"
"H"
"L"
P
P: Odd parity
i=0 to 4
Figure 16.32 SIM Interface Format
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17. A/D Converter
M32C/80 Group
17. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter with a capacitive coupling amplifier.
The result of an A/D conversion is stored into the A/D registers corresponding to selected pins. It is stored
into the AD00 register only when DMAC operating mode is entered.
Table 17.1 lists specifications of the A/D converter. Figure 17.1 shows a block diagram of the
A/D converter. Figures 17.2 to 17.6 show registers associated with the A/D converter.
Table 17.1 A/D Converter Specifications
Item
A/D Conversion Method
Analog Input
Voltage(1)
Specification
Successive approximation (with a capacitive coupling amplifier)
0V to AVCC (VCC1)
Operating Clock, ØAD(2)
fAD, fAD/2, fAD/3, fAD/4, fAD/6, fAD/8
Resolution
8 bits or 10 bits
Operating Mode
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
repeat sweep mode 1
Analog Input Pins(3)
10 pins
8 pins for AN0 to AN7
2 extended input pins (ANEX0 and ANEX1)
A/D Conversion Start Condition
• Software trigger
The ADST bit in the AD0CON0 register is set to "1" (A/D conversion started) by
program
• External trigger (re-trigger is enabled)
__________
When a falling edge is applied to the AD TRG pin after the ADST bit is set to "1" by
program
• Hardware trigger (re-trigger is enabled)
The timer B2 interrupt request of the three-phase motor control timer functions
(after the ICTB2 counter completes counting) is generated after the ADST bit is
set to "1" by program
Conversion Rate Per Pin
• Without the sample and hold function
8-bit resolution : 49 ØAD cycles
10-bit resolution : 59 ØAD cycles
• With the sample and hold function
8-bit resolution : 28 ØAD cycles
10-bit resolution : 33 ØAD cycles
NOTES:
1. Analog input voltage is not affected by the sample and hold function status.
2. ØAD frequency must be under 16 MHz when VCC1=5V.
ØAD frequency must be under 10 MHz when VCC1=3.3V.
Without the sample and hold function, the ØAD frequency is 250 kHz or more.
With the sample and hold function, the ØAD frequency is 1 MHz or more.
3. AVCC=VREF=VCC1, A/D input voltage (for AN0 to AN7, ANEX0, and ANEX1) ≤ VCC1.
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17. A/D Converter
M32C/80 Group
0
ADTRG
1
Timer B2 interrupt request
of the three-phase motor
control timer functions
1
EX TRG0
TRG bit in the
AD0CON0 register
TRG0 bit in the
AD0CON2 register
OPA1 and OPA0 bits in
the AD0CON1 register
P96 ANEX1
P95 ANEX0
1X
X1
01
11
AN0
AN1
AN2
P10
AN3
AN4
AN5
AN6
AN7
000
001
00
010
011
100
101
110
CH2 to CH0 bits in the
the AD0CON0 register
111
AD00 register
Comparator 0
AD01 register
AD02 register
Decoder
AD03 register
AD04 register
AD05 register
AD06 register
AD07 register
AD0CON0 register
Successive
conversion register
Resistor ladder
AD0CON1 register
AD0CON2 register
1
1/3
AD0CON3 register
1/2
1
1
1/2
0
0
CSK2 bit in the AD0CON3 register
CSK0 bit in the AD0CON0 register
CSK1 bit in the AD0CON1 register
Figure 17.1 A/D Converter Block Diagram
Rev. 1.00 Nov. 01, 2005 Page 221 of 330
REJ09B0271-0100
1
0
1/2
fAD
0
ØAD
17. A/D Converter
M32C/80 Group
A/D0 Control Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AD0CON0
Bit
Symbol
Address
039616
After Reset
0016
Bit Name
Function
RW
b2 b1b0
CH0
CH1
Analog Input Pin
Select Bit(2, 3, 6, 7)
CH2
RW
0 0 0: AN0
0 0 1: AN1
0 1 0: AN2
0 1 1: AN3
1 0 0: AN4
1 0 1: AN5
1 1 0: AN6
1 1 1: AN7
RW
RW
b4 b3
MD0
RW
MD1
0 0: One-shot mode
A/D Operating Mode 0 1: Repeat mode
Select Bit 0(2)
1 0: Single sweep mode
1 1: Repeat sweep mode 0 or 1
TRG
Trigger Select Bit
0: Software trigger
1: External trigger, hardware trigger(4)
RW
ADST
A/D Conversion
Start Flag
0: A/D conversion stops
1: A/D conversion starts(4)
RW
CKS0
Frequency Select
Bit
(Note 5)
RW
RW
NOTES:
1. When the AD0CON0 register is rewritten during the A/D conversion, the conversion result is
indeterminate.
2. Analog input pins must be set again after changing an A/D operating mode.
3. The CH2 to CH0 bit settings are enabled in one-shot mode and repeat mode.
4. To set the TRG bit to "1", select the cause of trigger by setting the TRG0 bit in the AD0CON2 register.
Then set the ADST bit to "1" after the TRG bit is set to "1".
5. AD frequency must be under 16 MHz when VCC1=5V.
AD frequency must be under 10 MHz when VCC1=3.3V.
Combination of the CKS0, CKS1 and CKS2 bits selects AD.
The CKS2 Bit in the
AD0CON3 Register
The CKS0 Bit in the
AD0CON0 Register
0
0
1
1
0
The CKS1 Bit in the
AD0CON1 Register
0
1
0
1
0
1
AD
fAD divided by 4
fAD divided
fAD divided
fAD
fAD divided
fAD divided
by 3
by 2
by 8
by 6
6. AVCC=VREF=VCC1, AD input voltage (for AN0 to AN7, ANEX0, ANEX1) ≤ VCC1.
7. Set the PSC_7 bit in the PSC register to "1" to use the P10 pin as an analog input pin.
Figure 17.2 AD0CON0 Register
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17. A/D Converter
M32C/80 Group
A/D0 Control Register 1(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AD0CON1
Bit
Symbol
Address
039716
After Reset
0016
Bit Name
Function
RW
Single sweep mode and repeat sweep mode 0
b1 b0
SCAN0
A/D Sweep Pin
Select Bit(2, 7)
RW
0 0: AN0, AN1
0 1: AN0 to AN3
1 0: AN0 to AN5
1 1: AN0 to AN7
Repeat sweep mode 1(3)
b1 b0
0 0: AN0
0 1: AN0, AN1
1 0: AN0 to AN2
1 1: AN0 to AN3
SCAN1
RW
MD2
A/D Operating
Mode Select Bit 1
0: Any mode other than repeat sweep mode 1
1: Repeat sweep mode 1
RW
BITS
8/10-Bit Mode
Select Bit
0: 8-bit mode
1: 10-bit mode
RW
CKS1
Frequency Select
Bit
(Note 4)
RW
VCUT
VREF Connection
Bit
0: No VREF connection(8)
1: VREF connection
RW
b7 b6
OPA0
OPA1
External Op-Amp
Connection Mode
Bit(5)
0 0: ANEX0 and ANEX1 are not used(6)
0 1: Signal into ANEX0 is A/D converted
1 0: Signal into ANEX1 is A/D converted
1 1: External op-amp connection mode
RW
RW
NOTES:
1. When the AD0CON1 register is rewritten during the A/D conversion, the conversion result is
indeterminate.
2. The SCAN1 and SCAN0 bit settings are disabled in repeat sweep mode 1.
3. This pin is commonly used in the A/D conversion when the MD2 bit is set to "1".
4. Refer to the note for the CKS0 bit in the AD0CON0 register.
5. In one-shot mode and repeat mode, the OPA1 and OPA0 bits can be set to "012" or "102" only. Do not
set the OPA0 and OPA1 bits to "012" or "102" in other modes.
6. To set the OPA1 and OPA0 bits to "002", set the PSL3_5 bit in PSL3 register to "0" (other than
ANEX0) and the PSL3_6 bit to "0" (other than ANEX1).
7. AVCC=VREF=VCC1, AD input voltage (for AN0 to AN7, ANEX0, ANEX1) ≤ VCC1.
8. Do not set the VCUT bit to "0" during the A/D conversion.
VREF is a reference voltage for AD0 only. The VCUT bit setting does not affect the VREF performance
of the D/A converter.
Figure 17.3 AD0CON1 Register
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17. A/D Converter
M32C/80 Group
A/D0 Control Register 2(1)
b7
b6
0 0
b5
b4
b3
b2
b1
b0
0 0
Symbol
Address
AD0CON2
039416
Bit
Symbol
SMP
(b2 - b1)
(b4 - b3)
TRG0
(b7 - b6)
Bit Name
After Reset
XX0X X0002
Function
A/D Conversion
Method Select Bit
0: Without the sample and hold funtion
1: With the sample and hold function
Reserved Bit
Set to "0".
RW
When read, its content is indeterminate.
Rev. 1.00 Nov. 01, 2005 Page 224 of 330
REJ09B0271-0100
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
External Trigger
Request Source
Select Bit
0: Selects ADTRG
1: Selects a timer B2 interrupt request
of the three-phase motor control
timer functions (after the ICTB2
counter completes counting)
Reserved Bit
Set to "0".
RW
When read, its content is indeterminate.
NOTE:
1. When the AD0CON2 register is rewritten during the A/D conversion, the conversion result is
indeterminate.
Figure 17.4 AD0CON2 Register
RW
RW
17. A/D Converter
M32C/80 Group
A/D0 Control Register 3(1, 2)
b7
b6
b5
0 0 0
b4
b3
b2
b1
b0
Symbol
AD0CON3
0
Bit
Symbol
DUS
(b1)
CKS2
(b4 - b3)
(b7 - b5)
Address
039516
After Reset
XXXX X0002
Bit Name
Function
RW
DMAC Operation
Select Bit
0: Disables DMAC operating mode
1: Enables DMAC operating mode(3, 4)
RW
Reserved Bit
Set to "0".
When read, its content is indeterminate.
RW
Frequency Select Bit (Note 5)
RW
Reserved Bit
When read, its content is indeterminate.
RO
Reserved Bit
Set to "0".
When read, its content is indeterminate.
RW
NOTES:
1. When the AD0CON3 register is rewritten during the A/D conversion, the conversion result is
indeterminate.
2. The AD0CON3 register may be read uncorrectly during the A/D conversion. It must be read or written
after the A/D converter stops operating.
3. When the DUS bit is set to "1", the AD00 register stores all A/D conversion results.
4. When the DUS bit is set to "1", set the DMAC.
5. Refer to the note for the CKS0 bit in the AD0CON0 register.
Figure 17.5 AD0CON3 Register
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17. A/D Converter
M32C/80 Group
A/D0 Register i (i =0 to 7)(1, 2, 3, 4, 5)
b15
b8 b7
b0
Symbol
AD00
AD01 to AD03
AD04 to AD06
AD07
Address
038116 - 038016
038316 - 038216, 038516 - 038416, 038716 - 038616
038916 - 038816, 038B16 - 038A16, 038D16 - 038C16
038F16 - 038E16
After Reset
00000000 XXXXXXXX2
Indeterminate
Indeterminate
Indeterminate
Function
RW
8 low-order bits in an A/D conversion result
RO
In 10-bit mode: 2 high-order bits in an A/D conversion result
In 8-bit mode: when read, its content is indeterminate.
RO
When read, its content is indeterminate.
RO
NOTES:
1. In DMAC operating mode, register value read by program is indeterminate.
2. Register value is indeterminate when written while the A/D conversion is stopped.
3. Register value is indeterminate if the next A/D conversion result is stored before reading the register.
4. The AD00 register is available in DMAC operating mode. Other registers are indeterminate.
5. In DMAC operating mode and 10-bit mode, set DMAC for a 16-bit transfer.
Figure 17.6 AD00 to AD07 Registers
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17. A/D Converter
M32C/80 Group
17.1 Mode Description
17.1.1 One-shot Mode
In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table 17.2
lists specifications of one-shot mode.
Table 17.2 One-shot Mode Specifications
Item
Function
Specification
The CH2 to CH0 bits in the AD0CON0 register and the OPA1 and OPA0 bits in the
AD0CON1 register select a pin. Analog voltage applied to the pin is converted to a
digital code once
Start Condition
• When the TRG bit in the AD0CON0 register is set to "0" (software trigger),
the ADST bit in the AD0CON0 register is set to "1" (A/D conversion starts) by
program
• When the TRG bit is set to "1" (external trigger, hardware trigger):
__________
- a falling edge is applied to the AD TRG pin after the ADST bit is set to "1" by
program
- The timer B2 interrupt request of three-phase motor control timer functions
(after the ICTB2 register counter completes counting) is generated after the
ADST bit is set to "1" by program
Stop Condition
• A/D conversion is completed (the ADST bit is set to "0" when the software trigger is
selected)
• The ADST bit is set to "0" (A/D conversion stopped) by program
Interrupt Request Generation Timing A/D conversion is completed
Analog Voltage Input Pins
Select one pin from AN0 to AN7, ANEX0, or ANEX1
Reading of A/D Conversion Result • When the DUS bit in the AD0CON3 register is set to "0" (DMAC operating
mode disabled), the microcomputer reads the AD0j register (j=0 to 7) corresponding to selected pin
• When the DUS bit is set to "1" (DMAC operating mode enabled), do not read the
AD00 register. A/D conversion result is stored in the AD00 register after the A/D
conversion is completed. DMAC transfers the conversion result to any memory
space. Refer to 12. DMAC for DMAC settings
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17. A/D Converter
M32C/80 Group
17.1.2 Repeat Mode
In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table
17.3 lists specifications of repeat mode.
Table 17.3 Repeat Mode Specifications
Item
Function
Specification
The CH2 to CH0 bits in the AD0CON0 register and the OPA1 and OPA0 bits in the
AD0CON1 register select a pin. Analog voltage applied to the pin is repeatedly
converted to a digital code
Start Condition
Same as one-shot mode
Stop Condition
The ADST bit in the AD0CON0 register is set to "0" (A/D conversion stopped) by
program
Interrupt Request Generation Timing • When the DUS bit in the AD0CON3 register is set to "0" (DMAC operating
mode disabled), no interrupt request is generated.
• When DUS bit is set to "1" (DMAC operating mode enabled), an interrupt request
is generated every time an A/D conversion is completed.
Analog Voltage Input Pins
Select one pin from AN0 to AN7, ANEX0, or ANEX1
Reading of A/D Conversion Result • When the DUS bit is set to "0", the microcomputer reads the AD0j register (j=0 to
7) corresponding to the selected pin.
• When DUS bit is set to "1", do not read the AD00 register. A/D conversion result
is stored in the AD00 register after the A/D conversion is completed. DMAC
transfers the conversion result to any memory space.
Refer to 12. DMAC for DMAC settings
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17. A/D Converter
M32C/80 Group
17.1.3 Single Sweep Mode
In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital
code. Table 17.4 lists specifications of single sweep mode.
Table 17.4 Single Sweep Mode Specifications
Item
Function
Specification
The SCAN1 and SCAN0 bits in the AD0CON1 register select pins. Analog voltage
applied to the pin is converted one-by-one to a digital code
Start Condition
Same as one-shot mode
Stop Condition
Same as one-shot mode
Interrupt Request Generation Timing • When the DUS bit in the AD0CON3 register is set to "0" (DMAC operating
mode disabled), an interrupt request is generated after a sweep is completed.
• When DUS bit is set to "1" (DMAC operating mode enabled), an interrupt
request is generated every time an A/D conversion is completed
Analog Voltage Input Pins
Select from AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins) or AN0
to AN7 (8 pins)
Reading of A/D Conversion Result • When the DUS bit is set to "0", the microcomputer reads the AD0j register (j=0 to
7) corresponding to selected pins
• When DUS bit is set to "1", do not read the AD00 register. A/D conversion result
is stored in the AD00 register after the A/D conversion is completed. DMAC
transfers the conversion result to any memory space. Refer to 12. DMAC for
DMAC settings
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17. A/D Converter
M32C/80 Group
17.1.4 Repeat Sweep Mode 0
In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code.
Table 17.5 lists specifications of repeat sweep mode 0.
Table 17.5 Repeat Sweep Mode 0 Specifications
Item
Specification
Function
The SCAN1 and SCAN0 bits in the AD0CON1 register select pins. Analog voltage
Start Condition
Same as one-shot mode
Stop Condition
The ADST bit in the AD0CON0 register is set to "0" (A/D conversion stopped) by
applied to the pins is repeatedly converted to a digital code
program
Interrupt Request Generation Timing • When the DUS bit in the AD0CON3 register is set to "0" (DMAC operating mode
disabled), no interrupt request is generated
• When DUS bit is set to "1" (DMAC operating mode enabled), an interrupt request
is generated every time an A/D conversion is completed
Analog Voltage Input Pins
Select from AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins) or AN0
to AN7 (8 pins)
Reading of A/D Conversion Result • When the DUS bit is set to "0", the microcomputer reads the AD0j register (j=0 to
7) corresponding to selected pins
• When the DUS bit is set to "1", do not read the AD00 register. A/D conversion
result is stored in the AD00 register after the A/D conversion is completed.
DMAC transfers the conversion result to any memory space. Refer to 12. DMAC
for DMAC settings
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17. A/D Converter
M32C/80 Group
17.1.5 Repeat Sweep Mode 1
In repeat sweep mode 1, analog voltage selectively applied to eight pins is repeatedly converted to a
digital code. Table 17.6 lists specifications of repeat sweep mode 1.
Table 17.6 Repeat Sweep Mode 1 Specifications
Item
Function
Specification
The SCAN1 and SCAN0 bits in the AD0CON1 register select 8 pins. Analog voltage selectively applied to 8 pins is repeatedly converted to a digital code
e.g., When ANi0 is selected (i =none, 0, 2, 15), analog voltage is converted to a
digital code in the following order:
AN0
AN1
AN0
AN2
AN0
AN3 ....... etc.
Start Condition
Same as one-shot mode (Any trigger generated during an A/D conversion is invalid)
Stop Condition
The ADST bit is set to "0" (A/D conversion stopped) by program
Interrupt Request Generation Timing • When the DUS bit in the AD0CON3 register is set to "0" (DMAC operating
mode disabled), no interrupt request is generated
• When DUS bit is set to "1" (DMAC operating mode enabled), an interrupt request
is generated every time an A/D conversion is completed
Analog Voltage Input Pins
AN0 to AN7 (8 pins)
Prioritized Pins
AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins) or AN0 to AN3 (4 pins)
Reading of A/D Conversion Result • When the DUS bit is set to "0", the microcomputer reads the AD0j register (j=0 to
7) corresponding to selected pins
• When the DUS bit is set to "1", do not read the AD00 register. A/D conversion
result is stored in the AD00 register after the A/D conversion is completed.
DMAC transfers the conversion result to any memory space. Refer to 12. DMAC
for DMAC settings
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17. A/D Converter
M32C/80 Group
17.2 Functions
17.2.1 Resolution Select Function
The BITS bit in the AD0CON1 register determines the resolution. When the BITS bit is set to "1" (10-bit
precision), the A/D conversion result is stored into bits 9 to 0 in the AD0j register (j = 0 to 7). When the
BITS bit is set to "0" (8-bit precision), the A/D conversion result is stored into bits 7 to 0 in the AD0j
register.
17.2.2 Sample and Hold Function
When the SMP bit in the AD0CON2 register is set to "1" (with the sample and hold function), A/D conversion rate per pin increases to 28 ØAD cycles for 8-bit resolution and 33 ØAD cycles for 10-bit resolution.
The sample and hold function is available in all operating modes. Start the A/D conversion after selecting
whether the sample and hold function is to be used or not.
17.2.3 Trigger Select Function
The TRG bit in the AD0CON0 register and the TRG0 bit in the AD0CON2 register select the trigger to
start the A/D conversion. Table 17.9 lists settings of the trigger select function.
Table 17.9 Trigger Select Function Settings
Bit and Setting
AD0CON0 Register
TRG = 0
Trigger
AD0CON2 Register
-
Software trigger
The A/D0 starts the A/D conversion when the ADST bit in the
AD0CON0 register is set to "1"
TRG = 1(1)
TRG0 = 0
External trigger(2)
__________
Falling edge of a signal applied to ADTRG
TRG0 = 1
Hardware trigger(2)
The timer B2 interrupt request of three-phase motor control timer
functions (after the ICTB2 counter completes counting)
NOTES:
1. A/D0 starts the A/D conversion when the ADST bit is set to "1" (A/D conversion started) and a trigger is generated.
2. The A/D conversion is restarted if an external trigger or a hardware trigger is inserted during the A/D conversion.
(The A/D conversion in process is aborted.)
17.2.4 DMAC Operating Mode
DMAC operating mode is available with all operating modes. When the A/D converter is in multi-port
single sweep mode or multi-port repeat sweep mode 0, the DMAC operating mode must be used. When
the DUS bit in the AD0CON3 register is set to "1" (DMAC operating mode enabled), all A/D conversion
results are stored into the AD00 register. DMAC transfers data from the AD00 register to any memory
space every time an A/D conversion is completed in each pin. 8-bit DMA transfer must be selected for 8bit resolution and 16-bit DMA transfer for 10-bit resolution. Refer to 12. DMAC for instructions.
Rev. 1.00 Nov. 01, 2005 Page 232 of 330
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17. A/D Converter
M32C/80 Group
17.2.5 Extended Analog Input Pins
In one-shot mode and repeat mode, the ANEX0 and ANEX1 pins can be used as analog input pins. The
OPA1 and OPA0 bits in the AD0CON1 register select which pins to use as analog input pins. An A/D
conversion result for the ANEX0 pin is stored into the AD00 register. The result for the ANEX1 pin is
stored into the AD01 register, but is stored into the AD00 register when the DUS bit in the AD0CON3
register is set to "1" (DMAC operating mode enabled).
17.2.6 External Operating Amplifier (Op-Amp) Connection Mode
In external op-amp connection mode, multiple analog voltage can be amplified by one external op-amp
using extended analog input pins ANEX0 and ANEX1.
When the OPA1 and OPA0 bits in the AD0CON1 register are set to "112" (external op-amp connection),
voltage applied to the AN0 to AN7 pins are output from ANEX0. Amplify this output signal by an external
op-amp and apply it to ANEX1.
Analog voltage applied to ANEX1 is converted to a digital code and the A/D conversion result is stored
into the corresponding AD0j register (j=0 to 7). A/D conversion rate varies depending on the response of
the external op-amp. The ANEX0 pin cannot be connected to the ANEX1 pin directly.
Figure 17.7 shows an example of an external op-amp connection.
Table 17.10 Extended Analog Input Pin Settings
AD0CON1 Register
OPA1 Bit
ANEX0 Function
ANEX1 Function
OPA0 Bit
0
0
Not used
Not used
0
1
P95 as an analog input
Not used
1
0
Not used
P96 as an analog input
1
1
Output to an external op-amp
Input from an external op-amp
Analog
input
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Resistor ladder
Successive conversion register
ANEX0
ANEX1
External op-amp
Figure 17.7 External Op-Amp Connection
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Comparator 0
17. A/D Converter
M32C/80 Group
17.2.7 Power Consumption Reducing Function
When the A/D converter is not used, the VCUT bit in the AD0CON1 register isolates the resistor ladder of
the A/D converter from the reference voltage input pin (VREF). Power consumption is reduced by shutting
off any current flow into the resistor ladder from the VREF pin.
When using the A/D converter, set the VCUT bit to "1" (VREF connection) before setting the ADST bit in
the AD0CON0 register to "1" (A/D conversion started). Do not set the ADST bit and VCUT bit to "1"
simultaneously, nor set the VCUT bit to "0" (no VREF connection) during the A/D conversion. The VCUT
bit does not affect the VREF performance of the D/A converter.
17.2.8 Output Impedance of Sensor Equivalent Circuit under A/D Conversion
For perfect A/D converter performance, complete internal capacitor (C) charging, shown in Figure 17.8,
for the specified period (T) as sampling time. Output Impedance of the sensor equivalent circuit (R0) is
determined by the following equations:
VC = VIN {1 – e
When t = T, VC = VIN –
e
–
–
1
X
Y
T
C (R0 + R)
=
–
1
C (R0 + R)
t
}
VIN = VIN (1 –
X
)
Y
X
Y
X
1
T= ln
C (R0 +R)
Y
T
R0 = –
X
C • ln
Y
–R
where:
VC = Voltage between pins
R = Internal resistance of the microcomputer
X = Precision (error) of the A/D converter
Y = Resolution of the A/D converter (1024 in 10-bit mode, and 256 in 8-bit mode)
Figure 17.8 shows analog input pin and external sensor equivalent circuit. The impedance (R0) can be
obtained if the voltage between pins (VC) changes from 0 to VIN-(0.1/1024) VIN in the time (T), when the
difference between VIN and VC becomes 0.1LSB.
(0.1/1024) means that A/D precision drop, due to insufficient capacitor charge, is held to 0.1LSB at time of A/
D conversion in the 10-bit mode. Actual error, however, is the value of absolute precision added to 0.1LSB.
When ØAD = 10 MHz, T = 0.3 µs in the A/D conversion mode with the sample and hold function. Output
impedance (R0) for sufficiently charging capacitor (C) in the time (T) is determined by the following equation:
Using T = 0.3 µs, R = 7.8 kΩ, C = 1.5 pF, X = 0.1, Y = 1024,
R0 = –
0.3 X 10-6
1.5 X 10 –12 • ln
0.1
–7.8 X103 = 13.9 X 103
1024
Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error)
0.1LSB or less, is approximately 13.9 kΩ maximum.
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17. A/D Converter
M32C/80 Group
Microcopmuter
Sensor equivalent
circuit
R0
R (7.8 kΩ)
VIN
Sampling time
C (1.5 pF)
VC
3
Sample and hold function is enabled : φAD
2
Sample and hold function is disabled : φAD
Figure 17.8 Analog Input Pin and External Sensor Equivalent Circuit
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18. D/A Converter
M32C/80 Group
18. D/A Converter
The D/A converter consists of two separate 8-bit R-2R ladder D/A converters.
Digital code is converted to an analog voltage when a value is written to the corresponding DAi registers
(i=0,1). The DAiE bit in the DACON register determines whether the D/A conversion result output is provided or not. Set the DAiE bit to "1" (output enabled) to disable a pull-up of a corresponding port.
Output analog voltage (V) is calculated from value n (n=decimal) set in the DAi register.
V = VREF x n (n = 0 to 255)
256
VREF : reference voltage (not related to VCUT bit setting in the AD0CON1 register)
Table 18.1 lists specifications of the D/A converter. Table 18.2 lists the DA0 and DA1 pin settings. Figure
18.1 shows a block diagram of the D/A converter. Figure 18.2 shows the D/A control register. Figure 18.3
shows a D/A converter equivalent circuit.
When the D/A converter is not used, set the DAi register to "0016" and the DAiE bit to "0" (output disabled).
Table 18.1 D/A Converter Specifications
Item
D/A Conversion Method
Resolution
Analog Output Pin
Specification
R-2R
8 bits
2 channels
Table 18.2 Pin Settings
Port
Function
Setting
PD9
Register(1)
PS3 Register(1)
PSL3 Register
P93
DA0 output
PD9_3=0
PS3_3=0
PSL3_3=1
P94
DA1 output
PD9_4=0
PS3_4=0
PSL3_4=1
NOTE:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write
enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1"
and the instruction to set the PD9 and PS3 registers.
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18. D/A Converter
M32C/80 Group
AA
AA
Low-Order Bits of Data Bus
DA0 Register
DA0E 0
R-2R Resistor Ladder
A
DA0
1
DA1 Register
DA1E 0
R-2R Resistor Ladder
DA1
1
DA0E, DA1E: Bits in the DACON register
Figure 18.1 D/A Converter
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18. D/A Converter
M32C/80 Group
D/A Control Register
b7
b6
b5
b4
b3
b2
b1
Symbol
DACON
b0
Address
039C16
After Reset
XXXX XX002
Bit
Symbol
Bit Name
DA0E
D/A0 Output Enable Bit
0: Disables an output
1: Enables an output
RW
DA1E
D/A1 Output Enable Bit
0: Disables an output
1: Enables an output
RW
(b7 - b2)
Function
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
D/A Register i (i=0, 1)
b7
b0
Symbol
DA0, DA1
Address
039816, 039A16
After Reset
Indeterminate
Function
Output value of D/A conversion
Setting Range
RW
0016 to FF16
RW
Figure 18.2 DACON Register, DA0 and DA1 Registers
r
DA0E
"0"
R
R
R
R
R
R
R
2R
DA0
"1"
2R
2R
2R
2R
2R
2R
2R
LSB
MSB
D/A register 0
2R
0
1
AVSS
VREF(4)
NOTES:
1. The above applies when the DA0 register is set to "2A16".
2. This circuitry is the same for D/A1.
3. To reduce power consumption when the D/A converter is not used, set the DAiE bit (i=0, 1) to "0"
(output disabled) and the DAi register to "0016" to stop current from flowing into the R-2R resistor.
4. VREF is not related to VCUT bit setting in the AD0CON1 register.
Figure 18.3 D/A Converter Equivalent Circuit
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19. CRC Calculation
M32C/80 Group
19. CRC Calculation
The CRC (Cyclic Redundancy Check) calculation detects an error in data blocks. A generator polynomial
of CRC_CCITT (X16 + X12 + X5 + 1) generates CRC code.
The CRC code is a 16-bit code generated for a block of data of desired length. This block of data is in 8-bit
units.The CRC code is set in the CRCD register every time one-byte data is transferred to the CRCIN
register after a default value is written to the CRCD register. CRC code generation for one-byte data is
completed in two cycles.
Figure 19.1 shows a block diagram of a CRC circuit. Figure 19.2 shows CRC-associated registers. Figure
19.3 shows an example of the CRC calculation.
High-order bits of data bus
AAA
AAAA AAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAA
AAAAAA
Low-order bits of data bus
8 low-order bits
8 highorder bits
CRCD register
CRC code generation circuit
x16 + x12 + x5 + 1
CRCIN register
Figure 19.1 CRC Calculation Block Diagram
CRC Data Register
b15
b8 b7
b0
Symbol
Address
After Reset
CRCD
037D16- 037C16
Indeterminate
Function
Setting Range
RW
After default value is written to the CRCD
register, the CRC code can be read from the
CRCD register by writing data to the CRCIN
register. Bit position of the default value is
inversed. The inversed value is read as the CRC
code.
000016 to FFFF16
RW
CRC Input Register
b7
b0
Symbol
CRCIN
Address
037E16
Function
Data input.
Inverse bit position of data.
Figure 19.2 CRCD Register and CRCIN Register
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REJ09B0271-0100
After Reset
Indeterminate
Setting Range
RW
0016 to FF16
RW
19. CRC Calculation
M32C/80 Group
CRC Calculation and Setup Procedure to Generate CRC Code for "80C416"
CRC Calculation for M32C
value of the CRCIN register with inversed bit position
generator polynomial
CRC Code : a remainder of a division,
Generator Polynomial : X
16
12
+X
5
+ X + 1 (1 0001 0000 0010 00012)
Setting Steps
(1) Inverse a bit position of "80C416" per byte by program
"8016"
"0116", "C416"
"2316"
b15
b0
(2) Set "000016" (default value)
CRCD register
b7
b0
CRCIN register
Bit position of the CRC code for "8016"
(918816) is inversed to "118916", which is
stored into the CRCD register in 3rd cycle.
(3) Set "0116"
b15
b0
CRCD register
118916
b7
b0
CRCIN register
Bit position of the CRC code for "80C416"
(825016) is inversed to "0A4116", which is
stored into the CRCD register in 3rd cycle.
(4) Set "2316"
b15
b0
0A4116
CRCD register
Details of CRC Calculation
As shown in (3) above, bit position of "0116" (000000012) written to the CRCIN register is inversed and becomes
"100000002".
Add "1000 0000 0000 0000 0000 00002", as "100000002" plus 16 digits, to "000016" as the default value of the
CRCD register to perform the modulo-2 division.
1000 1000
Modulo-2 Arithmetic is
data
1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000
calculated on the law below.
1000 1000 0001 0000 1
0+0=0
1000 0001 0000 1000 0
0+1=1
Generator Polynomial
1000 1000 0001 0000 1
1+0=1
1001 0001 1000 1000
1+1=0
-1=1
CRC Code
"0001 0001 1000 10012 (118916)", the remainder "1001 0001 1000 10002 (918816)" with inversed bit position, can
be read from the CRCD register.
When going on to (4) above, "2316 (001000112)" written in the CRCIN register is inversed and becomes
"110001002".
Add "1100 0100 0000 0000 0000 00002", as "110001002" plus 16 digits, to "1001 0001 1000 10002" as a
remainder of (3) left in the CRCD register to perform the modulo-2 division.
"0000 1010 0100 00012 (0A4116)", the remainder with inversed bit position, can be read from CRCD register.
Figure 19.3 CRC Calculation
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20. X/Y Conversion
M32C/80 Group
20. X/Y Conversion
The X/Y conversion rotates a 16 x 16 matrix data by 90 degrees and inverses high-order bits and low-order
bits of a 16-bit data. Figure 20.1 shows the XYC register.
The 16-bit XiR register (i=0 to 15) and 16-bit YjR register (j=0 to 15) are allocated to the same address. The
XiR register is a write-only register, while the YjR register is a read-only register. Access the XiR and YjR
registers from an even address in 16-bit units. Performance cannot be guaranteed if the XiR and YiR
registers are accessed in 8-bit units.
X/Y Control Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
XYC
02E016
Bit
Symbol
After Reset
XXXX XX002
Bit Name
Function
RW
XYC0
Read Mode Set Bit
0: Data is converted
1: No data is converted
RW
XYC1
Write Mode Set Bit
0: Bit alignment is not converted
1: Bit alignment is converted
RW
(b7 - b2)
Figure 20.1 XYC Register
Rev. 1.00 Nov. 01, 2005 Page 241 of 330
REJ09B0271-0100
Noting is assigned. When write, set to "0".
When read, its content is indeterminate.
20. X/Y Conversion
M32C/80 Group
The XYC0 bit in the XYC register determines how to read the YjR register.
By reading the YjR register when the XYC0 bit is set to "0" (data conversion), bit j in the X0R to X15R
registers can be read simultaneously.
For example, bit 0 in the X0R register can be read if reading bit 0 in the Y0R register, bit 0 in the X1R
register if reading bit 1 in the Y0R register..., bit 0 in the X14R register if reading bit 14 in the Y0R register
and bit 0 in the X15R register if reading bit 15 in the Y0R register.
Figure 20.2 shows the conversion table when the XYC0 bit is set to "0". Figure 20.3 shows an example of
the X/Y conversion.
Y15R register
Y14R register
Y13R register
Y12R register
Y11R register
Y10R register
Y9R register
Y8R register
Y7R register
Y6R register
Y5R register
Y4R register
Y3R register
Y2R register
Y1R register
Y0R register
Address to be read
b15
b0
Bits in the YjR register
b0
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
AAA
A
AA
AA
A
AAA
A
AA
b15
Address to
be written
X0R register
X1R register
X2R register
X3R register
X4R register
X5R register
X6R register
X7R register
X8R register
X9R register
X10R register
X11R register
X12R register
X13R register
X14R register
X15R register
Bits in the XiR register
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Figure 20.2 Conversion Table when Setting the XYC0 Bit to "0"
X0R register
X1R register
X2R register
Y0R register
Y1R register
Y2R register
X3R register
X4R register
X5R register
X6R register
X7R register
X8R register
Y3R register
Y4R register
Y5R register
Y6R register
Y7R register
Y8R register
X9R register
X10R register
X11R register
X12R register
X13R register
X14R register
X15R register
Y9R register
Y10R register
Y11R register
Y12R register
Y13R register
Y14R register
Y15R register
Figure 20.3 X/Y Conversion
Rev. 1.00 Nov. 01, 2005 Page 242 of 330
REJ09B0271-0100
AA
AAAAAA
AAAAAA
AA
AA
AA
AAAAAAA
AA
AA
AA AAAA
AA
AA
AA
AA
AA
AAA
AA
A
20. X/Y Conversion
M32C/80 Group
By reading the YjR register when the XYC0 bit in the XYC register is set to "1" (no data conversion), the
value written to the XiR register can be read directly. Figure 20.4 shows the conversion table when the
XYC0 bit is set to "1."
Address to be written
Address to be read
AA
AA
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
X0R register, Y0R register
X1R register, Y1R register
X2R register, Y2R register
X3R register, Y3R register
X4R register, Y4R register
X5R register, Y5R register
X6R register, Y6R register
X7R register, Y7R register
X8R register, Y8R register
X9R register, Y9R register
X10R register, Y10R register
X11R register, Y11R register
X12R register, Y12R register
X13R register, Y13R register
X14R register, Y14R register
X15R register, Y15R register
b15
b0
Bits in the XiR register
Bits in the YjR register
i=0 to 15
j=0 to 15
Figure 20.4 Conversion Table when Setting the XYC0 Bit to "1"
The XYC1 bit in the XYC register selects bit alignment of the value in the XiR register.
By writing to the XiR register while the XYC1 bit is set to "0" (no bit alignment conversion), bit alignment is
written as is. By writing to the XiR register while the XYC1 bit is set to "1" (bit sequence replaced), bit
alignment is written inversed.
Figure 20.5 shows the conversion table when the XYC1 bit is set to "1".
b15
b0
b15
b0
Data to be written
Bits in XiR register
(i=0 to 15)
Figure 20.5 Conversion Table when Setting the XYC1 Bit to "1"
Rev. 1.00 Nov. 01, 2005 Page 243 of 330
REJ09B0271-0100
21. Intelligent I/O
M32C/80 Group
21. Intelligent I/O
The intelligent I/O is a multifunctional I/O port for clock synchronous serial I/O and HDLC data processing.
The intelligent I/O has two sets of two 8-bit shift registers for communications.
Table 21.1 lists functions and channels of the intelligent I/O.
Table 21.1 Intelligent I/O Functions and Channels
Function
Communication
Description
Communication unit 0
Clock Synchronous Serial I/O Mode
Available
HDLC Data Processing Mode
Available
Communication unit 1
Available
Rev. 1.00 Nov. 01, 2005 Page 244 of 330
REJ09B0271-0100
21. Intelligent I/O
M32C/80 Group
Communication Unit 0
ISRxD0 ISCLK0
Transmit Interrupt Request
SIO0TR(1)
CCS1 and CCS0
01
f1
f2n
f8
10
11
G0TB Register
(Transmit Buffer Register)
SOF
Generation Circuit
Transmit
Buffer
Bit Insert Circuit
Transmit
Register
Transmit Latch
Transmission
Transmit Data
Generation Circuit
TXSL
G0TCRC
Register
0
ISTxD0
1
Data
Selector
G0TO Register
Clock Wait
Control Circuit
HDLC Data Transmit
Interrupt Request
G0TOR(1)
Transmit
Register
Transmit
CKDIR Operation
Clock
0
Transmit
Buffer
1
Receive Operation Clock
Reception
Arbitration
Receive Data
Generation Circuit
G0RCRC
Register
G0RI Register
Receive
Buffer
Receive
Register
Data
Selector
Bit Insert Check
0
G0RB Register
Receive Interrupt
Request
SIO0RR(1)
Receive
Buffer
1
RXSL
G0DR Register
(Receive Data Register)
Receive
Register
Shift
Register
Buffer
Register
G0CMP0 register
G0CMP0 register
G0CMP0 register
G0CMP3 Register
Special
Communication
Interrupt Request
SRT0R(1)
Special Interrupt
Check
Comparator
Comparator
Comparator
Comparator
HDLC Data Receive
Interrupt Request
G0RIR(1)
Communication Unit 1
G1TB Register
(Transmit Buffer Register)
SOF
Generation Circuit
Transmit
Buffer
Bit Insert Circuit
Transmit
Register
Transmit Latch
Transmission
TXSL
Transmit
Register
Transmit
Operation
Clock
0
1
CKDIR
ISRxD1
0
Reception
Bit Insert Check
Data
Selector
G1RB Register
Receive
Buffer
1
RXSL
HDLC Data
Transmit
Interrupt Request
G1TOR(1)
Receive Data
Generation Circuit
G1RCRC
Register
G1RI Register
Receive
Register
ISTxD1
Transmit
Buffer
Receive
Operation
Clock
Arbitration
Receive
Buffer
Polarity
Inverse
G1TO Register
10
11
SIO1TR(1)
1
Clock Wait
Control Circuit
ISCLK1
0
Data
Selector
01
Transmit Interrupt
Request
G1TCRC
Register
CCS3 and CCS2
f1
f2n
f8
Transmit Data
Generation Circuit
G1DR Register
(Receive Data Register)
Receive Interrupt
Request
SIO1RR(1)
Receive
Register
Shift
Register
Special Interrupt
Check
Buffer
Register
G1CMP0 Register
G1CMP0
(8bit) Register
G1CMP0
(8bit) Register
(8bit) Register
G1CMP3
Special
Communication
Interrupt Request
SRT1R(1)
Comparator
Comparator
(8bit)
Comparator
(8bit)
(8bit)
Comparator
HDLC Data Receive
Interrupt Request
G1RIR(1)
NOTE:
1. See Figure 10.14.
CKDIR: Bit in the GiMR Register (i=0,1)
TXSL, RXSL: Bits in the GiEMR Register
CCS1 and CCS0: Bits in the CCS Register
Figure 21.1 Intelligent I/O Communication Unit Block Diagram
Rev. 1.00 Nov. 01, 2005 Page 245 of 330
REJ09B0271-0100
21. Intelligent I/O (Communication Function)
M32C/80 Group
21.1 Communication Unit 0 and 1 Communication Function
In the intelligent I/O communication units, 8-bit clock synchronous serial I/O or HDLC data processing is
available.
Figures 21.2 to 21.11 show registers associated with the communication function.
Receive Input Register i (i=0,1)
b7
b0
Symbol
Address
After Reset
G0RI, G1RI
00EC16, 012C16
Indeterminate
Function
Set data to be transmitted to a received
data generation circuit
Setting Range
RW
0016 to FF16
WO
Transmit Output Register i (i=0,1)
b7
b0
Symbol
G0TO, G1TO
Address
00EE16, 012E16
After Reset
Indeterminate
Function
Can read a data transmitted by a transmitted data generation circuit
Figure 21.2 G0RI and G1RI Registers, G0TO and G1TO Registers
Rev. 1.00 Nov. 01, 2005 Page 246 of 330
REJ09B0271-0100
RW
RO
21. Intelligent I/O (Communication Function)
M32C/80 Group
SI/O Communication Control Register i (i=0, 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
Address
After Reset
G0CR, G1CR
00EF16, 012F16
0000 X0112
Bit
Symbol
TI
Bit Name
Transmit Buffer
Empty Flag
Transmit Register
TXEPT
Empty Flag
RI
Receive Complete
Flag
Function
RW
0: Data in the GiTB register
1: No data in the GiTB register
RO
0: Data in the transmit register
(during transmission)
1: No data in the transmit register
(transmit completed)
RO
0: No data in the GiRB register
1: Data in the GiRB register
RO
(b3)
Nothing is assigned. When write, set to "0".
When read, its contents is indeterminate.
TE
Transmit Enable Bit
0: Transmit disabled
1: Transmit enabled
RW
RE
Receive Enable Bit
0: Receive disabled
1: Receive enabled
RW
Reserved Bit
Set to "0"
RW
(b7 - b6)
SI/O Receive Buffer Register i (i=0, 1)
b15
b8 b7
b0
Symbol
G0RB, G1RB
Bit
Symbol
Address
00E916-00E816, 012916-012816
Bit Name
After Reset
XXX0 XXXX XXXX XXXX2
Function
Received data
(b7 - b0)
RW
RW
Nothing is assigned.
(b11 - b8) When read, its content is indeterminate.
OER
Overrun Error Flag
0: No overrun error
1: Overrun error found
Nothing is assigned.
(b15 - b13) When read, its content is indeterminate.
Figure 21.3 G0CR and G1CR Registers, G0RB and G1RB Registers
Rev. 1.00 Nov. 01, 2005 Page 247 of 330
REJ09B0271-0100
RO
21. Intelligent I/O (Communication Function)
M32C/80 Group
SI/O Communication Mode Register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
00ED16
G0MR
0 0 0
Bit
Symbol
Bit Name
CKDIR
(b5 - b3)
UFORM
IRS
Function
b1 b0
GMD0
GMD1
After Reset
0016
Communication Mode
Select Bit
0 1: Clock synchronous serial I/O
mode
1 1: HDLC data processing mode(1)
RW
RW
RW
Internal/External Clock
Select Bit
0: Internal clock
1: External clock
RW
Reserved Bit
Set to "0"
RW
Transfer Format
Select Bit
0: LSB first
1: MSB first
RW
Transmit Interrupt
Source Select Bit
0: No data in the G0TB register
(TI=1)
1: Transmission is completed
(TXEPT=1)
RW
NOTE:
1. Set the GM1 and GM0 bits to "012" or "112" only.
SI/O Communication Mode Register 1
b7
b6
b5
b4
b3
0 0 0
b2
b1
b0
Symbol
Address
012D16
G1MR
Bit
Symbol
Bit Name
CKDIR
(b5 - b3)
UFORM
IRS
Communication Mode
Select Bit
0 1: Clock synchronous serial I/O
mode
1 1: HDLC data processing mode(1)
RW
RW
RW
Internal/External Clock
Select Bit
0: Internal clock
1: External clock
RW
Reserved Bit
Set to "0"
RW
Transfer Format
Select Bit
0: LSB first
1: MSB first
RW
Transmit Interrupt
Source Select Bit
0: No data in the G1TB register
(TI=1)
1: Transmission is completed
(TXEPT=1)
RW
NOTE:
1. Set the GM1 and GM0 bits to "012" or "112" only.
Figure 21.4 G0MR and G1MR Registers
Rev. 1.00 Nov. 01, 2005 Page 248 of 330
REJ09B0271-0100
Function
b1 b0
GMD0
GMD1
After Reset
0016
21. Intelligent I/O (Communication Function)
M32C/80 Group
SI/O Expansion Mode Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
Address
G0EMR
00FC16
Bit
Symbol
After Reset
0016
Bit Name
Function
RW
Reserved Bit
Set to "0"
RW
CRCV
CRC Default Value
Select Bit
0: Set to "000016"
1: Set to "FFFF16"
RW
ACRC
CRC Reset Select Bit
0: Not reset
1: Reset(2)
RW
BSINT
Bit Stuffing Error
Interrupt Select Bit
0: Not used
1: Used
RW
RXSL
Receive Source
Switch Bit
0: ISRxD0 pin
1: G0RI register
RW
TXSL
Transmit Source
Switch Bit
0: ISTxD0 pin
1: G0TO register
RW
(b0)
b7 b6
CRC0
CRC Generation
Polynomial Select Bit
CRC1
0 0: X8+X4+X+1
0 1: Do not set to this value
1 0: X16+X15+X2+1
1 1: X16+X12+X5+1
RW
RW
NOTES:
1. The G0EMR register is used in HDLC data processing mode. Maintain the value after reset or set
it to "0016" in clock synchronous serial I/O mode.
2. CRC is reset when data in the G0CMP3 register matches received data.
SI/O Expansion Mode Register 1(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
G1EMR
Bit
Symbol
Address
013C16
After Reset
0016
Bit Name
Function
RW
SMODE
Synchronous Mode
Select Bit
0: Re-synchronous mode not used
1: Re-synchronous mode
RW
CRCV
CRC Default Value
Select Bit
0: Set to "000016"
1: Set to "FFFF16"
RW
ACRC
CRC Reset Select Bit
0: Not reset
1: Reset(2)
RW
BSINT
Bit Stuffing Error
Interrupt Select Bit
0: Not used
1: Used
RW
RXSL
Receive Source
Switch Bit
0: ISRxD1 pin
1: G1RI register
RW
TXSL
Transmit Source
Switch Bit
0: ISTxD1 pin
1: G1TO register
RW
b7 b6
CRC0
CRC Generation
Polynomial Select bit
CRC1
0 0: X8+X4+X+1
0 1: Do not set to this value
1 0: X16+X15+X2+1
1 1: X16+X12+X5+1
RW
RW
NOTES:
1. The G1EMR register is used in HDLC data processing mode. Maintain the value after reset or set it
to "0016" in clock synchronous serial I/O mode.
2. CRC is reset when data in the G1CMP3 register matches received data.
Figure 21.5 G0EMR and G1EMR Registers
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21. Intelligent I/O (Communication Function)
M32C/80 Group
SI/O Expansion Transmit Control Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0
0
Symbol
G0ETC
Bit
Symbol
Address
00FF16
After Reset
0000 0XXX2
Bit Name
Function
RW
Reserved Bit
Set to "0"
Transmit CRC
Enable Bit
0: Not used
1: Used
RW
Reserved Bit
Set to "0"
RW
TBSF0
Transmit Bit Stuffing "1"
Insert Select Bit
0: "1" is not inserted
1: "1" is inserted
RW
TBSF1
Transmit Bit Stuffing "0"
Insert Select Bit
0: "0" is not inserted
1: "0" is inserted
RW
(b3 - b0)
TCRCE
(b5)
NOTE:
1. The G0ETC register is used in HDLC data processing mode. Maintain the value after reset or set it
to "0016" in clock synchronous serial I/O mode.
SI/O Expansion Transmit Control Register 1(1)
b7
b6
b5
0
b4
b3
0
b2
b1
b0
Symbol
G1ETC
Bit
Symbol
(b2 - b0)
(b3)
TCRCE
(b5)
Address
013F16
After Reset
0000 0XXX2
Bit Name
Reserved Bit
Function
When read,
its content is indeterminate
RW
RO
Reserved Bit
Set to "0"
RW
Transmit CRC
Enable Bit
0: Not used
1: Used
RW
Reserved Bit
Set to "0"
RW
TBSF0
Transmit Bit Stuffing "1" 0: "1" is not inserted
1: "1" is inserted
Insert Select Bit
RW
TBSF1
Transmit Bit Stuffing "0" 0: "0" is not inserted
1: "0" is inserted
Insert Select Bit
RW
NOTE:
1. The G1ETC register is used in HDLC data processing mode. Maintain the value after reset or set it
to "0016" in clock synchronous serial I/O mode.
Figure 21.6 G0ETC and G1ETC Registers
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21. Intelligent I/O (Communication Function)
M32C/80 Group
SI/O Expansion Receive Control Register i (i=0,1)(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
G0ERC, G1ERC
Address
00FD16, 013D16
After Reset
0016
Bit
Symbol
Bit Name
Function
CMP0E
Data Compare
Function 0
Select Bit
CMP1E
Data Compare
Function 1
Select Bit
0: The GiDR register (receive data register) is
not compared with the GiCMP0 register
1: The GiDR register is compared with the
GiCMP0 register
0: The GiDR register (receive data register) is
not compared with the GiCMP1 register
1: The GiDR register is compared with the
GiCMP1 register
CMP2E
Data Compare
Function 2
Select Bit
CMP3E
Data Compare
Function 3
Select Bit
0: The GiDR register (receive data register) is
not compared with the GiCMP2 register
1: The GiDR register is compared with the
GiCMP2 register
0: The GiDR register (receive data register) is
not compared with the GiCMP3 register
1: The GiDR register is compared with the
GiCMP3 register(2)
RCRCE
Receive CRC
Enable Bit
0: Not used
1: Used
RW
0: Receive shift operation disabled
1: Receive shift operation enabled
RW
0: "1" is not deleted
1: "1" is deleted
RW
0: "0" is not deleted
1: "0" is deleted
RW
Receive Shift
Operation
Enable Bit
Receive Bit
RBSF0 Stuffing "1" Delete
Select Bit
Receive Bit
RBSF1 Stuffing "0" Delete
Select Bit
RSHTE
RW
RW
RW
RW
RW
NOTES:
1. The GiERC register is used in HDLC data processing mode.
Set to "0010 00002" in clock synchronous serial I/O mode.
2. Set the CMP3E bit to "1" to set the ACRC bit in the GiEMR register to "1" (CRC reset function used).
Figure 21.7 G0ERC and G1ERC Registers
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21. Intelligent I/O (Communication Function)
M32C/80 Group
SI/O Special Communication Interrupt Detect Register 0 (1, 2)
b7
b6
b5
b4
b3
0
b2
b1
b0
0 0
Symbol
Address
00FE16
G0IRF
Bit
Symbol
Bit Name
After Reset
0016
Function
RW
Reserved Bit
Set to "0"
RW
Bit Stuffing Error
Detect Flag
0: Not detected
1: Detected
RW
Reserved Bit
Set to "0"
RW
IRF0
Interrupt Source
Determination
Flag 0
IRF1
Interrupt Source
Determination
Flag 1
IRF2
Interrupt Source
Determination
Flag 2
IRF3
Interrupt Source
Determination
Flag 3
0: The G0DR register (receive data register)
does not match the G0CMP0 register
1: The G0DR register matches the G0CMP0
register
0: The G0DR register (receive data register)
does not match the G0CMP1 register
1: The G0DR register matches the G0CMP1
register
0: The G0DR register (receive data register)
does not match the G0CMP2 register
1: The G0DR register matches the G0CMP2
register
0: The G0DR register (receive data register)
does not match the G0CMP3 register
1: The G0DR register matches the G0CMP3
register
(b1 - b0)
BSERR
(b3)
RW
RW
RW
RW
NOTES:
1. The G0IRF register is used in HDLC data processing mode. Do not use it in clock synchronous serial
I/O mode.
2. The SRT0R bit in the IIO4IR register is set to "1" if the IRF3 to IRF0 or BSERR bit is set to "1".
Figure 21.8 G0IRF Register
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21. Intelligent I/O (Communication Function)
M32C/80 Group
SI/O Special Communication Interrupt Detect Register 1(1,2)
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
Address
013E16
G1IRF
Bit
Symbol
After Reset
0016
Bit Name
Function
RW
Reserved Bit
Set to "0"
RW
BSERR
Bit Stuffing Error
Detect Flag
0: Not detected
1: Detected
RW
ABT
Arbitration Lost
Detect Flag
0: Not detected
1: Detected
RW
IRF0
Interrupt Source
Determination
Flag 0
IRF1
Interrupt Source
Determination
Flag 1
IRF2
Interrupt Source
Determination
Flag 2
IRF3
Interrupt Source
Determination
Flag 3
0: The G1DR register (receive data register)
does not match the G1CMP0 register
1: The G1DR register (receive data register)
matches the G1CMP0 register
0: The G1DR register (receive data register)
does not match the G1CMP1 register
1: The G1DR register (receive data register)
matches the G1CMP1 register
0: The G1DR register (receive data register)
does not match the G1CMP2 register
1: The G1DR register (receive data register)
matches the G1CMP2 register
0: The G1DR register (receive data register)
does not match the G1CMP3 register
1: The G1DR register (receive data register)
matches the G1CMP3 register
(b1 - b0)
RW
RW
RW
RW
NOTES:
1. The G1IRF register is used in HDLC data processing mode. Maintain the value after reset or set it to
"0016" in clock synchronous serial I/O mode.
2. The SRT1R bit in the IIO4IR register is also set to "1" if the IRF3 to IRF0, BSERR, or ABT bit is set to "1".
Transmit Buffer (Receive Data) Register (i=0,1)
b7
b0
Symbol
G0TB, G0DR
G1TB, G1DR
Address
00EA16
After Reset
Indeterminate
012A16
Indeterminate
Function
RW
Set data to be transmitted.
In HDLC data processing mode, the receive data register is read by
reading the GiTB register. Value is written to the transmit buffer register
by writing it to the GiTB register. In HDLC data processing mode, the
value set in the GiRI register is transferred to the GiDR register.
RW
Figure 21.9 G1IRF Register, G0TB and G1TB / G0DR and G1DR Registers
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21. Intelligent I/O (Communication Function)
M32C/80 Group
Data Compare Register ij (i=0,1, j=0 to 3)
b7
b0
Symbol
Address
After Reset
G0CMP0 to G0CMP3
G1CMP0 to G1CMP3
00F016, 00F116, 00F216, 00F316
013016, 013116, 013216, 013316
Indeterminate
Indeterminate
Function
Setting Range
RW
0016 to FF16
RW
Data to be compared
NOTE:
1. Set the GiMSK0 register to use the GiCMP0 register.
Set the GiMSK1 register to use the GiCMP1 register.
Data Mask Register ij (i=0,1, j=0,1)
b7
b0
Symbol
Address
After Reset
G0MSK0, G0MSK1
G1MSK0, G1MSK1
00F416, 00F516
013416, 013516
Indeterminate
Indeterminate
Function
Setting Range
RW
0016 to FF16
RW
Masked data for received data
Set incomparable bit to "1"
Transmit CRC Code Register i (i=0,1)
b15
b8 b7
b0
Symbol
G0TCRC, G1TCRC
Address
00FB16-00FA16, 013B16-013A16
After Reset
000016
Function
RW
Result of the transmit CRC calculation(1, 2)
RO
NOTES:
1. The calculated result is reset by setting the TE bit in the GiCR register to "0" (transmit disabled).
The CRCV bit in the GiEMR register selects a default value.
2. Transmit CRC calculation is performed with each bit of data transmitted while the TCRCE bit in
the GiETC register is set to "1" (used).
Receive CRC Code Register i (i=0,1)
b15
b8 b7
b0
Symbol
G0RCRC, G1RCRC
Address
00F916-00F816, 013916-013816
After Reset
Indeterminate
Function
RW
Result of the receive CRC calculation(1, 2, 3)
RO
NOTES:
1. The calculated result is reset by setting the RCRCE bit in the GiERC register to "0" (not used).
If the ACRC bit in the GiEMR register is set to "1" (reset), the result is reset by matching data in the
GiCMPj register (j=0 to 3) with the received data.
2. The result is reset to the default value selected by the CRCV bit in the GiEMR register before
reception starts.
3. Receive CRC calculation is performed with every bit of data received while the RCRCE bit in the
GiERC register is set to "1" (used).
Figure 21.10 G0CMP0 to G0CMP3 Registers and G1CMP0 to G1CMP3 Registers
G0MSK0 and G0MSK1 Registers, G1MSK0 and G1MSK1 Registers
G0TCRC and G1TCRC Registers, G0RCRC and G1RCRC Registers
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21. Intelligent I/O (Communication Function)
M32C/80 Group
Communication Clock Select Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
00F616
CCS
Bit
Symbol
After Reset
XXXX 00002
Bit Name
Function
RW
b1b0
CCS0
Communication Unit 0
Clock Select Bit
CCS1
0 0: Clock stopped
0 1: f1(1)
1 0: f2n
1 1: f8
RW
RW
b3b2
CCS2
Communication Unit 1
Clock Select Bit
CCS3
0 0: Clock stopped
0 1: f1(1)
1 0: f2n
1 1: f8
Nothing is assigned. When write, set to "0".
(b7 - b4) When read, its contents is indeterminate.
NOTE:
1. This setting is enabled in HDLC data processing mode. Do not set the CCS1 and CC0 bits or
CCS3 and CCS2 bits to "012" in clock synchronous serial I/O mode.
Figure 21.11 CCS Register
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RW
RW
21. Intelligent I/O (Communication Function)
M32C/80 Group
21.1.1 Clock Synchronous Serial I/O Mode (Communication Units 0 and 1)
In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. f8 or f2n
can be selected as the transfer clock.
Table 21.2 lists specifications of clock synchronous serial I/O mode for the communication units 0 and 1.
Tables 21.3 and 21.4 list clock settings. Table 21.5 lists register settings. Tables 21.6 and 21.7 list pin
settings. Figure 21.12 shows an example of transmit and receive operation.
Table 21.2 Clock Synchronous Serial I/O Mode Specifications (Communication Units 0 and 1)
Item
Specification
Transfer Data Format
Transfer data: 8 bits long
Transfer Clock(1)
Transmit Start Condition
See Tables 21.3 and 21.4
Set registers associated with the waveform generating function, the GiMR and GiERC
registers (i=0,1). Then, set as is written below after at least one transfer clock cycle.
• Set the TE bit in the GiCR register to "1" (transmit enabled)
Receive Start Condition
• Set the TI bit in the GiCR register to "0" (data in the GiTB register)
Set registers associated with the waveform generating function, the GiMR and GiERC
registers. Then, set as is written below after at least one transfer clock cycle.
• Set the RE bit in the GiCR register to "1" (receive enabled)
• Set the TE bit to "1" (transmit enabled)
• Set the TI bit to "0" (data in the GiTB register)
Interrupt Request
• While transmitting, one of the following conditions can be selected to set the SIOiTR
bit to "1" (interrupt requested) (See Figure 10.14):
_
The IRS bit in the GiMR register is set to "0" (no data in the GiTB register) and
data is transferred to the transmit register from the GiTB register
_
The IRS bit is set to "1" (transmission completed) and data transfer from the
transmit register is completed
• While receiving, the following condition can be selected to set SIOiRR bit is set to "1"
(data reception is completed):
Data is transferred from the receive register to the GiRB register (See Figure 10.14)
Error Detection
Selectable Function
Overrun error(2)
This error occurs, when the next data reception is started and the 8th bit of the next
data is received before reading the GiRB register
• LSB first or MSB first
Select either bit 0 or bit 7 to transmit or receive data
NOTES:
1. In clock synchronous serial I/O mode, set the RSHTE bit in the GiERC register (i=0, 1) to "1" (receive
shift operation enabled).
2. When an overrun error occurs, the GiRB register is indeterminate.
The ISTxDi pin outputs a high-level ("H") signal between selecting operating mode and starting transfer.
Table 21.3 Clock Settings (Communication Unit 0)
Transfer Clock
f8
f2n(1)
Input from ISCLK0
G0MR Register
CKDIR Bit
0
0
1
CCS Register
CCS0 Bit
CCS1 Bit
1
1
0
1
-
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
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21. Intelligent I/O (Communication Function)
M32C/80 Group
Table 21.4 Clock Settings (Communication Unit 1)
Transfer Clock
f8
f2n(2)
Input from ISCLK1
G1MR Register
CKDIR Bit
0
0
1
CCS Register
CCS2 Bit
CCS3 Bit
1
1
0
1
-
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Table 21.5 Register Settings in Clock Synchronous Serial I/O Mode
Register
CCS
GiERC
GiMR
GiCR
GiTB
GiRB
Bit
CCS1, CCS0
CCS3, CSS2
7 to 0
GMD1, GMD0
CKDIR
UFORM
IRS
TI
TXEPT
RI
TE
RE
–
–
Function
Communication Unit 1
Communication Unit 0
Setting not required when using the
Select transfer clock
communication unit 1 only
Select transfer clock
Setting not required when using the
Set to "0010 00002"
communication unit 0 only
Set to "012"
Select internal clock or external clock
Select either LSB first or MSB first
Select what cause the transmit interrupt to be generated
Transmit buffer empty flag
Transmit register empty flag
Receive complete flag
Set to "1" to enable transmission and reception
Set to "1" to enable reception
Write data to be transmitted
Received data and error flag are stored
i=0, 1
Table 21.6 Pin Settings in Clock Synchronous Serial I/O Mode (1)
Setting
Port
Function
PS1 Register
PSL1 Register
PSC Register
PSD1 Register
PD7 Register
P73
ISTxD1 Output
PS1_3=1
PSL1_3=0
PSC_3=1
-
-
P74
ISCLK1 Input
PS1_4=0
-
-
-
PD7_4=0
ISCLK1 Output
PS1_4=1
PSL1_4=0
PSC_4=1
-
-
P75
ISRxD1 Input
PS1_5=0
-
-
-
PD7_5=0
P76
ISTxD0 Output
PS1_6=1
PSL1_6=0
PSC_6=0
PSD1_6=0
-
P77
ISCLK0 Input
PS1_7=0
-
-
-
PD7_7=0
ISCLK0 Output
PS1_7=1
PSL1_7=0
-
-
-
Table 21.7 Pin Settings (2)
Setting
Port
P80
Function
ISRxD0 Input
PS2 Register
PD8 Register
PS2_0=0
PD8_0=0
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21. Intelligent I/O (Communication Function)
M32C/80 Group
When f8, f2n or External Clock is Selected as the Communication clock
(Communication Units 0 and 1)
Write to the GiTB register
"1"
f8, f2n or
External Clock "0"
"1"
TE Bit
"0"
Transfer Clock
ISTxDi Pin Output
(transmit data)
Bit 0
Bit 1
Bit 2
Bit 6
Bit7
SIOiTR Bit when IRS=0 "1"
(no data in the
GiTB register)
"0"
SIOiTR Bit when IRS=1 "1"
(transmission
"0"
completed)
Write "0" by program
if setting to "0"
Write "0" by program
if setting to "0"
ISRxDi Pin Input
(received data)
Bit 0
Bit 1
Bit 2
Bit 6
Bit7
"1"
SIOiRR Bit
"0"
Write "0" by program if setting to "0"
The above applies under the following conditions:
• The CKDIR bit in the GiMR register is set to "0" (internal clock)
• The CCS1 and CCS0 bits or the CCS3 and CCS2 bits in the CCS register
are set to "102" or "112"
• The UFORM bit in the GiMR register is set to "0" (LSB first)
Figure 21.12 Transmit and Receive Operation
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SIOiTR bit: Bit in the IIOjIR register (j=1, 3)
SIOiRR bit: Bit in the IIOkIR register (k=0, 2)
IRS bit: Bit in the GiMR register
TE bit: Bit in the GiCR register
i=0, 1
21. Intelligent I/O (Communication Function)
M32C/80 Group
21.1.2 HDLC Data Processing Mode (Communication Units 0 and 1)
In HDLC data processing mode, bit stuffing, flag detection, abort detection and CRC calculation are available
for HDLC control. f1, f8 or f2n can be selected as the transfer clock. No pin is used.
To convert data, data to be transmitted is written to the GiTB register (i=0,1) and the data conversion result is
restored after data conversion. If any data are in the GiTO register after data conversion, the conversion is
terminated. If no data is in the GiTO register, bit stuffing processing is executed regardless of no data available in the transmit output buffer. A CRC value is calculated every time one bit is converted. If no data is in the
GiRI register, received data conversion is terminated.
Table 21.8 list specifications of the HDLC data processing mode. Tables 21.9 and 21.10 list clock settings.
Table 21.11 lists register settings.
Table 21.8 HDLC Processing Mode Specifications (Communication Units 0 and 1)
Item
Specification
Input Data Format
8-bit data fixed, bit alignment is optional
Output Data Format
8-bit data fixed
Transfer Clock
See Tables 21.9 and 21.10
I/O Method
• During transmit data processing,
value set in the GiTB register is converted in HDLC data processing mode and
transferred to the GiTO register.
• During received data processing,
value set in the GiRI register is converted in HDLC data processing mode and
transferred to the GiRB register. The value in the GiRI register is also transferred to
the GiTB register (received data register).
Bit Stuffing
During transmit data processing, "0" following five continuous "1" is inserted.
During received data processing, "0" following five continuous "1" is deleted.
Flag Detection
Write the flag data "7E16" to the GiCMPj register (j=0 to 3) to use the special commu-
Abort Detection
Write the masked data "0116" to the GiMSKj register
CRC
The CRC1 and CRC0 bits are set to "112" (X16+X12+X5+1).
The CRCV bit is set to "1" (set to "FFFF16").
nication interrupt (the SRTiR bit in the IIO4IR register)
• During transmit data processing,
CRC calculation result is stored into the GiTCRC register. The TCRCE bit in the
GiETC register is set to "1" (transmit CRC used).
The CRC calculation result is reset when the TE bit in the GiCR register is set to "0"
(transmit disabled).
• During received data processing,
CRC calculation result is stored into the GiRCRC register. The RCRCE bit in the
GiERC register is set to "1" (receive CRC used).
The CRC calculation result is reset by comparing the flag data "7E16" and matching
the result with the value in the GiCMP3 register. The ACRC bit in the GiEMR register is set to "1" (CRC reset).
Data Processing Start
Condition
The following conditions are required to start transmit data processing:
• The TE bit in the GiCR register is set to "1" (transmit enabled)
• Data is written to the GiTB register
The following conditions are required to start receive data processing:
• The RE bit in the GiCR register is set to "1" (receive enabled)
• Data is written to the GiRI register
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21. Intelligent I/O (Communication Function)
M32C/80 Group
Table 21.8 HDLC Processing Mode Specifications (Continued)
Item
Interrupt
Request(1)
Specification
During transmit data processing,
• One of the following conditions can be selected to set the GiTOR bit in the
_
interrupt request register to "1" (interrupt request) (see Figure 10.14).
When the IRS bit in the GiMR register is set to "0" (no data in the GiTB
register) and data is transferred from the GiTB register to the transmit register (transmit start).
_
When the IRS bit is set to "1" (transmission completed) and data transfer from
the transmit register to the GiTO register is completed.
• When data, which is already converted to HDLC data, is transferred from the
receive register of the GiTO register to the transmit buffer, the GiTOR bit is set
to "1"
During received data processing,
• When data is transferred from the GiRI register to the GiRB register (reception
completed), the GiRIR bit is set to "1" (See Figure 10.14).
• When received data is transferred from the receive buffer of the GiRI register to
the receive register, the GiRIR bit is set to "1".
• When the GiTB register is compared to the GiCMPj register (j=0 to 3), the
SRTiR bit is set to "1".
NOTE:
1. See Figure 10.14 for details on the GiTOR bit, GiRIR bit and SRTiR bit.
Table 21.9 Clock Settings (Communication Unit 0)
Transfer Clock(1)
f1
f8
f2n(2)
CCS Register
CCS0 Bit
CCS1 Bit
1
0
1
1
0
1
NOTES:
1. The transfer clock for reception is generated when the RSHTE bit in the G0ERC register is set to "1"
(receive shift operation enabled).
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Table 21.10 Clock Settings (Communication Unit 1)
Transfer Clock(1)
f1
f8
f2n(2)
CCS Register
CCS2 Bit
CCS3 Bit
1
0
1
1
0
1
NOTES:
1. The transfer clock for reception is generated when the RSHTE bit in the G1ERC register is set to "1"
(receive shift operation enabled).
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
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21. Intelligent I/O (Communication Function)
M32C/80 Group
Table 21.11 Register Settings in HDLC Processing Mode
Register
GiMR
GiEMR
GiCR
GiETC
GiERC
GiIRF
GiCMP0,
GiCMP1
GiCMP2
GiCMP3
GiMSK0,
GiMSK1
GiTCRC
GiRCRC
GiTO
GiRI
GiRB
GiTB
CCS
Bit
GMD1, GMD0
CKDIR
UFORM
IRS
7 to 0
TI
TXEPT
RI
TE
RE
TCRCE
TBSF1, TBSF0
CMP2E to CMP0E
CMP3E
RCRCE
RSHTE
RBSF1, RBSF0
BSERR
IRF3 to IRF0
7 to 0
Function
Set to "112"
Set to "0"
Set to "0"
Select what causes the transmit interrupt to be generated
Set to "1111 01102"
Transmit buffer empty flag
Transmit register empty flag
Receive complete flag
Transmit enable bit
Receive enable bit
Select whether transmit CRC is used or not
Transmit bit stuffing
Select whether received data is compared or not
Set to "1"
Select whether receive CRC is used or not
Set to "1" to use it in the receiver
Receive bit stuffing
Set to "0"
Select what causes an interrupt to be generated
Write "FE16" to abort processing
7 to 0
7 to 0
7 to 0
Data to be compared
Write "7E16"
Write "0116" to abort processing
15 to 0
15 to 0
7 to 0
7 to 0
7 to 0
7 to 0
Transmit CRC calculation result can be read
Receive CRC calculation result can be read
Data, which is output from a transmit data generation circuit, can be read
Set data input to a receive data generation circuit
Received data is stored
For transmission: write data to be transmitted
For reception: received data for comparison is stored
Select the HDLC processing clock
Select the HDLC processing clock
CCS1, CCS0
CCS3, CCS2
i=0, 1
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22. Programmable I/O Ports
22. Programmable I/O Ports
87 programmable I/O ports from ports P0 to P10 (excluding P85) are available. The direction registers
determine each port status, input or output. The pull-up control registers determine whether the ports,
divided into groups of four ports, are pulled up or not. P85 is an input port and no pull-up for this port is
______
______
allowed. The P8_5 bit in the P8 register indicates an NMI input level since P85 shares pins with NMI.
Figures 22.1 to 22.4 show programmable I/O port configurations.
Each pin functions as the programmable I/O port, an I/O pin for internal peripheral functions or the bus
control pin.
To use the pins as input or output pins for internal peripheral functions, refer to the explanations for each
fuction. Refer to 7. Bus when used as the bus control pin.
The registers associated with the programmable I/O ports are as follows.
22.1 Port Pi Direction Register (PDi Register, i=0 to 10)
Figure 22.5 shows the PDi register.
The PDi register selects input or output status of a programmable I/O port. Each bit in the PDi register
corresponds to a port.
In memory expansion and microprocessor mode, the PDi register cannot control pins being used as bus
_____
_______
_______ _______ _____ ________ _______ _____
_________
control pins (A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE/CLKOUT, HLDA/
_________
_______
ALE, HOLD, ALE and RDY). No bit controlling P85 is provided in the direction registers.
22.2 Port Pi Register (Pi Register, i=0 to 10)
Figure 22.6 shows the Pi register.
The Pi register writes and reads data to communicate with external devices. The Pi register consists of a
port latch to hold output data and a circuit to read pin states. Each bit in the Pi register corresponds to a port.
In memory expansion and microprocessor mode, the Pi register cannot control pins being used as bus
_____
_______
_______ _______ _____ ________ _______ _____
_________
control pins (A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE/CLKOUT, HLDA/
_________
_______
ALE, HOLD, ALE and RDY).
22.3 Function Select Register Aj (PSj Register) (j=0 to 3)
Figures 22.7 and 22.8 show the PSj registers.
The PSj register selects either I/O port or peripheral function output if an I/O port shares pins with a peripheral function output (excluding DA0 and DA1.)
When multiple peripheral function outputs are assigned to a pin, set the PSL0 to PSL3, PSC, PSC3, and
PSD1 registers to select which function is used.
Tables 22.3 to 22.10 list peripheral function output control settings for each pin.
22.4 Function Select Register B0 to B3 (PSL0 to PSL3 Registers)
Figures 22.9 and 22.10 show the PSL0 to PSL3 registers.
When multiple peripheral function outputs are assigned to a pin, the PSL0 to PSL3 registers select which
peripheral function output is used.
Refer to 22.10 Analog Input and Other Peripheral Function Input for the PSL3_6 to PSL3_3 bits in the
PSL3 register.
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22. Programmable I/O Ports
22.5 Function Select Register C (PSC and PSC3 Registers)
Figures 22.11 and 22.12 show the PSC and PSC3 registers.
When multiple peripheral function outputs are assigned to a pin, the PSC and PSC3 registers select which
peripheral function output is used.
Refer to 22.10 Analog Input and Other Peripheral Function Input for the PSC_7 bit in the PSC register.
22.6 Function Select Register D (PSD1 Register)
Figure 22.12 shows the PSD1 register.
When multiple peripheral function outputs are assigned to a pin, the PSD1 register selects which peripheral
function output is used.
22.7 Pull-up Control Register 0 to 3 (PUR0 to PUR3 Registers)
Figures 22.13 and 22.14 show the PUR0 to PUR3 registers.
The PUR0 to PUR3 registers select whether the ports, divided into groups of four ports, are pulled up or not.
Ports with bits in the PUR0 to PUR3 registers set to "1" (pull-up) and the direction registers set to "0" (input
mode) are pulled up.
Set bits in the PUR0 and PUR1 registers in ports P0 to P5, running as bus, to "0" (no pull-up) in memory
expansion mode and microprocessor mode. Ports P0, P1 and P40 to P43 can be pulled up when they are
used as input ports in memory expansion mode and microprocessor mode.
22.8 Port Control Register (PCR Register)
Figure 22.14 shows the PCR register.
The PCR register selects either CMOS output or N-channel open drain output as port P1 output format. If
the PCR0 bit is set to "1", N-channel open drain output is selected because the P-channel in the CMOS port
is turned off. This is, however, not a perfect open drain. Therefore, the absolute maximum rating of the
input voltage is between -0.3V and VCC2 + 0.3V.
If P1 is used as a port for data bus in memory expansion mode and microprocessor mode, set the PCR0 bit
to "0". If P1 is used as a port in memory expansion mode and microprocessor mode, the PCR0 bit determines the output format.
22.9 Analog Input and Other Peripheral Function Input
The PSL3_6 to PSL3_3 bits in the PSL3 register and the PSC_7 bit in the PSC register each separate
analog I/O ports from other peripheral functions. Setting the corresponding bit to "1" (analog I/O) to use the
analog I/O port (DA0, DA1, ANEX0, ANEX1, AN4 to AN7) prevents an intermediate potential from being
impressed to other peripheral functions. The impressed intermediate potential may cause increase in
power consumption.
Set the corresponding bit to "0" (except analog I/O) when analog I/O is not used. All peripheral function
inputs except the analog I/O port are available when the corresponding bit is set to "0". These inputs are
indeterminate when the bit is set to "1". When the PSC_7 bit is set to "1", key input interrupt request remains
_____
_____
unchanged regardless of KI0 to KI3 pin input level change.
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22. Programmable I/O Ports
M32C/80 Group
Programmable I/O Ports
Select Pull-up
Direction Register
Port Latch
Data Bus
A
Input to each
Peripheral Function
B
C
Analog Signal
Option
Port
(A)
Hysteresis
P00 to P07
P20 to P27
P30 to P37
P40 to P47
P50 to P52
P54
P55
P56
P57
P83, P84
P86
P87
P100 to P103
P104 to P107
: Available
: Not Available
Figure 22.1 Programmable I/O Ports (1)
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Circuit (B)
Peripheral Function
Input
Circuit (C)
Analog I/F
22. Programmable I/O Ports
M32C/80 Group
Programmable I/O Ports with the Port Control Register
Select Pull-up
Direction Register
PCR Register
Port Latch
Data Bus
A
Input to each
Peripheral Function
Option
Port
B
Circuit (B)
Peripheral Function
Input
(A)
Hysteresis
P10 to P14
P15 to P17
: Available
: Not Available
Programmable I/O Ports with the Function Select Register
Write Signal to INV03
Value Written to INV03
INV03
T Q
D
R
RESET
NMI
INV05
INV02
Select Pull-up
PS1 and PS2
Registers
Direction Register
Output from each
Peripheral Function
Data Bus
Port Latch
Input to each
Peripheral Function
Port: P72 to P75, P80, P81
Figure 22.2 Programmable I/O Ports (2)
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REJ09B0271-0100
22. Programmable I/O Ports
M32C/80 Group
Programmable I/O ports with the Function Select Register
Select Pull-up
D
PS0 to PS9
Registers
Direction Register
Output from each
Peripheral Function
Data Bus
Port Latch
A
Input to each
Peripheral Function
B
C
Analog Signal
Option
Port
(A)
Hysteresis
Circuit (B)
Peripheral Function
Input
P53
P60 to P67
P70, P71
(1)
P76, P77
P82
P90 to P92
P93 to P96
P97
: Available
: Not Available
NOTE:
1. P70 and P71 are ports for the N-channel open drain output.
Figure 22.3 Programmable I/O Ports (3)
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Circuit (C)
Analog I/F
Circuit (D)
22. Programmable I/O Ports
M32C/80 Group
Input Port (P85)
Data Bus
NMI
Figure 22.4 Programmable I/O Ports (4)
Port Pi Direction Register
b7
b6
b5
b4
b3
b2
b1
b0
(i=0 to 10) (2)
Symbol
PD0 to PD3
PD4 to PD7
Address
03E216, 03E316, 03E616, 03E716
03EA16, 03EB16, 03C216, 03C316
After Reset
0016
0016
PD8
PD9, PD10
03C616(3)
03C716(1), 03CA16
00X0 00002
0016
Bit
Symbol
Bit Name
Function
RW
PDi_0
Port Pi0 Direction
Bit
0: Input mode (Functions as input port)
1: Output mode (Functions as output port) RW
PDi_1
Port Pi1 Direction
Bit
0: Input mode (Functions as input port)
RW
1: Output mode (Functions as output port)
PDi_2
Port Pi2 Direction
Bit
0: Input mode (Functions as input port)
RW
1: Output mode (Functions as output port)
PDi_3
Port Pi3 Direction
Bit
0: Input mode (Functions as input port)
RW
1: Output mode (Functions as output port)
PDi_4
Port Pi4 Direction
Bit
0: Input mode (Functions as input port)
RW
1: Output mode (Functions as output port)
PDi_5
Port Pi5 Direction
Bit
0: Input mode (Functions as input port)
1: Output mode (Functions as output port) RW
PDi_6
Port Pi6 Direction
Bit
0: Input mode (Functions as input port)
RW
1: Output mode (Functions as output port)
PDi_7
Port Pi7 Direction
Bit
0: Input mode (Functions as input port)
1: Output mode (Functions as output port)
RW
NOTES:
1. Set the PD9 register immediately after the PRC2 bit in the PRCR register is set to "1" (write enabled).
Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and
the instruction to set the PD9 register.
2. In memory expansion mode and microprocessor mode, the PDi register cannot control pins being
used as bus control pins (A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/WR, WRH/BHE,
BCLK/ALE/CLKOUT, RD, HLDA/ALE, HOLD, ALE and RDY).
3. Nothing is assigned in the PD8_5 bit in the PD8 register.
If write, set these bits to "0". When read, their contents are indeterminate.
Figure 22.5 PD0 to PD10 Registers
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22. Programmable I/O Ports
M32C/80 Group
Port Pi Register (i=0 to 10)(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
P0 to P5
P6 to P10
Bit
Symbol
Address
03E016, 03E116, 03E416, 03E516, 03E816, 03E916
03C016, 03C116(2), 03C416(3), 03C516, 03C816
After Reset
Indeterminate
Indeterminate
Function
Bit Name
RW
Pi_0
Port Pi0 Bit
RW
Pi_1
Port Pi1 Bit
RW
Pi_2
Port Pi2 Bit
Pi_3
Port Pi3 Bit
Pi_4
Port Pi4 Bit
Pin levels can be read by reading
bits corresponding to programmable
ports in input mode.
Pin levels can be controlled by
writing to bits corresponding to
programmable ports in output mode.
RW
RW
RW
0: "L" level
1: "H" level
Pi_5
Port Pi5 Bit
Pi_6
Port Pi6 Bit
RW
Pi_7
Port Pi7 Bit
RW
RW
NOTES:
1. In memory expansion mode and microprocessor mode, the Pi register cannot control pins being used
as bus control pins (A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/WR, WRH/BHE, RD,
BCLK/ALE/CLKOUT, HLDA/ALE, HOLD, ALE and RDY).
2. P70 and P71 are ports for the N-channel open drain output. The pins go into high-impedance states
when P70 and P71 output "H" signal.
3. The P8_5 bit is for read only.
Figure 22.6 P0 to P10 Registers
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22. Programmable I/O Ports
M32C/80 Group
Function Select Register A0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PS0
Bit
Symbol
Address
03B016
After Reset
0016
Bit Name
Function
RW
PS0_0
Port P60 Output
Function Select Bit
0: I/O port
1: RTS0
RW
PS0_1
Port P61 Output
Function Select Bit
0: I/O port
1: CLK0 output
RW
PS0_2
Port P62 Output
Function Select Bit
0: I/O port
1: Selected by the PSL0_2 bit
RW
PS0_3
Port P63 Output
Function Select Bit
0: I/O port
1: TXD0/SDA0 output
RW
PS0_4
Port P64 Output
Function Select Bit
0: I/O port
1: Selected by the PSL0_4 bit
RW
PS0_5
Port P65 Output
Function Select Bit
0: I/O port
1: CLK1 output
RW
PS0_6
Port P66 Output
Function Select Bit
0: I/O port
1: Selected by the PSL0_6 bit
RW
PS0_7
Port P67 Output
Function Select Bit
0: I/O port
1: TXD1/SDA1 output
RW
Function Select Register A1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PS1
Address
03B116
After Reset
0016
Bit
Symbol
Bit Name
PS1_0
Port P70 Output
Function Select Bit
0: I/O port
1: Selected by the PSL1_0 bit
RW
PS1_1
Port P71 Output
Function Select Bit
0: I/O port
1: Selected by the PSL1_1 bit
RW
PS1_2
Port P72 Output
Function Select Bit
0: I/O port
1: Selected by the PSL1_2 bit
RW
PS1_3
Port P73 Output
Function Select Bit
0: I/O port
1: Selected by the PSL1_3 bit
RW
PS1_4
Port P74 Output
Function Select Bit
0: I/O port
1: Selected by the PSL1_4 bit
RW
PS1_5
Port P75 Output
Function Select Bit
0: I/O port
1: Selected by the PSL1_5 bit
RW
PS1_6
Port P76 Output
Function Select Bit
0: I/O port
1: Selected by the PSL1_6 bit
RW
PS1_7
Port P77 Output
Function Select Bit
0: I/O port
1: Selected by the PSL1_7 bit
RW
Figure 22.7 PS0 Register and PS1 Register
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REJ09B0271-0100
Function
RW
22. Programmable I/O Ports
M32C/80 Group
Function Select Register A2
b7
b6
b5
0 0
b4
b3
b2
b1
b0
0 0
Symbol
Address
PS2
03B416
After Reset
00X0 00002
Bit
Symbol
Bit Name
PS2_0
Port P80 Output
Function Select Bit
0: I/O port
1: Selected by the PSL2_0 bit
RW
PS2_1
Port P81 Output
Function Select Bit
0: I/O port
1: Selected by the PSL2_1 bit
RW
PS2_2
Port P82 Output
Function Select Bit
0: I/O port
1: Selected by the PSL2_2 bit
RW
Reserved Bit
Set to "0"
RW
(b4 - b3)
Function
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b5)
Reserved Bit
(b7 - b6)
RW
Set to "0"
Function Select Register A3(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PS3
Bit
Symbol
Address
03B516
After Reset
0016
Bit Name
Function
RW
PS3_0
Port P90 Output
Function Select Bit
0: I/O port
1: CLK3 output
RW
PS3_1
Port P91 Output
Function Select Bit
0: I/O port
1: Selected by the PSL3_1 bit
RW
PS3_2
Port P92 Output
Function Select Bit
0: I/O port
1: Selected by the PSL3_2 bit
RW
PS3_3
Port P93 Output
Function Select Bit
0: I/O port
1: RTS3
RW
PS3_4
Port P94 Output
Function Select Bit
0: I/O port
1: RTS4
RW
PS3_5
Port P95 Output
Function Select Bit
0: I/O port
1: CLK4 output
RW
PS3_6
Port P96 Output
Function Select Bit
0: I/O port
1: Selected by the PSC3_6 bit
RW
PS3_7
Port P97 Output
Function Select Bit
0: I/O port
1: Selected by the PSL3_7 bit
RW
NOTE:
1. Set the PS3 register immediately after the PRC2 bit in the PRCR register is set to "1" (write enabled).
Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1"
and the instruction to set the PS3 register.
Figure 22.8 PS2 Register and PS3 Register
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22. Programmable I/O Ports
M32C/80 Group
Function Select Register B0
b7
b6
0
b5
b4
0
b3
b2
0
b1
b0
0
0
Symbol
PSL0
Bit
Symbol
(b1 - b0)
PSL0_2
Address
03B216
After Reset
0016
Bit Name
Reserved Bit
Function
Set to "0"
RW
Port P62 Output Peripheral 0: SCL0 output
Function Select Bit
1: STXD0
RW
Reserved Bit
RW
Set to "0"
(b3)
PSL0_4
(b5)
PSL0_6
(b7)
RW
Port P64 Output Peripheral 0: RTS1
Function Select Bit
1: Do not set to this value
RW
Reserved Bit
RW
Set to "0"
Port P66 Output Peripheral 0: SCL1 output
Function Select Bit
1: STXD1
RW
Reserved Bit
RW
Set to "0"
Function Select Register B1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PSL1
Bit
Symbol
Address
03B316
Bit Name
After Reset
0016
Function
RW
PSL1_0
Port P70 Output Peripheral 0: Selected by the PSC_0 bit
Function Select Bit
1: TA0OUT output(1)
RW
PSL1_1
Port P71 Output Peripheral 0: Selected by the PSC_1 bit
1: STXD2(1)
Function Select Bit
RW
PSL1_2
Port P72 Output Peripheral 0: Selected by the PSC_2 bit
Function Select Bit
1: TA1OUT output(1)
RW
PSL1_3
Port P73 Output Peripheral 0: Selected by the PSC_3 bit
Function Select Bit
1: V(1)
RW
PSL1_4
Port P74 Output Peripheral 0: Selected by the PSC_4 bit
Function Select Bit
1: W(1)
RW
PSL1_5
Port P75 Output Peripheral 0: W
Function Select Bit
1: Do not set to this value
RW
PSL1_6
Port P76 Output Peripheral 0: Selected by the PSC_6 bit
Function Select Bit
1: TA3OUT output(1)
RW
PSL1_7
Port P77 Output Peripheral 0: ISCLK0 output
1: Do not set to this value
Function Select Bit
RW
NOTE:
1. When setting the PSL1_i (i=0 to 4, 6) bit to "1", set the corresponding PSC_i bit in the PSC register
to "0".
Figure 22.9 PSL0 Register and PSL1 Register
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REJ09B0271-0100
22. Programmable I/O Ports
M32C/80 Group
Function Select Register B2
b7
b6
b5
0 0
b4
b3
0
0 0
b2
b1
b0
Symbol
PSL2
Bit
Symbol
Address
03B616
After Reset
00X0 00002
Function
Bit Name
RW
PSL2_0
Port P80 Output Peripheral 0: TA4OUT output
Function Select Bit
1: U
RW
PSL2_1
Port P81 Output Peripheral 0: U
Function Select Bit
1: Do not set to this value
RW
Reserved Bit
RW
(b4 - b2)
(b5)
(b7 - b6)
Set to "0"
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Reserved Bit
Set to "0"
RW
Function Select Register B3
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
PSL3
Bit
Symbol
(b0)
Address
03B716
After Reset
0016
Bit Name
Reserved Bit
Function
Set to "0"
RW
RW
PSL3_1
Port P91 Output Peripheral 0: SCL3 output
1: STxD3
Function Select Bit
RW
PSL3_2
Port P92 Output Peripheral 0: TxD3/SDA3 output
Function Select Bit
1: Do not set to this value
RW
PSL3_3
Port P93 Output Peripheral 0: Except DA0
1: DA0(1)
Function Select Bit
RW
PSL3_4
Port P94 Output Peripheral 0: Except DA1
Function Select Bit
1: DA1(1)
RW
PSL3_5
Port P95 Output Peripheral 0: Except ANEX0
1: ANEX0(1)
Function Select Bit
RW
PSL3_6
Port P96 Output Peripheral 0: Except ANEX1
Function Select Bit
1: ANEX1(1)
RW
PSL3_7
Port P97 Output Peripheral 0: SCL4 output
Function Select Bit
1: STxD4
RW
NOTE:
1. Although DA0, DA1, ANEX0 and ANEX1 can be used when this bit is set to "0", power consumption
may increase.
Figure 22.10 PSL2 Register and PSL3 Register
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22. Programmable I/O Ports
M32C/80 Group
Function Select Register C
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PSC
Bit
Symbol
Address
03AF16
After Reset
00X0 00002
Bit Name
Function
RW
PSC_0
Port P70 Output Peripheral 0: TxD2/SDA2 output
Function Select Bit
1: Selected by the PSD1_0 bit
RW
PSC_1
Port P71 Output Peripheral 0: SCL2 output
Function Select Bit
1: Do not set to this value
RW
PSC_2
Port P72 Output Peripheral 0: CLK2 output
Function Select Bit
1: V
RW
PSC_3
Port P73 Output Peripheral 0: RTS2
Function Select Bit
1: ISTxD1
RW
PSC_4
Port P74 Output Peripheral 0: TA2OUT output
Function Select Bit
1: ISCLK1
RW
(b5)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
PSC_6
Port P76 Output Peripheral 0: Selected by the PSD1_6 bit
1: Do not set to this value
Function Select Bit
PSC_7
Key Input Interrupt
Disabled Select Bit
0: P104 to P107 or KI0 to KI3
1: AN4 to AN7(1)
RW
RW
NOTE:
1. Set the ILVL2 to ILVL0 bits in the the KUPIC register to "0002" (interrupt disabled) when changing
the PSC_7 bit setting.
Although AN4 to AN7 can be used when the PSC_7 bit is set to "0", power consumption may increase.
Figure 22.11 PSC Register
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REJ09B0271-0100
22. Programmable I/O Ports
M32C/80 Group
Function Select Register C3
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PSC3
Address
03AD16
Bit
Symbol
After Reset
X0XX XXXX2
Bit Name
Function
RW
Nothing is assigned. When write, set to "0".
(b5 - b0) When read, its content is indeterminate.
PSC3_6
(b7)
Port P96 Output Peripheral 0: TxD4/SDA4 output
Function Select Bit
1: Do not set to this value
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Function Select Register D1
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
PSD1
Bit
Symbol
(b1 - b0)
Address
03A716
After Reset
X0XX XX002
Bit Name
Reserved Bit
Function
Set to "0"
RW
RW
Nothing is assigned. When write, set to "0".
(b5 - b2) When read, its content is indeterminate.
PSD1_6
(b7)
Port P76 Output Peripheral 0: ISTxD0
Function Select Bit
1: Do not set to this value
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Figure 22.12 PSC3 Register and PSD1 Register
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REJ09B0271-0100
RW
22. Programmable I/O Ports
M32C/80 Group
Pull-Up Control Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
PUR0
03F016
Bit
Symbol
After Reset
0016
Bit Name
Function
RW
PU00
P00 to P03 Pull-up
PU01
P04 to P07 Pull-up
PU02
P10 to P13 Pull-up
Pull-up setting for corresponding port RW
0: Not pulled up
RW
1: Pulled up
RW
PU03
P14 to P17 Pull-up
RW
PU04
P20 to P23 Pull-up
RW
PU05
P24 to P27 Pull-up
RW
PU06
P30 to P33 Pull-up
RW
P34 to P37 Pull-up
RW
PU07
NOTE:
1. Set each bit in the PUR0 register to "0" when ports P0 to P5 become bus control pins in memory
expansion mode and microprocessor mode. When using the ports as I/O ports, pull-up or no
pull-up setting can be selected.
Pull-Up Control Register 1(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR1
Bit
Symbol
Address
03F116
After Reset
XXXX 00002
Bit Name
Function
RW
PU10
P40 to P43 Pull-up
PU11
P44 to P47 Pull-up
PU12
P50 to P53 Pull-up
Pull-up setting for corresponding port RW
0: Not pulled up
RW
1: Pulled up
RW
PU13
P54 to P57 Pull-up
RW
Nothing is assigned. When write, set to "0".
(b7 - b4) When read, its content is indeterminate.
NOTES:
1. Set each bit in the PUR1 register to "0" when ports P0 to P5 become bus control pins in memory
expansion mode and microprocessor mode. When using the ports as I/O ports, pull-up or no pull-up
setting can be selected.
Pull-Up Control Register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR2
Bit
Symbol
Address
03DA16
After Reset
0016
Bit Name
Function
RW
PU20
P60 to P63 Pull-up
PU21
P64 to P67 Pull-up
PU22
P72 to P73 Pull-up(1)
PU23
P74 to P77 Pull-up
RW
PU24
P80 to P83 Pull-up
RW
Pull-up setting for corresponding port RW
0: Not pulled up
RW
1: Pulled up
RW
P87 Pull-up(2)
PU25
P84 to
PU26
P90 to P93 Pull-up
RW
P94 to P97 Pull-up
RW
PU27
NOTES:
1. P70 and P71 cannot be pulled up.
2. P85 cannot be pulled up.
Figure 22.13 PUR0 Register, PUR1 Register and PUR2 Register
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REJ09B0271-0100
RW
22. Programmable I/O Ports
M32C/80 Group
Pull-Up Control Register 3
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR3
0 0 0 0 0 0
Bit
Symbol
Address
03DB16
Bit Name
PU30
P100 to P103 Pull-up
PU31
P104 to P107 Pull-up
(b7 - b2)
After Reset
0016
Reserved Bit
Function
RW
Pull-up setting for corresponding port
RW
0: Not pulled up
1: Pulled up
RW
Set to "0"
RW
Port Control Register
b7
b6
b5
b4
b3
b2
b1
0
0
b0
Symbol
PCR
Bit
Symbol
PCR0
Address
03FF16
After Reset
XXXX XXX02
Bit Name
Function
RW
Port P1 Control Bit(1)
0 : CMOS output
1 : N-channel open drain output(2)
RW
Reserved Bit
Set to "0"
RW
(b2 - b1)
Nothing is assigned. When write, set to "0".
(b7 - b3) When read, its content is indeterminate.
NOTES:
1. Set the PCR0 bit to "0" when P1 operates a port for data bus in memory expansion mode and
microprocessor mode. When using P1 as I/O port, CMOS port or N-channel open drain output port
can be selected.
2. This function is designed not to make port P1 a full open drain but to turn off the P channel in the
CMOS port.
Absolute maximum rating of the input voltage is between -0.3V and VCC2 + 0.3V.
Figure 22.14 PUR3 Register and PCR Register
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REJ09B0271-0100
M32C/80 Group
22. Programmable I/O Ports
Table 22.1 Unassigned Pin Settings in Single-Chip Mode
Pin Name
Setting
P0 to P10
Enter input mode and connect each pin to VSS via a resistor (pull-down);
(1,2,3)
(excluding P85)
or enter output mode and leave pins open
XOUT(4)
Leave pin open
_______
NMI(P85)
Connect pin to VCC1 via a resistor (pull-up)
AVCC
Connect pin to VCC1
AVSS, VREF, BYTE
Connect pins to VSS
NOTES:
1. If the port enters output mode and is left open, it is in input mode before output mode is entered by
program after reset. While the port is in input mode, voltage level on the pins is indeterminate and
power consumption may increase.
Direction register settings may be changed by noise or failure caused by noise. Configure direction
register settings regulary to increase the reliability of the program.
2. Use the shortest possible wiring to connect the microcomputer pins to unassigned pins (within 2 cm).
3. P70 and P71 must output low-level ("L") signals if they are in output mode. They are ports N-channel
open drain outputs.
4. When the external clock is applied to the XIN pin, set the pin as written above.
Table 22.2 Unassigned Pin Setting in Memory Expansion Mode and Microprocessor Mode
Pin Name
Setting
P6 to P10
Enter input mode and connect each pin to VSS via a resistor (pull-down);
(1,2,3)
(excluding P85)
or enter output mode and leave pins open
_______
_________
BHE, ALE, HLDA,
Leave pin open
(5)
XOUT , BCLK
_______
NMI(P85)
Connect pin to VCC1 via a resistor (pull-up)
_______ __________
RDY, HOLD
Connect pins to VCC2 via a resistor (pull-up)
AVCC
Connect pin to VCC1
AVSS, VREF
Connect pins to VSS
NOTES:
1. If the port enters output mode and is left open, it is in input mode before output mode is entered by
program after reset. While the port is in input mode, voltage level on the pins is indeterminate and
power consumption may increase.
Direction register settings may be changed by noise or failure caused by noise. Configure direction
register settings regulary to increase the reliability of the program.
2. Use the shortest possible wiring to connect the microcomputer pins to unassigned pins (within 2 cm).
3. P70 and P71 must outputs low-level ("L") signals if they are in output mode. They are N-channel
open-drain outputs.
4. When the external clock is applied to the XIN pin, set the pin as written above.
Rev. 1.00 Nov. 01, 2005 Page 277 of 330
REJ09B0271-0100
22. Programmable I/O Ports
M32C/80 Group
Microcomputer
Microcomputer
P0 to P10 (except for P85)
P6 to P10 (except for P85)
(Input mode)
·
·
·
(Input mode)
(Output mode)
(Input mode)
·
·
·
(Input mode)
··
·
Open
(Output mode)
VCC1
BHE
HLDA
ALE
XOUT
BCLK
Open
VCC1
AVCC
BYTE
HOLD
RDY
AVSS
VREF
VSS
In single-chip mode
Figure 22.15 Unassigned Pin Handling
Rev. 1.00 Nov. 01, 2005 Page 278 of 330
REJ09B0271-0100
VCC1
Open
NMI(P85)
NMI(P85)
XOUT
··
·
AVCC
AVSS
VREF
In memory expansion mode or
microprocessor mode
Open
VCC2
VCC1
VSS
22. Programmable I/O Ports
M32C/80 Group
Table 22.3 Port P6 Peripheral Function Output Control
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
PS0 Register
_________ _______
0: P6
0/CTS0/SS0
________
1: RTS0
0: P61/CLK0(input)
1: CLK0(output)
0: P62/RxD0/SCL0(input)
1: Selected by the PSL0 register
0: P63/SRxD0/SDA0(input)
1: TxD0/SDA0 (output)
_________ _______
0: P64/CTS1/SS1
1: Selected by the PSL0 register
0: P65/CLK1(input)
1: CLK1(output)
0: P66/RxD1/SCL1(input)
1: Selected by the PSL0 register
0: P67/SRxD1/SDA1(input)
1: TxD1/SDA1(output)
PSL0 Register
Set to "0"
Set to "0"
0: SCL0(output)
1: STxD0
Set to "0"
________
0: RTS1
1: Do not set this value
Set to "0"
0: SCL1(output)
1: STxD1
Set to "0"
Table 22.4 Port P7 Peripheral Function Output Control
PS1 Register
Bit 0 0: P70/TA0OUT(input)/SRxD2/
SDA2 (input)
1: Selected by the PSL1 register
Bit 1 0: P71/TB5IN/TA0IN/RxD2/
SCL2 (input)
1: Selected by the PSL1 register
PSL1 Register
PSC Register(1)
0: Selected by the PSC register 0: TxD2/SDA2(output)
PSD1 Register
Set to "0"
1: TA0OUT(output)
1: Do not set to this value
0: Selected by the PSC register 0: SCL2(output)
Set to "0"
1: STxD2
1: Do not set to this value
0: Selected by the PSC register 0: CLK2(output)
Bit 2 0: P72/TA1OUT(input)/
CLK2(input)
1: Selected by the PSL1 register 1: TA1OUT(output)
1: V
_________ ______
Set to "0"
_________
Bit 3 0: P73/TA1IN/CTS2/SS2/
1: Selected by the PSL1 register
Bit 4 0: P74/ISCLK1(input)/
TA2OUT(input)
1: Selected by the PSL1 register
0: Selected
by the PSC register 0: RTS2
__
1: V
1: ISTxD1
0: Selected by the PSC register 0: TA2OUT(output)
Bit 5 0: P75/TA2IN/ISRxD1
1: Selected by the PSL1 register
Bit 6 0: P76/TA3OUT(input)
1: Selected by the PSL1 register
Bit 7 0: P77/TA3IN/ISCLK0(input)
1: Selected by the PSL1 register
0: W
1: Do not se to this value
0: Selected by the PSC register
1: TA3OUT(output)
0: ISCLK0(output)
1: Do not set to this value
1: W
Set to "0"
Set to "0"
1: ISCLK1(output)
___
Set to "0"
Set to "0"
0: Selected by the PSD1 register 0: ISTxD0
1: Do not set to this value
1: Do not set to this value
_____
_____
0: P104 to P107 or KI0 to KI3 Set to "0"
1: AN4 to AN7
(No relation to P77)
NOTE:
1. When setting the PSL1_i bit (i=0 to 4, 6) to "1", set the corresponding PSC_i bit to "0".
Rev. 1.00 Nov. 01, 2005 Page 279 of 330
REJ09B0271-0100
22. Programmable I/O Ports
M32C/80 Group
Table 22.5 Port P8 Peripheral Function Output Control
PS2 Register
0: P80/ISRxD0/TA4OUT(input)
1: Selected by the PSL2 register
Bit 1
0: P81/TA4IN
1: Selected by the PSL2 register
________
Bit 2
0: P82/INT0
1: Selected by the PSL2 register
Bit 3 to 7 Set to "000002"
Bit 0
PSL2 Register
0: TA4OUT(output)
1: U
____
0: U
1: Do not set to this value
Set to "0"
Table 22.6 Port P9 Peripheral Function Output Control
PS3 Register
Bit 0 0: P90/TB0IN/CLK3(input)
1: CLK3(output)
Bit 1 0: P91/TB1IN/RxD3/SCL3(input)
1: Selected by the PSL3 register
Bit 2 0: P92/TB2IN/SRxD3/SDA3(input)
1: Selected by the PSL3 register
_______
_______
Bit 3 0: P9
3/TB3IN/CTS3/SS3/DA0(output)
________
1: RTS3
________ ______
Bit 4 0: P9
4/TB4IN/CTS4/SS4/DA1(output)
________
1: RTS4
Bit 5 0: P95/ANEX0/CLK4(input)/
1: CLK4(output)
Bit 6 0: P96/SRxD4/ANEX1/SDA4(input)
1: Selected by the PSC3 register
__________
Bit 7 0: P97/RxD4/ADTRG/SCL4(input)
1: Selected by the PSL3 register
PSL3 Register
Set to "0"
PSC3 Register
Set to "0"
0: SCL3(output)
1: STxD3
0: TxD3/SDA3(output)
1: Do not set to this value
0: Except DA0
1: DA0
0: Except DA1
1: DA1
0: Except ANEX0
1: ANEX0
0: Except ANEX1
1: ANEX1
0: SCL4(output)
1: STxD4
Set to "0"
Table 22.7 Port P10 Peripheral Function Output Control
PSC Register
_____
_____
Bit 7 0: P104 to P107 or KI0 to KI3
1: AN4 to AN7
Rev. 1.00 Nov. 01, 2005 Page 280 of 330
REJ09B0271-0100
Set to "0"
Set to "0"
Set to "0"
Set to "0"
0: TxD4/SDA4 output
1: Do not set to this value
Set to "0"
23. Electrical Characteristics
M32C/80 Group
23. Electrical Characteristics
Table 23.1 Absolute Maximum Ratings
Condition
Value
Unit
VCC1, VCC2
Symbol
Supply Voltage
Parameter
VCC1=AVCC
-0.3 to 6.0
V
VCC2
Supply Voltage
-
-0.3 to VCC1
V
AVCC
Analog Supply Voltage
VI
Input Voltage
VCC1=AVCC
RESET, CNVSS, BYTE, P60-P67, P72-P77,
P80-P87, P90-P97, P100-P107, VREF, XIN
P00-P07, P10-P17, P20-P27, P30-P37,
P40-P47, P50-P57
Output Voltage
V
V
-0.3 to VCC2+0.3
P70, P71
VO
-0.3 to 6.0
-0.3 to VCC1+0.3
-0.3 to 6.0
P60-P67, P72-P77, P80-P84, P86, P87,
P90-P97, P100-P107, XOUT
-0.3 to VCC1+0.3
P00-P07, P10-P17, P20-P27, P30-P37,
P40-P47, P50-P57
-0.3 to VCC2+0.3
P70, P71
V
-0.3 to 6.0
Pd
Power Dissipation
500
mW
Topr
Operating Ambient Temperature
-20 to 85/
-40 to 85(1)
°C
Tstg
Storage Temperature
-65 to 150
°C
NOTE:
1. Contact our sales office if temperature range of -40 to 85° C is required.
Rev. 1.00 Nov. 01, 2005 Page 281 of 330
REJ09B0271-0100
Topr=25° C
23. Electrical Characteristics
M32C/80 Group
Table 23.2 Recommended Operating Conditions
(VCC1= VCC2=3.0V to 5.5V at Topr=– 20 to 85oC unless otherwise specified)
Symbol
Parameter
VCC1, VCC2
AVCC
Supply Voltage (VCC1≥ VCC2)
Analog Supply Voltage
VSS
Supply Voltage
AVSS
Analog Supply Voltage
Input High ("H")
Voltage
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
Input Low ("L")
Voltage
Min.
3.0
Typ.
5.0
VCC1
Max.
5.5
0
VIH
VIL
Standard
0
V
0.8VCC2
VCC2
P60-P67, P72-P77, P80-P87(3), P90-P97, P100-P107, XIN,
RESET, CNVSS, BYTE
P70, P71
0.8VCC1
VCC1
0.8VCC1
6.0
P00-P07, P10-P17 (in single-chip mode)
0.8VCC2
VCC2
P00-P07, P10-P17
(in memory expansion mode and microprocesor mode)
P20-P27, P30-P37, P40-P47, P50-P57
0.5VCC2
VCC2
0
0.2VCC2
0
0.2VCC1
0
0.2VCC2
0
0.16VCC2
P90-P97, P100-P107, XIN,
RESET, CNVSS, BYTE
P00-P07, P10-P17 (in single-chip mode)
P00-P07, P10-P17
(in memory expansion mode and microprocesor mode)
Peak Output High
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57,
("H") Current(2)
P60-P67, P72-P77, P80-P84, P86, P87, P90-P97,
P100-P107
Average Output
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57,
High ("H") Current(1) P60-P67, P72-P77, P80-P84, P86, P87, P90-P97,
P100-P107
Peak Output Low
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57,
("L") Current(2)
P60-P67, P70-P77, P80-P84, P86, P87, P90-P97,
P100-P107
Average Output Low P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57,
("L") Current(1)
P60-P67, P70-P77, P80-P84, P86, P87, P90-P97,
P100-P107
NOTES:
1. Typical values when average output current is 100 ms.
2. Total IOL(peak) for P0, P1, P2, P86, P87, P9, and P10 must be 80 mA or less.
Total IOL(peak) for P3, P4, P5, P6, P7, and P80 to P84 must be 80 mA or less.
Total IOH(peak) for P0, P1, and P2 must be -40 mA or less.
Total IOH(peak) for P86, P87, P9, and P10 must be -40 mA or less.
Total IOH(peak) for P3, P4, and P5 must be -40 mA or less.
Total IOH(peak) for P6, P7, and P80 to P84 must be -40 mA or less.
3. VIH and VIL reference for P87 applies when P87 is used as a programmable input port.
It does not apply when P87 is used as XCIN.
Rev. 1.00 Nov. 01, 2005 Page 282 of 330
REJ09B0271-0100
V
V
V
P20-P27, P30-P37, P40-P47, P50-P57
P60-P67, P70-P77, P80-P87(3),
Unit
V
V
-10.0
mA
-5.0
mA
10.0
mA
5.0
mA
23. Electrical Characteristics
M32C/80 Group
Table 23.2 Recommended Operating Conditions (Continued)
(VCC1=VCC2=3.0V to 5.5V at Topr=–20 to 85oC unless otherwise specified)
Symbol
f(BCLK)
f(XIN)
f(XCIN)
CPU Operation Frequency
Main Clock Input Frequency
Min.
On-chip Oscillator Frequency (Topr=25° C)
f(PLL)
PLL Clock Frequency
Wait Time to Stabilize PLL Frequency Synthesizer
Rev. 1.00 Nov. 01, 2005 Page 283 of 330
REJ09B0271-0100
Typ.
Max.
Unit
VCC1=4.2 to 5.5 V
0
32
MHz
VCC1=3.0 to 5.5 V
0
24
MHz
VCC1=4.2 to 5.5 V
0
32
MHz
VCC1=3.0 to 5.5 V
0
24
MHz
Sub Clock Frequency
f(Ring)
tSU(PLL)
Standard
Parameter
0.5
32.768
50
kHz
1
2
MHz
VCC1=4.2 to 5.5 V
10
32
MHz
VCC1=3.0 to 5.5 V
10
24
MHz
VCC1=5.0 V
5
ms
VCC1=3.3 V
10
ms
23. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
Table 23.3 Electrical Characteristics
(VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr= –20 to 85oC, f(BCLK)=32MHZ unless otherwise specified)
Symbol
VOH
Parameter
Output High ("H")
Voltage
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57
P60-P67, P72-P77, P80-P84, P86, P87, P90P97, P100-P107
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57
P60-P67, P72-P77, P80-P84, P86, P87, P90P97, P100-P107
XOUT
XCOUT
VOL
Output Low ("L")
Voltage
Condition
Standard
IOH=-5mA
VCC2-2.0
Max.
VCC2
IOH=-5mA
VCC1-2.0
VCC1
IOH=-200µA
VCC2-0.3
VCC2
IOH=-200µA
VCC1-0.3
VCC1
3.0
VCC1
IOH=-1mA
Min.
Typ.
High Power
No load applied
2.5
Low Power
No load applied
1.6
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOL=5mA
P50-P57, P60-P67, P70-P77, P80-P84, P86,
P87, P90-P97, P100-P107
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOL=200µA
P50-P57, P60-P67, P70-P77, P80-P84, P86,
VT+-VT- Hysteresis
P87, P90-P97, P100-P107
XOUT
IOL=1mA
XCOUT
High Power
No load applied
0
Low Power
No load applied
0
HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN,
Unit
V
V
V
V
2.0
V
0.45
V
2.0
V
V
0.2
1.0
V
0.2
1.8
5.0
V
µA
-5.0
µA
167
kΩ
60
MΩ
MΩ
V
mA
INT0-INT5, ADTRG, CTS0-CTS4, CLK0-CLK4,
TA0OUT-TA4OUT, NMI, KI0-KI3, RxD0-RxD4,
SCL0-SCL4, SDA0-SDA4
RESET
IIH
Input High ("H")
Current
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=5V
P50-P57, P60-P67, P70-P77, P80-P87, P90-P97,
P100-P107, XIN, RESET, CNVSS, BYTE
IIL
Input Low ("L")
Current
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=0V
P50-P57, P60-P67, P70-P77, P80-P87, P90-P97,
P100-P107, XIN, RESET, CNVSS, BYTE
RPULLUP Pull-up Resistance
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=0V
20
40
P50-P57, P60-P67, P72-P77, P80-P84, P86,
P87, P90-P97, P100-P107
RfXIN
RfXCIN
VRAM
ICC
Feedback Resistance
Feedback Resistance
RAM Standby Voltage
Power Supply Current
XIN
XCIN
In stop mode
In single-chip mode,
output pins are left
open and other pins
are connected to VSS.
Rev. 1.00 Nov. 01, 2005 Page 284 of 330
REJ09B0271-0100
1.5
15
2.0
f(BCLK)=32 MHz, Square wave,
No division
f(BCLK)=32 kHz, In wait mode,
Topr=25° C
While clock stops, Topr=25° C
While clock stops, Topr=85° C
22
µA
10
0.8
5
20
µA
µA
23. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
Table 23.4 A/D Conversion Characteristics (VCC1=VCC2=AVCC=VREF=4.2 to 5.5V, Vss= AVSS = 0V at
Topr=–20 to 85oC, f(BCLK) = 32MHZ unless otherwise specified)
Symbol
Parameter
Standard
Measurement Condition
Min.
-
INL
Resolution
VREF=VCC1
Integral Nonlinearity Error
DNL
Unit
Typ. Max.
10
AN0 to AN7, ANEX0,
ANEX1
±3
External op-amp
connection mode
±7
Bits
LSB
LSB
VREF=VCC1=VCC2=5V
LSB
LSB
Differential Nonlinearity Error
±1
-
Offset Error
±3
LSB
-
Gain Error
±3
LSB
40
kΩ
RLADDER
Resistor Ladder
tCONV
10-bit Conversion Time(1, 2)
VREF=VCC1
8
Time(1, 2)
LSB
2.06
µs
1.75
µs
0.188
µs
tCONV
8-bit Conversion
tSAMP
Sampling Time(1)
VREF
Reference Voltage
2
VCC1
V
VIA
Analog Input Voltage
0
VREF
V
NOTES:
1. Divide f(XIN), if exceeding 16 MHz, to keep φAD frequency at 16 MHz or less.
2. With using the sample and hold function.
Table 23.5 D/A Conversion Characteristics (VCC1=VCC2=VREF=4.2 to 5.5V, VSS=AVSS=0V
at Topr=–20 to 85oC, f(BCLK) = 32MHZ unless otherwise specified)
Symbol
Parameter
Standard
Measurement Condition
Min.
tSU
Typ.
Unit
Max.
Resolution
8
Absolute Accuracy
Setup Time
RO
Output Resistance
IVREF
Reference Power Supply Input Current
4
10
(Note 1)
NOTE:
1. Measurement when using one D/A converter. The DAi register (i=0, 1) of the D/A converter, not being
used, is set to "0016". The resistor ladder in the A/D converter is excluded.
IVREF flows even if the VCUT bit in the AD0CON1 register is set to "0" (no VREF connection).
Rev. 1.00 Nov. 01, 2005 Page 285 of 330
REJ09B0271-0100
Bits
1.0
%
3
µs
20
kΩ
1.5
mA
23. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
Timing Requirements
(VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr=–20 to 85oC unless otherwise specified)
Table 23.6 External Clock Input
Symbol
Parameter
Standard
Min.
Unit
Max.
tc
External Clock Input Cycle Time
31.25
ns
tw(H)
External Clock Input High ("H") Width
13.75
ns
13.75
tw(L)
External Clock Input Low ("L") Width
tr
External Clock Rise Time
5
ns
ns
tf
External Clock Fall Time
5
ns
Table 23.7 Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Min.
Max.
Unit
tac1(RD-DB)
Data Input Access Time (RD standard)
(Note 1)
ns
tac1(AD-DB)
Data Input Access Time (AD standard, CS standard)
(Note 1)
ns
tac2(RD-DB)
Data Input Access Time (RD standard, when accessing a space with the multiplexrd bus)
(Note 1)
ns
tac2(AD-DB)
Data Input Access Time (AD standard, when accessing a space with the multiplexed bus)
(Note 1)
ns
tsu(DB-BCLK)
Data Input Setup Time
26
ns
tsu(RDY-BCLK)
RDY Input Setup Time
26
ns
30
ns
tsu(HOLD-BCLK) HOLD Input Setup Time
th(RD-DB)
Data Input Hold Time
0
ns
th(BCLK-RDY)
RDY Input Hold Time
0
ns
th(BCLK-HOLD)
HOLD Input Hold Time
0
td(BCLK-HLDA)
HLDA Output Delay Time
ns
25
NOTE:
1. Values can be obtained from the following equations, according to BCLK frequecncy and external bus cycles. Insert a
wait state or lower the operation frequency, f(BCLK), if the calculated value is negative.
9
10 X m
tac1(RD – DB) = f(BCLK) X 2
tac1(AD – DB) =
109 X n
f(BCLK)
– 35
[ns] (if external bus cycle is aφ + bφ, m=(bx2)+1)
– 35
[ns] (if external bus cycle is aφ + bφ, n=a+b)
– 35
[ns] (if external bus cycle is aφ + bφ, m=(bx2)-1)
9
tac2(RD – DB) =
10 X m
f(BCLK) X 2
tac2(AD – DB) =
109 X p
– 35
f(BCLK) X 2
[ns] (if external bus cycle is aφ + bφ, p={(a+b-1)x2}+1)
Rev. 1.00 Nov. 01, 2005 Page 286 of 330
REJ09B0271-0100
ns
23. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
Timing Requirements
(VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr=–20 to 85oC unless otherwise specified)
Table 23.8 Timer A Input (Count Source Input in Event Counter Mode)
Symbol
Standard
Parameter
Min.
Unit
Max.
tc(TA)
TAiIN Input Cycle Time
100
ns
tw(TAH)
TAiIN Input High ("H") Width
40
ns
tw(TAL)
TAiIN Input Low ("L") Width
40
ns
Table 23.9 Timer A Input (Gate Input in Timer Mode)
Standard
Symbol
Parameter
Min.
Max.
Unit
tc(TA)
TAiIN Input Cycle Time
400
ns
tw(TAH)
TAiIN Input High ("H") Width
200
ns
tw(TAL)
TAiIN Input Low ("L") Width
200
ns
Table 23.10 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(TA)
TAiIN Input Cycle Time
200
ns
tw(TAH)
TAiIN Input High ("H") Width
100
ns
tw(TAL)
TAiIN Input Low ("L") Width
100
ns
Table 23.11 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tw(TAH)
TAiIN Input High ("H") Width
100
ns
tw(TAL)
TAiIN Input Low ("L") Width
100
ns
Table 23.12 Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(UP)
TAiOUT Input Cycle Time
tw(UPH)
TAiOUT Input High ("H") Width
1000
ns
tw(UPL)
TAiOUT Input Low ("L") Width
1000
ns
tsu(UP-TIN)
TAiOUT Input Setup Time
400
ns
th(TIN-UP)
TAiOUT Input Hold Time
400
ns
Rev. 1.00 Nov. 01, 2005 Page 287 of 330
REJ09B0271-0100
2000
ns
23. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 23.13 Timer B Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
100
ns
tw(TBH)
TBiIN Input High ("H") Width (counted on one edge)
40
ns
tw(TBL)
TBiIN Input Low ("L") Width (counted on one edge)
40
ns
tc(TB)
TBiIN Input Cycle Time (counted on both edges)
200
ns
tw(TBH)
TBiIN Input High ("H") Width (counted on both edges)
80
ns
tw(TBL)
TBiIN Input Low ("L") Width (counted on both edges)
80
ns
Table 23.14 Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
400
Unit
tc(TB)
TBiIN Input Cycle Time
ns
tw(TBH)
TBiIN Input High ("H") Width
200
ns
tw(TBL)
TBiIN Input Low ("L") Width
200
ns
Table 23.15 Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(TB)
TBiIN Input Cycle Time
tw(TBH)
TBiIN Input High ("H") Width
200
ns
tw(TBL)
TBiIN Input Low ("L") Width
200
ns
400
ns
Table 23.16 A/D Trigger Input
Symbol
Parameter
Standard
Min.
Max
Unit
tc(AD)
ADTRG Input Cycle Time (required for trigger)
1000
ns
tw(ADL)
ADTRG Input Low ("L") Width
125
ns
Table 23.17 Serial I/O
Symbol
tc(CK)
Parameter
CLKi Input Cycle Time
Standard
Min.
Max.
200
Unit
ns
tw(CKH)
CLKi Input High ("H") Width
100
ns
tw(CKL)
CLKi Input Low ("L") Width
100
ns
td(C-Q)
TxDi Output Delay Time
80
ns
th(C-Q)
TxDi Hold Time
0
ns
tsu(D-C)
RxDi Input Setup Time
30
ns
th(C-Q)
RxDi Input Hold Time
90
ns
_______
Table 23.18 External Interrupt INTi Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(INH)
INTi Input High ("H") Width
250
ns
tw(INL)
INTi Input Low ("L") Width
250
ns
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REJ09B0271-0100
23. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 23.19 Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space)
Symbol
Parameter
Measurement
Condition
Standard
Min.
Unit
Max.
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (BCLK standard)
th(RD-AD)
Address Output Hold Time (RD standard)
0
ns
th(WR-AD)
Address Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-CS)
Chip-Select Signal Output Delay Time
18
-3
ns
ns
18
ns
th(BCLK-CS)
Chip-Select Signal Output Hold Time (BCLK standard)
-3
ns
th(RD-CS)
Chip-Select Signal Output Hold Time (RD standard)
0
ns
th(WR-CS)
Chip-Select Signal Output Hold Time (WR standard)
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
td(BCLK-WR)
WR Signal Output Delay Time
th(BCLK-WR)
WR Signal Output Hold Time
See Figure 23.1
(Note 1)
ns
18
ns
18
ns
-5
ns
-5
ns
td(DB-WR)
Data Output Delay Time (WR standard)
(Note 2)
ns
th(WR-DB)
Data Output Hold Time (WR standard)
(Note 1)
ns
tw(WR)
WR Output Width
(Note 2)
ns
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
10 9
th(WR – DB) =
– 10 [ns]
f(BCLK) X 2
10 9
th(WR – AD) =
– 10 [ns]
f(BCLK) X 2
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles.
9
tw(WR) =
10 X n
f(BCLK) X 2
– 15
[ns]
(if external bus cycle is aφ + bφ, n=(bx2)-1)
– 20
[ns]
(if external bus cycle is aφ + bφ, m= b)
9
td(DB – WR) =
10 X m
f(BCLK)
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23. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
Switching Characteristics
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 23.20 Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
Symbol
Parameter
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (BCLK standard)
Measurement
Condition
Standard
Min.
Unit
Max.
18
-3
ns
ns
th(RD-AD)
Address Output Hold Time (RD standard)
(Note 1)
ns
th(WR-AD)
Address Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-CS)
Chip-Select Signal Output Delay Time
th(BCLK-CS)
Chip-Select Signal Output Hold Time (BCLK standard)
th(RD-CS)
Chip-Select Signal Output Hold Time (RD standard)
th(WR-CS)
Chip-Select Signal Output Hold Time (WR standard)
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
td(BCLK-WR)
WR Signal Output Delay Time
18
ns
-3
ns
(Note 1)
ns
(Note 1)
See Figure 23.1
ns
18
-5
ns
ns
18
ns
th(BCLK-WR)
WR Signal Output Hold Time
-5
ns
td(DB-WR)
Data Output Delay Time (WR standard)
(Note 2)
ns
th(WR-DB)
Data Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-ALE)
ALE Signal Output Delay Time (BCLK standard)
th(BCLK-ALE)
ALE Signal Output Hold Time (BCLK standard)
18
ns
-5
ns
td(AD-ALE)
ALE Signal Output Delay Time (address standard)
(Note 3)
ns
th(ALE-AD)
ALE Signal Output Hold Time (address standard)
(Note 4)
ns
tdz(RD-AD)
Address Output Float Start Time
8
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
th(RD – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(RD – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
9
th(WR – CS) =
10
f(BCLK) X 2
– 10
[ns]
th(WR – DB) =
10 9
f(BCLK) X 2
– 10
[ns]
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.
9
td(DB – WR) =
10 X m
– 25
f(BCLK) X 2
[ns] (if external bus cycle is aφ + bφ, m= (bx2)-1)
3. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.
9
td(AD – ALE) =
10 X n
f(BCLK) X 2
– 20
[ns] (if external bus cycle is aφ + bφ, n= a)
4. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.
9
th(ALE – AD) =
10 X n
f(BCLK) X 2
– 10
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[ns] (if external bus cycle is aφ + bφ, n= a)
ns
23. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
Figure 23.1 P0 to P10 Measurement Circuit
Rev. 1.00 Nov. 01, 2005 Page 291 of 330
REJ09B0271-0100
30pF
23. Electrical Characteristics
M32C/80 Group
Vcc1=Vcc2=5V
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
[ Read Timing ] (1φ +1φ Bus Cycle)
BCLK
td(BCLK-CS)
th(BCLK-CS)
18ns.max(1)
-3ns.min
CSi
th(RD-CS)
tcyc
0ns.min
td(BCLK-AD)
th(BCLK-AD)
18ns.max(1)
-3ns.min
ADi
BHE
th(RD-AD)
0ns.min
td(BCLK-RD)
18ns.max
RD
th(BCLK-RD)
tac1(RD-DB)(2)
-5ns.min
tac1(AD-DB)(2)
DB
Hi-Z
tsu(DB-BCLK)
th(RD-DB)
26ns.min(1)
0ns.min
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. Varies with operation frequency:
tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)+1)
tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is aφ + bφ, n=a+b)
[ Write timing ] (1φ +1φ Bus Cycle)
BCLK
th(BCLK-CS)
td(BCLK-CS)
18ns.max
-3ns.min
CSi
tcyc
th(WR-CS)(3)
td(BCLK-AD)
th(BCLK-AD)
18ns.max
-3ns.min
ADi
BHE
td(BCLK-WR)
WR,WRL,
WRH
18ns.max
tw(WR)(3)
th(WR-AD)(3)
th(BCLK-WR)
-5ns.min
td(DB-WR)(3)
th(WR-DB)(3)
DBi
NOTE:
3. Varies with operation frequency:
td(DB-WR)=(tcyc x m-20)ns.min
(if external bus cycle is aφ+bφ, m=b)
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
(if external bus cycle is aφ+bφ , n=(bx2)-1)
Figure 23.2 VCC1=VCC2=5V Timing Diagram (1)
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REJ09B0271-0100
Measurement Conditions:
• VCC1=VCC2=4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH=2.0V, VOL=0.8V
9
tcyc=
10
f(BCLK)
23. Electrical Characteristics
M32C/80 Group
Vcc1=Vcc2=5V
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
[ Read Timing ] (2φ +2φ Bus Cycle)
BCLK
td(BCLK-ALE)
th(BCLK-ALE)
-5ns.min
18ns.max
ALE
th(BCLK-CS)
tcyc
td(BCLK-CS)
-3ns.min
18ns.max
th(RD-CS)(1)
CSi
td(AD-ALE)(1)
th(ALE-AD)
ADi
/DBi
Address
(1)
tsu(DB-BCLK) 26ns.min
Data input
tdz(RD-AD)
Address
8ns.max
td(BCLK-AD)
ADi
BHE
th(RD-DB)
tac2(RD-DB)(1)
18ns.max
(1)
td(BCLK-RD)
tac2(AD-DB)
th(BCLK-RD)
18ns.max
th(BCLK-AD)
-3ns.min
0ns.min
th(RD-AD)
(1)
-5ns.min
RD
NOTE:
1. Varies with operation frequency:
td(AD-ALE)=(tcyc/2 x n-20)ns.min (if external bus cycle is aφ + bφ, n=a)
th(ALE-AD)=(tcyc/2 x n-10)ns.min (if external bus cycle is aφ + bφ, n=a)
th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)-1)
tac2(AD-DB)=(tcyc/2 x p-35)ns.max (if external bus cycle is aφ + bφ, p={(a+b-1) x 2}+1)
[ Write Timing ] (2φ +2φ Bus Cycle)
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-5ns.min
ALE
tcyc
td(BCLK-CS)
th(BCLK-CS)
(2)
th(WR-CS)
-3ns.min
18ns.max
CSi
td(AD-ALE)
ADi
/DBi
(2)
(2)
th(ALE-AD)
Address
Address
Data output
td(DB-WR)
td(BCLK-AD)
(2)
(2)
th(WR-DB)
18ns.max
ADi
BHE
-3ns.min
td(BCLK-WR)
WR,WRL,
WRH
(if external bus cycle is aφ + bφ, n=a)
th(ALE-AD)=(tcyc/2 x n -10)ns.min
(if external bus cycle is aφ + bφ, n=a)
th(WR-AD)=(tcyc/2-10)ns.min,
th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min
td(DB-WR)=(tcyc/2 x m-25)ns.min
Figure 23.3 VCC1=VCC2=5V Timing Diagram (2)
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th(BCLK-WR)
18ns.max
NOTE:
2. Varies with operation frequency:
td(AD-ALE)=(tcyc/2 x n - 20)ns.min
(if external bus cycle is aφ + bφ, m=(b x 2)-1)
th(BCLK-AD)
th(WR-AD) (2)
-5ns.min
Measurement Conditions:
• VCC1=VCC2=4.2 to 5.5V
• Input high and low voltage:
VIH=2.5V, VIL=0.8V
• Output high and low voltage:
VOH=2.0V, VOL=0.8V
9
tcyc= 10
f(BCLK)
23. Electrical Characteristics
M32C/80 Group
Vcc1=Vcc2=5V
tc(TA)
tw(TAH)
TAiIN Input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT Input
tw(UPL)
TAiOUT Input
(Counter increment/
decrement input)
In event counter mode
TAiIN Input
th(TIN–UP)
tsu(UP–TIN)
(When counting on the falling edge)
TAiIN Input
(When counting on the rising edge)
tc(TB)
tw(TBH)
TBiIN Input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG Input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
th(C–D)
RxDi
tw(INL)
INTi Input
tw(INH)
NMI input
2 CPU clock cycles +
300ns or more
("L" width)
Figure 23.4 VCC1=VCC2=5V Timing Diagram (3)
Rev. 1.00 Nov. 01, 2005 Page 294 of 330
REJ09B0271-0100
2 CPU clock cycles +
300ns or more
23. Electrical Characteristics
M32C/80 Group
Vcc1=Vcc2=5V
Memory Expansion Mode and Microprocessor Mode
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
th(BCLK–RDY)
tsu(RDY–BCLK)
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD Input
HLDA Output
td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
P50 to P52
td(BCLK–HLDA)
Hi–Z
Measurement Conditions
• VCC1=VCC2=4.2 to 5.5V
• Input high and low voltage: VIH=4.0V, VIL=1.0V
• Output high and low voltage: VOH=2.5V, VOL=2.5V
Figure 23.5 VCC1=VCC2=5V Timing Diagram (4)
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23. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=3.3V
Table 23.21 Electrical Characteristics (VCC1=VCC2=3.0 to 3.6V, VSS=0V at Topr = –20 to 85oC,
f(BCLK)=24MHZ unless otherwise specified)
Symbol
VOH
Parameter
Output High ("H")
Voltage
Condition
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOH=-1mA
Max.
VCC2
P50-P57
P60-P67, P72-P77, P80-P84, P86, P87, P90-
VCC1-0.6
VCC1
V
2.7
VCC1
V
XCOUT
IOH=-0.1mA
High Power
Low Power
Output Low ("L")
Voltage
VT+-VT- Hysteresis
Unit
Min.
Typ.
VCC2-0.6
P97, P100-P107
XOUT
VOL
Standard
No load applied
2.5
No load applied
1.6
V
V
V
P00-P07, P10-P17, P20-P27, P30-P37, P40P47, P50-P57, P60-P67, P70-P77, P80-P84,
P86, P87, P90-P97, P100-P107
XOUT
IOL=1mA
0.5
V
IOL=0.1mA
0.5
V
XCOUT
High Power
No load applied
0
V
Low Power
No load applied
0
V
0.2
1.0
V
0.2
1.8
V
VI=3V
4.0
µA
VI=0V
-4.0
µA
500
kΩ
35
MΩ
MΩ
V
mA
HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN,
INT0-INT5, ADTRG, CTS0-CTS4, CLK0CLK4, TA0OUT-TA4OUT, NMI, KI0-KI3, RxD0RxD4, SCL0-SCL4, SDA0-SDA4
RESET
IIH
Input High ("H")
Current
IIL
Input Low ("L")
Current
P00-P07, P10-P17, P20-P27, P30-P37, P40P47, P50-P57, P60-P67, P70-P77, P80-P87,
P90-P97, P100-P107, XIN, RESET, CNVSS,
BYTE
P00-P07, P10-P17, P20-P27, P30-P37, P40P47, P50-P57, P60-P67, P70-P77, P80-P87,
P90-P97, P100-P107, XIN, RESET, CNVSS,
BYTE
RPULLUP Pull-up Resistance
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=0V
40
70
P50-P57, P60-P67, P72-P77, P80-P84, P86,
P87, P90-P97, P100-P107
RfXIN
RfXCIN
VRAM
ICC
Feedback Resistance
Feedback Resistance
RAM Standby Voltage
Power Supply
Current
XIN
XCIN
in stop mode
Measurement condition:
In single-chip mode,
output pins are left open
and other pins are
connected to VSS.
3.0
30.0
2.0
f(BCLK)=24 MHz, Square wave,
No division
f(BCLK)=32 kHz, In wait mode,
Topr=25° C
17
While clock stops, Topr=25° C
0.8
While clock stops, Topr=85° C
Rev. 1.00 Nov. 01, 2005 Page 296 of 330
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µA
10
5
µA
50
µA
23. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=3.3V
Table 23.22 A/D Conversion Characteristics (VCC1=VCC2=AVCC=VREF= 3.0 to 3.6V, VSS=AVSS=0V
at Topr = –20 to 85oC, f(BCLK) = 24MHZ unless otherwise specified)
Symbol
Parameter
Standard
Measurement Condition
Unit
Min. Typ. Max.
-
Resolution
INL
DNL
Integral Nonlinearity Error
No S&H (8-bit)
VREF=VCC1
10
Bits
VCC1=VCC2=VREF=3.3V
±2
LSB
Differential Nonlinearity Error
No S&H (8-bit)
±1
LSB
-
Offset Error
No S&H (8-bit)
±2
LSB
-
Gain Error
No S&H (8-bit)
±2
LSB
40
kΩ
RLADDER
Resistor Ladder
VREF=VCC1
Time(1, 2)
tCONV
8-bit Conversion
VREF
Reference Voltage
VIA
Analog Input Voltage
8.0
µs
6.1
3.3
VCC1
V
0
VREF
V
S&H: Sample and Hold
NOTES:
1. Divide f(XIN), if exceeding 10 MHz, to keep φAD frequency at 10 MHz or less.
2. S&H not available.
Table 23.23 D/A Conversion Characteristics (VCC1=VCC2=VREF=3.0 to 3.6V, VSS=AVSS=0V
at Topr = –20 to 85oC, f(BCLK) = 24MHZ unless otherwise specified)
Symbol
Parameter
Standard
Measurement Condition
Min. Typ.
tSU
-
Resolution
-
Absolute Accuracy
Setup Time
RO
Output Resistance
IVREF
Reference Power Supply Input Current
4
(Note 1)
10
Unit
Max.
8
Bits
1.0
%
3
µs
20
kΩ
1.0
mA
NOTE:
1. Measurement results when using one D/A converter. The DAi register (i=0, 1) of the D/A converter, not being
used, is set to "0016". The resistor ladder in the A/D converter is excluded.
IVREF flows even if the VCUT bit in the AD0CON1 register is set to "0" (no VREF connection).
Rev. 1.00 Nov. 01, 2005 Page 297 of 330
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23. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=3.3V
Timing Requirements
(VCC1=VCC2= 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 23.24 External Clock Input
Symbol
Parameter
Standard
Min.
Unit
Max.
tc
External Clock Input Cycle Time
41
ns
tw(H)
External Clock Input High ("H") Width
18
ns
tw(L)
External Clock Input Low ("L") Width
18
tr
External Clock Rise Time
5
ns
tf
External Clock Fall Time
5
ns
ns
Table 23.25 Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Min.
Max.
Unit
tac1(RD-DB)
Data Input Access Time (RD standard)
(Note 1)
ns
tac1(AD-DB)
Data Input Access Time (AD standard, CS standard)
(Note 1)
ns
tac2(RD-DB)
Data Input Access Time (RD standard, when accessing a space with the multiplexed bus)
(Note 1)
ns
tac2(AD-DB)
Data Input Access Time (AD standard, when accessing a space with the multiplexed bus)
(Note 1)
ns
tsu(DB-BCLK)
Data Input Setup Time
30
tsu(RDY-BCLK)
RDY Input Setup Time
ns
40
ns
tsu(HOLD-BCLK) HOLD Input Setup Time
60
ns
th(RD-DB)
Data Input Hold Time
0
ns
th(BCLK-RDY)
RDY Input Hold Time
0
ns
th(BCLK-HOLD)
HOLD Input Hold Time
0
ns
td(BCLK-HLDA)
HLDA Output Delay Time
25
ns
NOTE:
1. Values can be obtained from the following equations, according to BCLK frequecncy and external bus cycles. Insert a
wait state or lower the operation frequency, f(BCLK), if the calculated value is negative.
9
10 X m
tac1(RD – DB) = f(BCLK) X 2
– 35
[ns] (if external bus cycle is aφ + bφ, m=(bx2)+1)
– 35
[ns] (if external bus cycle is aφ + bφ, n=a+b)
– 35
[ns] (if external bus cycle is aφ + bφ, m=(bx2)-1)
9
tac1(AD – DB) =
10 X n
f(BCLK)
9
tac2(RD – DB) =
10 X m
f(BCLK) X 2
tac2(AD – DB) =
109 X p
– 35
f(BCLK) X 2
[ns] (if external bus cycle is aφ + bφ, p={(a+b-1)x2}+1)
Rev. 1.00 Nov. 01, 2005 Page 298 of 330
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23. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=3.3V
Timing Requirements
(VCC1=VCC2= 3.0 to 3.6V, VSS= 0V at Topr = –20 to 85oC unless otherwise specified)
Table 23.26 Timer A Input (Count Source Input in Event Counter Mode)
Symbol
Standard
Parameter
Min.
Unit
Max.
tc(TA)
TAiIN Input Cycle Time
100
ns
tw(TAH)
TAiIN Input High ("H") Width
40
ns
tw(TAL)
TAiIN Input Low ("L") Width
40
ns
Table 23.27 Timer A Input (Gate Input in Timer Mode)
Standard
Symbol
Parameter
Min.
Max.
Unit
tc(TA)
TAiIN Input Cycle Time
400
ns
tw(TAH)
TAiIN Input High ("H") Width
200
ns
tw(TAL)
TAiIN Input Low ("L") Width
200
ns
Table 23.28 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(TA)
TAiIN Input Cycle Time
200
ns
tw(TAH)
TAiIN Input High ("H") Width
100
ns
tw(TAL)
TAiIN Input Low ("L") Width
100
ns
Table 23.29 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tw(TAH)
TAiIN Input High ("H") Width
100
ns
tw(TAL)
TAiIN Input Low ("L") Width
100
ns
Table 23.30 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(UP)
TAiOUT Input Cycle Time
2000
ns
tw(UPH)
TAiOUT Input High ("H") Width
1000
ns
tw(UPL)
TAiOUT Input Low ("L") Width
1000
ns
tsu(UP-TIN)
TAiOUT Input Setup Time
400
ns
th(TIN-UP)
TAiOUT Input Hold Time
400
ns
Rev. 1.00 Nov. 01, 2005 Page 299 of 330
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23. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=3.3V
Timing Requirements
(VCC1=VCC2= 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 23.31 Timer B Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
100
ns
tw(TBH)
TBiIN Input High ("H") Width (counted on one edge)
40
ns
tw(TBL)
TBiIN Input Low ("L") Width (counted on one edge)
40
ns
tc(TB)
TBiIN Input Cycle Time (counted on both edges)
200
ns
tw(TBH)
TBiIN Input High ("H") Width (counted on both edges)
80
ns
tw(TBL)
TBiIN Input Low ("L") Width (counted on both edges)
80
ns
Table 23.32 Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
400
Unit
tc(TB)
TBiIN Input Cycle Time
ns
tw(TBH)
TBiIN Input High ("H") Wdth
200
ns
tw(TBL)
TBiIN Input Low ("L") Width
200
ns
Table 23.33 Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(TB)
TBiIN Input Cycle Time
tw(TBH)
TBiIN Input High ("H") Width
200
ns
tw(TBL)
TBiIN Input Low ("L") Width
200
ns
400
ns
Table 23.34 A/D Trigger Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(AD)
ADTRG Input Cycle Time (required for trigger)
1000
ns
tw(ADL)
ADTRG Input Low ("L") Width
125
ns
Table 23.35 Serial I/O
Symbol
tc(CK)
Parameter
CLKi Input Cycle Time
Standard
Min.
Max.
200
Unit
ns
tw(CKH)
CLKi Input High ("H") Width
100
ns
tw(CKL)
CLKi Input Low ("L") Width
100
ns
td(C-Q)
TxDi Output Delay Time
th(C-Q)
TxDi Hold Time
0
ns
tsu(D-C)
RxDi Input Setup Time
30
ns
th(C-Q)
RxDi Input Hold Time
90
ns
80
ns
_______
Table 23.36 External Interrupt INTi Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(INH)
INTi Input High ("H") Width
250
ns
tw(INL)
INTi Input Low ("L") Width
250
ns
Rev. 1.00 Nov. 01, 2005 Page 300 of 330
REJ09B0271-0100
23. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=3.3V
Switching Characteristics
(VCC1=VCC2=3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 23.37 Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space)
Symbol
Parameter
Measurement
Condition
Standard
Min.
Unit
Max.
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (BCLK standard)
0
ns
th(RD-AD)
Address Output Hold Time (RD standard)
0
ns
th(WR-AD)
Address Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-CS)
Chip-Select Signal Output Delay Time
th(BCLK-CS)
Chip-Select Signal Output Hold Time (BCLK standard)
18
th(RD-CS)
Chip-Select Signal Output Hold Time (RD standard)
th(WR-CS)
Chip-Select Signal Output Hold Time (WR standard)
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
18
0
See Figure 23.1
td(BCLK-WR)
WR Signal Output Delay Time
WR Signal Output Hold Time
ns
ns
0
ns
(Note 1)
ns
18
-3
th(BCLK-WR)
ns
ns
ns
18
ns
0
ns
td(DB-WR)
Data Output Delay Time (WR standard)
(Note 2)
ns
th(WR-DB)
Data Output Hold Time (WR standard)
(Note 1)
ns
tw(WR)
WR Output Width
(Note 2)
ns
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
th(WR – DB) =
10 9
f(BCLK) X 2
– 20
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles.
9
tw(WR) =
10 x n
f(BCLK) X 2
– 15
[ns] (if external bus cycle is aφ + bφ, n=(b x 2)-1)
– 20
[ns]
9
td(DB – WR) =
10 x m
f(BCLK)
Rev. 1.00 Nov. 01, 2005 Page 301 of 330
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(if external bus cycle is aφ + bφ, m=b)
23. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=3.3V
Switching Characteristics
(VCC1 = VCC2 = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 23.38 Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
Symbol
Parameter
Measurement
Condition
Standard
Min.
Unit
Max.
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (BCLK standard)
0
ns
th(RD-AD)
Address Output Hold Time (RD standard)
(Note 1)
ns
th(WR-AD)
Address Output Hold Time (WR standard)
(Note 1)
td(BCLK-CS)
Chip-Select Signal Output Delay Time
18
th(BCLK-CS)
Chip-Select Signal Output Hold Time (BCLK standard)
th(RD-CS)
Chip-Select Signal Output Hold Time (RD standard)
th(WR-CS)
Chip-Select Signal Output Hold Time (WR standard)
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
ns
18
td(BCLK-WR)
WR Signal Output Delay Time
WR Signal Output Hold Time
ns
0
ns
(Note 1)
ns
(Note 1)
See Figure 23.1
ns
18
-3
th(BCLK-WR)
ns
ns
ns
18
ns
0
ns
td(DB-WR)
Data Output delay Time (WR standard)
(Note 2)
ns
th(WR-DB)
Data Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-ALE)
ALE Signal Output Delay Time (BCLK standard)
th(BCLK-ALE)
ALE Signal Output Hold Time (BCLK standard)
18
-2
ns
ns
td(AD-ALE)
ALE Signal Output Delay Time (address standard)
(Note 3)
ns
th(ALE-AD)
ALE Signal Output Hold Time (address standard)
(Note 4)
ns
tdz(RD-AD)
Address Output Float Start Time
8
NOTES:
1. Values can be obtained by the following equations, according to BLCK frequency.
th(RD – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(RD – CS) =
10 9
f(BCLK) X 2
–10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – DB) =
10 9
f(BCLK) X 2
– 20
[ns]
2. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles.
9
td(DB – WR) =
10 X m
– 25
f(BCLK) X 2
[ns] (if external bus cycle is aφ + bφ, m=(b+2)-1)
3. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles.
9
td(AD – ALE) =
10 x n
f(BCLK) X 2
– 20
[ns] (if external bus cycle is aφ + bφ, n=a)
4. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles.
9
th(ALE – AD) =
10 x n
f(BCLK) X 2
– 10
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[ns] (if external bus cycle is aφ + bφ, n=a)
ns
M32C/80 Group
23. Electrical Characteristics
Vcc1=Vcc2=3.3V
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
[Read Timing] (1φ + 1φ Bus Cycles)
BCLK
td(BCLK-CS)
th(BCLK-CS)
0ns.min
18ns.max(1)
CSi
th(RD-CS)
tcyc
0ns.min
td(BCLK-AD)
th(BCLK-AD)
18ns.max(1)
ADi
BHE
0ns.min
td(BCLK-RD)
18ns.max
th(RD-AD)
0ns.min
RD
th(BCLK-RD)
tac1(RD-DB)(2)
-3ns.min
tac1(AD-DB)(2)
DB
Hi-Z
tsu(DB-BCLK)
th(RD-DB)
30ns.min(1)
0ns.min
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. Varies with operation frequency.
tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2) + 1)
tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is aφ + bφ, n = a + b)
[Write Timing] (1φ + 1φ Bus Cycles)
BCLK
th(BCLK-CS)
td(BCLK-CS)
0ns.min
18ns.max
CSi
th(WR-CS)(3)
tcyc
td(BCLK-AD)
th(BCLK-AD)
18ns.max
ADi
BHE
0ns.min
td(BCLK-WR) tw(WR)(3)
th(WR-AD)(3)
18ns.max
WR,WRL,
WRH
th(BCLK-WR)
0ns.min
td(DB-WR)(3)
th(WR-DB)(3)
DBi
NOTE:
3. Varies with operation frequency.
td(DB-WR)=(tcyc x m-20)ns.min
(if external bus cycle is aφ + bφ, m=b)
th(WR-DB)=(tcyc/2-20)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
Measurement Conditions
• VCC1=VCC2=3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH=1.5V, VOL=1.5V
tcyc=
(if external bus cycle is aφ + bφ, n=(bx2)-1)
Figure 23.6 VCC1=VCC2=3.3V Timing Diagram (1)
Rev. 1.00 Nov. 01, 2005 Page 303 of 330
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10
9
f(BCLK)
23. Electrical Characteristics
M32C/80 Group
Vcc1=Vcc2=3.3V
Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space and using the multiplexed bus)
[ Read Timing ] (2φ +2φ Bus Cycles)
BCLK
td(BCLK-ALE)
th(BCLK-ALE)
18ns.max
-2ns.min
ALE
th(BCLK-CS)
tcyc
td(BCLK-CS)
0ns.min
18ns.max
th(RD-CS)(1)
CSi
td(AD-ALE)(1)
th(ALE-AD)
ADi
/DBi
(1)
Address
tsu(DB-BCLK) 30ns.min
Data input
tdz(RD-AD)
Address
8ns.max
td(BCLK-AD)
ADi
BHE
th(RD-DB)
tac2(RD-DB)(1)
18ns.max
(1)
td(BCLK-RD)
tac2(AD-DB)
th(BCLK-RD)
18ns.max
th(BCLK-AD)
0ns.min
0ns.min
th(RD-AD)
(1)
-3ns.min
RD
NOTE:
1. Varies with operation frequency:
td(AD-ALE)=(tcyc/2 x n-20)ns.min (if external bus cycle is aφ + bφ, n=a)
th(ALE-AD)=(tcyc/2 x n-10)ns.min (if external bus cycle is aφ + bφ, n=a)
th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)-1)
tac2(AD-DB)=(tcyc/2 x p-35)ns.max (if external bus cycle is aφ + bφ, p={(a+b-1) x 2}+1)
[ Write Timing ] (2φ +2φ Bus Cycles)
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
tcyc
td(BCLK-CS)
th(BCLK-CS)
(2)
th(WR-CS)
0ns.min
18ns.max
CSi
td(AD-ALE)
ADi
/DBi
(2)
(2)
th(ALE-AD)
Address
Address
Data output
td(DB-WR)
td(BCLK-AD)
(2)
(2)
th(WR-DB)
18ns.max
ADi
BHE
0ns.min
td(BCLK-WR)
WR,WRL,
WRH
18ns.max
NOTE:
2. Varies with operation frequency:
td(AD-ALE)=(tcyc/2 x n - 20)ns.min
(if external bus cycle is aφ + bφ, n=a)
th(ALE-AD)=(tcyc/2 x n -10)ns.min
(if external bus cycle is aφ + bφ, n=a)
th(WR-AD)=(tcyc/2-10)ns.min,
th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-20)ns.min
td(DB-WR)=(tcyc/2 x m-25)ns.min
(if external bus cycle is aφ + bφ, m=(b x 2)-1)
Figure 23.7 VCC1=VCC2=3.3V Timing Diagram (2)
Rev. 1.00 Nov. 01, 2005 Page 304 of 330
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th(BCLK-AD)
th(BCLK-WR)
th(WR-AD) (2)
0ns.min
Measurement Conditions:
• VCC1=VCC2=3.0 to 3.6V
• Input high and low voltage:
VIH=1.5V, VIL=0.5V
• Output high and low voltage:
VOH=1.5V, VOL=1.5V
9
tcyc= 10
f(BCLK)
M32C/80 Group
23. Electrical Characteristics
Vcc1=Vcc2=3.3V
tc(TA)
tw(TAH)
TAiIN Input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT Input
tw(UPL)
TAiOUT Input
(Counter increment/
decrement input)
In event counter mode
TAiIN Input
th(TIN–UP)
tsu(UP–TIN)
(When counting on falling edge)
TAiIN Input
(When counting on rising edge)
tc(TB)
tw(TBH)
TBiIN Input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG Input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
th(C–D)
RxDi
tw(INL)
INTi Input
tw(INH)
NMI input
2 CPU clock cycles +
300ns or more
("L" width)
Figure 23.8 VCC1=VCC2=3.3V Timing Diagram (3)
Rev. 1.00 Nov. 01, 2005 Page 305 of 330
REJ09B0271-0100
2 CPU clock cycles +
300ns or more
23. Electrical Characteristics
M32C/80 Group
Vcc1=Vcc2=3.3V
Memory Expansion Mode and Microprocessor Mode
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
td(BCLK–HLDA) td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
P50 to P52
Hi–Z
Measurement Conditions:
• VCC1=VCC2=3.0 to 3.6V
• Input high and low voltage: VIH=2.4V, VIL=0.6V
• Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 23.9 VCC1=VCC2=3.3V Timing Diagram (4)
Rev. 1.00 Nov. 01, 2005 Page 306 of 330
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th(BCLK–RDY)
24. Precautions (Reset)
M32C/80 Group
24. Precautions
24.1 Reset
Voltage applied to the VCC1 pin must meet the SVCC standard.
Table 24.1 Power Supply Increasing Slope
Symbol
Standard
Parameter
Min.
Power Supply Increasing Slope (VCC1)
SVCC
0.05
SVCC
Power Supply Increasing Slope
(VCC1)
V
SVCC
0V
Figure 24.1 SVCC Timing
Rev. 1.00 Nov. 01, 2005 Page 307 of 330
REJ09B0271-0100
Typ.
Unit
Max.
V/ms
24. Precautions (Bus)
M32C/80 Group
24.2 Bus
__________
24.2.1 HOLD Signal
When entering microprocessor mode or memory expansion mode from single-chip mode and using
HOLD input, set the PM01 and PM00 bits to "112" (microprocessor mode) or to "012" (memory expansion
mode) after setting the PD4_7 to PD4_0 bits in the PD4 register and the PD5_2 to PD5_0 bits in the PD5
register to "0" (input mode).
__________
_____
_______
_______
______ ______ ________ ______ _______
________
P40 to P47 (A16 to A22, A23, CS0 to CS3, MA8 to MA12) and P50 to P52 (RD/WR/BHE, RD/WRL/WRH)
__________
are not placed in high-impedance states even when a low-level ("L") signal is applied to the HOLD pin, if
the PM01 and PM00 bits are set to "112" (microprocessor mode) or to "012" (memory expansion mode)
after setting the PD4_7 to PD4_0 bits in the PD4 register and the PD5_2 to PD5_0 bits in the PD5 register
to "1" (output mode) in single-chip mode.
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24. Precautions (Special Function Registers (SFRs))
M32C/80 Group
24.3 Special Function Registers (SFRs)
24.3.1 Register Settings
Table 24.2 lists registers containing bits which can only be written to. Set these registers with immediate
values. When establishing the next value by altering the present value, write the present value to the
RAM as well as to the register. Transfer the next value to the register after making changes in the RAM.
Table 24.2 Registers with Write-only Bits
Register
Address
Register
Address
WDTS Register
000E16
U3BRG Register
032916
G0RI Register
00EC16
U3TB Register
032B16, 032A16
G1RI Register
012C16
U2BRG Register
033916
U1BRG Register
02E916
U2TB Register
033B16, 033A16
U1TB Register
02EB16, 02EA16
UDF Register
034416
Register(1)
034716, 034616
U4BRG Register
02F916
TA0
U4TB Register
02FB16, 02FA16
TA1 Register(1)
034916, 034816
TA11 Register
030316, 030216
TA2 Register(1)
034B16, 034A16
030516, 030416
TA3
Register(1)
034D16, 034C16
Register(1)
034F16, 034E16
TA21 Register
TA41 Register
030716, 030616
TA4
DTT Register
030C16
U0BRG Register
036916
ICTB2 Register
030D16
U0TB Register
036B16, 36A16
NOTE:
1. In one-shot timer mode and pulse width modulation mode only.
Rev. 1.00 Nov. 01, 2005 Page 309 of 330
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M32C/80 Group
24. Precautions (Clock Generation Circuit)
24.4 Clock Generation Circuit
24.4.1 CPU Clock
• When the CPU operating frequency is 24 MHz or more, use the following procedure for better EMC
(Electromagnetic Compatibility) performance.
1) Oscillator connected between the XIN and XOUT pins, or external clock applied to the
XIN pin, has less than 24 MHz frequency.
2) Use the PLL frequency synthesizer to multiply the main clock.
24.4.2 Sub Clock
Set the CM03 bit to "0" (XCIN-XCOUT drive capacity "LOW") when selecting the sub clock (XCIN-XCOUT) as
the CPU clock, or Timer A or Timer B count source (fC32).
24.4.2.1 Sub Clock Oscillation
When oscillating the sub clock, set the CM04 bit in the CM0 register to "1" (XCIN-XCOUT oscillation
function) after setting the CM07 bit in the CM0 register to "0" (clock other than sub clock) and the
CM03 bit to "1" (XCIN-XCOUT drive capacity "HIGH"). Set the CM03 bit to "0" after sub clock oscillation
stabilizes.
Set the sub clock as the CPU clock, or Timer A or Timer B count source (fC32) after the above settings
are completed.
24.4.2.2 Using Stop Mode
When the microcomputer enters stop mode, the CM03 bit is automatically set to "1" (XCIN-XCOUT drive
capacity "HIGH"). Use the following procedure to select the main clock as the CPU clock when entering stop mode.
1) Set the CM17 bit in the CM1 register to "0" (main clock).
2) Set the CM21 bit in the CM2 register to "0" (clock selected by the CM17 bit).
3) Set the CM07 bit in the CM0 register to "0" (clock selected by the CM21 bit divided by the MCD
register setting).
After exiting stop mode, wait for the sub clock oscillation to stabilize. Then set the CM03 bit to "0" and
the CM07 bit to "1" (sub clock).
24.4.2.3 Oscillation Parameter Matching
If the sub slock oscillation parameters have only been evaluated with the drive capacity "HIGH", the
parameters should be reevaluated for drive capacity "LOW".
Contact your oscillator manufacturer for details on matching parameters.
Rev. 1.00 Nov. 01, 2005 Page 310 of 330
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24. Precautions (Clock Generation Circuit)
M32C/80 Group
24.4.3 PLL Frequency Synthesizer
Stabilize supply voltage to meet the power supply standard when using the PLL frequency synthesizer.
Table 24.3 Power Supply Ripple
Symbol
Standard
Parameter
Min.
f(ripple)
Power Supply Ripple Tolerable Frequency (VCC1)
VP-P(ripple)
Power Supply Ripple Voltage Fluctuation Range
10
kHz
VCC1=5V
0.5
V
VCC1=3.3V
0.3
V
1
V/ms
0.3
V/ms
VCC1=5V
VCC(|
V/ T|)
Unit
Typ. Max.
Power Supply Ripple Voltage Fluctuation Rate
VCC1=3.3V
f(ripple)
f(ripple)
Power Supply Ripple Tolerable Frequency
(VCC1)
Vp-p(ripple)
Power Supply Ripple Amplitude
Voltage
VCC1
Vp-p(ripple)
Figure 24.2 Power Supply Fluctuation Timing
24.4.4 External Clock
Do not stop an external clock running if the main clock is selected as the CPU clock while the external
clock is applied to the XIN pin.
Do not set the CM05 bit in the CM0 register to "1" (main clock stopped) while the external clock input is
used for the CPU clock.
24.4.5 Clock Divide Ratio
Set the PM12 bit in the PM1 register to "0" (no wait state) when changing the MCD4 to MCD0 bit settings
in the MCD register.
24.4.6 Power Consumption Control
Stabilize the main clock, sub clock or PLL clock to switch the CPU clock source to each clock.
24.4.6.1 Wait Mode
When entering wait mode while the CM02 bit in the CM0 register is set to "1" (peripheral function stop
in wait mode), set the MCD4 to MCD0 bits in the MCD register to maintain the 10-MHz CPU clock
frequency or less.
When entering wait mode, the instruction queue reads ahead to instructions following the WAIT instruction, and the program stops. Write at least 4 NOP instructions after the WAIT instruction.
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24. Precautions (Clock Generation Circuit)
M32C/80 Group
24.4.6.2 Stop Mode
• Use the following procedure to select the main clock as the CPU clock when entering stop mode.
1) Set the CM17 bit in the CM1 register to "0" (main clock).
2) Set the CM21 bit in the CM2 register to "0" (clock selected by the CM17 bit).
3) Set the CM07 bit in the CM0 register to "0" (clock selected by the CM21 bit divided by the MCD
register setting).
If the PLL clock is selected as the CPU clock source, set the CM17 bit to "0" (main clock) and the
PLC07 bit in the PLC0 register to "0" (PLL off) before entering stop mode.
______
• The microcomputer cannot enter stop mode if a low-level signal ("L") is applied to the NMI pin.
Apply a high-level ("H") signal instead.
____________
• If stop mode is exited by any reset, apply an "L" signal to the RESET pin until a main clock oscillation is stabilized enough.
______
• If using the NMI interrupt to exit stop mode, use the following procedure to set the CM10 bit in the
CM1 register (all clocks stopped).
______
1) Exit stop mode with using the NMI interrupt.
2) Generate a dummy interrupt.
3) Set the CM10 bit to "1".
e.g.,
int
#63
; dummy interrupt
bset cm1
; all clocks stopped
/* dummy interrupt handling */
dummy
reit
• When entering stop mode, the instruction queue reads ahead to instructions following the instruction setting the CM10 bit in the CM1 register to "1" (all clocks stopped), and the program stops.
When the microcomputer exits stop mode, the instruction lined in the instruction queue is executed
before the interrupt routine for recovery is done.
Write the JMP.B instruction, as follows, after the instruction setting the CM10 bit in the CM1 register
to "1" (all clocks stopped).
e.g.,
bset 0, prcr
; protection removed
bset 0, cm1
; all clocks stopped
jmp.b LABEL_001
; JMP.B instruction executed (no instuction between JMP.B
; and LABEL.)
LABEL_001:
nop
; NOP (1)
nop
; NOP (2)
nop
; NOP (3)
nop
; NOP (4)
mov.b #0, prcr
; Protection set
•
•
•
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24. Precautions (Clock Generation Circuit)
24.4.6.3 Suggestions for Reducing Power Consumption
The followings are suggestions for reducing power consumption when programming or designing
systems.
Ports: I/O ports maintains the same state despite the microcomputer entering wait mode or stop
mode. Current flows through active output ports. Feedthrough current flows through input ports in a
high-impedance state. Set unassigned ports as input ports and stabilize electrical potential before
entering wait mode or stop mode.
A/D Converter: If the A/D conversion is not performed, set the VCUT bit in the AD0CON1 register
to "0" (no VREF connection). Set the VCUT bit to "1" (VREF connection) and wait at least 1µs before
starting the A/D conversion.
D/A Converter: Set the DAi bit (i=0, 1) in the DACON register to "0" (output disabled) and set the
DAi register to "0016" when the D/A conversion is not performed.
Peripheral Function Stop: Set the CM02 bit in the CM0 register while in wait mode to stop unnecessary peripheral functions. However, this does not reduce power consumption because the peripheral function clock (fc32) generating from the sub clock does not stop. When in low-speed mode
and low-power consumption mode, do not enter wait mode when the CM02 bit is set to "1" (peripheral clock stops in wait mode).
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24. Precautions (Protection)
24.5 Protection
The PRC2 bit setting in the PRCR register is changed to "0" (write disabled) when an instruction is written
to any address after the PRC2 bit is set to "1" (write enabled). Write instruction immediately after setting the
PRC2 bit to "1" to change registers protected by the PRC2 bit. Do not generate an interrupt or a DMA
transfer between the instruction to set the PRC2 bit to "1" and the following instruction.
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24. Precautions (Interrupts)
M32C/80 Group
24.6 Interrupts
24.6.1 ISP Setting
After reset, the ISP is set to "00000016". The program runs out of control if an interrupt is acknowledged
before the ISP is set. Therefore, the ISP must be set before an interrupt request is generated. Set the ISP
to an even address, which allows interrupt sequences to be executed at a higher speed.
_______
_______
To use NMI interrupt, set the ISP at the beginning of the program. The NMI interrupt can be acknowledged after the first instruction has been executed after reset.
_______
24.6.2 NMI Interrupt
_______
_______
• NMI interrupt cannot be denied. Connect the NMI pin to VCC via a resistor (pull-up) when not in use.
_______
• The P8_5 bit in the P8 register indicates the NMI pin value. Read the P8_5 bit only to determine the pin
_______
level after a NMI interrupt occurs.
_______
• "H" and "L" signals applied to the NMI pin must be over 2 CPU clock cycles + 300 ns wide.
_______
• NMI interrupt request may not be acknowledged if this and other interrupt requests are generated
simultaneously.
______
24.6.3 INT Interrupt
• Edge Sensitive
______
______
"H" and "L" signals applied to the INT0 to INT5 pins must be at least 250 ns wide, regardless of the CPU
clock.
• Level Sensitive
______
______
"H" and "L" signals applied to the INT0 to INT5 pins must be at least 1 CPU clock cycle + 200 ns wide.
For example, "H" and "L" must be at least 234ns wide if XIN=30MHz with no division.
______
______
• The IR bit setting may change to "1" (interrupt requested) when switching the polarity of the INT0 to INT5
pins. Set the IR bit to "0" (no interrupt requested) after selecting the polarity. Figure 24.3 shows an
______
example of the switching procedure for the INT interrupt.
Set the ILVL2 to ILVL0 bits in the INTiIC
register (i = 0 to 5) to "0002" (level 0)
(INT interrupt disabled)
Set the POL bit in the INTiIC register
Set the IR bit in the INTiIC register to "0"
Set the ILVL2 to ILVL0 bits to "0012" (level 1)
to "1112" (level 7)
(INT interrupt request acknowledgement enabled)
______
Figure 24.3 Switching Procedure for INT Interrupt
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24. Precautions (Interrupts)
24.6.4 Watchdog Timer Interrupt
Reset the watchdog timer after a watchdog timer interrupt occurs.
24.6.5 Changing Interrupt Control Register
To change the interrupt control register while the interrupt request is denied, follow the instructions below.
Changing IR bit
The IR bit setting may not change to "0" (no interrupt requested) depending on the instructions written.
If this is a problem, use the following instruction to change the register: MOV
Changing Bits Except IR Bit
When an interrupt request is generated while executing an instruction, the IR bit may not be set to "1"
(interrupt requested) and the interrupt may be ignored. If this is a problem, use the following instructions
to change the register: AND, OR, BCLR, BSET
24.6.6 Changing IIOiIR Register (i = 0 to 4)
Use the following instructions to set bits 1 to 7 in the IIOilR register to "0" (no interrupt requested): AND,
BCLR
24.6.7 Changing RLVL Register
The DMAII bit is indeterminate after reset. When using the DMAII bit to generate an interrupt, set the
interrupt control register after setting the DMAII bit to "0" (interrupt priority level 7 available for interrupts).
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24. Precautions (DMAC)
24.7 DMAC
• Set DMAC-associated registers while the MDi1 and MDi0 bits (i=0 to 3) in the channel to be used are set
to "002" (DMA disabled). Set the MDi1 and MDi0 bits to "012" (single transfer) or "112" (repeat transfer)
at the end of setup procedure to start DMA requests.
• Do not set the DRQ bit in the DMiSL register to "0" (no request).
If a DMA request is generated but the receiving channel is not ready to receive(1), the DMA transfer does
not occur and the DRQ bit is set to "0".
NOTE:
1. The MDi1 and MDi0 bits are set to "002" or the DCTi register is set to "000016" (transferred 0
times).
• To start a DMA transfer by a software trigger, set the DSR bit and DRQ bit in the DMiSL register to "1"
simultaneously.
e.g.,
OR.B #0A0h,DMiSL
; Set the DSR and DRQ bits to "1" simultaneously
• Do not generate a channel i DMA request when setting the MDi1 and MDi0 bits in the DMDj register
(j=0,1) corresponding to channel i to "012" (single transfer) or "112" (repeat transfer), if the DCTi register
of channel i is set to "1".
• Select the peripheral function which causes the DMA request after setting the DMA-associated regis______
ters. If none of the conditions above (setting INT interrupt as DMA request source) apply, do not write
"1" to the DCTi register.
• Enable DMA(2) after setting the DMiSL register (i=0 to 3) and waiting six BCLK cycles or more by
program.
NOTE:
2. DMA is enabled when the values set in the MDi1 and MDi0 bits in the DMDj register are
changed from "002" (DMA disabled) to "012" (single transfer) or "112" (repeat transfer).
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24. Precautions (Timer)
24.8 Timer
24.8.1 Timers A and B
Timers stop after reset. Set the TAiS(i=0 to 4) bit or TBjS(j=0 to 5) bit in the TABSR register or TBSR
register to "1" (starts counting) after setting operating mode, count source and counter.
The following registers and bits must be set while the TAiS bit or TBjS bit is set to "0" (stops counting).
• TAiMR, TBjMR register
• TAi, TBj register
• UDF register
• TAZIE, TA0TGL, TA0TGH bits in the ONSF register
• TRGSR register
24.8.2 Timer A
The TA1OUT, TA2OUT and TA4OUT pins are placed in high-impedance states when a low-level ("L") signal
_______
is applied to the NMI pin while the INV03 and INV02 bits in the INVC0 register are set to "112" (forced
_______
cutoff of the three-phase output by an "L" signal applied to the NMI pin).
24.8.2.1 Timer A (Timer Mode)
• The TAiS bit (i=0 to 4) in the TABSR register is set to "0" (stops counting) after reset. Set the TAiS
bit to "1" (starts counting) after selecting an operating mode and setting the TAi register.
• The TAi register indicates the counter value during counting at any given time. However, the
counter is "FFFF16" when reloading. The setting value can be read after setting the TAi register
while the counter stops and before the counter starts counting.
24.8.2.2 Timer A (Event Counter Mode)
• The TAiS (i=0 to 4) bit in the TABSR register is set to "0" (stops counting) after reset. Set the TAiS
bit to "1" (starts counting) after selecting an operating mode and setting the TAi register.
• The TAi register indicates the counter values during counting at any given time. However, the
counter will be "FFFF16" during underflow and "000016" during overflow, when reloading. The setting value can be read after setting the TAi register while the counter stops and before the counter
starts counting.
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24. Precautions (Timer)
24.8.2.3 Timer A (One-shot Timer Mode)
• The TAiS (i=0 to 4) bit in the TABSR register is set to "0" (stops counting) after reset. Set the TAiS
bit to "1" (starts counting) after selecting an operating mode and setting the TAi register.
• The followings occur when the TABSR register is set to "0" (stops counting) while counting:
- The counter stops counting and the microcomputer reloads contents of the reload register.
- The TAiOUT pin becomes low ("L").
- The IR bit in the TAiIC register is set to "1" (interrupt requested) after one CPU clock cycle.
• The output of the one-shot timer is synchronized with an internal count source. When set to an
external trigger, there is a delay of one count source cycle maximum, from trigger input to the TAiIN
pin to the one-shot timer output.
• The IR bit is set to "1" when the following procedures are performed to set timer mode:
- selecting one-shot timer mode after reset.
- switching from timer mode to one-shot timer mode.
- switching from event counter mode to one-shot timer mode.
Therefore, set the IR bit to "0" to generate a timer Ai interrupt (IR bit) after performing these procedures.
• When a trigger is generated while counting, the reload register reloads and continues counting
after the counter has decremented once following a re-trigger. To generate a trigger while counting,
wait at least 1 count source cycle after the previous trigger has been generated and generate a retrigger.
• If an external trigger input is selected to start counting in timer A one-shot timer mode, do not
provide another external trigger input again for 300 ns before the timer A counter value reaches
"000016". One-shot timer may stop counting.
24.8.2.4 Timer A (Pulse Width Modulation Mode)
• The TAiS(i=0 to 4) bit in the TABSR register is set to "0" (stops counting) after reset. Set the TAiS bit
to "1" (starts counting) after selecting an operating mode and setting the TAi register.
• The IR bit is set to "1" when the following procedures are performed to set timer mode:
- Selecting PWM mode after reset
- Switching from timer mode to PWM mode
- Switching from event counter mode to PWM mode
Therefore, set the IR bit to "0" by program to generate a timer Ai interrupt (IR bit) after performing
these procedures.
• The followings occur when the TAiS bit is set to "0" (stops counting) while PWM pulse is output:
- The counter stops counting
- Output level changes to low ("L") and the IR bit changes to "1" when the TAiOUT pin is held high ("H")
- The IR bit and the output level remain unchanged when TAiOUT pin is held "L"
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24. Precautions (Timer)
24.8.3 Timer B
24.8.3.1 Timer B (Timer Mode, Event Counter Mode)
• The TBiS (i=0 to 5) bit is set to "0" (stops counting) after reset. Set the TBiS bit to "1" (starts
counting) after selecting an operating mode and setting TBi register.
The TB2S to TB0S bits are bits 7 to 5 in the TABSR register. The TB5S to TB3S bits are bits 7 to 5
in the TBSR register.
• The TBi register indicates the counter value during counting at any given time. However, the
counter is "FFFF16" when reloading. The setting value can be read after setting the TBi register
while the counter stops and before the counter starts counting.
24.8.3.2 Timer B (Pulse Period/Pulse Width Measurement Mode)
• The IR bit in the TBiIC (i=0 to 5) register is set to "1" (interrupt requested) when the valid edge of a
pulse to be measured is input and when the timer Bi counter overflows. The MR3 bit in the TBiMR
register determines the interrupt source within an interrupt routine.
• Use another timer to count how often the timer counter overflows when an interrupt source cannot
be determined by the MR3 bit, such as when a pulse to be measured is input at the same time the
timer counter overflows.
• To set the MR3 bit in the TBiMR register to "0" (no overflow), set the TBiMR register after the MR3
bit is set to "1" (overflow) and one or more cycles of the count source are counted, while the TBiS
bits in the TABSR and TBSR registers are set to "1" (starts counting).
• The IR bit in the TBiIC register is used to detect overflow only. Use the MR3 bit only to determine
interrupt source within an interrupt routine.
• Indeterminate values are transferred to the reload register during the first valid edge input after
counting is started. Timer Bi interrupt request is not generated at this time.
• The counter value is indeterminate when counting is started. Therefore, the MR3 bit setting may
change to "1" (overflow) and causes timer Bi interrupt requests to be generated until a valid edge is
input after counting is started.
• The IR bit may be set to "1" (interrupt requested) if the MR1 and MR0 bits in the TBiMR register are
set to a different value after a count begins. If the MR1 and MR0 bits are rewritten, but to the same
value as before, the IR bit remains unchanged.
• Pulse width measurement measures pulse width continuously. Use program to determine whether
measurement results are high ("H") or low ("L").
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24. Precautions (Serial I/O)
24.9 Serial I/O
24.9.1 Clock Synchronous Serial I/O Mode
_______
The RTS2 and CLK2 pins are placed in high-impedance states when a low-level ("L") signal is applied to
______
the NMI pin while the INV03 and INV02 bits in the INVC0 register are set to "112" (forced cutoff of the
_______
three-phase output by an "L" signal applied to the NMI pin).
24.9.1.1 Transmission /Reception
_______
________
When the RTS function is used while an external clock is selected, the output level of the RTSi pin is
held "L" indicating that the microcomputer is ready for reception. The transmitting microcomputer is
________
notified that reception is possible. The output level of the RTSi pin becomes high ("H") when reception
________
________
begins. Therefore, connecting the RTSi pin to the CTSi pin of the transmitting microcomputer synchro_______
nizes transmission and reception. The RTS function is disabled if an internal clock is selected.
24.9.1.2 Transmission
When an external clock is selected while the CKPOL bit in the UiC0 (i=0 to 4) register is set to "0" (data
is transmitted on the falling edge of the transfer clock and received on the rising edge) and the external
clock is held "H", or when the CKPOL bit is set to "1" (data is transmitted on the rising edge of the
transfer clock and received on the falling edge) and the external clock is held "L", meet the following
conditions:
• Set the TE bit in the UiC1 register to "1" (receive enabled)
• Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
________
________
• Apply "L" signal to the CTSi pin if the CTS function is selected
24.9.1.3 Reception
Activating the transmitter in clock synchronous serial I/O mode generates the shift clock. Therefore,
set for transmission even if the microcomputer is used for reception only. Dummy data is output from
the TxDi pin while receiving.
If an internal clock is selected, the shift clock is generated when the TE bit in the UiC1 registers is set
to "1" (receive enabled) and dummy data is set in the UiTB register. If an external clock is selected, the
shift clock is generated when the external clock is input into CLKi pin while the TE bit is set to "1"
(receive enabled) and dummy data is set in the UiTB register.
When receiving data consecutively while the RE bit in the UiC1 register is set to "1" (data in the UiRB
register) and the next data is received by the UARTi reception register, an overrun error occurs and
the OER bit in the UiRB register is set to "1" (overrun error). In this case, the UiRB register is indeterminate. When overrun error occurs, program both reception and transmission registers to retransmit
earlier data. The IR bit in the SiRIC does not change when an overrun error occurs.
When receiving data consecutively, feed dummy data to the low-order byte in the UiTB register every
time a reception is made.
When an external clock is selected while the CKPOL bit in the UiC0 register is set to "0" (data is
transmitted on the falling edge of the transfer clock and received on the rising edge) and the external
clock is held "H" or when the CKPOL bit is set to "1" (data is transmitted on the rising edge of the
transfer clock and received on the falling edge) and the external clock is held "L", meet the following
conditions:
• Set the RE bit in the UiC1 register to "1" (receive enabled)
• Set the TE bit in the UiC1 register to "1" (transmit enabled)
• Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
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24. Precautions (Serial I/O)
24.9.2 UART Mode
Set the UiERE bit (i=0 to 4) in the UiC1 register after setting the UiMR register.
24.9.3 Special Mode 1 (I2C Mode)
To generate the start condition, stop condition or restart condition, set the STSPSEL bit in the UiSMR4
register to "0" first. Then, change each condition generating bit (the STAREQ bit, STPREQ bit or
RSTAREQ bit) setting from "0" to "1" after going through a half cycle of the transfer clock.
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24. Precautions (A/D Converter)
M32C/80 Group
24.10 A/D Converter
• Set the AD0CON0 (bit 6 excluded), AD0CON1, AD0CON2, AD0CON3, and AD0CON4 registers while
the A/D conversion is stopped (before a trigger is generated).
• Wait a minimum of 1µs before starting the A/D conversion when changing the VCUT bit setting in the
AD0CON1 register from "0" (VREF no connection) to "1" (VREF connection).
Change the VCUT bit setting from "1" to "0" after the A/D conversion is completed.
• Insert capacitors between the AVCC pin, VREF pin, analog input pin ANi (i=0 to 7) and AVSS pin to
prevent latch-ups and malfunctions due to noise, and to minimize conversion errors. The same applies
to the VCC and VSS pins. Figure 24.4 shows the use of capacitors to reduce noise.
Microcomputer
VCC1
VCC1
VCC
AVCC
VSS
VREF
C4
C1
C2
AVSS
VCC2
C3
VCC
C5
ANi
VSS
ANi: ANi, AN0i, AN15i and AN2i (i=0 to 7)
NOTES:
1. C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF, C5≥0.1µF (reference)
2. Use thick and shortest possible wiring to connect capacitors.
Figure 24.4 Use of Capacitors to Reduce Noise
• Set the bit in the port direction register, which corresponds to the pin being used as the analog input, to
__________
"0" (input mode). Set the bit in the port direction register, which corresponds to the ADTRG pin, to "0"
(input mode) if the TRG bit in the AD0CON0 register is set to "1" (external trigger).
• When generating a key input interrupt, do not use the AN4 to AN7 pins as analog input pins (key input
interrupt request is generated when the A/D input voltage becomes "L").
• The φAD frequency must be 16MHz or less. When the sample and hold function is not activated, the φAD
frequency must be 250 kHz or more. If the sample and hold function is activated, the φAD frequency
must be 1MHz or more.
• Set the CH2 to CH0 bits in the AD0CON0 register or the SCAN1 and SCAN0 bits in the AD0CON1
register to re-select analog input pins when changing A/D conversion mode.
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24. Precautions (A/D Converter)
• AVCC = VREF = VCC1, A/D input voltage (for AN0 to AN7, ANEX0, and ANEX1) ≤ VCC1.
• Wrong values are stored in the AD0i register (i=0 to 7) if the CPU reads the AD0i register while the AD0i
register stores results from a completed A/D conversion. This occurs when the CPU clock is set to a
divided main clock or a sub clock.
In one-shot mode or single sweep mode, read the corresponding AD0i register after verifying that the A/D
conversion has been completed. The IR bit in the AD0IC register determines the completion of the A/D
conversion.
In repeat mode, repeat sweep mode 0 and repeat sweep mode 1 use an undivided main clock as the
CPU clock.
• Conversion results of the A/D converter are indeterminate if the ADST bit in the AD0CON0 register is set
to "0" (A/D conversion stopped) and the conversion is forcibly terminated by program during the A/D
conversion. The AD0i register not performing the A/D conversion may also be indeterminate.
If the ADST bit is changed to "0" by program, during the A/D conversion, do not use any values obtained
from the AD0i registers.
• External triggers cannot be used in DMAC operating mode. Do not read the AD00 register by program.
• Do not perform the A/D conversion in wait mode.
• Set the MCD4 to MCD0 bits in the MCD register to "100102" (no division) if using the sample and hold
function.
• Do not acknowledge any interrupt requests, even if generated, before setting the ADST bit, if the A/D
conversion is terminated by setting the ADST bit in the AD0CON0 register to "0" (A/D conversion
stopped) while the microcomputer is A/D converting in single sweep mode.
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24. Precautions (Intelligent I/O)
24.11 Intelligent I/O
24.11.1 Register Setting
Operations, controlled by the values written to the G0RI and G1RI, G0TO and G1TO, G0CR and G1CR,
G0RB and G1RB, G0MR and G1MR, G0EMR and G1EMR, G0ETC and G1ETC, G0ERC and G1ERC,
G0IRF, G1IRF, G0TB and G1TB, G0CMP0 to G0CMP3, G1CMP0 to G1CMP3, G0MSK0 and G0MSK1,
G1MSK0 and G1MSK1, G0TCRC and G1TCRC, G0RCRC and G1RCRC registers are affected by the
transfer clock.
Set trasfer clock before setting the G0RI and G1RI, G0TO and G1TO, G0CR and G1CR, G0RB and
G1RB, G0MR and G1MR, G0EMR and G1EMR, G0ETC and G1ECT, G0ERC and G1ERC, G0IRF and
G1IRF, G0TB and G1TB, G0CMP0 to G0CMP3, G1CMP0 to G1CMP3, G0MSK0 and G0MSK1,
G1MSK0 and G1MSK1, G0TCRC and G1TCRC, G0RCRC and G1RCRC registers.
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24. Precautions (Programmable I/O Ports)
M32C/80 Group
24.12 Programmable I/O Ports
• Because ports P72 to P75, P80, and P81 have three-phase PWM output forced cutoff function, they are
_______
affected by the three-phase motor control timer function and the NMI pin when these ports are set for
output functions (port output, timer output, three-phase PWM output, serial I/O output, intelligent I/O
output).
_______
Table 24.4 shows the INVC0 register setting, the NMI pin input level and the state of output ports.
_______
Table 24.4 INVC0 Register and the NMI Pin
Setting Value of the INVC0 Register
INV02 Bit
INV03 Bit
Signal level Applied
to the NMI Pin
P72 to P75, P80, P81 Pin States
(When Setting Them as Output Pins)
0
(Not Using the Three-Phase
Motor Control Timer
Functions)
-
-
Provides functions selected by the
PS1, PSL1, PSC, PS2, PSL2
registers
1
(Using the Three-Phase
Motor Control Timer
Functions)
0
(Three-Phase Motor Control
Timer Output Disabled)
-
High-impedance state
1
(Three-Phase Motor Control
Timer Output Enabled)(1)
H
Provides functions selected by the
PS1, PSL1, PSC, PS2, PSL2
registers
L
High-impedance state
(Forcibly Terminated)
NOTE:
_______
1. The INV03 bit is set to "0" after a low-level ("L") signal is applied to the NMI pin.
• The availability of pull-up resistors is indeterminate until internal power voltage stabilizes, if the RESET
pin is held "L".
• The input threshold voltage varies between programmable I/O ports and peripheral functions. Therefore, if the level of the voltage applied to a pin shared by both programmable I/O ports and peripheral
functions is not within the recommended operating condition, VIH and VIL (neither "H" nor "L"), the level
may vary depending on the programmable ports and peripheral functions.
Rev. 1.00 Nov. 01, 2005 Page 326 of 330
REJ09B0271-0100
M32C/80 Group
24. Precautions (Noise)
24.13 Noise
Connect a bypass capacitor (0.1µF or more) between VCC and VSS by shortest path, using thick wires.
Rev. 1.00 Nov. 01, 2005 Page 327 of 330
REJ09B0271-0100
Package Dimensions
M32C/80 Group
Package Dimensions
JEITA Package Code
P-LQFP100-14x14-0.50
RENESAS Code
PLQP0100KB-A
Previous Code
100P6Q-A / FP-100U / FP-100UV
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
c1
Reference
Symbol
c
E
*2
HE
b1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
100
26
1
ZE
Terminal cross section
25
Index mark
ZD
y
*3
e
A1
c
A
A2
F
bp
e
x
y
ZD
ZE
L
L1
L
x
L1
Detail F
JEITA Package Code
P-QFP100-14x20-0.65
RENESAS Code
PRQP0100JB-A
Previous Code
100P6S-A
Dimension in Millimeters
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
MASS[Typ.]
1.6g
HD
*1
D
80
51
81
50
HE
*2
E
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
Reference
Symbol
100
31
30
c
F
A2
Index mark
ZD
A1
A
1
L
*3
e
y
Rev. 1.00 Nov. 01, 2005 Page 328 of 330
REJ09B0271-0100
bp
Detail F
D
E
A2
HD
HE
A
A1
bp
c
e
y
ZD
ZE
L
Dimension in Millimeters
Min Nom Max
19.8 20.0 20.2
13.8 14.0 14.2
2.8
22.5 22.8 23.1
16.5 16.8 17.1
3.05
0.1 0.2
0
0.25 0.3 0.4
0.13 0.15 0.2
0°
10°
0.5 0.65 0.8
0.10
0.575
0.825
0.4 0.6 0.8
Register Index
M32C/80 Group
Register Index
A
AD00 to AD07 226
AD0CON0 222
AD0CON1 223
AD0CON2 224
AD0CON3 225
AIER 101
C
CCS 255
CM0 58, 107
CM1 59
CM2 61
CPSRF 62
CRCD 239
CRCIN 239
D
DA0, DA1 238
DACON 238
DCT0 to DCT3 114
DM0SL to DM3SL 111
DMA0 to DMA3 115
DMD0, DMD1 113
DRA0 to DRA3 115
DRC0 to DRC3 114
DS 39
DSA0 to DSA3 115
DTT 161
E
EWCR0 to EWCR3 45
G
G0CMP0 to G0CMP3 254
G0CR, G1CR 247
G0DR, G1DR 253
G0EMR 249
G0ERC, G1ERC 251
G0ETC 250
G0IRF 252
G0MR 248
G0MSK0, G0MSK1 254
Rev. 1.00 Nov. 01, 2005 Page 329 of 330
REJ09B0271-0100
G0RB, G1RB 247
G0RCRC, G1RCRC 254
G0RI, G1RI 246
G0TB, G1TB 253
G0TCRC, G1TCRC 254
G0TO, G1TO 246
G1CMP0 to G1CMP3 254
G1EMR 249
G1ETC 250
G1IRF 253
G1MR 248
G1MSK0, G1MSK1 254
I
ICTB2 162
IDB0, IDB1 161
IFSR 99, 176
IIO0IE to IIO4IE 104
IIO0IR to IIO4IR 103
Interrupt Control 90, 91
INVC0 159
INVC1 160
M
MCD
60
O
ONSF
133
P
P0 to P15 268
PCR 276
PD0 to PD15 267
PLC0 63
PLC1 63
PM0 36
PM1 37
PM2 64
PRCR 81
PS0 269
PS1 269
PS2 270
PS3 270
Register Index
M32C/80 Group
PSC
PSC3
PSD1
PSL0
PSL1
PSL2
PSL3
PUR0
PUR1
PUR2
PUR3
273
274
274
271
271
272
272
275
275
275
276
R
RLVL 92, 121
RMAD0 to RMAD7 101
T
TA0 to TA4 131
TA0MR to TA4MR 132, 137, 140, 143, 145
TA1, TA2, TA4, TA11, TA21, TA41 162
TA1MR, TA2MR, TA4MR 164
TABSR 132, 148, 163
TB0 to TB5 147
TB0MR to TB5MR 148, 150, 152, 154
TB2 163
TB2MR 164
TB2SC 162
TBSR 149
TCSPR 62, 134
TRGSR 134, 163
U
U0BRG to U4BRG 170
U0C0 to U4C0 171
U0C1 to U4C1 172
U0MR to U4MR 170
U0RB to U4RB 169
U0SMR to U4SMR 172
U0SMR2 to U4SMR2 173
U0SMR3 to U4SMR3 174
U0SMR4 to U4SMR4 175
U0TB to U4TB 169
UDF 133
Rev. 1.00 Nov. 01, 2005 Page 330 of 330
REJ09B0271-0100
W
WDC 106
WDTS 106
X
X0R to X15R
XYC 241
241
Y
Y0R to Y15R
241
REVISION HISTORY
Rev.
Date
1.00
Nov., 05
M32C/80 Group Hardware Manual
Description
Summary
Page
New Document
C-1
RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER
HARDWARE MANUAL
M32C/80 Group
Publication Data :
Rev.1.00 Nov. 01, 2005
Published by : Sales Strategic Planning Div.
Renesas Technology Corp.
© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
M32C/80 Group
Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan