STMicroelectronics M28C17-120P6T 16k 2k x 8 parallel eeprom with software data protection Datasheet

M28C17
16K (2K x 8) PARALLEL EEPROM
with SOFTWARE DATA PROTECTION
NOT FOR NEW DESIGN
FAST ACCESS TIME: 90ns
SINGLE 5V ± 10% SUPPLY VOLTAGE
LOW POWER CONSUMPTION
FAST WRITE CYCLE:
– 64 Bytes Page Write Operation
– Byte or Page Write Cycle: 3ms Max
ENHANCED END OF WRITE DETECTION:
– Ready/Busy Open Drain Output
– Data Polling
– Toggle Bit
PAGE LOAD TIMER STATUS BIT
HIGH RELIABILITY SINGLE POLYSILICON,
CMOS TECHNOLOGY:
– Endurance >100,000 Erase/Write Cycles
– Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
SOFTWARE DATA PROTECTION
M28C17 is replaced by the products
described on the document M28C16A
DESCRIPTION
The M28C17 is a 2K x 8 low power Parallel
EEPROM fabricated with SGS-THOMSON proprietary single polysilicon CMOS technology. The
device offers fast access time with low power dissipation and requires a 5V power supply.
The M28C17 offers the same features than the
M28C16, in addition to the Ready/Busy pin.
The circuit has been designed to offer a flexible
microcontroller interface featuring both hardware
28
1
PDIP28 (P)
28
1
SO28 (MS)
300 mils
Figure 1. Logic Diagram
VCC
11
A0 - A10
8
A0-A10
W
Table 1. Signal Names
PLCC32 (K)
DQ0-DQ7
M28C17
E
RB
Address Input
DQ0 - DQ7
Data Input / Output
W
Write Enable
E
Chip Enable
G
Output Enable
RB
Ready / Busy
VCC
Supply Voltage
VSS
Ground
November 1997
This is information on a product still in production but not recommended for new design.
G
VSS
AI01487
1/17
M28C17
VCC
W
NC
A8
A9
NC
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI01506B
RB
DU
VCC
W
NC
28
1
27
2
26
3
25
4
24
5
23
6
22
7
M28C17
21
8
20
9
19
10
18
11
17
12
13
16
14
15
A7
NC
RB
NC
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Figure 2B. LCC Pin Connections
1 32
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
9
M28C17
25
A8
A9
NC
NC
G
A10
E
DQ7
DQ6
17
DQ1
DQ2
VSS
DU
DQ3
DQ4
DQ5
Figure 2A. DIP Pin Connections
AI01508C
Warning: NC = Not Connected.
Warning: NC = Not Connected, DU = Don’t Use.
Figure 2C. SO Pin Connections
DESCRIPTION (cont’d)
and software handshaking with Ready/Busy, Data
Polling and Toggle Bit. The M28C17 supports 64
byte page write operation. A Software Data Protection (SDP) is also possible using the standard
JEDEC algorithm.
RB
NC
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
M28C17
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI01507B
Warning: NC = Not Connected.
2/17
VCC
W
NC
A8
A9
NC
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
PIN DESCRIPTION
Addresses (A0-A10). The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E). The chip enable input must be
low to enable all read/write operations. When Chip
Enable is high, power consumption is reduced.
Output Enable (G). The Output Enable input controls the data output buffers and is used to initiate
read operations.
Data In/ Out (DQ0 - DQ7). Data is written to or read
from the M28C17 through the I/O pins.
Write Enable (W). The Write Enable input controls
the writing of data to the M28C17.
Ready/Busy (RB). Ready/Busy is an open drain
output that can be used to detect the end of the
internal write cycle.
M28C17
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
Ambient Operating Temperature
– 40 to 125
°C
TSTG
Storage Temperature Range
– 65 to 150
°C
VCC
Supply Voltage
– 0.3 to 6.5
V
VIO
Input/Output Voltage
– 0.3 to VCC +0.6
V
VI
Input Voltage
– 0.3 to 6.5
V
4000
V
TA
VESD
Electrostatic Discharge Voltage (Human Body model)
(2)
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. 100pF through 1500Ω; MIL-STD-883C, 3015.7
Table 3. Operating Modes (1)
Mode
E
G
W
DQ0 - DQ7
Standby
1
X
X
Hi-Z
Output Disable
X
1
X
Hi-Z
Write Disable
X
X
1
Hi-Z
Read
0
0
1
Data Out
Write
0
1
0
Data In
Chip Erase
0
V
0
Hi-Z
Note: 1. 0 = VIL; 1 = VIH; X = VIL or VIH; V = 12 ± 5%.
OPERATION
In order to prevent data corruption and inadvertent
write operations an internal VCC comparator inhibits
Write operation if VCC is below VWI (see Table 7).
Access to the memory in write mode is allowed after
a power-up as specified in Table 7.
Read
The M28C17 is accessed like a static RAM. When
E and G are low with W high, the data addressed
is presented on the I/O pins. The I/O pins are high
impedance when either G or E is high.
Write
Write operations are initiated when both W and E
are low and G is high.The M28C17 supports both
E and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurs last and the Data on the rising edge of E or
W which ever occurs first. Once initiated the write
operation is internally timed until completion.
Page Write
Page write allows up to 64 bytes to be consecutively latched into the memory prior to initiating a
programming cycle. All bytes must be located in a
single page address, that is A6-A10 must be the
same for all bytes. The page write can be initiated
during any byte write operation.
Following the first byte write instruction the host
may send another address and data with a minimum data transfer rate of 1/tWHWH (see Figure 13).
If a transition of E or W is not detected within tWHWH,
the internal programming cycle will start.
Chip Erase
The contents of the entire memory may be erased
to FFh by use of the Chip Erase command by
setting Chip Enable (E) Low and Output Enable
(G) to VCC + 7.0V. The chip is cleared when a 10ms
low pulse is applied to the Write Enable pin.
3/17
M28C17
Figure 3. Block Diagram
RB
VPP GEN
A0-A5
ADDRESS
LATCH
X DECODE
A6-A10
(Page Address)
RESET
E
G
W
CONTROL LOGIC
64K ARRAY
ADDRESS
LATCH
Y DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
AI01488
Microcontroller Control Interface
The M28C17 provides two write operation status
bits and one status pin that can be used to minimize
the system write cycle. These signals are available
on the I/O port bits DQ7 or DQ6 of the memory
during programming cycle only, or as the RB signal
on a separate pin.
Figure 4. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP
TB
PLTS Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DP = Data Polling
TB = Toggle Bit
PLTS = Page Load Timer Status
Data Polling bit (DQ7). During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
4/17
ished the true logic value appears on DQ7 in the
read cycle.
Toggle bit (DQ6). The M28C17 offers another way
for determining when the internal write cycle is
completed. During the internal Erase/Write cycle,
DQ6 will toggle from "0" to "1" and "1" to "0" (the
first read value is "0") on subsequent attempts to
read the memory. When the internal cycle is completed the toggling will stop and the device will be
accessible for a new Read or Write operation.
Page Load Timer Status bit (DQ5). In the Page
Write mode data may be latched by E or W. Up to
64 bytes may be input. The Data output (DQ5)
indicates the status of the internal Page Load
Timer. DQ5 may be read by asserting Output Enable Low (tPLTS). DQ5 Low indicates the timer is
running, High indicates time-out after which the
write cycle will start and no new data may be input.
Ready/Busy pin. The RB pin provides a signal at
its open drain output which is low during the
erase/write cycle, but which is released at the
completion of the programming cycle.
M28C17
Figure 5. Software Data Protection Enable Algorithm and Memory Write
WRITE AAh in
Address 555h
Page
Write
Instruction
(Note 1)
WRITE AAh in
Address 555h
Page
Write
Instruction
(Note 1)
WRITE 55h in
Address 2AAh
WRITE 55h in
Address 2AAh
WRITE A0h in
Address 555h
WRITE A0h in
Address 555h
WRITE
is enabled
SDP is set
Write Page
(1 up to 64 bytes)
SDP ENABLE ALGORITHM
WRITE IN MEMORY
WHEN SDP IS SET
AI01509B
Note: 1. MSB Address bits (A6 to A10) differ during these specific Page Write operations.
Figure 6. Software Data Protection Disable
Algorithm
WRITE AAh in
Address 555h
WRITE 55h in
Address 2AAh
Page
Write
Instruction
WRITE 80h in
Address 555h
WRITE AAh in
Address 555h
WRITE 55h in
Address 2AAh
WRITE 20h in
Address 555h
Unprotected State
AI01510
Software Data Protection
The M28C17 offers a software controlled write
protection facility that allows the user to inhibit all
write modes to the device including the Chip Erase
instruction. This can be useful in protecting the
memory from inadvertent write cycles that may
occur due to uncontrolled bus conditions.
The M28C17 is shipped as standard in the "unprotected" state meaning that the memory contents
can be changed as required by the user. After the
Software Data Protection enable algorithm is issued, the device enters the "Protect Mode" of
operation where no further write commands have
any effect on the memory contents. The device
remains in this mode until a valid Software Data
Protection (SDP) disable sequence is received
whereby the device reverts to its "unprotected"
state. The Software Data Protection is fully nonvolatile and is not changed by power on/off sequences.
To enable the Software Data Protection (SDP) the
device requires the user to write (with a Page Write)
three specific data bytes to three specific memory
locations as per Figure 5. Similarly to disable the
Software Data Protection the user has to write
specific data bytes into six different locations as per
Figure 6 (with a Page Write). This complex series
ensures that the user will never enable or disable
the Software Data Protection accidentally.
5/17
M28C17
Table 4. AC Measurement Conditions
Figure 8. AC Testing Equivalent Load Circuit
Input Rise and Fall Times
≤ 20ns
Input Pulse Voltages
0.4V to 2.4V
Input and Output Timing Ref. Voltages
0.8V to 2.0V
1.3V
1N914
Note that Output Hi-Z is defined as the point where data is no
longer driven.
3.3kΩ
Figure 7. AC Testing Input Output Waveforms
2.4V
DEVICE
UNDER
TEST
OUT
CL = 30pF
2.0V
0.8V
0.4V
CL includes JIG capacitance
AI00826
AI01129
Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
Parameter
Test Condition
Input Capacitance
CIN
Output Capacitance
COUT
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 6. Read Mode DC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
0V ≤ VIN ≤ VCC
10
µA
ILO
Output Leakage Current
0V ≤ VIN ≤ VCC
10
µA
Supply Current (TTL inputs)
E = VIL, G = VIL , f = 5 MHz
30
mA
ICC (1)
Supply Current (CMOS inputs)
E = VIL, G = VIL , f = 5 MHz
25
mA
ICC1
(1)
Supply Current (Standby) TTL
E = VIH
1
mA
ICC2
(1)
Supply Current (Standby) CMOS
E > VCC –0.3V
100
µA
VIL
Input Low Voltage
– 0.3
0.8
V
VIH
Input High Voltage
2
VCC +0.5
V
VOL
Output Low Voltage
IOL = 2.1 mA
0.4
V
VOH
Output High Voltage
IOH = –400 µA
2.4
V
Note: 1. All I/O’s open circuit.
Table 7. Power Up Timing (1) (TA = 0 to 70°C or –40 to 85°C)
Symbol
Parameter
Max
Unit
tPUR
Time Delay to Read Operation
1
µs
tPUW
Time Delay to Write Operation (once VCC ≥ 4.5V)
10
ms
VWI
Write Inhibit Threshold
3.0
Note: 1. Sampled only, not 100% tested.
6/17
Min
4.2
V
M28C17
Table 8. Read Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol
Alt
Parameter
M28C17
Test
Condition
-90
min
-120
max
min
Unit
-150
max
min
max
tAVQV
tACC
Address Valid to
Output Valid
E = VIL,
G = VIL
90
120
150
ns
tELQV
tCE
Chip Enable Low to
Output Valid
G = VIL
90
120
150
ns
tGLQV
tOE
Output Enable Low
to Output Valid
E = VIL
40
45
50
ns
(1)
tDF
Chip Enable High
to Output Hi-Z
G = VIL
0
40
0
45
0
50
ns
tGHQZ (1)
tDF
Output Enable High
to Output Hi-Z
E = VIL
0
40
0
45
0
50
ns
tAXQX
tOH
Address Transition
to Output Transition
E = VIL,
G = VIL
0
tEHQZ
0
0
ns
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Figure 9. Read Mode AC Waveforms
VALID
A0-A10
tAVQV
tAXQX
E
tGLQV
tEHQZ
G
tELQV
DQ0-DQ7
tGHQZ
DATA OUT
Hi-Z
AI01511B
Note: Write Enable (W) = High
7/17
M28C17
Table 9. Write Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol
Alt
tAVWL
tAS
tAVEL
Parameter
Test Condition
Min
Address Valid to Write Enable Low
E = VIL, G = VIH
0
ns
tAS
Address Valid to Chip Enable Low
G = VIH, W = VIL
0
ns
tELWL
tCES
Chip Enable Low to Write Enable Low
G = VIH
0
ns
tGHWL
tOES
Output Enable High to Write Enable
Low
E = VIL
0
ns
tGHEL
tOES
Output Enable High to Chip Enable Low
W = VIL
0
ns
tWLEL
tWES
Write Enable Low to Chip Enable Low
G = VIH
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
50
ns
tELAX
tAH
Chip Enable Low to Address Transition
50
ns
tWLDV
tDV
Write Enable Low to Input Valid
E = VIL, G = VIH
1
µs
tELDV
tDV
Chip Enable Low to Input Valid
G = VIH, W = VIL
1
µs
tELEH
tWP
Chip Enable Low to Chip Enable High
50
ns
tWHEH
tCEH
Write Enable High to Chip Enable High
0
ns
tWHGL
tOEH
Write Enable High to Output Enable
Low
0
ns
tEHGL
tOEH
Chip Enable High to Output Enable Low
0
ns
tEHWH
tWEH
Chip Enable High to Write Enable High
0
ns
tWHDX
tDH
Write Enable High to Input Transition
0
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
50
ns
tWLWH1
tWP
Write Enable Low to Write Enable High
50
ns
tWHWH
tBLC
Byte Load Repeat Cycle Time
tWHRH
tWC
Write Cycle Time
tWHRL
tDB
Write Enable High to Ready/Busy Low
tEHRL
tDB
Chip Enable High to Ready/Busy Low
tDVWH
tDS
Data Valid before Write Enable High
50
ns
tDVEH
tDS
Data Valid before Chip Enable High
50
ns
Note: 1. With a 3.3 kΩ external pull-up resistor.
8/17
Max
Unit
100
µs
3
ms
Note 1
150
ns
Note 1
150
ns
0.15
M28C17
Figure 10. Write Mode AC Waveforms - Write Enable Controlled
VALID
A0-A10
tAVWL
tWLAX
E
tELWL
tWHEH
G
tGHWL
tWLWH1
tWHGL
W
tWLDV
tWHWL
DATA IN
DQ0-DQ7
tDVWH
tWHDX
RB
tWHRL
AI01128
Figure 11. Write Mode AC Waveforms - Chip Enable Controlled
VALID
A0-A10
tAVEL
tELAX
E
tGHEL
tELEH
G
tWLEL
tEHGL
W
tELDV
DQ0-DQ7
tEHWH
DATA IN
tDVEH
tEHDX
RB
tEHRL
AI01513
9/17
M28C17
Figure 12. Page Write Mode AC Waveforms - Write Enable Controlled
A0-A10
Addr 0
Addr 1
Addr 2
Addr n
E
tPLTS
G
tWHWL
tWHRH
W
tWLWH
Byte 0
DQ0-DQ7
tWHWH
tWHWH
Byte 1
Byte 2
Byte n
DQ5
Byte n
tWHRL
RB
AI01514
Figure 13. Software Protected Write Cycle Waveforms
G
E
tWLWH
tWHWL
tWHWH
W
tAVEL
tWLAX
Byte Address
A0-A5
tWHDX
A6-A10
555h
2AAh
Page Address
555h
tDVWH
DQ0-DQ7
AAh
55h
A0h
Byte 0
Byte 62
Byte 63
AI01515
Note: A6 through A10 must specify the same page address during each high to low transition of W (or E) after the software code has been
entered. G must be high only when W and E are both low.
10/17
M28C17
Figure 14. Data Polling Waveform Sequence
Address of the last byte of the Page Write instruction
A0-A10
E
G
W
DQ7
DQ7
DQ7
LAST WRITE
DQ7
DQ7
INTERNAL WRITE SEQUENCE
DQ7
READY
AI01516
Figure 15. Toggle Bit Waveform Sequence
A0-A10
E
G
W
DQ6
(1)
LAST WRITE
TOGGLE
INTERNAL WRITE SEQUENCE
READY
AI01517
Note: 1. First Toggle bit is forced to ’0’.
11/17
M28C17
Figure 16. Chip Erase Wavforms
tWHEH
E
G
tGLWH
W
tELWL
tWLWH2
tWHRH
AI01484B
Table 10. Chip Erase AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol
Parameter
Test Condition
Min
Max
Unit
tELWL
Chip Enable Low to Write Enable Low
G = VCC + 7V
1
µs
tWHEH
Write Enable High to Chip Enable High
G = VCC + 7V
0
ns
tWLWH2
Write Enable Low to Write Enable High
G = VCC + 7V
10
ms
tGLWH
Output Enable Low to Write Enable High
G = VCC + 7V
1
µs
tWHRH
Write Enable High to Write Enable Low
G = VCC + 7V
12/17
3
ms
M28C17
ORDERING INFORMATION SCHEME
Example:
M28C17
Speed
-90 K
Package
1
T
Temperature Range
-90
90ns
P PDIP28
1
0 to 70 °C
-120
120ns
K PLCC32
6
–40 to 85 °C
-150
150ns
Option
T
Tape & Reel
Packing
MS SO28 300mils
Devices are shipped from the factory with the memory content set at all "1’s" (FFh).
For a list of available options (Package, etc...) or for further information on any aspect of this device, please
contact the SGS-THOMSON Sales Office nearest to you.
13/17
M28C17
PDIP28 - 28 pin Plastic DIP, 600 mils width
mm
Symb
Typ
inches
Min
Max
A
3.94
A1
Min
Max
5.08
0.155
0.200
0.38
1.78
0.015
0.070
A2
3.56
4.06
0.140
0.160
B
0.38
0.56
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.30
0.008
0.012
D
34.70
37.34
1.366
1.470
E
14.80
16.26
0.583
0.640
E1
12.50
13.97
0.492
0.550
–
–
–
–
eA
15.20
17.78
0.598
0.700
L
3.05
3.82
0.120
0.150
S
1.02
2.29
0.040
0.090
α
0°
15°
0°
15°
N
28
e1
2.54
Typ
0.100
28
PDIP28
A2
A1
B1
B
A
L
α
e1
eA
C
D
S
N
E1
E
1
PDIP
Drawing is not to scale.
14/17
M28C17
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
Symb
Typ
inches
Min
Max
A
2.54
A1
Typ
Min
Max
3.56
0.100
0.140
1.52
2.41
0.060
0.095
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
12.32
12.57
0.485
0.495
D1
11.35
11.56
0.447
0.455
D2
9.91
10.92
0.390
0.430
E
14.86
15.11
0.585
0.595
E1
13.89
14.10
0.547
0.555
E2
12.45
13.46
0.490
0.530
e
1.27
–
–
0.050
–
–
j
0.89
–
–
0.035
–
–
N
32
32
Nd
7
7
Ne
9
9
CP
0.10
0.004
PLCC32
D
D1
A1
j
1 N
B1
E1 E
Ne
e
D2/E2
B
A
Nd
PLCC
CP
Drawing is not to scale.
15/17
M28C17
SO28 - 28 lead Plastic Small Outline, 300 mils body width
mm
Symb
Typ
inches
Min
Max
A
2.46
A1
Min
Max
2.64
0.097
0.104
0.13
0.29
0.005
0.011
A2
2.29
2.39
0.090
0.094
B
0.35
0.48
0.014
0.019
C
0.23
0.32
0.009
0.013
D
17.81
18.06
0.701
0.711
E
7.42
7.59
0.292
0.299
–
–
–
–
H
10.16
10.41
0.400
0.410
L
0.61
1.02
0.024
0.040
α
0°
8°
0°
8°
N
28
e
1.27
CP
Typ
0.050
28
0.10
0.004
SO28
A
A2
C
B
CP
e
D
N
E
H
1
A1
SO-b
Drawing is not to scale.
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α
L
M28C17
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