Maxim MAX14912 Low power and heat dissipation Datasheet

MAX14912/MAX14913
General Description
The MAX14912/MAX14913 have eight 640mA smart highside switches that can also be configured as push-pull
drivers for high-speed switching. The propagation delay
from input to switching of the high-side/low-side drivers is
1µs (max). Each high-side driver has a low on-resistance
of 230mΩ (max) at 500mA load current at TA = 125°C.
The device is configured and controlled either through pins
or the SPI interface. The SPI interface is daisy-chainable,
which allows efficient cascading of multiple devices. SPI
also supports command mode, for the highest detailed
diagnostic information. The MAX14912 allows configuration
through SPI in parallel and serial setting modes, while
the MAX14913 only supports configuration through SPI in
serial setting mode.
Open-load detection in high-side mode detects both
open-wire conditions in the switch on/off states, and
LED drivers provide indication of per-channel fault and
status conditions. Internal active clamps accelerate the
shutdown of inductive loads fast in high-side mode.
The MAX14912/MAX14913 are available in a 56-pin QFN
8mm x 8mm package.
Applications
●● Industrial Digital Outputs
●● PLC Systems
●● Building Automation
Ordering Information appears at end of data sheet.
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Benefits and Features
●● Low Power and Heat Dissipation
• 230mΩ (max) High-Side RON at TA = 125°C
• High-Efficiency 5V/100mA Buck Regulator
●● Fast Switching Ideal for High-Speed Control Systems
• 0.1µs (typ.) Propagation Delay (High-Side Mode)
• 0.5µs (typ.) Propagation Delay (Push-Pull Mode)
• 200kHz Switching-Rate Capability in Push-Pull Mode
• Fast Inductive Load Demagnetization
●● Robust Operation
• 60V Abs Max VDD Rating
• Safe-Demagnetization: Turn-Off of Unlimited Inductance
• IEC61000-4-2 8kV Air Gap/6kV Contact ESD Protection
• ±1kV/42Ω Surge Protection with TVS on VDD
• Robust SPI Interface with Watchdog and CRC
• -40°C to +125°C Ambient Operating Temperature
Range
●● Extensive Diagnostics Reduces System Downtime
• Per Driver and Chip Thermal Shutdown
• Open-Wire Detection in High-Side Mode
• Low Supply Voltage Warning
• Undervoltage Detection
• Overvoltage Detection on OUT
• Overcurrent Detection
• LED Drivers for Visual Fault and Output State Indication
●● Flexible Interface for Ease of Design
• Serial and/or Parallel Control Interface
• Per-Channel Configuration and Monitoring
• Wide Logic Voltage Range (1.6V to 5.5V)
●● Small Package and High Integration Enables
Compact High-Density I/O Modules
• 56-Pin QFN 8mm x 8mm Package
• Eight High-Side Switches/Push-Pull Drivers
• Daisy-Chainable SPI Interface
19-7777; Rev 3; 8/16
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Typical Application Circuit
10µF
1µF, 5V
100µH
100nF
24V
38V
V5
VL
LX
VPMP
VDD
BUKEN
1µF
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
OUT6
OUT5
OUT7
OUT7
OUT8
OUT8
SRIAL
3.3V
FLTR
EN
VDD
VDD A
DIGITAL
ISOLATOR
GPIO
FAULT
VDD B
SDI
OUT
MAX12931
IN
GND B
GND A
MAX14912/
MAX14913
CS
CLK
CMND /IN2
SDO
3.3V
CONTROLLER
CFP
VDDA
VDDB
PUSHPL
CFN
200nF, 50V
SPI
MAX14935
GNDA
38V
100nF
OUTB 2
OUTB 3
INB
GND
24V
1µF, 5V
OUTB 1
DIGITAL
ISOLATOR
PGND
GND
GNDB
V5
VL
LX
VPMP
VDD
OUT1
1uF
OUT9
SRIAL
FLTR
OUT2
OUT10
OUT3
OUT11
OUT4
OUT12
OUT5
OUT13
OUT6
OUT14
OUT7
OUT15
OUT8
OUT16
EN
CMND /IN2
FAULT
MAX14912/
MAX14913
SDI
CLK
CS
SDO
CFP
CFN
BUKEN
PUSHPL
GND
PGND
200nF, 50V
www.maximintegrated.com
Maxim Integrated │ 2
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Absolute Maximum Ratings
(All voltages relative to GND.)
VDD.........................................................................-0.3V to +60V
PGND....................................................................-0.3V to +0.3V
BUKEN, LX................................................ -0.3V to (VDD + 0.3V)
VPMP.................................................(VDD - 0.3V) to (VDD + 6V)
OUT_ (continuous voltage).............(VDD - 49V) to (VDD + 0.3V)
V5, VL.......................................................................-0.3V to +6V
CFP............................................. (VDD - 0.3V) to (VPMP + 0.3V)
CFN.........................................................-0.3V to (VPMP + 0.3V)
SDO.............................................................. -0.3V to (VL + 0.3V)
SDI, CLK, CS...........................................................-0.3V to +6V
IN_, PUSHPL, FLTR, SRIAL, EN,
FAULT, CERR/IN4, WDFLT/IN6...........................-0.3V to +6V
LED_, LD_.................................................... -0.3V to (V5 + 0.3V)
Inductive Kickback Energy OUT_ pins: IL < 0.6A......... Unlimited
OUT_ Load Current...........................................Internally Limited
Continuous-Current (any other terminal).........................±100mA
Continuous Power Dissipation (TA = +70°C)
QFN (derate 47.6mW/°C above 70°C).......................3800mW
Junction Temperature........................................Internally Limited
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (Soldering, 10sec).............................. +300°C
Package Thermal Characteristics (Note 1)
Thermal Resistances QFN56-EP package
Junction-to-Ambient Thermal Resistance (θJA),
Multilayer Board............................................................21°C/W
Junction-to-Case Thermal Resistance (θJC),
Multilayer Board...........................................................1.0°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics
(VDD = +10V to +36V, V5 = +4.5V to +5.5V, VL = +1.6V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C and VDD = +24V, CDCDC = 10µF, LDCDC = 100µH, CFLY = 200nF, CPUMP = 10µF, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
36
V
SUPPLY
VDD Supply Voltage
VDD Supply Current
VDD
IDD
VDD Undervoltage-Lockout
Threshold
VDD_UV
VDD Undervoltage-Lockout
Hysteresis
VDD_UVHYST
VDD Low-Voltage Warning
Threshold
VDD_LV
VDD Low-Voltage Warning
Hysteresis
VDD_LVHYST
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10.5
HS mode, EN = high, OUT_
outputs high (no switching), no
load, V5 and VL supplied externally
1.1
PP mode, EN = high, 100kHz
switching on all OUT_, V5 and VL
supplied externally, no load
14
V5 = 5V, VDD rising
mA
8.5
V5 = 5V
VDD falling
V5 = 5V
1.5
22
9.5
1
12
13
2
V
V
14
V
V
Maxim Integrated │ 3
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Electrical Characteristics (continued)
(VDD = +10V to +36V, V5 = +4.5V to +5.5V, VL = +1.6V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C and VDD = +24V, CDCDC = 10µF, LDCDC = 100µH, CFLY = 200nF, CPUMP = 10µF, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
V5/VL Supplies
V5 Supply Voltage
(Supplied Externally)
V5 Supply Current
(V5 Supplied Externally)
V5
IV5
V5 Undervoltage-Lockout
Threshold
VV5_UV
V5 Undervoltage-Lockout
Hysteresis
VV5_UVHYST
VL Supply Voltage
VL
VL Supply Current
IVL
VL Undervoltage-Lockout
Threshold
4.5
HS mode, EN = high, OUT_
outputs high, no load, no LEDs
connected
2.2
3.2
mA
PP mode, EN = high, OUT_
switching at 100kHz, no load, no
LEDs connected
8.5
11
mA
4.2
V
VDD = 24V, V5 rising
3.8
VDD = 24V
0.3
1.6
All logic inputs high or low
VL_UV
VL falling
VDCDC_UVLO
VDD rising
1.12
V
5.5
V
24
35
µA
1.27
1.52
V
5V DC-DC REGULATOR
Undervoltage-Lockout
Threshold of the DC-DC
Regulator
Undervoltage-Lockout
Threshold of the DC-DC
Regulator Hysteresis
Output Regulated Voltage
V
VDCDC_
0.5
UVLOHY
VDCDC
Current Limit
ICL_DCDC
Turn-On Time
TON_DCDC
Switching Frequency
6.6
0mA to 90mA external load current
4.85
5.0
5.15
100
Delay from VDD crossing the
UVLO threshold until the DC-DC
regulator finishes soft-start
fDCDC
V
mA
3.0
3.4
3.7
ms
540
600
660
kHz
110
230
mΩ
0.87
1.2
A
DRIVER OUTPUTS (OUT_)
HS Mode On-Resistance
HS Mode Current Limit
ROUT_HS
ILIM
HS Mode Current-Limit V/I
Slope
HS Mode Weak Pulldown
Current
www.maximintegrated.com
HS mode, HS = on, IOUT_ =
-500mA (Note 6)
EN = high, HS = on,
VOUT__ = VDD -1V
0.64
(See Overcurrent and Short-Circuit
Protection section)
ILKG
High-side mode, OL detect = off,
HS = off, 7V < VOUT_ < VDD
150
65
100
Ω
135
µA
Maxim Integrated │ 4
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Electrical Characteristics (continued)
(VDD = +10V to +36V, V5 = +4.5V to +5.5V, VL = +1.6V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C and VDD = +24V, CDCDC = 10µF, LDCDC = 100µH, CFLY = 200nF, CPUMP = 10µF, unless otherwise noted.)
PARAMETER
Push-Pull Mode HS OnResistance
Push-Pull Mode LS OnResistance
Push-Pull Mode Current Limit
SYMBOL
TYP
MAX
UNITS
ROUT_PP
PP mode, HS = on, EN = high,
IOUT_ = -500mA (Note 6)
110
230
mΩ
VOL_PP
PP mode, LS = on, EN = high,
IOUT = 500mA
1
2.5
Ω
ILIM_PP
CONDITIONS
MIN
PP mode, EN = High, OUT_ =
high, VOUT_ = VDD - 1V
0.64
0.87
1.2
A
PP mode, EN = High, OUT_ = low,
3V < VOUT_ < VDD
0.44
0.68
0.81
A
OPEN-LOAD DETECT (OUT_)
IOL_HSOFF
OL detect = on, high-side mode,
HS = off, 7V < VOUT_ < VDD -1V
50
74
100
µA
Open-Load Detect Threshold,
High-Side Off
VOL_T
OL detect = on, high-side mode,
HS = off, LED turns off/on
6.4
6.7
7.35
V
Open-Load Detect Threshold
Current, High-Side On
IOL_HSON
OL detect = on, high-side mode,
HS = on, 0V < VOUT_ < (VDD -1V)
1
2
3
mA
TDEB_OL
Reliable open-load detection
reading is obtained only if both
the switch input state and the load
level do not change for TDEB_OL,
high-side = on/off
Open-Load Pullup Current,
High-Side Off
Debounce Filter
100
ms
LOGIC (I/O)
Input Voltage High
VIH
Input Voltage Low
VIL
Input Threshold Hysteresis
VL < 2.5V
0.8 x VL
VL ≥ 2.5V
0.7 x VL
V
VL < 2.5V
0.16 x VL
VL ≥ 2.5V
0.3 x VL
VIHYST
0.1 x VL
V
V
Input Pulldown Resistor
RI
All logic input pins, except CS
(Note 2)
140
200
275
kΩ
Input Pullup Resistor
RI
CS input (Note 2)
140
200
275
kΩ
Output Logic-High (SDO)
Output Logic-Low
VOH
IL = -5mA
VOL
IL = +5mA
RL_SDO
CS = high
Output Logic-Low
VODL
IL = +5mA
Leakage
IODL
Open-drain output off, pins are at
5.5V
SDO Pulldown Resistor
OPEN-DRAIN OUTPUTS (FAULT, CERR/IN4, WDFLT/IN6)
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VL - 0.33V
140
-1
V
200
0.33
V
275
kΩ
0.58
V
+1
µA
Maxim Integrated │ 5
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Electrical Characteristics (continued)
(VDD = +10V to +36V, V5 = +4.5V to +5.5V, VL = +1.6V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C and VDD = +24V, CDCDC = 10µF, LDCDC = 100µH, CFLY = 200nF, CPUMP = 10µF, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
VOH_LED
LEDH = on, ILED = 5mA
MIN
TYP
MAX
UNITS
LED DRIVERS (LEDH_, LDL_)
Output Voltage High
Output Leakage Current High
Output Voltage Low
Output Leakage Current Low
LED Driver Scan Rate
Fault-LED Minimum On-Time
ILH
VOL_LED
ILL
FLED
tFAULT_ON
LEDH_ = off, V = 0V
V5 - 0.3
V
-50
µA
LDL = on, ILED = 5mA
0.3
LDL = off, V = 5V
Update rate for each LED
1.07
Fault LED is turned on for at least
tFAULT_ON
1.18
V
50
µA
1.31
kHz
200
ms
PROTECTION
OUT_ Clamp Negative
Voltage
VCL
Channel Thermal-Shutdown
Temperature
TJSHDN
Channel Thermal-Shutdown
Hysteresis
TJSHDN_HYST
Chip Thermal Shutdown
TCSHDN
Chip Thermal-Shutdown
Hysteresis
TCSHDN_HYST
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Relative to VDD. EN = high
Junction temperature rising. Per
channel
Temperature rising
49
56
64.5
V
167
°C
17
°C
150
°C
8
°C
Maxim Integrated │ 6
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
AC Electrical Characteristics
(VDD = +10V to +36V, V5 = +4.5V to +5.5V, VL = +1.6V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C and VDD = +24V, CDCDC = 10µF, LDCDC = 100µH, CFLY = 200nF, CPUMP = 10µF, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power-Up Delay
tPOWERUP
EN = high time from VDD > VDD_UV
to switches turned-on, VHVBUCKEN
= 0V or VDD
5.5
ms
Enable Delay
tENABLE
All power supplies above UVLO
thresholds; time from EN positive
edge to switches turned on
0.1
µs
Push-Pull Switchover Delay
tD_PPMODE
Delay from high-side to push-pull
switchover
45
µs
OUT_ OUTPUTS
High-side mode, delay from IN_ or
positive CS edge to OUT_ to 0.8 x
VDD. CL = 100pF, FLTR = low.
Output Propagation Delay LH
Output Propagation Delay HL
tPD_LH
tPD_HL
0.35
0.7
µs
Push-pull mode, delay from IN_ or
CS positive edge to OUT_ rising to
0.8 x VDD. CL = 100pF, FLTR = low
(Figure 2)
0.40
High-side mode, delay from IN_
negative edge or CS switching high
to OUT_ falling by 0.5V. RL = 48Ω,
FLTR = low (Figure 1, Note 5)
0.1
Push-pull mode, delay between IN_
switching low or CS switching high
to OUT_ falling to 0.2 x VDD. CL =
100pF, FLTR = low (Figure 2)
0.35
0.7
0.7
µs
Output-to-Output Propagation
Skew LH
tPD_SK_LH
Push-pull modes, CL = 1nF,
FLTR = X (Note 3, Note 7)
-100
0
100
ns
Output-to-Output Propagation
Skew HL
tPD_SK_HL
Push-pull modes, RL = 5kΩ,
CL = 1nF, FLTR = X (Note 7)
-100
0
100
ns
Output Rise Time
Output Fall Time
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tR
tF
Push-pull mode, 20% to 80%
VDD, CL = 100pF, FLTR = X
(Note 7)
0.3
µs
High-side mode, 20% to 80%
VDD, FLTR = X (Note 7)
0.3
µs
Push-pull mode, 80% to 20% VDD,
VDD < 30V, CL = 100pF,
FLTR = X (Note 7)
0.05
Maxim Integrated │ 7
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
AC Electrical Characteristics (continued)
(VDD = +10V to +36V, V5 = +4.5V to +5.5V, VL = +1.6V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C and VDD = +24V, CDCDC = 10µF, LDCDC = 100µH, CFLY = 200nF, CPUMP = 10µF, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CRC ERROR DETECTION (CERR/IN4)
tPDL_CERR
SRIAL = high, CRC/IN3 = high,
OUT_ detects a CRC error on SDI
data, ISOURCE = 5mA
tPDH_CERR
SRIAL = high, CRC/IN3 = high,
OUT_ clears/CERR/IN4,
ISOURCE = 5mA
tWD_ACC
SRIAL = high, WDEN/IN5 = high.
See Table 5 for watchdog timeout
selection.
Propagation Delay
14.5
ns
17
ns
WATCHDOG TIMER
Watchdog Timeout Accuracy
-10
+10
%
GLITCH FILTERS
Pulse Length of Rejected
Glitch
Passes Pulse Length
Glitch Filter Delay Time
tFPL_GF
tFD_GF
tD_GF
FLTR = high, on EN, CS, _IN_ pins
80
FLTR = X, SRIAL and PUSHPL pins
170
FLTR = high, on EN, CS, _IN_ pins
260
FLTR = X, SRIAL and PUSHPL pins
550
ns
ns
FLTR = high, on EN, CS, _IN_ pins
140
FLTR = X, SRIAL and PUSHPL pins
320
ns
SPI TIMING CHARACTERISTICS
2.5V ≤ VL < 5.5V
CLK Clock Period
tCH+CL
50
ns
CLK Pulse-Width High
tCH
10
ns
CLK Pulse-Width Low
tCL
10
ns
CS Fall-to-CLK Rise Time
tCSS
FLTR = low (Note 5)
12
FLTR = high
260
ns
SDI Hold Time
tDH
5
ns
SDI Setup Time
tDS
5
ns
Output Data Propagation
Delay
tDO
SDO Rise-and-Fall Times
tFT
CS Hold Time
tCSH
CS Pulse Width High
tCSPW
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CL = 10pF. CLK falling-edge to
SDO stable
30
1
40
FLTR = low (Note 5).
15
FLTR = high
260
ns
ns
ns
ns
Maxim Integrated │ 8
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
AC Electrical Characteristics (continued)
(VDD = +10V to +36V, V5 = +4.5V to +5.5V, VL = +1.6V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C and VDD = +24V, CDCDC = 10µF, LDCDC = 100µH, CFLY = 200nF, CPUMP = 10µF, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.6V ≤ VL < 2.5V
CLK Clock Period
tCH+CL
60
ns
CLK Pulse-Width High
tCH
13
ns
CLK Pulse-Width Low
tCL
13
ns
CS Fall to CLK Rise Time
tCSS
FLTR = low (Note 5)
15
FLTR = high
260
ns
SDI Hold Time
tDH
10
ns
SDI Setup Time
tDS
10
ns
Output Data Propagation
Delay
tDO
SDO Rise-and-Fall Times
tFT
CS Hold Time
tCSH
CS Pulse-Width High
tCSPW
Note 2:
Note 3:
Note
Note
Note
Note
4:
5:
6:
7:
CL = 10pF. CLK falling-edge to
SDO stable
40
2.5
FLTR = low (Note 5)
ns
ns
40
ns
20
ns
All units are production tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Channel-to-channel skew is defined as the difference in propagation delays between channels on the same device with
the same polarity.
All logic input pins except CS have a pulldown resistor. CS has a pullup resistor.
Specification is guaranteed by design; not production tested.
Excludes bond wire resistance.
X - means do not care.
ESD Characteristics
PARAMETER
ESD
Note 8:
SYMBOL
VESD
CONDITIONS
MIN
TYP
MAX
UNITS
OUT_ pins. Contact (Note 8)
±8
kV
OUT_ pins. Air Discharge
±15
kV
All other pins. Human Body Model
±2
kV
Bypass each VDD pin to AGND with a 1µF capacitor as close as possible to the device for high-ESD protection.
www.maximintegrated.com
Maxim Integrated │ 9
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Test Circuits/Timing Diagrams
VL
0.1µF
VL
50Ω
TEST
SOURCE
1µF
VDD
1µF
V5
VDD
V5
MAX14912/
MAX14913
IN_/CS
FLTR
O_
PUSHPL
GND
CL
PGND
VL
RL
VL
IN_
50%
GND
CS
50%
tPDHS_LH
VDD
GND
tPDHS_HL
VDD
tPDHS_LH
0.5V
GND
VDD
80%
O_
tPDHS_HL
VDD - 0.5V
O_
0.5V
GND
50%
VDD
VDD - 0.5V
O_
50%
80%
O_
GND
20%
GND
tR
tF
20%
tR
tF
Figure 1. High-Side Mode Timing Characteristics
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Maxim Integrated │ 10
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Test Circuits/Timing Diagrams (continued)
VL
0.1μF
VL
VDD
1μF
V5
VDD
V5
PUSHPL
MAX14912/
MAX14913
50Ω
1μF
IN_/CS
TEST
SOURCE
O_
FLTR
GND
CL
PGND
RL
VL
VL
IN_
50%
GND
tPDPP_LH
VDD
CS
50%
50%
GND
tPDPP_HL
VDD
0.8 x VDD
O_
50%
tPDPP_LH
tPDPP_HL
0.8 x VDD
O_
0.2 x VDD
GND
tPDSK_LH
VDD
0.2 x VDD
GND
tPDSK_HL
VDD
0.8 x VDD
O_
80%
O_
GND
0.2 x VDD
GND
20%
tF
tR
tR
tF
Figure 2. Push-Pull Mode Timing Characteristics
CS
tCSS
tCL
tCH
tCSH
CLK
tDS
tDH
SDI
tDO
SDO
tFT
Figure 3. SPI Timing Diagram
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Maxim Integrated │ 11
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Typical Operating Characteristics
(VDD = 24V; V5 = 5V, VL = 3.3V, TA = +25°C, unless otherwise noted.)
0.80
HIGH-SIDE RON
VDD = 10V, 24V, & 36V
24V
140
0.60
36V
0.40
10V
0
200
400
1.5
100
1
0
0.00
600
150
LOW-SIDE
50
0.20
120
2
HIGH-SIDE
-40
10
1
3.0
IDD (mA)
PROPAGATION DELAY (µs)
3.5
0.6
HIGH-TO-LOW
0.4
0
10
60
HIGH-TO-LOW
0.10
0.05
LOW-TO-HIGH
-40
10
0.0
TEMPERATURE (°C)
110
35.0
toc06
PUSH-PULL MODE, DC-DC ACTIVE
ALL CHANNELS SWITCHING, NO LOADS
VDD = 36V
20.0
15.0
PUSH-PULL MODE
10.0
VDD = 24V
5.0
0.5
110
60
SUPPLY CURRENT
vs. SWITCHING FREQUENCY
25.0
1.0
LOW-TO-HIGH
-40
0.15
30.0
2.5
1.5
0.1
toc05
HIGH-SIDE MODE
2.0
0.3
0.2
VDD = 10V TO 36V, OUTPUT LOAD 48Ω || 100PF
TEMPERATURE (ºC)
4.0
0.7
0.5
HIGH-SIDE MODE
0.20
0.00
NO LOADS, NO SWITCHING
OUTPUTS HIGH, DC-DC ACTIVE
4.5
VDD = 24V, OUTPUT LOAD 1KΩ || 100PF
0.8
110
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
5.0
toc04
PUSH-PULL MODE
0.9
60
0
0.25
TEMPERATURE (ºC)
ILOAD (mA)
PROPAGATION DELAY
vs. TEMPERATURE
0.5
HIGH-SIDE PROPAGATION DELAY
vs. TEMPERATURE
toc03
0.30
2.5
IDD (mA)
160
HIGH-SIDE RON (mΩ)
180
toc02
200
LOW-SIDE RON (Ω)
1.00
RON RESISTANCE
vs. TEMPERATURE
250
1.20
200
100
1.40
HIGH-SIDE PROPAGATION DELAY (µs)
LOW-SIDE RON
VDD = 10V, 24V, OR 36V
220
HIGH-SIDE RON (mΩ)
toc01
LOW-SIDE RON (Ω)
RON RESISTANCE
vs. LOAD CURRENT
240
10
20
30
VDD (V)
40
DUTY CYCLE 50%
0
50
100
150
200
FREQUENCY (kHz)
LED DRIVER OUTPUT
vs. LOAD CURRENT
6.00
0.0
VDD = 10V
toc07
HIGH-SIDE
LED DRIVER OUTPUT (V)
5.00
4.00
3.00
2.00
LOW-SIDE
1.00
0.00
0
10
20
30
40
50
ILOAD (mA)
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Maxim Integrated │ 12
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
CERR/IN4
33 32
31
30 29
CRC/IN3
WDFLT /IN6
35 34
WDEN/IN5
36
CNFG /IN7
FLTR
38 37
S16/IN8
40 39
GND
LEDH37
41
V5
LEDH48
42
LEDH15
FAULT
TOP VIEW
LEDH26
Pin Configuration
PUSHPL
43
28 CMND/IN2
BUKEN
44
27 OL/IN1
VDD
45
26 VDD
OUT5
46
25 OUT4
VDD
47
24 VDD
OUT6
48
VDD
49
GND
50
OUT7
51
20 OUT2
VDD
52
19 VDD
OUT8
53
18 OUT1
VDD
54
17 VDD
EN
55
UVLO
56
23 OUT3
MAX14912/
MAX14913
22 VDD
21 GND
16 SRIAL
+
5
6
7
8
9
10
11 12
LDLS 1-4
LDLF 5-8
LDLF 1-4
CFN
CFP
VPMP
GND
LX
PGND
VL
13
14
SDI
4
CLK
3
SDO
2
LDLS 5-8
15 CS
1
QFN
8mm x 8mm
Pin Description
PIN
NAME
FUNCTION
LED DRIVERS
1, 2
LDLS5-8,
LDLS1-4
Status LED Cathode Outputs (Open-Drain Low-Side)
3, 4
LDLF5-8,
LDLF1-4
Fault LED Cathode Outputs (Open-Drain Low-Side)
38–41
LEDH15,
LEDH26,
LEDH37,
LEDH48
LED Anode Connections (Open-Drain High-Side). Connect a resistor in series to set the diode
current.
POWER SUPPLY
5
CFN
Charge-Pump Flying Capacitor
6
CFP
Charge-Pump Flying Capacitor. Connect a 200nF/50V capacitor to CFN.
7
VPMP
8, 21, 36, 50
GND (4x)
9
LX
www.maximintegrated.com
Charge-Pump Output. Connect a 10μF/5V capacitor between VPMP and VDD. VPMP is not
intended for use as a power supply for other devices.
Ground. Connect all GND pins together.
DC-DC Converter Switching Output. Connect LX to the switching-side of the inductor.
Maxim Integrated │ 13
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Pin Description (continued)
PIN
NAME
10
PGND
FUNCTION
11
VL
17, 19, 22, 24,
26, 45, 47, 49,
52, 54
VDD (10x)
Supply Voltage, Nominally 24V. Connect all VDD together. Bypass VDD to GND through a 1µF
capacitor.
37
V5
5V Supply Input. V5 can be powered by an external 5V supply or the internal 5V buck. Bypass
V5 to GND through a 10µF ceramic capacitor.
44
BUKEN
Enable Input for Buck Regulator. BUKEN should be permanently connected to either VDD or
GND—do not switch BUKEN. Connect BUKEN to GND if not using the internal buck. Connect
BUKEN to VDD to use the internal buck.
56
UVLO
Ground for the DC-DC Converter. Connect to GND.
Logic Supply Input. VL defines the levels on all I/O logic interface pins. Bypass VL to GND
through a 100nF ceramic capacitor.
UVLO is an Open-Drain, Undervoltage Indicator of the VDD Supply.
SERIAL INTERFACE
12
SDO
Serial-Data Output. SPI MISO data output to controller.
13
SDI
Serial-Data Input. SPI MOSI data from controller.
14
CLK
Serial-Clock Input from SPI Controller
15
CS
Chip-Select Input from Controller
LOGIC INTERFACE
16
SRIAL
Serial/Parallel Select Input. Drive SRIAL high to set the MAX14912/MAX14913 outputs through
the serial interface. Drive SRIAL low to set the MAX14912/MAX14913outputs through the
parallel (_/IN) pins. SRIAL does not affect serial readback of diagnostic/status information.
27
OL/IN1
Open-Load Select Input/IN1 Input. In serial mode (SRIAL = high), drive OL/IN1 = high to enable
open-load detection on all eight OUT_ outputs when in high-side operation. In parallel mode
(SRIAL = low), OL/IN1 sets OUT1 on/off/high/low.
28
CMND/IN2
Command Mode SPI Input/IN2 Logic Input. In serial mode (SRIAL = high), CMND/IN2 enables
command-based SPI access (see Detailed Description section for details).
In parallel mode (SRIAL = low), CMND/IN2 sets OUT2 on/off/high/low.
29
CRC/IN3
CRC Select Input/IN3 Input. In serial mode (SRIAL = high), drive CRC/IN3 = high to enable CRC
error detection on serial data. In parallel mode (SRIAL = low), CRC/IN3 sets OUT3 on/off/high/
low.
30
CERR/IN4
CRC Error Detection Output/IN4 Input. In serial mode (SRIAL = high) with error checking
enabled (CRC/IN3 = high), CERR/IN4 is an open-drain output whose transistor turns on when
the device detects an error on SDI data. In parallel mode (SRIAL = low), CERR/IN4 sets OUT4
on/off/high/low.
31
WDEN/IN5
Watchdog Enable Input/ IN5 Input. In serial mode (SRIAL= high), WDEN/IN5 enables the
watchdog timer. In parallel mode (SRIAL= low), WDEN/IN5 sets OUT5 on/off/high/low.
32
WDFLT/IN6
Watchdog Fault Output/IN6 Input. In serial mode (SRIAL = high), WDFLT/IN6 is the open-drain
watchdog fault output, which turns on when a watchdog fault is detected while WDEN/IN5 is
high. In parallel mode (SRIAL = low), WDFLT/IN6 sets OUT6 on/off/high/low.
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Maxim Integrated │ 14
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Pin Description (continued)
PIN
33
NAME
FUNCTION
CNFG/IN7
Configure Input/IN7 Input. In serial mode (SRIAL = high), drive CNFG/IN7 high to enable perchannel configuration through the serial interface. In serial mode, drive CNFG/IN7 low to allow
setting the OUT_ outputs through the serial interface. In parallel mode (SRIAL = low), CNFG/IN7
sets OUT7 on/off/high/low.
16-Bit Serial Select/IN8 Input.
In serial mode (SRIAL = high), drive S16/IN8 high to select 16-bit serial-interface operation.
Drive S16/IN8 low in serial mode for 8-bit serial operation.
In parallel mode (SRIAL = low), S16/IN8 sets OUT8 on/off/high/low.
34
S16/IN8
35
FLTR
Glitch Filter Enable Input. Set FLTR high to enable glitch filtering on all parallel logic inputs and
CS.
42
FAULT
Open-Drain Fault Output. The FAULT transistor turns on low when a fault condition (driver
shutdown or open-load detect) occurs.
43
PUSHPL
Push-Pull, High Slew-Rate Configuration Input. When PUSHPL is set high, all OUT_ pins
operate in push-pull mode. When PUSHPL is set low, all OUT_ pins operate in high-side mode.
55
EN
Output Enable Input. Driving EN low turns all high-side OUT_ switches off, and three-states all
push-pull OUT_ drivers and turns all LED drivers off. Driving EN high enables normal operation.
SWITCH/DRIVER OUTPUTS
18, 20, 23, 25,
46, 48, 51, 53
OUT1–OUT8
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Driver Output N. May be configured as a high-side switch or push-pull output.
Maxim Integrated │ 15
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Functional (or Block) Diagram
BUKEN
VDD LX
PGND
V5
CFP
BUCK
VL
CFN
VDD
VPMP
CHARGE PUMP
VDD
FLTR
V5
PUSHPL
VDD
DRIVE +
MONITOR
UV
MONITOR
OL/IN1
CMND/IN2
EN
CRC/IN3
WDEN/IN5
EN
VDD
UVLO
PARALLEL
INTERFACE
CERRB/IN4
MAX14912
MAX14913
WDFLT /IN6
OUT8
DRIVE +
MONITOR
CNFG /IN7
S16/IN8
OUT7
EN
CONFIG
AND
SETTING
SRIAL
CS
VDD
CLK
SERIAL
INTERFACE
SDI
WATCHDOG
DRIVE +
MONITOR
SDO
FAULT
DIAGNOSTICS
UVLO
OUT2
VDD
LEDH15
LEDH26
LEDH37
LED
DRIVERS
FAULT , LEVEL
Shutdn
DRIVE +
MONITOR
OL
OUT1
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LDLF 5-8
LDLF 1-4
LDLS 5-8
LDLS 1-4
LEDH48
EN
GND
Maxim Integrated │ 16
MAX14912/MAX14913
Detailed Description
High-Side Mode
The high-side drivers (HS) have 230mΩ (max) on-resistance
when sourcing 500mA at TA = +125°C. The OUT_ output
voltage can go below ground, as can occur during
inductive load turn-off/demagnetization. Internal clamping
diodes limit the negative excursion to (VDD - VCL) and
allow free-wheeling currents to demagnetize the inductive
loads quickly.
Low-side transistors (LS) can be switched in to provide
push-pull operation. Fast discharge of ground-connected
RC loads is achieved by push-pull drive. In push-pull
mode, the OUT_ outputs are clamped to GND.
Output Parallelization
The devices support paralleling of channels in high-side
mode to provide higher current. The channels can be
paired (1-2, 3-4, 5-6, and 7-8) by setting two bits of the
SPI register 3: joinUP and joinDW (see Table 6).
When joinDW = 1, OUT1 and OUT2 are connected
together, and OUT3 and OUT4 are connected together,
and:
Octal High-Speed, High-Side
Switch/Push-Pull Driver
in parallel, the internal clamp with the lowest clamp voltage
turns on and dissipates all the energy.
Channel diagnostics for fault detection remains independent
in case of paralleling the outputs.
Open-Load/Wire Detection
Detection of an open-load condition can be enabled on
a per-channel basis through serial configuration, or globally in serial mode through the OL/IN1 input. Open-load
detection works in high-side mode only. It operates with
the HS driver either on or off.
When the HS switch is off, a current source is enabled,
which pulls OUT_ to VDD when the wire is open. If the
OUT_ voltage is above VOL_T, an open load is signaled.
When the HS switch is on, the voltage across the HS
switch is monitored. If this drop is below a load current of
IOL_HSON, an open-load fault is reported.
The switch input state and the load condition must both be
stable for at least tDEB_OL to get a reliable reading.
When an open-load condition is detected on an output:
1)
The F_ bit is set for that output in the serial diagnostic
data.
●●
Input signals related to channels 2 and 4 are
neglected;
2)
●●
Output status is determined by inputs 1 and 3;
The fault LED is turned on for at least 200ms for that
channel.
●●
Push-pull mode is disabled.
3)
The open-drain global FAULT transistor is turned on
for at least 200ms.
When joinUP = 1, OUT5 and OUT6 are connected together,
and OUT7 and OUT8 are connected together, and:
●●
Input signals related to channels 6 and 8 are
neglected;
●●
Output status is determined by inputs 5 and 7;
●●
Push-pull mode is disabled.
The above configuration can be used without any additional
external zener clamping.
Besides pairing of drivers through internal configuration,
multiple OUTs can be operated in parallel by tying the
OUT_ together and driving the inputs simultaneously. In
this case, an external zener clamp is required per output
set for quenching the energy during inductive load turnoff. The external clamp voltage of this zener diode must
be lower than the minimum internal clamp voltage (VCL
(min)). The reason is that there is channel-to-channel
variation between the internal clamp voltages. Without an
external zener diode, during turn-off of channels connected
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VDD
HS
OPEN
IOL_HSOFF
OPEN
WIRE
OUT_
VOL_T
RL
LS
GND
Figure 4. Open-Wire Load Detection
Maxim Integrated │ 17
MAX14912/MAX14913
Watchdog
The watchdog timer allows monitoring activity on the CS
input in serial mode (SRIAL = high). Drive WDEN/IN5 high
to enable the watchdog function. The watchdog monitors
and expects activity on the CS input. The WD timer is
reset at every CS falling edge. If the timer is not reset
after the timeout delay, see Table 8), all OUT_ outputs are
turned off and the watchdog fault output (WDFLTB/IN6)
transitions low until the next CS falling edge.
The watchdog timeout can be selected in SPI command
mode (see the Configuration and Monitoring section). Bits
selection in Register 3: WD[1:0] = 00 for 0.9s, WD[1:0] = 01
for 0.45s and WD[1:0] = 10 for 0.15s. The default value is
0.9s.
Thermal Management
Every driver’s temperature is constantly monitored while
VDD > VDD_UV. If the temperature of a driver rises above
the thermal-shutdown threshold of TJSHDN, that channel
is automatically turned off for protection. The drivers are
turned on again once the temperature drops by a hysteresis
margin of TJSHDN_HYST.
Both high and low-side drivers are thermally protected
with a per-driver protection circuit.
When a driver turns off due to thermal shutdown:
1)
A fault is indicated through the global FAULT output.
2)
The F_ bit of that channel is set in the diagnostic
byte in the SPI interface.
3)
The fault LED driver turns on for that channel.
The device also has a chip thermal shutdown that triggers
a FAULT output and all the channels shut down if the temperature rises above TCSHDN.
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Octal High-Speed, High-Side
Switch/Push-Pull Driver
Overcurrent and Short-Circuit Protection
In the event of a short-circuit or high current at an OUT_
output, the load current is limited on a per-channel basis
to ILIM_HS for the high-side (HS) driver and to ILIM_PP for
the low-side (LS) driver. Additionally, when a short circuit
is detected, the affected OUT_ output is put in a safe slowmode in order to prevent damages in case its IN_ input is
switching at a high frequency. In order to restore normal
operation, the IN_ input of the affected channel has to
be kept low for at least 20ms. While in slow-mode, the
low-to-high and high-to-low transitions at OUT_ are slewrate limited to around 3V/µs. A short-circuit or overcurrent
generally creates a temperature rise in the chip; both the
HS and LS FETs’ temperatures are continuously monitored.
When any switch temperature exceeds TJSHDN, the
corresponding OUT_ output is put in a high-impedance
state until the temperature falls by the hysteresis.
If the case temperature is below TCSHDN, a short circuit
on one output will allow the other outputs to operate normally.
The HS current-limit circuit features a controlled dV/dI
slope that improves stability with inductive loads. In other
words, the current is limited to a nonconstant value that
increases with (VDD - VOUT) with a slope of 1A/150V.
WDEN/IN5
CS
WATCHDOG
WDFLT/IN6
Figure 5. Watchdog Timer
Maxim Integrated │ 18
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Undervoltage Lockout
and should be chosen according to the LED’s current/lightintensity requirements. Every LED that is on, is pulsed on
with a 25% duty cycle.
When the VL, VDD, or V5 supply voltages are under their
respective UVLO thresholds, all OUT_ outputs are turned
off (three-stated) and the open-load detect current sources are turned off; they automatically turn back on once the
VDD/V5 rises to above the UVLO thresholds.
Undervoltage conditions can be read out through SPI.
The UVLO open-drain output pin indicates whether VDD
is below the VDD_UV threshold.
Configuration and Monitoring
The MAX14912/MAX14913 can be configured, set, and
monitored through either a parallel or serial interface. The
serial interface allows greater configuration flexibility and
provides more monitoring information. For the MAX14913, in
parallel setting mode (SRIAL = low), the SPI cannot be used
for configuring the device, SPI is only available for monitoring.
LED Drivers
The 4 x 4 LED driver crossbar matrix offers a pin-optimized
configuration for driving 16 LEDs. Per-channel output
status and the fault conditions are indicated by individual
LEDs. If a FAULT LED is turned on for an output, the
corresponding LEVEL LED is always turned off. This
mitigates false information about the status of the affected
OUT_ pin.
For every current-limiting resistor (R), each of the four
LEDs in the vertical string are pulsed so that current only
flows through one LED at any given time. Therefore, the
resistors (R) determine the LED current through one LED
Global Configuration
Pin-based configuration does not require the use of the
SPI interface. It is global and allows for the configuration
of all OUT_ as high-side outputs, push-pull outputs, and
enables open-load detection. See Table 1 for details.
In cases where configuration is possible through the
parallel and/or serial interface, Table 2 documents the
priority.
MAX14912
MAX14913
5V
LEDH15
LEDH26
R
LEDH37
R
LEDH48
R
R
FAULT 1 - 4
LDLF1-4
FAULT 5 - 8
LDLF 5-8
STATUS1 - 4
LDLS1-4
STATUS 5 - 8
LDLS 5-8
GND
Figure 6. LED Output Status and Fault-Detection Matrix
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Maxim Integrated │ 19
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Table 1. Global Configuration Pins
INPUT
SRIAL
CONFIGURATION
PUSHPL
X
Configures all OUT_ outputs as push-pull or high-side.
0 = All drivers in high-side mode unless configured as push-pull by serial interface.
1 = All drivers in push-pull mode.
OL/IN1
1
Enables global open-load detection in serial mode.
0 = Open-load detection disabled unless enabled by serial interface.
1 = Open-load detection enabled for all high-side mode switches.
CRC/IN3
1
Enables CRC generation and error detection on the serial interface.
0 = CRC error detection disabled.
1 = CRC error detection enabled.
FLTR
X
Enables anti-glitch filtering on all logic input pins except SDI and CLK. (Note 1)
0 = Glitch filtering disabled.
1 = Glitch filtering enabled.
WDEN/IN5
1
Enables watchdog on the SPI interface.
0 = Watchdog disabled.
1 = Watchdog enabled.
Note 1: PUSHPL and SRIAL are always filtered, independent of FLTR logic.
Table 2. Configuration Priority
CONFIGURATION
Push-Pull/
High-Side
SRIAL
1
PRIORITY
PUSHPL
RESULT
Low
OUT_ drivers in high-side mode, unless configured individually
as push-pull through the serial interface.
High
All OUT_ drivers in push-pull mode, independent of serial
configuration.
OL/IN1
Open-Load Detection
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1
RESULT
Low
Open-load detection off, unless configured individually through
the serial interface.
High
Open-load detection enabled on all OUT_ outputs that operate
in high-side mode.
Maxim Integrated │ 20
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Parallel Interface: Setting the OUT_ Output Driver
The parallel mode (SRIAL = low) uses one input pin (IN_)
to set each output (OUT_). Table 3 shows the settings that
depend on the configured mode.
In parallel setting mode (SRIAL = low), the MAX14913
can only be configured via the global configuration inputs:
PUSHPL and FLTR, not on a per-channel basis through
SPI. This means that all high-side drivers are either in
high-side or push-pull operation. Open-load detection is
enabled and cannot be disabled in parallel setting mode.
The MAX14912 can be configured with full flexibility in
parallel setting mode.
Serial Controller Interface
The serial interface can be used in all setting modes. It
is based on CPOL = low and CPHA = low, meaning that
the SDI data is latched-in on the rising edge of CLK and
new SDO data is written on the falling edge of CLK. The
default idle CLK state needs to be low. The SDO output
is only actively driven when the SPI master drives CS low,
it is otherwise weakly pulled down by an internal 200kΩ
resistor when CS is high.
Table 3. SRIAL = Low
DRIVER MODE
IN_
High-Side
0
High-side off
OUT_ STATE
High-Side
1
High-side on
Push-Pull
0
Push-pull output low
Push-Pull
1
Push-pull output high
The SPI interface provides per channel and detailed global
diagnostics. In serial setting mode (SRIAL = high), the
outputs are set on/off/high/low by the serial interface. Serial
mode also allows per channel and global configuration. In
parallel setting mode (SRIAL = low), the MAX14913 does
not allow configuration through SPI, while the MAX1912
can be configured per channel and globally.
The SPI interface can be operated in either command
mode or direct mode. Command mode is available in both
parallel and serial modes and provides higher information
content and supports more configuration options. See
Table 4 for details. Direct mode SPI is only available in
serial setting mode (SRIAL = high). In direct SPI mode,
output setting and per channel configuration is written
directly (without a command byte) and diagnostics data is
provided either in an 8 or 16-bit SPI cycle.
In both command and direct SPI modes, when the highside/push-pull drivers are set on/off/high/low via SPI,
the outputs change state at the end of the SPI cycle, on
the rising CS edge, with a sub 1µs propagation delay, as
defined in the Electrical Properties Table. In direct and
command mode SPI, diagnostic and status information
is sampled at the beginning of each SPI cycle, initiated
by the falling CS edge and is then sequentially written out
on SDO on each falling CLK edge. Command SPI mode
allows reading back the chip configuration and status
and diagnostics, as selected via the command byte. This
information is then written out on the following SPI cycle.
Table 4. SPI interface Modes Selection and Description
PIN
COMMAND
MODE
DIRECT SPI
8-BIT/16-BIT OPERATION
SPI
MODE
SRIAL
1
1
RESULT
CMND CNFG
/IN2 /IN7
0
0
S16
/IN8
BITS
0
8
Per-channel OUT_
setting
Per-channel fault
1
16
Per-channel OUT_
setting and HS/PP
selection
Per-channel fault
and level
0
8
Per-channel config:
HS/PP
Per-channel fault
1
16
Per-channel config:
HS/PP and OL
detection on/off
Per-channel fault
and level
0
1
SDI
SDO
NOTES
OUT set by SPI. FAULT is the
real-time status of the fault (driver
shutdown or open-load)
OUT level does not change
1
1
X
X
16
8-bit-command +
8-bit data
Previous command
output
OUT level may or may not change
depending on command
0
X
X
X
16
8-bit-command +
8-bit data
Previous command
output
OUT set by INx pins. MAX14912
allows SPI configuration. MAX14913
does not allow SPI configuration.
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Maxim Integrated │ 21
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Daisy-Chain SPI Operation
Direct SPI Serial Interface: 8-bit Mode
The device supports daisy-chain operation, allowing control/
monitoring of multiple MAX14912/MAX14913 devices
from a single serial interface with one common chip-select
signal. The identical data that is clocked into SDI, is
clocked out of SDO with a one SPI cycle delay. This is
illustrated in Figure 8.
SRIAL = high, CMND = low, S16 = low.
Figure 9 shows an 8-bit cycle that reads the per-channel
diagnostic data and sets/configures the outputs in a single
8-bit cycle. Table 5 illustrates the meaning of the SPI bits.
The data returned on SDO is the per-channel fault status.
Pin CNFG is used to select whether the SDI input bits set
the output level or the output mode (high-side or pushpull).
CLK
CLK
D A T A - I
SDI
MOSI
MCU
CLK
C 1
F I
F O - I
C 1
D I
A G - I
C 1
SDI
SDO
CS
CLK
C 2
F I
F O - I
C 2
D I
A G - I
C 2
SDO
SDI
CS
MAX14912/
MAX14913
CS
D A T A - I
D A T A - I
C 3
F I
F O - I
C 3
D I
A G - I
C 3
SDO
CS
MAX14912/
MAX14913
MAX14912/
MAX14913
MISO
Figure 7. Daisy-Chain Connection
CS
CLK
SDI
D8
D7
D6
SDO
F8
F7
F6
D5
F5
D4
D3
D2
D1
F4
F3
F2
F1
Figure 8. SPI Cycle in 8-Bit Direct SPI Mode
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Maxim Integrated │ 22
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Direct SPI Serial Interface: 16-Bit Mode
Table 6. 16-Bit SPI Direct Mode Bit
Definition
SRIAL = High, CMND = Low, S16 = High
Figure 9 shows a 16-bit read/write cycle that reads the
per-channel diagnostic data and configures/sets the outputs
in a single 16-bit cycle.
BIT
BIT VALUE CNFG
D_
The data returned on SDO is the per-channel fault status.
The CNFG pin is used to select whether the input bits sent
to SDI set the output level or the output mode (high-side
or push-pull). Moreover, in 16-bit mode, the open-load
detection can be enabled on a per-channel basis.
C_
D_C_
Table 5. 8-Bit SPI Direct Mode Bit
Definition
BIT
BIT VALUE CNFG
D_
F_
F_
DEFINITION
In high-side mode: set HS off
In push-pull mode: HS off, LS on
0
Low
1
In high-side mode: set HS switch on
Low In push-pull mode: set HS switch
on, LS off
0
High Configure high-side mode
1
High Configure push-pull mode
0
X
1
X
L_
DEFINITION
In high-side mode: HS off, LS off
In push-pull mode: HS off, LS on
0
Low
1
Low HS on, LS off
0
Low High-side mode
1
Low Push-pull mode
00
High
01
High Push-pull mode
10
High High-side mode with open-load detection
11
High Not used
High-side mode; open-load detection
defined by OL/IN1 pin
0
X
No fault
1
X
Fault status (thermal protection or openload)
0
X
Output level < 7V
1
X
Output level > 7V
No fault
Fault (thermal protection or open
load
CS
CLK
SDI
SDO
D8
D7
D6
D5
D4
D3
D2
D1
C8
C7
C6
C5
C4
C3
C2
C1
F8
F7
F6
F5
F4
F3
F2
F1
L8
L7
L6
L5
L4
L3
L2
L1
Figure 9. SPI Cycle in 16-Bit Direct SPI Mode
www.maximintegrated.com
Maxim Integrated │ 23
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Command Mode SPI
CMND = High
In serial setting mode (SRIAL = high), command SPI
mode allows setting, configuration and monitoring. In
parallel setting mode (SRIAL = low) command mode
allows monitoring. While the MAX14912 supports SPI
configuration in parallel mode, configuration is not
supported in the MAX14913. In command mode, the input
is always a command + data word; pins CNFG, S16, and
OL are ignored. The output word returns the information
requested during the previous SPI cycle.
Table 7 lists the registers accessible in command mode,
while Table 8 lists the commands and their effect.
In command mode, a latched version of all faults is available.
In other words, the device keeps any fault in memory until
the user decides to clear the fault registers. Each bit of
fault registers 4, 5, and 6 is set as soon as its corresponding
real-time fault signal goes high. At the end of any SPI
cycle during which the SDI MSB (the Z bit) has been set
to 1, all fault registers are cleared at once (see Table 8).
If [SRIAL = high and CMND = high], the global FAULT
signal is latched as well (see Table 9 for more details
on the global FAULT signal). Otherwise, it is a real-time
global fault status.
In command mode, both the latched and the real-time
faults can be read out. All commands except #4 returns
the same real-time data as in the 16-bit mode. Command
#4 can be used to read any register and, for fault registers
4, 5, and 6, it returns both the latched and real-time value
of any fault signal.
Table 7. SPI REGISTERS (Accessible Only in COMMAND Mode)
REG
R/W
PURPOSE
7
6
5
4
3
2
1
0
0
R/W
Switch/Driver Settings
(Note 10)
IN8
IN7
IN6
IN5
IN4
IN3
IN2
IN1
Default
0
0
0
0
0
0
0
0
Push-Pull/High-Side
Configuration (Note 11)
PP8
PP7
PP6
PP5
PP4
PP3
PP2
PP1
Default
0
0
0
0
0
0
0
0
Open Load Detect
Enable (Note 11)
OL_EN8
OL_EN7
OL_EN6
OL_EN5
OL_EN4
OL_EN3
OL_EN2
OL_EN1
Default
0
0
0
0
0
0
0
0
Watchdog Config. And
Channel Paralleling
(Note 11)
—
—
—
—
joinUP
joinDW
WD1
WD0
Default
0
0
0
0
0
0
0
0
1
2
3
R/W
R/W
R/W
4
R
Per-Channel Open-Load
Condition
OL8*
OL7*
OL6*
OL5*
OL4*
OL3*
OL2*
OL1*
5
R
Per-Channel Thermal
Shutdown
THSD8*
THSD7*
THSD6*
THSD5*
THSD4*
THSD3*
THSD2*
THSD1*
6
R
Global Faults
WDfault
CRCfault
DCDC
CurrentLimit
8CKmult
THSDglob* 5V UVLO
Error*
VDD
UVLO
VDD
WARN
7
R
OUT Overvoltage
Detection
(Note 9)
OV8
OV7
OV6
OV2
OV1
OV5
OV4
OV3
Note 9: Bits are set when the OUT_ voltage is higher than VDD. These bits are real-time.
Note 10: Register 0 can be written to, but will not change the output states in Parallel (SRIAL = low) setting mode, since the outputs
are then only set through the IN_ pins.
Note 11: Registers 1, 2, 3 can be written to in the MAX14913, but will not change the configuration in Parallel (SRIAL = low) setting mode.
* Faults are stretched in time to a minimum duration of 200ms.
www.maximintegrated.com
Maxim Integrated │ 24
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Table 8. COMMAND MODE Protocol
SDI
SDO
VALID ON NEXT
CYCLE
COMMAND
NO.
FUNCTION
0
Set OUT State
(Reg 0)
(Note 15)
Z0000000
DDDDDDDD
FFFFFFFF.LLLLLLLL
D = 0 : HS off; LS on (in PP)
D = 1 : HS on; LS off
L: Output Level
F: Fault (Real-Time)12
Z = 1: Clear Fault Registers13
1
Set HS/PP Mode
(Reg 1) (Note 16)
Z0000001
DDDDDDDD
FFFFFFFF.LLLLLLLL
D = 0 : HS Mode
D = 1 : PP Mode
2
Set OL Detection
(Reg 2) (Note 16)
Z0000010
DDDDDDDD
FFFFFFFF.LLLLLLLL
D = 0 : OL Detection Off
D = 1 : OL Detection On (HS Mode)
3
Set Configuration
(Reg 3) (Note 16)
Z0000011
0000JJAB
FFFFFFFF.LLLLLLLL
AB: Watchdog 00 = 0.90s 01 = 0.45s
10 = 0.15s J = 1: Channels are
Coupled (PP Disabled)
4
Read Register
(Note 14)
Z0100000
00000NNN
5
Read Real-Time
Status (Note 12)
Z0110000
—
COMMAND
DATA
COMMENT
NNN = 0,1,2,3: Q = Reg value, A = 0
NNN = 4,5,6: Q = Reg value, A =
AAAAAAAA.QQQQQQQQ
Real_time
NNN = 7: Q = 0, A = Real_time
FFFFFFFF.LLLLLLLL
F-L Status Readout (Real-Time).
No Data is Written
Note 12: F bits are the logical OR of thermal protection and open-load detection real-time signals.
Note 13: Any fault bit inside registers 4, 5, and 6 are set as soon as its corresponding event happens. All fault registers are cleared
only by setting Z = 1 (this is possible during any command cycle). The registers get cleared at CS rising edge. If Z = 1 the
registers are not cleared in case of SPI communication error (CRC, 8-CK).
If SRIAL = 1 and CMND = 1, the Z bit clears also the FAULT IRQ signal.
Note 14: The Q bits are the value of the fault registers (that need to be cleared by means of the Z bit).
The A bits are the corresponding real-time values (i.e., the real-time fault signals). The real-time values are stretched by
200ms. Therefore, they have a time resolution of ~200ms.
Note 15: In parallel setting mode (SRIAL = low), writing to this registers does not change the real-time values or settings. These
can only be changed through pins.
Note 16: For the MAX14913 only, in parallel setting mode (SRIAL = low), writing to these registers does not change the configuration.
www.maximintegrated.com
Maxim Integrated │ 25
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Table 9. FAULT SUMMARY
FAULT NAME
WHAT IT CHECKS
EFFECT ON FAULT
PIN
NAME
Per-Channel Thermal
Shutdown (Note 17)
Temp (HS) > 170°C
or Temp (LS) > 170°C
Single-channel HS and LS
are turned off immediately.
FAULT
(Note 18)
Global Thermal
Shutdown
Die-Center Temperature >
150°C
All channels HS and LS are
FAULT
turned off.
Channel Open-Load
Detection
(If Enabled)
HS Mode Only.
HS On: Current < 2mA
HS Off: Current < 80µA
VDD UndervoltageLockout
VDD < VDD_UV
All channels HS and LS are
UVLO
turned off; all LEDs off
V5 UndervoltageLockout
V5 < VV5_UV
All channels HS and LS are
turned off; all LEDs off
VDD Warning
VDD < VVDD_WARN
Watch-Dog
(If Enabled)
Activity on CS:
Fault if no falling-edge for
more than 1.2s (or 600ms
or 200ms)
No 8-Multiple CK
Pulses
Number of CK pulses
during a CS low period not
a multiple of 8
CRC Error Detection
(If Enabled)
Received data does not
match the FCS word
FAULT
BEHAVIOR
REG
BIT(S)
Pin goes low on any
fault;
if command-mode: pin
goes high when Z bit
is set,
else: pin goes high
when no faults
Reg 5
Goes low
Reg 6 bit 1
Reg 6 bit 3
Reg 4
Reg 6 bit 2
Reg 6 bit 0
SPI input data is discarded
SPI input data is discarded
WDFLT
Goes high;
goes low at next CS
falling-edge
Reg 6 bit 7
FAULT
Goes low on CS rise;
Reg 6 bit 4
CERR
Goes high;
goes high on next CS
rise if fault does not
happen again
Reg 6 bit 6
Note 17: The HS or LS FETs are turned on/off according to the thermal protection signal generated by the analog circuit. On the
other hand, inside the logic circuit the thermal-protection signal is maintained high for at least 200ms (to filter out the
~10ms hysteretic cycling of the FET temperature).
Note 18: In command mode the FAULT pin behaves as an IRQ latched signal and can be cleared only by setting the Z bit to 1 (as
for any other fault register). In all other modes, FAULT is the logical OR of the real-time faults.
www.maximintegrated.com
Maxim Integrated │ 26
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Error Detection on the Serial Interface
CRC Detection
In serial mode (SRIAL = high), error-detection of the serial
data can be enabled to minimize incorrect operation/
misinformation due to data corruption of the SDI/SDO signals. If enabled, the devices performs error detection on
SDI data received from the controller, calculates a CRC
on the SDO data sent to the controller, and appends a
check byte to the SDO diagnostics/status data it sends to
the controller. This ensures that the data it receives from
the controller (setting/configuration), as well as the data
that it sends to the controller (diagnostics/status), has a
low likelihood of undetected errors.
Setting the CRC/IN3 input high enables CRC error detection.
A CRC frame-check sequence (FCS) is then sent along
with each serial transaction. The 7-bit FCS is based on the
generator polynomial (x7 + x5 + x4 + x2 + x + 1). The CRC
initialization condition is 0x7F. When CRC is enabled, the
device expects a check byte appended to the 8 or 16-bit
SDI program/configuration data it receives. The check
byte has the format shown in Figure 10.
The 7-bit FCS bits (CRI_) are calculated on the 8/16-bit
data, including the 1 in the first position of the check byte.
Therefore, the CRC is calculated on 9 or 17 bits. CRI1 is
the LSB of the FCS.
The device verifies the received FCS. If no error is
detected, it sets the OUT_ outputs and/or changes configuration per the SDI data. If a CRC error is detected, the
device does not change the OUT_ outputs and/or does
not change its configuration. Instead, it sets the CERRB/
IN4 output low (i.e., the open-drain CERRB/IN4 nMOS
output transistor is turned on) and sets the CERR (CRC
error) bit in the check byte that it appends to the 8/16-bit
SDO diagnostic/status data returned to the controller during the following serial communication cycle. In command
SPI mode, register 6 also reflects an CRC error condition.
The check byte the device appends to the 8/16-bit diagnostics/status data has the format shown in Figure 11.
CERR is the error-feedback bit that it sends back to the
controller to signal that a CRC error was detected on the
previous SDI data reception. Note that CERR is one state
delayed (i.e., it indicates if an error was detected in the
previous SPI data reception). The reason for the onecycle delay is due to the daisy-chain scheme.
CRO_ are the CRC bits that the device calculates on
the 8/16-bit diagnostics and/or status data, including the
CERR bit (i.e., calculated on 9/17 bits). This allows the
controller to check for errors on the SDO data received
from the device.
Clock Count for Multiples of 8
For each SPI cycle (between CS going low to CS going
high), the device counts the number of CLK pulses. The
8CKmult error flag (see Table 7) is asserted (goes high)
and the FAULT pin is asserted (goes low) if the counted
CLK pulses are not a multiple of 8. In this case, the SDi
data is ignored.
C
CS
C
C
C
C
C
C
C
C
C
Figure 10. SDI Check Byte Expected from Controller
www.maximintegrated.com
S
C
C
C
C
C
C
C
Figure 11. SDO Check Byte Sent by Device
Maxim Integrated │ 27
MAX14912/MAX14913
Applications Information
PCB Layout and Circuit Recommendations
●● Capacitor between VPMP and VDD: 10µF 5V;
●● Capacitor between CFN and CFP: 200nF 50V;
●● Capacitor on V5: only one 10µF plus a ceramic
100nF as fast bypass capacitor close to each chip.
A 1206 footprint 10µF cap is recommended;
●● LX trace must be as short as possible;
●● Connection between the inductor and V5 can be long;
●● Inductor is 100µH: ISAT > 0.35A, DCR ~1Ω (e.g., the
Coilcraft LPS4018-104ML);
●● GND and VDD connections: Dedicated PCB planes
for GND and another for VDD are recommended.
Driving Capacitive Loads
When charging/discharging purely capacitive loads with
a push-pull driver, the driver dissipates power that is proportional to the switching frequency. The power can be
estimated by PD ~ C x VDD2 x fSW, where C is the load
capacitance, VDD is the supply voltage, and fSW is the
switching frequency. For example, in an application with
a 1nF load and 100kHz switching frequency, each driver
dissipates 130mW at VDD = 36V. When driving purely
capacitive loads, consider a maximum capacitance of
approximately 10nF.
Driving Inductive Loads
During turn-off of inductive loads by the high-side switch,
the kickback voltage generated by the inductance is
clamped by the internal clamp to a voltage of -56V (typ)
relative to VDD.
Large inductance and higher initial currents in the inductive
load increase the time to until the inductance is demagnetized. Large energy dissipated in the chip through the
voltage clamp. The MAX14912/MAX14913 feature Safe
Demagnetization, which allows inductive loads of any
value to be turned off. In high-side mode, the MAX14912/
MAX14913 do not have a limitation to the maximum
inductive load that can be switched by the OUTs.
www.maximintegrated.com
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Board Layout
High-speed switches require proper layout and design
procedures for optimal performance. Ensure that powersupply bypass capacitors are placed as close as possible
to the device. Connect all VDD pins to a VDD plane.
Ensure that all pins have no more than 10mΩ between
them. In this case, a 1µF capacitor should be placed as
close as possible to the VDD pins. In case low-resistance
paths are not possible between the VDD pins, bypass
each pin to GND through a 100nF capacitor.
Surge Protection
The MAX14913 OUT_ pins achieve ±1kV/(42Ω + 0.5µF)
IEC-61000-4-5 1.2µs/50µs surge ratings by using only a
TVS protection diode on VDD, as shown in the Typical
Application Circuit.
A suppressor/TVS diode should be used between VDD
and GND to clamp high-surge transients on the VDD supply
input and surges from the O_ outputs. The standoff voltage
should be higher than the rated operating voltage of the
equipment, while the breakdown voltage should be below
75V.
Reverse Currents Into OUT
If currents flow into the OUT_ pins, the device will heat
up due to internal currents that flow through the device
to PGND. The allowed reverse currents thus depend on
VDD, the ambient temperature and the thermal resistance.
At 25°C ambient temperature the reverse current into
one OUT should be limited to 1A at VDD = 36V and 2A at
VDD = 24V. Driving higher currents into OUT can destroy
the device thermally.
Enable Time
At power-up and/or when EN is pulled high, all IN_ signals
must be kept low for at least 20ms.
Maxim Integrated │ 28
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Ordering Information
PART
TEMP RANGE
PACKAGE
PACKAGE CODE
PACKAGE BODY SIZE
LEAD PITCH
MAX14912AKN+*
-40°C to +125°C
QFN56
K5688+1
8mm x 8mm
0.5mm
MAX14912AKN+T*
-40°C to +125°C
QFN56
K5688+1
8mm x 8mm
0.5mm
MAX14913AKN+
-40°C to +125°C
QFN56
K5688+1
8mm x 8mm
0.5mm
MAX14913AKN+T
-40°C to +125°C
QFN56
K5688+1
8mm x 8mm
0.5mm
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*Future product—contact factory for availability.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
56 QFN-EP
K5688+1
21-100026
90-100006
www.maximintegrated.com
Maxim Integrated │ 29
MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Revision History
REVISION
NUMBER
REVISION
DATE
0
12/15
DESCRIPTION
Initial release
1
5/16
Updated Electrical Characteristics table
2
6/16
Updated VPMP abs max limit
3
8/16
Updated text and diagrams
PAGES
CHANGED
—
1, 3–5, 7, 9, 23, 29
3
2, 3, 9–11, 14, 18,
19, 24–26, 28
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2016 Maxim Integrated Products, Inc. │ 30

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