MITSUBISHI LSIs '97.3.21 M5M5V208FP,VP,RV,KV,KR -70L-W , -85L -W, -10L-W , -12L-W , -70LL-W, -85LL-W, -10LL-W, -12LL-W 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M5M5V208 is 2,097,152-bit CMOS static RAM organized as 262,144-words by 8-bit which is fabricated using high-performance quadruple-polysilicon and double metal CMOS technology. The use of thin film transistor(TFT) load cells and CMOS periphery results in a high density and low power static RAM. The M5M5V208 is designed for memory applications where high reliability, large storage, simple interfacing and battery back-up are important design objectives. The M5M5V208VP,RV,KV,KR are packaged in a 32-pin thin small outline package which is a high reliability and high density surface mount device(SMD).Two types of devices are available. VP,KV(normal lead bend type package),RV,KR(reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board. A17 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 DQ1 13 DQ2 14 DQ3 15 (0V)GND 16 FEATURE Type Access Power supply current time Active Stand-by (max) (max) (max) M5M5V208FP,VP,RV,KV,KR-70L 70ns M5M5V208FP,VP,RV,KV,KR-85L 85ns M5M5V208FP,VP,RV,KV,KR-10L 100ns M5M5V208FP,VP,RV,KV,KR-12L 120ns M5M5V208FP,VP,RV,KV,KR-70LL 70ns M5M5V208FP,VP,RV,KV,KR-85LL 85ns M5M5V208FP,VP,RV,KV,KR-10LL M5M5V208FP,VP,RV,KV,KR-12LL 100ns 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC(3V) A15 S2 W A13 A8 A9 A11 OE A10 S1 DQ8 DQ7 DQ6 DQ5 DQ4 Outline 32P2M-A(FP) 60µA (Vcc=3.6V) 27mA (Vcc=3.6V) 10µ A (Vcc=3.6V) 120ns • Single 2.7 ~ 3.6V power supply • W-version: operating temperature of -20 to +70°C • No clocks, No refresh • All inputs and outputs are TTL compatible. • Easy memory expansion and power down by S1 & S2 • Data retention supply voltage=2.0V • Three-state outputs: OR-tie capability • OE prevents data contention in the I/O bus • Common Data I/O • Battery backup capability • Small stand-by current · · · · · · · · · · 0.3µA(typ.) PACKAGE A11 A9 A8 A13 W S2 A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4 APPLICATION 5 6 7 8 9 10 11 12 13 M5M5V208VP,KV -W 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 S1 DQ8 DQ7 DQ6 DQ5 DQ4 GND DQ3 DQ2 DQ1 A0 A1 A2 A3 Outline 32P3H-E(VP), 32P3K-B(KV) A4 A5 A6 A7 A12 A14 A16 A17 Vcc A15 16 15 A13 A8 A9 A11 4 3 S2 W M5M5V208FP : 32 pin 525 mil SOP M5M5V208VP,RV : 32pin 8 X 20 mm2 TSOP M5M5V208KV,KR : 32pin 8 X 13.4 mm2 TSOP 1 2 3 4 17 18 19 20 21 22 14 13 12 11 10 9 8 7 6 5 M5M5V208RV,KR -W 2 1 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND DQ4 DQ5 DQ6 DQ7 DQ8 S1 A10 OE Outline 32P3H-F(RV), 32P3K-C(KR) Small capacity memory units Battery operating system Handheld communiation tools MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs '97.3.21 M5M5V208FP,VP,RV,KV,KR -70L-W , -85L -W, -10L-W , -12L-W , -70LL-W, -85LL-W, -10LL-W, -12LL-W 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM FUNCTION The operation mode of the M5M5V208 is determined by a combination of the device control inputs S1, S 2, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W, S1 or S2, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable OE directly controls the output stage. Setting the OE at a high level,the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while S1 and S 2 are in an active state (S1 = L ,S2 = H). When setting S1 at a high level or S2 at a low level, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by S1 or S2. The power supply current is reduced as low as the stand-by current which is specified as Icc3 or Icc4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the nonselected mode. FUNCTION TABLE S1 S2 W OE Mode DQ Icc X L X X Non selection High-impedance Standby H X X X Non selection High-impedance Standby L H L X Write D IN Active L H H L Read D OUT Active L H H H High-impedance Active BLOCK DIAGRAM * A4 A5 * 8 16 7 15 21 13 DQ1 22 14 23 15 DQ2 DQ3 25 17 26 18 27 19 A6 A7 6 14 5 13 A12 4 12 A14 A16 3 11 2 10 A17 A15 1 9 28 20 31 7 29 21 A0 12 20 A1 A2 11 19 10 18 A3 9 17 A10 23 31 A11 25 A9 A8 26 2 27 3 A13 28 4 262144 WORDS X 8 BITS 512 ROWS X 128 COLUMNS X 32 BLOCKS DQ4 DQ5 DQ6 DQ7 DQ8 CLOCK GENERATOR 5 29 W 30 22 6 30 S1 S2 32 24 8 32 24 16 1 OE VCC (3V) GND (0V) *Pin numbers inside dotted line show those of TSOP. MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs '97.3.21 M5M5V208FP,VP,RV,KV,KR -70L-W , -85L -W, -10L-W , -12L-W , -70LL-W, -85LL-W, -10LL-W, -12LL-W 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Supply voltage Vcc VI VO Pd Topr Tstr Conditions Input voltage Ratings – 0.5*~4.6 – 0.5* ~ Vcc + 0.5 With respect to GND Output voltage Power dissipation Operating temperature Storage temperature (Max 4.6) 0 ~ Vcc 700 – 20 ~ 70 – 65 ~150 Ta=25°C Unit V V V mW °C °C * –3.0V in case of AC ( Pulse width ≤ 30ns ) DC ELECTRICAL CHARACTERISTICS Symbol Parameter VIH High-level input voltage VIL VOH1 VOH2 Low-level input voltage High-level output voltage 1 High-level output voltage 2 VOL II IO Low-level output voltage Input current Output current in off-state Icc1 Icc2 Active supply current (CMOS-level Input) Active supply current (TTL-level Input) (Ta=– 20~70°C, Vcc= 2.7 ~ 3.6V, unless otherwise noted) Stand-by current Min –0.3* 2.4 Vcc -0.5V IOH= –0.5mA IOH= –0.05mA IOL=2mA VI=0 ~ Vcc S1=VIH or S2=VIL or OE=VIH VI/O=0 ~ Vcc S1 ≤ 0.2V, S2≥ Vcc-0.2V, other inputs ≤ 0.2V or ≥ Vcc-0.2V,output-open S1=VIL,S2=VIH, other inputs=VIH or VIL output-open Stand-by current Max Vcc +0.3V 0.6 V V V 0.4 ±1 V µA ±1 µA 20 25 f= 5MHz 10 13 f= 10MHz 22 27 f= 5MHz 12 15 -L -20 ~ +70°C 60 -20 ~ +70°C 2) S1 ≥ Vcc-0.2V, S2 ≥ Vcc-0.2V -LL -20 ~ +40°C other inputs=0 ~ Vcc 10 S1=VIH or S2=VIL,other inputs=0 ~ Vcc Unit V f= 10MHz +25°C Icc4 Typ 2.0 1) S2 ≤ 0.2V or Icc3 Limits Test conditions 1 0.3 mA mA µA 0.6 0.33 mA * –3.0V in case of AC ( Pulse width ≤ 30ns ) CAPACITANCE Symbol CI CO Parameter Input capacitance Output capacitance (Ta=– 20 ~ 70°C, Vcc= 2.7 ~ 3.6V, unless otherwise noted) Limits Test conditions Unit Typ Min Max pF VI=GND, VI=25mVrms, f=1MHz 7 pF VO=GND,VO=25mVrms, f=1MHz 9 Note 1: Direction for current flowing into an IC is positive (no mark). 2: Typical value is for Vcc = 3V, Ta = 25°C MITSUBISHI ELECTRIC 3 MITSUBISHI LSIs '97.3.21 M5M5V208FP,VP,RV,KV,KR -70L-W , -85L -W, -10L-W , -12L-W , -70LL-W, -85LL-W, -10LL-W, -12LL-W 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (Ta =– 20 ~ 70°C, Vcc= 2.7 ~ 3.6V, unless otherwise noted ) 1TTL (1) MEASUREMENT CONDITIONS ................................. Vcc Input pulse level ............. Input rise and fall time ..... Reference level ............... Output loads ................... 2.7 ~ 3.6V VIH=2.2V,VIL=0.4V 5ns VOH=VOL=1.5V Fig.1,CL=30pF CL=5pF (for ten,tdis) Transition is measured ±500mV from steady state voltage. (for ten,tdis) DQ CL including scope and JIG Fig.1 Output load (2) READ CYCLE -70L,LL Min Max 70 70 70 70 35 25 25 25 10 10 5 10 Limits -85L,LL -10L,LL Min Max Min Max 85 100 85 100 85 100 85 100 45 50 30 35 30 35 30 35 10 10 10 10 5 5 10 10 -12L,LL Min Max 120 120 120 120 60 40 40 40 10 10 5 10 -70L,LL Min Max tCW Write cycle time 70 tw(W) Write pulse width 55 tsu(A) Address setup time 0 tsu(A-WH) Address setup time with respect to W 65 tsu(S1) Chip select 1 setup time 65 tsu(S2) Chip select 2 setup time 65 tsu(D) Data setup time 30 th(D) Data hold time 0 trec(W) Write recovery time 0 tdis(W) 25 Output disable time from W low tdis(OE) Output disable time from OE high 25 ten(W) Output enable time from W high 5 ten(OE) 5 Output enable time from OE low Limits -85L,LL -10L,LL Min Max Min Max 85 100 60 75 0 0 70 85 70 85 70 85 35 40 0 0 0 0 30 35 30 35 5 5 5 5 -12L,LL Min Max 120 85 0 100 100 100 45 0 0 40 40 5 5 Symbol Parameter tCR ta(A) ta(S1) ta(S2) ta(OE) tdis(S1) tdis(S2) tdis(OE) ten(S1) ten(S2) ten(OE) tV(A) Read cycle time Address access time Chip select 1 access time Chip select 2 access time Output enable access time Output disable time after S1 high Output disable time after S2 low Output disable time after OE high Output enable time after S1 low Output enable time after S2 high Output enable time after OE low Data valid time after address Unit ns ns ns ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Symbol Parameter MITSUBISHI ELECTRIC Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 4 MITSUBISHI LSIs '97.3.21 M5M5V208FP,VP,RV,KV,KR -70L-W , -85L -W, -10L-W , -12L-W , -70LL-W, -85LL-W, -10LL-W, -12LL-W 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM (4) TIMING DIAGRAMS Read cycle tCR A0~17 ta(A) tv (A) ta (S1) S1 (Note 3) S2 tdis (S1) (Note 3) tdis (S2) (Note 3) ta (S2) (Note 3) ta (OE) ten (OE) OE tdis (OE) (Note 3) (Note 3) ten (S1) ten (S2) DQ1~8 DATA VALID W = "H" level Write cycle (W control mode) tCW A0~17 tsu (S1) S1 (Note 3) (Note 3) S2 tsu (S2) (Note 3) (Note 3) tsu (A-WH) OE tsu (A) tw (W) trec (W) W tdis (W) tdis (OE) DQ1~8 ten (W) ten(OE) DATA IN STABLE tsu (D) MITSUBISHI ELECTRIC th (D) 5 MITSUBISHI LSIs '97.3.21 M5M5V208FP,VP,RV,KV,KR -70L-W , -85L -W, -10L-W , -12L-W , -70LL-W, -85LL-W, -10LL-W, -12LL-W 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM Write cycle ( S1 control mode) tCW A0~17 tsu (A) tsu (S1) trec (W) S1 S2 (Note 3) (Note 3) (Note 5) W (Note 4) (Note 3) tsu (D) th (D) (Note 3) DATA IN STABLE DQ1~8 Write cycle (S2 control mode) tCW A0~17 S1 (Note 3) (Note 3) tsu (A) tsu (S2) trec (W) S2 (Note 5) W (Note 4) (Note 3) DQ1~8 tsu (D) th (D) (Note 3) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". 4: Writing is executed while S2 high overlaps S1 and W low. 5: When the falling edge of W is simultaneously or prior to the falling edge of S1 or rising edge of S2, the outputs are maintained in the high impedance state. 6: Don't apply inverted phase signal externally when DQ pin is output mode. MITSUBISHI ELECTRIC 6 MITSUBISHI LSIs '97.3.21 M5M5V208FP,VP,RV,KV,KR -70L-W , -85L -W, -10L-W , -12L-W , -70LL-W, -85LL-W, -10LL-W, -12LL-W 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Parameter Vcc (PD) VI (S1) Power down supply voltage Chip select input S1 Chip select input S2 VI (S2) Icc (PD) Power down supply current (Ta = – 20 ~ 70°C, unless otherwise noted) Test conditions Min 2 2.0 Limits Typ Max 0.2 Vcc = 3.0V -L S2 ≤ 0.2V or S1 ≥ Vcc - 0.2V,S2 ≥ Vcc - 0.2V -LL 0.3 50 8 Unit V V V µA (Note 7) Note7: ICC (PD) = 0.5µA (Max.) in case of Ta = +25°C (2) TIMING REQUIREMENTS (Ta = – 20 ~ 70°C, unless otherwise noted ) Symbol Parameter tsu (PD) Power down set up time trec (PD) Power down recovery time Test conditions Min Limits Typ Max 0 5 Unit ns ms (3) POWER DOWN CHARACTERISTICS S1 control mode Vcc t su (PD) 2.7V 2.7V t rec (PD) 2.2V 2.2V S1≥ Vcc - 0.2V S1 S2 control mode Vcc t su (PD) S2 2.7V 2.7V 0.2V t rec (PD) 0.2V S2 ≤ 0.2V MITSUBISHI ELECTRIC 7