TI1 LM5165 3-v to 65-v input, 150-ma synchronous buck converter with ultra-low iq Datasheet

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LM5165-Q1
SNVSAJ3A – MARCH 2016 – REVISED MARCH 2016
LM5165-Q1 3-V to 65-V Input, 150-mA Synchronous Buck Converter with Ultra-Low IQ
1 Features
3 Description
•
•
The LM5165-Q1 is a compact, easy-to-use, 3-V to
65-V, ultra-low IQ synchronous buck converter with
high efficiency over wide input voltage and load
current ranges. With integrated high-side and lowside power MOSFETs, up to 150-mA of output
current can be delivered at fixed output voltages of
3.3 V or 5 V, or an adjustable output. The converter is
designed to simplify implementation while providing
options to optimize the performance the target
application. Pulse Frequency Modulation (PFM) mode
is selected for optimal light-load efficiency or
Constant On-Time (COT) control for nearly constant
operating frequency. Both control schemes do not
require loop compensation while providing excellent
line and load transient response and short PWM ontime for large step-down conversion ratios.
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Qualified for Automotive Applications
AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: –40ºC to 125ºC
Ambient Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C5
Wide Input Voltage Range of 3 V to 65 V
Fixed (3.3 V, 5 V) or Adjustable Output Voltages
Maximum Output Current as High as 150 mA
10.5-µA No Load Quiescent Current
–40°C to 150°C Junction Temperature Range
Selectable PFM or COT Mode Operation
Switching Frequency as High as 600 kHz
Integrated 2-Ω PMOS Buck Switch
– Supports 100% Duty Cycle for Low Dropout
Integrated 1-Ω NMOS Synchronous Rectifier
– Eliminates External Rectifier Diode
Programmable Current Limit Setpoint (4 Levels)
900-µs Internal or Programmable Soft Start
Monotonic Startup into Pre-Biased Output
No Loop Compensation or Bootstrap Components
Precision Enable/Input UVLO with Hysteresis
Open-Drain Power Good Indicator
Active Slew Rate Control for Low EMI
Thermal Shutdown Protection with Hysteresis
10-Lead, 3-mm x 3-mm VSON Package
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
VSON (10)
3 mm x 3 mm
LM5165-Q1
2 Applications
•
•
•
The high-side p-channel MOSFET can operate at
100% duty cycle for lowest dropout voltage and does
not require a bootstrap capacitor for gate drive. Also,
the current limit setpoint is adjustable to optimize
inductor selection for a particular output current
requirement. Selectable/adjustable startup timing
options include minimum delay (no soft start),
internally fixed (900 µs), and externally programmable
soft start via an external capacitor. An open-drain
PGOOD indicator can be used for sequencing and
output voltage monitoring. The LM5165-Q1 is
qualified to automotive AEC-Q100 grade 1 and is
available in a VSON-10 package with 0.5-mm pin
pitch.
LM5165X-Q1
Automotive and Battery-powered Equipment
High-voltage LDO Replacement
General Purpose Bias Supplies
LM5165Y-Q1
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Schematic, Fixed Output
LF
68 H
VIN = 3V...65V
Typical Efficiency, VOUT = 5 V
100
VOUT = 5V *
90
VIN
LM5165X
EN
PGOOD
80
VOUT
COUT
22 F
SS
HYS
ILIM
RT
GND
Efficiency (%)
CIN
1 F
SW
70
60
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
50
40
* VOUT tracks VIN
if VIN < 5V
30
0.1
1
Output Current (mA)
10
30
D101
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5165-Q1
SNVSAJ3A – MARCH 2016 – REVISED MARCH 2016
www.ti.com
4 Revision History
Changes from Original (February 2016) to Revision A
•
2
Page
Product Preview to Production Data Release ....................................................................................................................... 1
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SNVSAJ3A – MARCH 2016 – REVISED MARCH 2016
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
6
6
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 20
8
Applications and Implementation ...................... 21
8.1 Application Information............................................ 21
8.2 Typical Applications ................................................ 21
9 Power Supply Recommendations...................... 35
10 PCB Layout .......................................................... 35
10.1 Layout Guidelines ................................................. 35
10.2 Layout Example .................................................... 36
11 Device and Documentation Support ................. 38
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
Device Support ....................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
38
38
38
38
38
12 Mechanical, Packaging, and Orderable
Information ........................................................... 38
Device Comparison Table (1) (2)
PART NUMBER
LM5165XQDRCRQ1
LM5165XQDRCTQ1
LM5165YQDRCRQ1
LM5165YQDRCTQ1
LM5165QDRCRQ1
LM5165QDRCTQ1
(1)
(2)
VOLTAGE OPTION
5.0V
3.3V
Adjustable
PACKAGE QUANTITY
3000
250
3000
250
3000
250
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or refer to the TI website.
Package drawings, thermal data and symbolization are available at www.ti.com/packaging.
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5 Pin Configuration and Functions
DRC Package
10-Pin VSON with Exposed Thermal Pad
Top View
SW
1
10
GND
SW
1
10
GND
VIN
2
9
HYS
VIN
2
9
HYS
ILIM
3
8
VOUT
ILIM
3
8
FB
SS
4
7
EN
SS
4
7
EN
RT
5
6
PGOOD
RT
5
6
PGOOD
LM5165X, LM5165Y
Fixed Output Versions
LM5165
Adjustable Output Version
Pin Functions
PIN
NAME
NO.
I/O (1)
DESCRIPTION
SW
1
P
Switching node that is internally connected to the drain of the high-side PMOS buck switch and the drain of
the low-side NMOS synchronous rectifier. Connect to the switching side of the power inductor.
VIN
2
P
Regulator supply input pin to high-side power MOSFET and internal bias rail LDO. Connect to input supply
and input capacitor CIN. Path from VIN to the input capacitor must be as short as possible.
ILIM
3
I
Programming pin for current limit. Connecting the appropriate resistor from ILIM to GND selects one of four
pre-set current limit options. Short ILIM to GND for the maximum current setting.
SS
4
I
Programming pin for the soft-start time. If a 100-kΩ resistor is connected from SS to GND, the internal softstart circuit is disabled and the FB comparator reference steps immediately from zero to full value when the
regulator is enabled by the EN input. If the SS pin is left open, the internal soft-start circuit ramps the FB
reference from zero to full value in 900 µs. If an appropriate capacitance is connected to the SS pin, the
soft-start time can be programmed as required.
RT
5
I
Mode selection and on-time programming pin for Constant On-Time (COT) control. Short RT to GND to
select PFM (pulse frequency modulation) operation. Connect a resistor from RT to GND to program the ontime, which sets the switching frequency for COT.
PGOOD
6
O
Power Good output flag pin. PGOOD is connected to the drain of an NFET that holds the pin low when
either FB or VOUT is below the regulation target. Use a pull-up resistor of 10 kΩ to 100 kΩ to the system
voltage rail or VOUT (no higher than 12 V).
EN
7
I
Input pin of the precision enable / UVLO comparator. The converter is enabled when the EN voltage is
greater than 1.212V.
VOUT/FB
8
I
Feedback input to voltage regulation loop. The VOUT pin connects the internal feedback resistor divider to
the regulator output voltage for fixed 3.3V and 5V options. The FB pin connects the internal feedback
comparator to an external resistor divider for the adjustable output voltage option. The FB comparator
reference voltage is nominally 1.223V.
HYS
9
O
Drain of an internal NFET that is turned off when the EN input is greater than the EN threshold. An external
resistor from HYS to the EN pin UVLO resistor divider programs the input UVLO hysteresis voltage.
GND
10
G
Regulator ground return.
PAD
-
P
Exposed pad. Connect to the GND pin and system ground on PCB. Path to CIN must be as short as
possible.
(1)
4
P = Power, G = Ground, I = Input, O = Output.
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6 Specifications
6.1 Absolute Maximum Ratings (1) (2)
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted). (1)
MIN
MAX
VIN to GND
PARAMETER
–0.3
68
EN to GND
–0.3
VIN + 0.3
–0.7
VIN + 0.3
SW to GND
PGOOD, VOUT
20-ns transient
(3)
to GND
UNIT
–3
Survives short to automotive battery voltage
–0.3
V
16
HYS to GND
–0.3
7
ILIM, SS, RT, FB (4) to GND
–0.3
3.6
TJ
Maximum junction temperature (5)
–40
150
°C
Tstg
Storage temperature range
–55
150
°C
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Fixed output versions.
Adjustable output version.
High junction temperatures degrade operating lifetime. Operating lifetime is derated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1) (2)
VESD
(1)
(2)
(3)
Electrostatic
discharge
Charged device model (CDM), per
AEC Q100-011 (3)
UNIT
±2000
Corner pins (SW, RT, PGOOD, GND)
±750
Other pins
±500
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe
manufacturing with a standard ESD control process.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250 V CDM allows safe
manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions (1)
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted).
PARAMETER
Input voltages
Output current
(2)
NOM
MAX
UNIT
VIN
3
65
EN
–0.3
VVIN
PGOOD
–0.3
12
HYS
–0.3
5
IOUT (COT mode)
0
150
mA
IOUT (PFM mode)
0
100
mA
–40
150
°C
Operating junction temperature (2)
Temperature
(1)
MIN
V
Operating Ratings are conditions under which the device is intended to be functional. For specifications and test conditions, see
Electrical Characteristics.
High junction temperatures degrade operating lifetimes. Operating lifetime is derated for junction temperatures greater than 125°C.
6.4 Thermal Information
LM5165-Q1
THERMAL METRIC (1)
VSON
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
47.7
RθJC(top)
Junction-to-case (top) thermal resistance
59.9
RθJB
Junction-to-board thermal resistance
22.1
ψJT
Junction-to-top characterization parameter
1.0
ψJB
Junction-to-board characterization parameter
22.2
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.0
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to +125°C junction temperature
range. VIN = 12 V (unless otherwise noted). (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QUIESCENT CURRENTS
IQ-SHD
VIN DC supply current, shutdown
VEN = 0 V, TA = 25°C
4.6
6.0
IQ-SLEEP
VIN DC supply current, no load
VFB = 1.5 V, TA = 25°C
10.5
15.0
IQ-SLEEP-VINMAX VIN DC supply current, no load, VIN = 65V
VFB = 1.5 V, VVIN = 65 V, TA = 25°C
11.0
15.0
IQ-ACTIVE-PFM
VIN DC supply current, active
PFM mode
205
IQ-ACTIVE-COT
VIN DC supply current, active
COT mode, RRT = 107 kΩ
300
µA
POWER SWITCHES
RDSON1
High-side MOSFET RDS(on)
ISW = –10 mA
2
RDSON2
Low-side MOSFET RDS(on)
ISW = 10 mA
1
Ω
CURRENT LIMITING
ILIM1
ILIM2
High-side peak current current threshold
ILIM3
ILIM4
ILIM shorted to GND
220
240
264
RILIM = 24.9 kΩ
155
180
205
RILIM = 56.2 kΩ
100
120
145
RILIM = 100 kΩ
48
60
75
mA
REGULATION COMPARATOR
VVOUT50
VOUT 5V DC setpoint
LM5165X
4.9
5.0
5.1
VVOUT33
VOUT 3.3V DC setpoint
LM5165Y
3.23
3.30
3.37
(1)
(2)
6
V
All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying
statistical process control.
The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows:
TJ = TA + (PD • θJA) where θJA (in °C/W) is the package thermal impedance provided in the Thermal Information section.
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Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to +125°C junction temperature
range. VIN = 12 V (unless otherwise noted).(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
VVOUT = 5 V, LM5165X-Q1
6.7
VVOUT = 3.3 V, LM5165Y-Q1
3.9
IVOUT
VOUT pin input current
VREF1
Lower FB regulation threshold (PFM, COT)
VREF2
Upper FB regulation threshold (PFM)
FBHYS-PFM
FB comparator PFM hysteresis
PFM mode
10
FBHYS-COT
FB comparator dropout hysteresis
COT mode
4
IFB
FB pin input bias current
VFB = 1 V
FBLINE-REG
FB threshold variation over line
VVIN = 3 V to 65 V
0.001
VOUTLINE-REG
VOUT threshold variation over line
LM5165X-Q1, VVIN = 6 V to 65 V
LM5165Y-Q1, VVIN = 4.5 V to 65 V
0.001
FB voltage rising, relative to VREF1
94%
FB voltage falling, relative to VREF1
87%
Adjustable output version
MAX
UNIT
µA
1.205
1.223
1.241
1.220
1.233
1.246
V
mV
100
nA
%/V
POWER GOOD
UVTRISING
UVTFALLING
PGOOD comparator
80
200
Ω
VIN falling, IPGOOD = 0.1 mA,
VPGOOD < 0.5 V
1.20
1.65
V
VFB = 1.2 V, VPGOOD = 5.5 V
10
100
nA
RPGOOD
PGOOD on-resistance
VFB = 1 V
VINMIN-PGOOD
Minimum VIN for valid PGOOD
IPGOOD
PGOOD off-state leakage current
ENABLE / UVLO
VIN-ON
Turn-on threshold
VIN voltage rising
2.60
2.75
2.95
V
VIN-OFF
Turn-off threshold
VIN voltage falling
2.35
2.45
2.60
V
VEN-ON
Enable turn-on threshold
EN voltage rising
1.163
1.212
1.262
V
VEN-OFF
Enable turn-off threshold
EN voltage falling
1.109
1.144
1.178
VEN-HYS
Enable hysteresis
VEN-SD
EN shutdown threshold
EN voltage falling
RHYS
HYS on-resistance
VEN = 1 V
80
200
Ω
IHYS
HYS off-state leakage current
VEN = 1.5 V, VHYS = 5.5 V
10
100
nA
ISS
Soft-start charging current
VSS = 1 V
10
µA
TSS-INT
Soft-start rise time
SS floating
900
µs
68
0.3
V
mV
0.6
V
SOFT-START
THERMAL SHUTDOWN
TJ-SD
Thermal shutdown threshold
170
TJ-SD-HYS
Thermal shutdown hysteresis
10
°C
6.6 Switching Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TON-MIN
Minimum controllable PWM on-time
TON1
PWM on-time
TON2
PWM on-time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
180
ns
16 kΩ from RT to GND
250
ns
75 kΩ from RT to GND
1000
ns
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6.7 Typical Characteristics
100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to the Typical Applications section for circuit designs.
70
60
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
50
40
30
0.1
1
10
Output Current (mA)
5-V, 25-mA Design
LF = 470 µH
COUT = 47 µF
70
60
40
30
0.1
30
D101
FSW(nom) = 100 kHz
RILIM ≥ 100 kΩ
See schematic,
Figure 37
90
90
80
80
70
60
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
30
0.1
1
10
See schematic,
Figure 50
LF = 47 µH
COUT = 10 µF
70
60
See schematic,
Figure 62
90
80
80
Efficiency (%)
Efficiency (%)
90
60
VIN = 18V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 65V
1
Output Current (mA)
See schematic,
Figure 57
LF = 47 µH
COUT = 10 µF
10
LF = 150 µH
COUT = 22 µF
70
60
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 65V
40
75
D105
FSW(nom) = 500 kHz
RILIM = 24.9 kΩ
100 150
D104
FSW(nom) = 160 kHz
RRT = 121 kΩ
50
Figure 5. Converter Efficiency: 12 V, 75 mA, PFM
8
10
Figure 4. Converter Efficiency: 3.3 V, 150 mA, COT
100
70
1
Output Current (mA)
Figure 3. Converter Efficiency: 3.3 V, 50 mA, PFM
30
0.1
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
30
0.1
100
40
100 150
D102
FSW(nom) = 230 kHz
RRT = 133 kΩ
40
FSW(nom) = 350 kHz
RILIM = 56.2 kΩ
50
LF = 220 µH
COUT = 22 µF
50
50
D103
Output Current (mA)
10
Figure 2. Converter Efficiency: 5 V, 150 mA, COT
100
Efficiency (%)
Efficiency (%)
Figure 1. Converter Efficiency: 5 V, 25 mA, PFM
40
1
Output Current (mA)
100
50
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
50
30
0.1
1
10
Output Current (mA)
See schematic,
Figure 65
LF = 150 µH
COUT = 10 µF
100 150
D106
FSW(nom) = 600 kHz
RRT = 143 kΩ
Figure 6. Converter Efficiency: 15 V, 150 mA, COT
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to the Typical Applications section for circuit designs.
2
4
3.5
1.5
2.5
RDSon (:)
RDSon (:)
3
2
1.5
1
1
0.5
0.5
40°C
25°C
150°C
40°C
0
0
10
20
30
40
Input Voltage (V)
50
60
70
0
150°C
20
30
40
Input Voltage (V)
50
60
70
D002
Figure 8. Low-Side MOSFET On-state Resistance vs Input
Voltage
1.24
1.25
1.245
FB Regulation Thresholds (V)
1.22
EN Thresholds (V)
10
D001
Figure 7. High-Side MOSFET On-state Resistance vs Input
Voltage
1.2
1.18
1.16
1.14
1.12
Rising
Falling
1.1
-50
-25
0
25
50
75
Temperature (°C)
100
125
1.235
1.23
1.225
1.22
1.215
1.205
-50
150
Rising
Falling
-25
0
D004
Figure 9. Enable Threshold Voltage vs Temperature
25
50
75
Temperature (°C)
100
125
150
D005
Figure 10. Feedback Comparator Voltage vs Temperature
3.36
VOUT Regulation Thresholds (V)
5.06
5.04
5.02
5
4.98
4.96
4.94
Rising
Falling
4.92
4.9
-50
1.24
1.21
5.08
VOUT Regulation Thresholds (V)
25°C
0
-25
0
25
50
75
Temperature (°C)
100
125
150
3.34
3.32
3.3
3.28
3.26
Rising
Falling
3.24
-50
-25
D007
LM5165X
0
25
50
75
Temperature (°C)
100
125
150
D006
LM5165Y
Figure 11. VOUT Regulation Thresholds vs Temperature
Figure 12. VOUT Regulation Thresholds vs Temperature
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to the Typical Applications section for circuit designs.
300
94
250
93
92
Current Limit (mA)
PGOOD Thresholds Relative to Falling
FB Threshold (%)
95
91
90
89
88
87
200
150
100
50
60 mA
120 mA
FB Rising
FB Falling
86
85
-50
-25
0
25
50
75
Temperature (°C)
100
125
0
-50
150
Figure 13. PGOOD Thresholds vs Temperature
25
50
75
Temperature (°C)
100
Pull Down Resistance (:)
200
150
100
50
60 mA
120 mA
150
D009
0
10
20
30
40
Input Voltage (V)
50
125
100
75
50
180 mA
240 mA
25
-50
0
60
70
-25
0
D010
25
50
75
Temperature (°C)
100
125
150
D011
Figure 16. PGOOD and HYS Pulldown RDS(on) vs
Temperature
Figure 15. Peak Current Limits vs Input Voltage
3
4
RT = 16 k:
RT = 75 k:
VIN UVLO Thresholds (V)
3.5
3
2.5
2
1.5
1
2.8
2.6
2.4
2.2
0.5
Rising
Falling
0
0
10
20
30
40
Input Voltagae (V)
50
60
70
2
-50
-25
D012
Figure 17. COT One-shot Timer TON vs Input Voltage
10
125
Figure 14. Peak Current Limits vs Temperature
250
Current Limit (mA)
0
150
300
One-Shot Time (µs)
-25
D008
180 mA
240 mA
0
25
50
75
Temperature (°C)
100
125
150
D013
Figure 18. Internal VIN UVLO Voltage vs Temperature
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to the Typical Applications section for circuit designs.
20
12
10
Current (PA)
Current (PA)
15
10
8
6
4
5
2
Sleep
Shutdown
0
-50
Sleep
Shutdown
0
-25
0
25
50
75
Temperature (°C)
100
125
150
0
Figure 19. VIN Sleep and Shutdown Supply Current vs
Temperature
20
30
40
Input Voltage (V)
50
60
70
D015
Figure 20. VIN Sleep and Shutdown Supply Current vs Input
Voltage
400
350
350
300
300
250
250
Current (PA)
Current (PA)
10
D014
200
150
200
150
100
100
50
50
COT
PFM
0
-50
COT
PFM
0
-25
0
25
50
75
Temperature (°C)
100
125
150
0
10
D016
RRT = 75 kΩ
20
30
40
Input Voltage (V)
50
60
70
D017
RRT = 75 kΩ
Figure 21. VIN Active Mode Supply Current vs Temperature
Figure 22. VIN Active Mode Supply Current vs Input Voltage
VOUT
100 mV/DIV
VOUT
100 mV/DIV
IL
50 mA/DIV
VSW
5 V/DIV
VSW
5 V/DIV
2 Ps/DIV
5-V, 150-mA Design
IL
200 mA/DIV
20 ms/DIV
5-V, 150-mA Design
Figure 23. Full Load Switching Waveforms, COT
Figure 24. No Load Switching Waveforms, COT
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to the Typical Applications section for circuit designs.
IL 200 mA/DIV
VIN 5 V/DIV
VOUT 1 V/DIV
IL 100 mA/DIV
VSW 10 V/DIV
200 Ps/DIV
2 ms/DIV
5-V, 150-mA Design
5-V, 150-mA Design
Figure 25. Full Load Startup, COT
Figure 26. Short Circuit, COT
VOUT 100 mV/DIV
VOUT 100 mV/DIV
VSW 5 V/DIV
IL
20 mA/DIV
IL 20 mA/DIV
VSW 10 V/DIV
20 ms/DIV
2 ms/DIV
5-V, 25-mA Design
5-V, 25-mA Design
Figure 27. Full Load Switching Waveforms, PFM
Figure 28. No Load Switching Waveforms, PFM
IL 20 mA/DIV
VIN 5 V/DIV
VOUT 1 V/DIV
IOUT 50 mA/DIV
VSW 10 V/DIV
100 Ps/DIV
2 ms/DIV
5-V, 25-mA Design
5-V, 25-mA Design
Figure 29. Full Load Startup, PFM
12
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Figure 30. Short Circuit, PFM
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7 Detailed Description
7.1 Overview
The LM5165-Q1 converter is an easy-to-use synchronous buck DC/DC regulator that operates from a 3-V to 65V supply voltage. The device is intended for step-down conversions from 3.3-V, 5-V, 12-V, 24-V, and 48-V
unregulated, semi-regulated and fully-regulated supply rails. With integrated high-side and low-side power
MOSFETs, the LM5165-Q1 delivers up to 150-mA DC load current with high efficiency and ultra-low input
quiescent current in a very small solution size. Designed for simple implementation, a choice of operating modes
offers flexibility to optimize its usage according to the target application. In constant on-time (COT) mode of
operation, ideal for low-noise, high current, fast load transient requirements, the device operates with predictive
on-time switching pulse. A quasi-fixed switching frequency over the input voltage range is achieved by using an
input voltage feedforward to set the on-time. Alternatively, pulse frequency modulation (PFM) mode,
complemented by an adjustable peak current limit, achieves exceptional light-load efficiency performance.
Control loop compensation is not required with either operating mode, reducing design time and external
component count.
The LM5165-Q1 incorporates other features for comprehensive system requirements, including an open-drain
Power Good circuit for power-rail sequencing and fault reporting, internally-fixed or externally-adjustable softstart, monotonic startup into prebiased loads, precision enable with customizable hysteresis for programmable
line undervoltage lockout (UVLO), adjustable cycle-by-cycle current limit for optimal inductor sizing, and thermal
shutdown with automatic recovery. These features enable a flexible and easy-to-use platform for a wide range of
applications. The pin arrangement is designed for simple PCB Layout, requiring only a few external components.
7.2 Functional Block Diagram
IN
VIN
LDO BIAS
REGULATOR
LM5165
VDD
VDD UVLO
EN
HYS
THERMAL
SHUTDOWN
VIN UVLO
1.212V
1.144V
I-LIMIT
ADJUST
ILIM
ENABLE
VIN
CURRENT
LIMIT
+
ON-TIME
ONE SHOT
VIN
SW
Control
Logic
ZERO CROSS
DETECT
HYSTERETIC
MODE
RT
OUT
VOUT/FB
+
ZC
R1(1)
FEEDBACK
R2(1)
+
GND
VOLTAGE
REFERENCE 1.223V
ENABLE
PGOOD
UV
REFERENCE
SOFT-START
SS
PG
1.150V
1.064V
Note:
(1) R1, R2 are implemented in the fixed output voltage versions only.
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7.3 Feature Description
7.3.1 Integrated Power MOSFETs
The LM5165-Q1 is a step-down buck converter with integrated high-side PMOS buck switch and low-side NMOS
synchronous switch. During the high-side MOSFET on-time, the SW voltage VSW swings up to approximately VIN,
and the inductor current increases with slope (VIN – VOUT)/LF. When the high-side MOSFET is turned off by the
control logic, the low-side MOSFET turns on after an adaptive deadtime. Inductor current flows through the lowside MOSFET with slope –VOUT/LF. Duty cycle D is defined as TON/TSW, where TON is the high-side MOSFET
conduction time and TSW is the switching period.
7.3.2 Selectable PFM or COT Mode Converter Operation
Figure 31 and Figure 32 show converter schematics for PFM and COT modes of operation.
VIN
LF
VIN
VOUT
VIN
LM5165X
LM5165Y
EN
RUV1
VOUT
CIN
COUT
PGOOD
SW
EN
FB
RUV2
PGOOD
SS
HYS
HYS
ILIM
RT
RFB1
LM5165
CIN
SS
VOUT
LF
VIN
SW
ILIM
RHYS
COUT
CSS
RFB2
RILIM
RT
GND
(a)
GND
(b)
Figure 31. PFM Mode Converter Schematics: (a) Fixed Output Voltage of 5 V or 3.3 V, (b) Adjustable
Output Voltage with Programmable Soft Start, Current Limit and UVLO
VIN
LF
VIN
LM5165X
LM5165Y
EN
VOUT
CIN
VOUT
VIN
PGOOD
SS
RUV1
SW
EN
FB
PGOOD
SS
CIN
RUV2
HYS
HYS
ILIM
RT
RRT
GND
RFB1
LM5165
RESR
COUT
VOUT
LF
VIN
SW
ILIM
RT
RHYS
RFB2
COUT
RILIM
RRT
(a)
CSS
RESR
GND
(b)
Figure 32. COT Mode Converter Schematics: (a) Fixed Output Voltage of 5 V or 3.3 V, (b) Adjustable
Output Voltage with Programmable Soft Start, Current Limit and UVLO
The LM5165-Q1 operates in PFM mode when RT is shorted to GND. Configured as such, the LM5165-Q1
behaves as a hysteretic voltage regulator operating in boundary conduction mode, controlling the output voltage
within upper and lower hysteresis levels according to the PFM feedback comparator hysteresis of 10 mV.
Figure 33 is a representation of the relevant output voltage and inductor current waveforms. The LM5165-Q1
provides the required switching pulses to recharge the output capacitor, followed by a sleep period where most of
the internal circuits are shut off. The load current is supported by the output capacitor during this time, and the
LM5165-Q1 current consumption approaches the sleep quiescent current of 10.5 µA. The sleep period duration
depends on load current and output capacitance.
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Feature Description (continued)
VIN
SW
Voltage
VOUT
VREF = 1.233V
10mV
FB
Voltage
(internal)
ILIM
Inductor
Current
IOUT2
IOUT1
t
ACTIVE
SLEEP
ACTIVE
SLEEP
ACTIVE
SLEEP ACTIVE
Figure 33. PFM Mode SW Node Voltage, Feedback Voltage and Inductor Current Waveforms
When operating in PFM mode at given input and output voltages, the chosen filter inductance dictates the PFM
pulse frequency as
FSW(PFM)
VOUT
LF ˜ IPK(PFM)
§
VOUT ·
˜ ¨1
¸
VIN ¹
©
(1)
where IPK(PFM) corresponds to one of the four programmable levels for peak limit of inductor current. See the
Adjustable Current Limit section for more detail.
Configured in COT mode, the LM5165-Q1 based converter turns on the high-side MOSFET with on-time
inversely proportional to VIN to operate with essentially fixed switching frequency when in continuous conduction
mode (CCM). Diode emulation mode (DEM) prevents negative inductor current, and pulse skipping maintains
highest efficiency at light load currents by decreasing the effective switching frequency. The COT-controlled
LM5165-Q1 waveforms in CCM and DEM are represented in Figure 34. The PWM on-time is set by resistor RRT
connected from RT to GND as shown in Figure 32. The control loop maintains a constant output voltage by
adjusting the PWM off-time.
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Feature Description (continued)
VIN
SW
Voltage
Extended
On-Time
VOUT
FB
Voltage
(internal)
Inductor
Current
VREF
4 mV
DCM
Operation
IOUT2
CCM
Operation
IOUT1
SLEEP
ACTIVE
t
ACTIVE
SLEEP
Figure 34. COT Mode SW Node Voltage, Feedback Voltage and Inductor Current Waveforms
The required on-time adjust resistance for a particular frequency is given in Equation 2 and tabulated in Table 1.
The maximum programmable on-time is 15 µs.
RRT ¬ªk: ¼º
VOUT ¬ª V ¼º 104
˜
FSW ª¬kHz º¼ 1.6
(2)
Table 1. On-Time Adjust Resistance (E96 EIA Values) for Various Switching
Frequencies and Output Voltages
FSW (kHz)
RRT (kΩ)
VOUT = 1.8 V
VOUT = 3.3 V
VOUT = 5 V
VOUT = 12 V
100
113
205
316
750
200
56.2
105
154
374
300
37.3
68.1
105
249
400
28
51.1
78.7
187
500
23.2
41.2
61.9
150
600
20
34
52.3
124
The choice of control mode and switching frequency requires a compromise between conversion efficiency,
quiescent current, and passive component size. Lower switching frequency implies reduced switching losses
(including gate charge losses, transition losses, etc.) and higher overall efficiency. Higher switching frequency, on
the other hand, implies a smaller LC output filter and hence a more compact design. Lower inductance also
helps transient response as the large-signal slew rate of inductor current increases. The ideal switching
frequency in a given application is a tradeoff and thus is determined on a case-by-case basis. It relates to the
input voltage, output voltage, most frequent load current level(s), external component choices, and circuit size
requirement. At light loads, the PFM converter has a relatively longer sleep time interval and thus operates with
lower input quiescent current and higher efficiency.
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7.3.3 COT Mode Light-Load Operation
Diode emulation mode (DEM) operation occurs when the low-side MOSFET switches off as inductor valley
current reaches zero. Here, the load current is less than half of the peak-to-peak inductor current ripple in CCM.
Turning off the low-side MOSFET at zero current reduces switching loss, and preventing negative current
conduction reduces conduction loss. Power conversion efficiency is thus higher in a DEM converter than an
equivalent forced-PWM CCM converter. With DEM operation, the duration that both power MOSFETs remain off
progressively increases as load current decreases.
7.3.4 Low Dropout Operation and 100% Duty Cycle Mode
If RDSON1 and RDSON2 are the high-side and low-side MOSFET on-state resistances, respectively, and RDCR is the
inductor DC resistance, the duty cycle in COT (CCM) or PFM mode is given by Equation 3.
D
VOUT
VIN
RDSON2
RDCR ˜ IOUT
RDSON1 RDSON2 ˜ IOUT
|
VOUT
VIN
(3)
The LM5165-Q1 offers a low input voltage to output voltage dropout by engaging the high-side MOSFET at
100% duty cycle. In COT mode, a frequency foldback feature effectively extends maximum duty cycle to 100%
during low dropout conditions or load-on transients. Based on the 4-mV FB comparator dropout hysteresis, the
duty cycle extends as needed at low input voltage conditions, corresponding to lower switching frequency. The
PWM on-time extends based on the requirement that the FB voltage exceeds the dropout hysteresis during a
given on-time. 100% duty cycle operation is eventually reached as the input voltage decreases towards the
output setpoint. The output voltage stays in regulation at a lower supply voltage, thus achieving an extremely low
dropout voltage.
Note that PFM mode operation provides an inherently natural transition to 100% duty cycle if needed for low
dropout applications.
Use Equation 4 to calculate the minimum input voltage to maintain output regulation.
VIN(min) VOUT IOUT ˜ RDSON1 RDCR
(4)
7.3.5 Adjustable Output Voltage (FB)
Three voltage feedback options are available: the fixed 3.3-V and 5-V versions include internal feedback
resistors that sense the output directly through the VOUT pin; the adjustable voltage option senses the output
through an external resistor divider connected from the output to the FB pin.
The LM5165-Q1 voltage regulation loop regulates the output voltage by maintaining the FB voltage equal to the
internal reference voltage, VREF1. A resistor divider programs the ratio from output voltage VOUT to FB. For a
target VOUT setpoint, calculate RFB2 based on the selected RFB1 using Equation 5.
1.223V
RFB2
˜ RFB1
VOUT 1.223V
(5)
Selecting RFB1 of 100 kΩ is recommended for most applications. A larger RFB1 consumes less DC current,
mandatory if light-load efficiency is critical. High feedback resistances generally require more careful feedback
path PCB layout. It is important to route the feedback trace away from the noisy area of the PCB. For more
layout recommendations, please refer to the PCB Layout section.
7.3.6 Adjustable Current Limit
The LM5165-Q1 manages overcurrent conditions by cycle-by-cycle current limiting of the peak inductor current.
The current sensed in the high-side MOSFET is compared every switching cycle to the current limit threshold set
by the ILIM pin. Current is sensed after a leading-edge blanking time following the high-side MOSFET turn-on
transition. The propagation delay of current limit comparator is 100 ns.
Four programmable peak current levels are available: 60 mA, 120 mA, 180 mA and 240 mA, corresponding to
resistors of 100 kΩ, 56.2 kΩ, 24.9 kΩ and 0 Ω connected at the ILIM pin, respectively. In turn, 25mA, 50mA,
75mA and 100mA output current levels in boundary conduction mode PFM operation are possible, respectively.
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Note that in PFM mode, the inductor current ramps from zero to the chosen peak threshold every switching
cycle. Consequently, the maximum output current is equal to half the peak inductor current. Meanwhile, the
corresponding output current capability in COT mode is higher as the ripple current is determined by the input
and output voltage and the chosen inductance.
7.3.7 Precision Enable (EN) and Hysteresis (HYS)
The precision EN input supports adjustable input undervoltage lockout (UVLO) with hysteresis programmed
independently via the HYS pin for application specific power-up and power-down requirements. EN connects to a
comparator-based input referenced to a 1.212-V bandgap voltage with 68-mV hysteresis. An external logic signal
can be used to drive the EN input to toggle the output on and off and for system sequencing or protection. The
simplest way to enable the LM5165's operation is to connect EN directly to VIN. This allows self-startup of the
LM5165-Q1 when VIN is within its valid operating range. However, many applications benefit from using a resistor
divider RUV1 and RUV2 as shown in Figure 35 to establish a precision UVLO level. In tandem with the EN setting,
use HYS to increase the voltage hysteresis as needed.
VIN
VIN
LM5165
RUV1
EN
LM5165
Enable
Comparator
7
RUV2
RUV1
EN
Enable
Comparator
7
RUV2
1.212V
1.144V
1.212V
1.144V
RHYS
HYS
9
80Ÿ
(a)
(b)
Figure 35. Programmable Input Voltage UVLO with (a) Fixed Hysteresis, (b) Adjustable Hysteresis
Use Equation 6 and Equation 7 to calculate the input UVLO voltages turn-on and turn-off voltages, respectively.
VIN(on)
§
RUV1 ·
1.212V ˜ ¨ 1
¸
© RUV2 ¹
(6)
VIN(off)
§
·
RUV1
1.144V ˜ ¨ 1
¸
© RUV2 RHYS ¹
(7)
There is also a low IQ shutdown mode when EN is pulled below a base-emitter voltage drop (approximately 0.6 V
at room temperature). If EN is below this hard shutdown threshold, the internal LDO regulator powers off and the
internal bias supply rail collapses, shutting down the bias currents of the LM5165-Q1. The LM5165-Q1 operates
in standby mode when the EN voltage is between the hard shutdown and precision enable thresholds.
7.3.8 Power Good (PGOOD)
The LM5165-Q1 provides a PGOOD flag pin to indicate when the output voltage is within the regulation level.
Use the PGOOD signal for startup sequencing of downstream converters, as shown in Figure 36, or for fault
protection and output monitoring. PGOOD is an open-drain output that requires a pull-up resistor to a DC supply
not greater than 12 V. Typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider
to decrease the voltage from a higher voltage pull-up rail.
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VIN(on) = 4.50 V
VIN(off) = 3.15 V
RUV1
100 k
VOUT(MASTER) = 2.5 V
LM5165
7
EN
RUV2
36.5 k
7
PGOOD 6
9
HYS
RHYS
20 k
FB
8
RFB1
100 k
VOUT(SLAVE) = 1.5 V
LM5165
EN
RPGOOD
10 k
1.223 V
RFB3
22.3 k
PGOOD 6
9
HYS
FB
8
1.223 V
RFB4
100 k
RFB2
95.3 k
Regulator #1
Startup based on
Input Voltage UVLO
Regulator #2
Sequential Startup
based on PGOOD
Figure 36. Master-Slave Sequencing Implementation using PGOOD and EN
When the FB voltage exceeds 94% of the internal reference VREF1, the internal PGOOD switch turns off and
PGOOD can be pulled high by the external pull-up. If the FB voltage falls below 87% of VREF1, the internal
PGOOD switch turns on, and PGOOD is pulled low to indicate that the output voltage is out of regulation. The
rising edge of PGOOD has a built-in deglitch delay of 5 µs.
7.3.9 Configurable Soft Start (SS)
The LM5165-Q1 has a flexible and easy-to-use soft start control pin, SS. The soft-start feature prevents inrush
current impacting the LM5165-Q1 and the input supply when power is first applied. Soft start is achieved by
slowly ramping up the target regulation voltage when the device is first enabled or powered up.
Selectable/adjustable startup timing options include minimum delay (no soft-start), 900-µs internally fixed soft
start, and an externally programmable soft start.
The simplest way to use the LM5165-Q1 is to leave the SS pin open. The LM5165-Q1 employs the internal softstart control ramp and starts up to the regulated output voltage in 900 µs. In applications with a large amount of
output capacitance, higher VOUT, or other special requirements, extend the soft-start time by connecting an
external capacitor CSS from SS to GND. Longer soft-start time further reduces the supply current needed to
charge the output capacitors and supply any output loading. An internal current source ISS of 10 µA charges CSS
and generates a ramp to control the ramp rate of the output voltage. Use Equation 8 to calculate the CSS
capacitance for a desired soft start time tSS.
CSS ª¬nF º¼ 8.1˜ t SS ª¬ms º¼
(8)
CSS is discharged by an internal FET when VOUT is shutdown by EN, UVLO or thermal shutdown.
It is desirable in some applications for the output voltage to reach its nominal setpoint in the shortest possible
time. Connecting a 100-kΩ resistor from SS to GND disables the soft-start circuit, and the LM5165-Q1 operates
in current limit during startup to rapidly charge the output capacitance.
As negative inductor current is prevented, the LM5165-Q1 is capable of startup into prebiased output conditions.
With a prebiased output voltage, the LM5165-Q1 waits until the soft-start ramp allows regulation above the
prebiased voltage and then follows the soft-start ramp to the regulation setpoint.
7.3.10 Thermal Shutdown
Thermal shutdown is an integrated self-protection to limit junction temperature and prevent damage related to
over-heating. Thermal shutdown turns off the device when the junction temperature exceeds 170°C to prevent
further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the
LM5165-Q1 restarts when the junction temperature falls to 160°C.
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7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides ON and OFF control for the LM5165-Q1. When VEN is below approximately 0.6 V, the
device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in
shutdown mode drops to 4.6 µA at VIN = 12 V. The LM5165-Q1 also employs internal bias rail undervoltage
protection. If the internal bias supply voltage is below its UV threshold, the regulator remains off.
7.4.2 Standby Mode
The internal bias rail LDO has a lower enable threshold than the regulator itself. When VEN is above 0.6 V and
below the precision enable threshold (1.212 V typically), the internal LDO is on and regulating. The precision
enable circuitry is turned on once the internal VCC is above its UV threshold. The switching action and voltage
regulation are not enabled until VEN rises above the precision enable threshold.
7.4.3 Active Mode in COT
The LM5165-Q1 is in active mode when VEN is above the precision enable threshold and the internal bias rail is
above its UV threshold. In COT active mode, the LM5165-Q1 is in one of three modes depending on the load
current:
1. CCM with fixed switching frequency when load current is above half of the peak-to-peak inductor current
ripple;
2. Pulse skipping and diode emulation mode (DEM) when the load current is less than half of the peak-to-peak
inductor current ripple in CCM operation. Refer to the COT Mode Light-Load Operation section for more
detail;
3. Frequency foldback mode to maintain output regulation at low dropout and for improved load-on transient
response. Refer to the Low Dropout Operation and 100% Duty Cycle Mode section for more detail.
7.4.4 Active Mode in PFM
Similarly, the LM5165-Q1 is in PFM active mode when VEN and the internal bias rail are above the relevant
thresholds, FB has fallen below the lower hysteresis level (VREF1), and boundary conduction mode is recharging
the output capacitor to the upper hysteresis level (VREF2). There is a 4-µs wake-up delay from sleep to active
states.
7.4.5 Sleep Mode in PFM
The LM5165-Q1 is in PFM sleep mode when VEN and the internal bias rail are above the relevant threshold
levels, VFB has exceeded the upper hysteresis level (VREF2), and the output capacitor is sourcing the load
current. In PFM sleep mode, the LM5165-Q1 operates with very low quiescent current.
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM5165-Q1 only requires a few external components to convert from a wide range of supply voltages to a
fixed output voltage. To expedite and streamline the process of designing of a LM5165-Q1-based converter, a
comprehensive LM5165-Q1 quick-start design tool is available for download to assist the designer with
component selection for a given application. WEBENCH® online software is also available to generate complete
designs, leveraging iterative design procedures and access to comprehensive component databases. The
following sections discuss the design procedure for both COT and PFM modes using specific circuit design
examples.
As mentioned previously, the LM5165-Q1 also integrates several optional features to meet system design
requirements, including precision enable, UVLO, programmable soft start, programmable switching frequency in
COT mode, adjustable current limit, and PGOOD indicator. Each application incorporates these features as
needed for a more comprehensive design. The application circuits detailed below show LM5165-Q1 configuration
options suitable for several application use cases. Please see the LM5165EVM-HD-C50X and LM5165EVM-HDP50A EVM user's guides for more detail.
8.2 Typical Applications
8.2.1 Design 1: Wide VIN, Low IQ COT Converter Rated at 5 V, 150 mA
The schematic diagram of a 5-V, 150-mA COT converter is given in Figure 37.
LF
220 H
U1
VIN = 5 V...65 V
VIN
CIN
1 F
LM5165X
EN
HYS
RRT
133 k:
VOUT = 5 V
IOUT = 150 mA
SW
RESR
1.5 :
VOUT
SS
RT
ILIM
PGOOD
GND
CSS
47 nF
COUT
22 F
Figure 37. Schematic for Design 1 with VIN(nom) = 12 V, VOUT = 5 V, IOUT(max) = 150 mA, FSW(nom) = 230 kHz
8.2.1.1 Design Requirements
The target full-load efficiency is 91% based on a nominal input voltage of 12 V and an output voltage of 5 V. The
required input voltage range is 5 V to 65 V. The LM5165X-Q1 is chosen to deliver a fixed 5-V output voltage. The
switching frequency is set by resistor RRT at 230 kHz. The output voltage soft-start time is 6 ms. The required
components are listed in Table 2.
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Typical Applications (continued)
Table 2. List of Components for Design 1 (1)
REF DES
QTY
SPECIFICATION
VENDOR
PART NUMBER
CIN
1
1 µF, 100 V, X7R, 1206 ceramic
TDK
C3216X7R2A105K160AA
COUT
1
22 µF, 10 V, X7R, 1206 ceramic
Murata
GRM31CR71A226KE15L
LF
1
220 µH ±20%, 0.29 A, 0.92 Ω typ DCR, 5.8 x 5.8 x 2.8 mm
Würth Electronik
WE-TPC 5828 744053221
220 µH ±30%, 0.3 A, 1.25 Ω max DCR, 5.8 x 5.8 x 3.0 mm
Bourns
SRR5028-221Y
RESR
1
1.5 Ω, 5%, 0402
Std
Std
RRT
1
133 kΩ, 1%, 0402
Std
Std
CSS
1
47 nF, 10 V, X7R, 0402 ceramic
Std
Std
U1
1
LM5165X-Q1 Synchronous Buck Converter, VSON-10, 5V Fixed
TI
LM5165XQDRCRQ1
(1)
See Third-Party Products Disclaimer.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Switching Frequency – RT
As mentioned, the switching frequency of a COT-configured LM5165-Q1 is set by the on-time programming
resistor at the RT pin. As shown by Equation 2, a standard 1% resistor of 133 kΩ gives a switching frequency of
230 kHz.
Note that at very low duty cycles, the minimum controllable on-time of the high-side MOSFET, TON(min), of 180 ns
may affect choice of switching frequency. In CCM, TON(min) limits the voltage conversion step-down ratio for a
given switching frequency. The minimum controllable duty cycle is given by
DMIN
TON(min) ˜ FSW
(9)
Given a fixed TON(min), it follows that higher switching frequency implies a larger minimum controllable duty cycle.
Ultimately, the choice of switching frequency for a given output voltage affects the available input voltage range,
solution size and efficiency. The maximum supply voltage for a given TON(min) before switching frequency
reduction occurs is given by Equation 10.
VOUT
VIN(max)
TON(min) ˜ FSW
(10)
8.2.1.2.2 Filter Inductor – LF
The inductor ripple current (assuming CCM operation) and peak inductor current are given respectively by
Equation 11 and Equation 12.
'IL
§
VOUT ·
˜ ¨1
¸
VIN ¹
©
'IL
IOUT(max)
2
VOUT
FSW ˜ LF
IL(peak)
(11)
(12)
For most applications, choose an inductance such that the inductor ripple current, ΔIL, is between 30% and 50%
of the rated load current at nominal input voltage. Calculate the inductance using Equation 13.
§
VOUT
VOUT ·
˜ ¨1
LF
¸
FSW ˜ 'IL(nom) ¨©
VIN(nom) ¸¹
(13)
Choosing a 220-µH inductor in this design results in 55 mA peak-to-peak ripple current at nominal input voltage
of 12 V, equivalent to 37% of the 150-mA rated load current. The peak inductor current at maximum input voltage
of 65 V is 195 mA, sufficiently below the LM5165-Q1 peak current limit of 240 mA.
22
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Check the inductor datasheet to ensure that the inductor's saturation current is well above the current limit setting
of a particular design. Ferrite designs have low core loss and are preferred at high switching frequencies, so
design goals can then concentrate on copper loss and preventing saturation. However, ferrite core materials
exhibit a hard saturation characteristic – the inductance collapses abruptly when the saturation current is
exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, not to
mention reduced efficiency and compromised reliability. Note that inductor saturation current generally deceases
as the core temperature increases.
8.2.1.2.3 Output Capacitors – COUT
Select the output capacitor to limit the capacitive voltage ripple at the converter output. This is the sinusoidal
ripple voltage that arises from the triangular ripple current flowing in the capacitor. Select an output capacitance
using Equation 14 to limit the voltage ripple component to 0.5% of the output voltage.
'IL(nom) ˜ 100
COUT t
FSW ˜ VOUT
(14)
Substituting ΔIL(nom) of 55 mA gives COUT greater than 5 μF. Mindful of the voltage coefficient of ceramic
capacitors, select a 22-µF, 10-V capacitor with X7R dielectric in 1206 footprint.
8.2.1.2.4 Series Ripple Resistor – RESR
Select a series resistor such that sufficient ripple in phase with the SW node voltage appears at the feedback
node, FB. Use Equation 15 to calculate the required ripple resistance, designated RESR.
20mV ˜ VOUT
RESR t
VREF ˜ 'IL(nom)
(15)
With VOUT of 5 V, VREF of 1.223 V, and ΔIL(nom) of 55 mA at the nominal input voltage of 12 V, the required RESR
is 1.5 Ω. Calculate the total output voltage ripple in CCM using Equation 16.
'VOUT
'IL ˜ RESR
2
§
·
1
¨
¸
© 8 ˜ FSW ˜ COUT ¹
2
(16)
8.2.1.2.5 Input Capacitor – CIN
An input capacitor is necessary to limit the input ripple voltage while providing switching-frequency AC current to
the buck power stage. To minimize the parasitic inductance in the switching loop, position the input capacitors as
close as possible to the VIN and GND pins of the LM5165-Q1. The input capacitors conduct a square-wave
current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component
of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak
ripple voltage amplitude is given by Equation 17.
IOUT ˜ D ˜ 1 D
'VIN
D ˜ IOUT ˜ RESR
FSW ˜ CIN
(17)
The input capacitance required for a particular load current, based on an input voltage ripple specification of
ΔVIN, is given by Equation 18.
CIN t
IOUT ˜ D ˜ 1 D
FSW ˜ 'VIN
D ˜ IOUT ˜ RESR
(18)
The recommended high-frequency capacitance is 1 µF or higher and should be a high-quality ceramic type X5R
or X7R with sufficient voltage rating. Based on the voltage coefficient of ceramic capacitors, choose a voltage
rating of twice the maximum input voltage. Additionally, some bulk capacitance is required if the LM5165-Q1
circuit is not located within approximately 5 cm from the input voltage source. This capacitor provides damping to
the resonance associated with parasitic inductance of the supply lines and high-Q ceramics.
8.2.1.2.6 Soft-Start Capacitor – CSS
Connect an external soft-start capacitor for a specific soft-start time. In this example, select a soft-start
capacitance of 47 nF based on Equation 8 to achieve a soft-start time of 6 ms.
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8.2.1.3 Application Performance Curves
Unless otherwise stated, application performance curves were taken at TA = 25 °C.
100
5.1
90
Efficiency (%)
70
60
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
50
40
30
0.1
1
10
100 150
D102
Output Current (mA)
Output Voltage (V)
5.05
80
5
4.95
VIN = 12V
VIN = 24V
4.9
0
25
50
75
100
Output Current (mA)
VOUT = 5 V
Figure 38. Efficiency
125
150
Figure 39. Load Regulation
70
1 MHz
10 MHz
VOUT 100 mV/DIV
60
CISPR22
50
40
30
Peak detector
20
VSW 5 V/DIV
10
0
Average detector
-10
Start 150 kHz
VIN = 13.5 V
IOUT = 100 mA
20 ms/DIV
Stop 30 MHz
LIN = 22 µH
CIN(EXT) = 10 µF
Figure 40. EMI Plot – CISPR 22 Filtered Emissions
VIN = 12 V
IOUT = 0 mA
Figure 41. SW Node and Output Ripple Voltage, No Load
VOUT 100 mV/DIV
VOUT 100 mV/DIV
VSW 2 V/DIV
VSW 5 V/DIV
VIN = 12 V
IOUT = 150 mA
Figure 42. SW Node and Output Ripple Voltage, Full Load
24
4 Ps/DIV
4 Ps/DIV
VIN = 5.7 V
IOUT = 150 mA
Figure 43. SW Node and Output Ripple Voltage Showing
Frequency Foldback Near Dropout
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VIN 5 V/DIV
VOUT 1 V/DIV
VOUT 1 V/DIV
VEN 1 V/DIV
IOUT 50 mA/DIV
IOUT 50 mA/DIV
2 ms/DIV
VIN stepped to 24 V
30-Ω Load
2 ms/DIV
VIN = 24 V
30-Ω Load
Figure 44. Startup, Full Load
Figure 45. Enable ON and OFF
VIN 1 V/DIV
VIN 1 V/DIV
VOUT 1 V/DIV
VOUT 1 V/DIV
IOUT 50 mA/DIV
IOUT 50 mA/DIV
4 ms/DIV
VIN brownout to 3.2 V
4 ms/DIV
VIN brownout to 3.2 V
Figure 46. Dropout Performance, 75-mA Resistive Load
Figure 47. Dropout Performance, 150-mA Resistive Load
VOUT 100 mV/DIV
VIN 2 V/DIV
IOUT 50 mA/DIV
IL 50 mA/DIV
VOUT 2 V/DIV
200 ms/DIV
10 Ps/DIV
VIN = 24 V
IOUT = 150 mA
Figure 48. Load Transient, 50 mA to 150 mA, 1 A/µs
Figure 49. Input Transient (Automotive Cold Crank Profile)
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8.2.2 Design 2: Small Solution Size PFM Converter Rated at 3.3 V, 50 mA
The schematic diagram of a 3.3-V, 50-mA PFM converter with minimum component count is given in Figure 50.
LF
47 H
U1
VIN = 3.5 V...65 V
VIN
VOUT = 3.3 V
IOUT = 50 mA
SW
LM5165Y
CIN
1 F
EN
HYS
COUT
10 F
VOUT
SS
PGOOD
ILIM
RT
GND
RILIM
56.2 k:
Figure 50. Schematic for Design 2 with VIN(nom) = 12 V, VOUT = 3.3 V, IOUT(max) = 50 mA, FSW(nom) = 350 kHz
8.2.2.1 Design Requirements
The target full-load efficiency of this design is 88% based on a nominal input voltage of 12 V and an output
voltage of 3.3 V. The required total input voltage range is 3.5 V to 65 V. The LM5165-Q1 has an internally-set
soft-start time of 900 µs and an adjustable peak current limit threshold. The BOM is listed in Table 3.
Table 3. List of Components for Design 2 (1)
REF DES
QTY
SPECIFICATION
VENDOR
PART NUMBER
CIN
1
1 µF, 100 V, X7S, 0805 ceramic
TDK
C2012X7S2A474M125AE
COUT
1
10 µF, 6.3 V, X7R, 0805 ceramic
Taiyo Yuden
JMK212AB7106KG-T
Murata
GRM21BR70J106KE76K
47 µH ±20%, 0.56 A, 650 mΩ max DCR, 3.9 x 3.9 x 1.7 mm
Coilcraft
LPS4018-473MRC
47 µH ±20%, 0.7 A, 620 mΩ typ DCR, 4.0 x 4.0 x 1.8 mm
Würth
74404042470
47 µH ±20%, 0.57 A, 650 mΩ typ DCR, 4.0 x 4.0 x 1.8 mm
Taiyo Yuden
NR4018T470M
LF
1
RILIM
1
56.2 kΩ, 1%, 0402
Std
Std
U1
1
LM5165Y-Q1 Synchronous Buck Converter, VSON-10, 3.3 V Fixed
TI
LM5165YQDRCRQ1
(1)
See Third-Party Products Disclaimer.
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Peak Current Limit Setting – RILIM
Install a 56.2 kΩ resistor from ILIM to GND to select a 120-mA peak current limit threshold setting to meet the
rated output current of 50 mA.
8.2.2.2.2 Switching Frequency – LF
Tie RT to GND to select PFM mode of operation. The inductor, input voltage, output voltage and peak current
determine the pulse switching frequency of a PFM-configured LM5165-Q1. For a given input voltage, output
voltage and peak current, the inductance of LF sets the switching frequency when the output is in regulation. Use
Equation 19 to select an inductance of 47 µH based on the target PFM converter switching frequency of 350 kHz
at 12-V input.
LF
26
§
VOUT
VOUT ·
˜ ¨1
¸
FSW(PFM) ˜ IPK(PFM) ©
VIN ¹
(19)
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IPK(PFM) in this example is the peak current limit setting of 120 mA plus an additional 10% margin added to
include the effect of the 100-ns peak current comparator delay. An additional constraint on the inductance is the
180-ns minimum on-time of the high-side MOSFET. Therefore, in order to keep the inductor current well
controlled, choose an inductance that is larger than LF(min) using Equation 20 where VIN(max) is the maximum input
supply voltage for the application, tON(min) is 180 ns, and IL(max) is the maximum allowed peak inductor current.
VIN(max) ˜ t ON(min)
LF(min)
IL(max)
(20)
Choose an inductor with saturation current rating above the peak current limit setting, and allow for derating of
the saturation current at the highest expected operating temperature.
8.2.2.2.3 Output Capacitor – COUT
The output capacitor, COUT, filters the inductor’s ripple current and stores energy to meet the load current
requirement when the LM5165-Q1 is in sleep mode. The output ripple has a base component of amplitude
VOUT/123 related to the 10-mV typical feedback comparator hysteresis in PFM. The wakeup time from sleep to
active mode adds a ripple voltage component that is a function of the output current. Approximate the total output
ripple by Equation 21.
IOUT ˜ 4 V 9OUT
'VOUT
COUT
123
(21)
Also, the output capacitance must be large enough to accept the energy stored in the inductor without a large
deviation in output voltage. Setting this voltage change equal to 0.5% of the output voltage results in
§ IPK(PFM)
COUT t 100 ˜ LF ˜ ¨¨
© VOUT
·
¸¸
¹
2
(22)
In general, select the capacitance of COUT to limit the output voltage ripple at full load current, ensuring that it is
rated for worst-case RMS ripple current given by IRMS = IPK(PFM)/2. In this design example, choose a 10-µF, 6.3-V
ceramic output capacitor with X7R dielectric and 0805 footprint.
8.2.2.2.4 Input Capacitor – CIN
The input capacitor, CIN, filters the high-side MOSFET's triangular current waveform, see Figure 72. To prevent
large ripple voltage, use a low ESR ceramic input capacitor sized for the worst-case RMS ripple current given by
IRMS = IOUT/2. In this design example, choose a 1-µF, 100-V ceramic input capacitor with X7S dielectric and 0805
footprint.
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8.2.2.3 Application Performance Curves
100
90
VOUT 100 mV/DIV
Efficiency (%)
80
70
VSW 5 V/DIV
60
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
50
40
30
0.1
1
10
50
D103
Output Current (mA)
VOUT = 3.3 V
10 Ps/DIV
VIN = 12 V
Figure 51. Efficiency
IOUT = 50 mA
Figure 52. SW Node and Output Ripple Voltage, Full Load
VEN 1 V/DIV
VIN 2 V/DIV
VOUT 1 V/DIV
VOUT 1 V/DIV
IOUT 20 mA/DIV
IOUT 20 mA/DIV
1 ms/DIV
VIN stepped to 12 V
66-Ω Load
1 ms/DIV
VIN = 12 V
66-Ω Load
Figure 53. Startup, Full Load
Figure 54. Enable ON and OFF
VIN 2 V/DIV
VOUT 100 mV/DIV
VOUT 1 V/DIV
IOUT 20 mA/DIV
200 ms/DIV
10 Ps/DIV
IOUT = 50 mA
VIN = 12 V
Figure 55. Load Transient, 0 mA to 50 mA, 1 A/µs
28
Figure 56. Input Voltage Transient (Automotive Cold Crank
Profile)
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8.2.3 Design 3: High Density 12-V, 75-mA PFM Converter
The schematic diagram of 12-V, 75-mA PFM converter is given in Figure 57.
LF
47 H
U1
VIN = 18 V...65 V
VIN
RUV1
RFB1
LM5165
10 M:
CIN
1 F
VOUT = 12 V
IOUT = 75 mA
SW
RUV2
825 k:
1 M:
EN
FB
PGOOD
SS
HYS
ILIM
RHYS
COUT
10 F
CSS
RFB2
22 nF
113 k:
RILIM
37.4 k:
RT
GND
24.9 k:
Figure 57. Schematic for Design 3 with VIN(nom) = 24 V, VOUT = 12 V, IOUT(max) = 75 mA, FSW(nom) = 500 kHz
8.2.3.1 Design Requirements
The full-load efficiency specification is 92% based on a nominal input voltage of 24 V and an output voltage of 12
V. The total input voltage range is 18 V to 65 V, with UVLO turn on and turn off at 16 V and 14.5 V, respectively.
The output voltage setpoint is established by feedback resistors, RFB1 and RFB2. The switching frequency is set
by inductor LF at 500 kHz at nominal input voltage. The required components are listed in Table 4.
Table 4. List of Components for Design 3 (1)
REF DES
QTY
CIN
1
COUT
1
SPECIFICATION
VENDOR
PART NUMBER
1 µF, 100 V, X7S, 0805 ceramic
Murata
GRJ21BC72A105KE11L
1 µF, 100 V, X7S, 0805 ceramic, AEC-Q200
TDK
CGA4J3X7S2A105K125AE
10 µF, 16 V, X7R, 0805 ceramic
Taiyo Yuden
EMK212BB7106MG-T
10 µF, 16 V, X7R, 0805 ceramic, AEC-Q200
TDK
CGA4J1X7S1C106K125AC
Coilcraft
LPS4018-473MRC
LF
1
47 µH ±20%, 0.56 A, 650 mΩ max DCR, 3.9 x 3.9 x 1.7 mm
AEC-Q200
RILIM
1
24.9 kΩ, 1%, 0402
Std
Std
RFB1
1
1 MΩ, 1%, 0402
Std
Std
RFB2
1
113 kΩ, 1%, 0402
Std
Std
RUV1
1
10 MΩ, 1%, 0603
Std
Std
RUV2
1
825 kΩ, 1%, 0402
Std
Std
RHYS
1
37.4 kΩ, 1%, 0402
Std
Std
CSS
1
22 nF, 10 V, X7R, 0402
Std
Std
U1
1
LM5165-Q1 Synchronous Buck Converter, VSON-10, 3mm x 3 mm TI
(1)
LM5165QDRCRQ1
See Third-Party Products Disclaimer.
8.2.3.2 Detailed Design Procedure
The component selection procedure for this PFM design is quite similar to that of Design 2, see Figure 50.
8.2.3.2.1 Peak Current Limit Setting – RILIM
Install a 24.9 kΩ resistor from ILIM to GND to select the 180-mA peak current limit setting for a rated output
current of 75 mA.
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8.2.3.2.2 Switching Frequency – LF
Tie RT to GND to select PFM mode of operation. Set the switching frequency by the filter inductance, LF.
Calculate an inductance of 47 µH based on the target PFM converter switching frequency of 500 kHz at 24-V
input using Equation 19. Use a peak current limit setting, IPK(PFM), of 180 mA plus an additional 50% margin in
this high-frequency design to include the effect of the 100-ns current limit comparator delay. Choose an inductor
with saturation current rating well above the peak current limit setting, and allow for derating of the saturation
current at the highest expected operating temperature.
8.2.3.2.3 Input and Output Capacitors – CIN, COUT
Choose a 1-µF, 100-V ceramic input capacitor with 0805 footprint. Such a capacitor is typically available in X5R
or X7S dielectric. Based on Equation 22, select a 10-µF, 16-V ceramic output capacitor with X7R dielectric and
0805 footprint.
8.2.3.2.4 Feedback Resistors – RFB1, RFB2
The output voltage of the LM5165-Q1 is externally adjustable using a resistor divider network. The divider
network comprises the upper feedback resistor RFB1 and lower feedback resistor RFB2. Select RFB1 of 1 MΩ to
minimize quiescent current and improve light-load efficiency in this application. With the desired output voltage
setpoint of 12 V and VFB = 1.223 V, calculate the resistance of RFB2 using Equation 5 as 113.5 kΩ. Choose the
closest available standard value of 113 kΩ for RFB2. Please refer to the Adjustable Output Voltage (FB) section
for more detail.
8.2.3.2.5 Undervoltage Lockout Setpoint – RUV1, RUV2, RHYS
Adjust the undervoltage lockout (UVLO) using an externally-connected resistor divider network of RUV1, RUV2 and
RHYS. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down
or brownouts when the input voltage is falling. The EN rising threshold for the LM5165-Q1 is 1.212 V.
Rearranging Equation 6 and Equation 7, the expressions to calculate RUV2 and RHYS are as follows.
VEN(on)
RUV2
˜ RUV1
VIN(on) VEN(on)
RHYS
VEN(off)
VIN(off)
VEN(off)
(23)
˜ RUV1 RUV2
(24)
Choose RUV1 as 10 MΩ to minimize input quiescent current. Given the desired input voltage UVLO thresholds of
16 V and 14.5V, calculate the resistance of RUV2 and RHYS as 825 kΩ and 37.4 kΩ, respectively. Please refer to
the Precision Enable (EN) and Hysteresis (HYS) section for more detail.
8.2.3.2.6 Soft Start – CSS
Install a 22-nF capacitor from SS to GND for a soft-start time of 3 ms.
30
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8.2.3.3 Application Performance Curves
100
VOUT 2 V/DIV
90
VIN 5 V/DIV
Efficiency (%)
80
IOUT 20 mA/DIV
70
60
VIN = 18V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 65V
50
40
30
0.1
1
10
1 ms/DIV
75
D105
Output Current (mA)
VIN stepped to 24 V
VOUT = 12 V
160-Ω Load
Figure 59. Startup, Full Load
Figure 58. Efficiency
VOUT 500 mV/DIV
VOUT 500 mV/DIV
VSW 10 V/DIV
VSW 10 V/DIV
VIN = 24 V
10 ms/DIV
10 Ps/DIV
IOUT = 75 mA
Figure 60. SW Node and Output Ripple Voltage, Full Load
VIN = 24 V
IOUT = 0 mA
Figure 61. SW Node and Output Ripple Voltage, No Load
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8.2.4 Design 4: 3.3-V, 150-mA COT Converter with High Efficiency
The schematic diagram of a 3.3-V, 150-mA COT converter is given in Figure 62.
LF
150 H
U1
VIN = 3 V...65 V
VIN
VOUT = 3.3 V *
IOUT = 150 mA
SW
LM5165Y
CIN
1 F
EN
HYS
RRT
121 k:
RESR
0.5 :
VOUT
COUT
22 F
SS
RT
ILIM
PGOOD
GND
CSS
33 nF
* VOUT tracks VIN if VIN d 3.3V
Figure 62. Schematic for Design 4 with VIN(nom) = 24 V, VOUT = 3.3 V, IOUT(max) = 150 mA, FSW(nom) = 160 kHz
8.2.4.1 Design Requirements
The target full-load efficiency is 91% based on a nominal input voltage of 24 V and an output voltage of 3.3 V.
The required input voltage range is 3 V to 65 V. The LM5165Y-Q1 is chosen to deliver a fixed 3.3-V output
voltage. The switching frequency is set by resistor RRT at approximately 160 kHz. The output voltage soft-start
time is 4 ms. The required components are listed in Table 5. The component selection procedure for this COT
design is quite similar to that of Design 1, see Figure 37.
Table 5. List of Components for Design 4 (1)
REF DES
QTY
SPECIFICATION
VENDOR
PART NUMBER
CIN
1
1 µF, 100 V, X7R, 1206 ceramic
Murata
GRM31CR72A105KA01L
COUT
1
22 µF, 6.3 V, X7S, 0805 ceramic
Murata
GRM21BR660J226ME39K
LF
1
150 µH ±20%, 0.29 A, 0.86 Ω typ DCR, 4.8 x 4.8 x 2.9 mm
Coilcraft
LPS5030-154MLC
RESR
1
0.5 Ω, 5%, 0402
Std
Std
RRT
1
121 kΩ, 1%, 0402
Std
Std
CSS
1
33 nF, 10 V, X7R, 0402 ceramic
Std
Std
U1
1
LM5165Y-Q1 Synchronous Buck Converter, VSON-10, 3.3V Fixed
TI
LM5165YQDRCRQ1
(1)
See Third-Party Products Disclaimer.
8.2.4.2 Application Performance Curves
100
VOUT 0.5 V/DIV
90
Efficiency (%)
80
70
60
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
50
40
30
0.1
1
10
Output Current (mA)
Figure 63. Efficiency
32
100 150
D104
VSW 5 V/DIV
VIN = 24 V
4 Ps/DIV
IOUT = 150 mA
Figure 64. SW Node and Output Ripple Voltages, Full Load
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8.2.5 Design 5: 15-V, 150-mA, 600-kHz COT Converter
The schematic diagram of a 15-V, 150-mA COT converter is given in Figure 65.
LF
150 H
U1
VIN = 24 V...48 V
VIN
RUV1
LM5165
10 M:
CIN
1 F
VOUT = 15 V
IOUT = 150 mA
SW
EN
RUV2
PGOOD
681 k:
HYS
RHYS
RFB1
499 k:
RESR
0.5 :
FB
SS
ILIM
COUT
10 F
RFB2
44.2 k:
CSS
47 nF
RT
40.2 k:
CFF
10 pF
GND
RRT
143 k:
Figure 65. Schematic for Design 5 with VIN(nom) = 36 V, VOUT = 15 V, IOUT(max) = 150 mA, FSW(nom) = 600 kHz
8.2.5.1 Design Requirements
The target full-load efficiency is 92% based on a nominal input voltage of 36 V and an output voltage of 15 V.
The input voltage operating range is 24 V to 48 V, but transients as high as 65 V are possible in the application.
UVLO turn on and turn off are set at 19 V and 17 V, respectively. The LM5165-Q1 switching frequency is set at
approximately 600 kHz by resistor RRT of 143 kΩ. The output voltage soft-start time is 6 ms. The required
components are listed in Table 6. The component selection procedure for this COT design is quite similar to that
of Design 1, see Figure 37.
Table 6. List of Components for Design 5 (1)
REF DES
QTY
SPECIFICATION
VENDOR
PART NUMBER
CIN
1
1 µF, 100 V, X7R, 1206 ceramic
AVX
12061C105KAT2A
COUT
1
10 µF, 25 V, X7R, 1206 ceramic
Taiyo Yuden
TMK316B7106KL-TD
LF
1
150 µH ±20%, 0.29 A, 0.86 Ω typ DCR, 4.8 x 4.8 x 2.9 mm
Coilcraft
LPS5030-154MLC
RESR
1
2.2 Ω, 5%, 0402
Std
Std
RRT
1
143 kΩ, 1%, 0402
Std
Std
RFB1
1
499 kΩ, 1%, 0402
Std
Std
RFB2
1
44.2 kΩ, 1%, 0402
Std
Std
RUV1
1
10 MΩ, 1%, 0603
Std
Std
RUV2
1
681 kΩ, 1%, 0402
Std
Std
RHYS
1
40.2 kΩ, 1%, 0402
Std
Std
CFF
1
10 pF, 10 V, X7R, 0402 ceramic
Std
Std
CSS
1
47 nF, 10 V, X7R, 0402 ceramic
Std
Std
U1
1
LM5165-Q1 Synchronous Buck Converter, VSON-10, 3 mm x 3 mm TI
(1)
LM5165QDRCRQ1
See Third-Party Products Disclaimer.
8.2.5.2 Detailed Design Procedure
8.2.5.2.1 COT Output Ripple Voltage Reduction
Depending on the required ripple resistance when operating in COT mode, the resultant output voltage ripple
may be deemed too high for a given application. One option is to place a feed-forward capacitor CFF in parallel
with the upper feedback resistor RFB1. Capacitor CFF increases the high-frequency gain from VOUT to VFB close to
unity such that the output voltage ripple couples directly to the FB node.
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8.2.5.3 Application Performance Curves
100
90
Efficiency (%)
80
VIN 10 V/DIV
70
60
VOUT 5 V/DIV
50
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 65V
40
30
0.1
1
10
IOUT 100 mA/DIV
2 ms/DIV
100 150
D106
Output Current (mA)
VIN stepped to 36 V
VOUT = 15 V
IOUT = 150 mA
Figure 67. Startup, Full Load
Figure 66. Efficiency
VOUT 100 m/DIV
VOUT 100 mV/DIV
VSW 10 V/DIV
VIN = 36 V
VSW 10 V/DIV
1 Ps/DIV
IOUT = 150 mA
Figure 68. SW Node and Output Ripple Voltage, Full Load
VEN 1 V/DIV
10 ms/DIV
VIN = 36 V
IOUT = 0 mA
Figure 69. SW Node and Output Ripple Voltage, No Load
VIN 10 V/DIV
VOUT 5 V/DIV
VOUT 1 V/DIV
IOUT 100 mA/DIV
IOUT 100 mA/DIV
400 Ps/DIV
2 ms/DIV
VIN = 36 V
VIN = 36 V
Figure 70. Enable ON and OFF
34
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Figure 71. Short Circuit Recovery
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9 Power Supply Recommendations
The LM5165-Q1 is designed to operate from an input voltage supply range between 3 V and 65 V. This input
supply should be able to provide the maximum input current and maintain a voltage above 3 V. Ensure that the
resistance of the input supply rail is low enough that an input current transient does not cause a high enough
drop at the LM5165-Q1 supply rail to cause a false UVLO fault triggering and system reset. If the input supply is
located more than a few inches from the LM5165-Q1 converter, additional bulk capacitance may be required in
addition to the ceramic input capacitance. A 4.7-μF electrolytic capacitor is a typical choice for this function,
whereby the capacitor ESR provides a level of damping against input filter resonances. A typical ESR of 0.5 Ω
provides enough damping for most input circuit configurations.
10 PCB Layout
The performance of any switching converter depends as much upon PCB layout as it does the component
selection. The following guidelines are provided to assist with designing a PCB with the best power conversion
performance, thermal performance, and minimized generation of unwanted EMI.
10.1 Layout Guidelines
PCB layout is a critical for good power supply design. There are several paths that conduct high slew-rate
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or
degrade the power supply's performance.
1. Bypass the VIN pin to GND with a low ESR ceramic capacitor of X5R or X7R dielectric. Place CIN as close
as possible to the LM5165-Q1 VIN and GND pins. Ground return paths for both the input and output
capacitors should consist of localized top-side planes that connect to the GND pin and exposed PAD.
2. Minimize the loop area formed by the input capacitor connections and the VIN and GND pins.
3. Locate the power inductor close to the SW pin. Minimize the area of the SW trace/plane to prevent excessive
capacitive coupling.
4. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.
5. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.
6. Have a single-point ground connection to the plane. Route the ground connections for the feedback, softstart, and enable components to the ground plane. This prevents any switched or load currents from flowing
in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic
output voltage ripple behavior.
7. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
8. Minimize trace length to the FB pin. Locate both feedback resistors close to the FB pin. Place CFF (if used)
directly in parallel with RFB1. Route the VOUT sense path away from noisy nodes and preferably on a layer at
the other side of a shielding layer.
9. Locate the components at RT and SS as close as possible to the device. Route with minimal trace lengths.
10. Provide adequate heat-sinking for the LM5165-Q1 to keep the junction temperature below 150°C. For
operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of
heat-sinking vias to connect the exposed PAD to the PCB ground plane. If the PCB has multiple copper
layers, connect these thermal vias to inner-layer ground planes.
10.1.1 Compact PCB Layout for EMI Reduction
Radiated EMI generated by high di/dt components relates to pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to
minimize radiated EMI is to identify the pulsing current path and minimize the area of that path.
The critical switching loop of the power stage in terms of EMI is denoted in Figure 72. The topological
architecture of a buck converter means that a particularly high di/dt current effective path exists in the loop
comprising the input capacitor and the LM5165-Q1's integrated MOSFETs, and it becomes mandatory to reduce
the parasitic inductance of this loop by minimizing the effective loop area.
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Layout Guidelines (continued)
VIN
VIN
2
CIN
LM5165
High-side
PMOS
gate driver
High
di/dt
loop
Q1
LF
1
Low-side
NMOS
gate driver
SW
VOUT
COUT
Q2
10
GND
GND
Figure 72. Synchronous Buck Converter with Power Stage Critical Switching Loop
The input capacitor provides the primary path for the high di/dt components of the high-side MOSFET's current.
Placing a ceramic capacitor as close as possible to the VIN and GND pins is the key to EMI reduction. Keep the
trace connecting SW to the inductor as short as possible and just wide enough to carry the load current without
excessive heating. Use short, thick traces or copper pours (shapes) for current conduction path to minimize
parasitic resistance. Place the output capacitor close to the VOUT side of the inductor, and connect the capacitor's
return terminal to the LM5165-Q1's GND pin and exposed PAD.
10.1.2 Feedback Resistor Layout
For the adjustable output voltage version of the LM5165-Q1, reduce noise sensitivity of the output voltage
feedback path by placing the resistor divider close to the FB pin, rather than close to the load. This reduces the
trace length of FB signal and noise coupling. The FB pin is the input to the feedback comparator and, as such, is
a high impedance node sensitive to noise. The output node is a low impedance node, so the trace from VOUT to
the resistor divider can be long if a short path is not available.
Route the voltage sense trace from the load to the feedback resistor divider away from the SW node path, the
inductor and VIN path to avoid contaminating the feedback signal with switch noise, while also minimizing the
trace length. This is most important when high feedback resistances, greater than 100 kΩ, are used to set the
output voltage. Also, route the voltage sense trace on a different layer from the inductor, SW node and VIN path,
such that there is a ground plane that separates the feedback trace from the inductor and SW node copper
polygon. This provides further shielding for the voltage feedback path from switching noise sources.
10.2 Layout Example
Figure 73 shows an example layout for the PCB top layer of a single-sided design. The bottom layer is
essentially a full ground plane except for short connecting traces for SW, EN and PGOOD.
36
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Layout Example (continued)
GND
connection
Short SW node
trace routed
underneath
RESR
LF
VIN
connection
COUT
CIN
Connect ceramic
input cap close to
VIN and GND
VOUT
connection
SW via
RFB2 RFB1 CFF RPG
RUV1
RILIM
RUV2
EN
connection
PGOOD
connection
CSS
RRT
Place SS cap
close to pin
RHYS
Thermal vias under
LM5165 PAD
Place FB resistors very
close to FB & GND pins
Figure 73. PCB Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
• LM5165-Q1 Quick-start Design Tool
• TIDesigns Reference Design Library
• WEBENCH® Designer
11.2 Documentation Support
11.2.1 Related Documentation
• LM5165-HD-P50A EVM User's Guide, SNVU474
• LM5165-HD-C50X EVM User's Guide, SNVU511
• AN-2162: Simple Success with Conducted EMI from DC-DC Converters, SNVA489
• Automotive Cranking Simulator User's Guide, SLVU984
• Using New Thermal Metrics Application Report, SBVA025
• Semiconductor and IC Package Thermal Metrics, SPRA953
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this datasheet, refer to the left-hand navigation.
38
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Feb-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM5165QDGSRQ1
PREVIEW
VSSOP
DGS
10
2500
TBD
Call TI
Call TI
-40 to 150
LM5165QDGSTQ1
PREVIEW
VSSOP
DGS
10
250
TBD
Call TI
Call TI
-40 to 150
LM5165QDRCRQ1
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
5165Q
LM5165QDRCTQ1
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
5165Q
LM5165XQDRCRQ1
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
5165XQ
LM5165XQDRCTQ1
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
5165XQ
LM5165YQDRCRQ1
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
5165YQ
LM5165YQDRCTQ1
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
5165YQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-Feb-2017
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM5165-Q1 :
• Catalog: LM5165
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LM5165QDRCRQ1
VSON
DRC
10
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
LM5165QDRCTQ1
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
LM5165XQDRCRQ1
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
LM5165XQDRCTQ1
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
LM5165YQDRCRQ1
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
LM5165YQDRCTQ1
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Sep-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5165QDRCRQ1
VSON
DRC
10
3000
367.0
367.0
35.0
LM5165QDRCTQ1
VSON
DRC
10
250
210.0
185.0
35.0
LM5165XQDRCRQ1
VSON
DRC
10
3000
367.0
367.0
35.0
LM5165XQDRCTQ1
VSON
DRC
10
250
210.0
185.0
35.0
LM5165YQDRCRQ1
VSON
DRC
10
3000
367.0
367.0
35.0
LM5165YQDRCTQ1
VSON
DRC
10
250
210.0
185.0
35.0
Pack Materials-Page 2
www.ti.com
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