MCP2050 LIN Transceiver with Voltage Regulator Features: • The MCP2050 is compliant with: - LIN Bus Specifications Version 1.3, 2.1 and with SAE J2602-2 • Support Baud Rates Up to 20 kBaud • 43V Load Dump Protected • Maximum Continuous Input Voltage of 30V • Wide LIN Compliant Supply Voltage, 6.0-18.0V • Extended Temperature Range: -40 to +125°C • Interface to PIC® EUSART and Standard USARTs • Wake-Up on LIN Bus Activity or Local Wake Input • LIN Bus Pin - Internal pull-up termination resistor and diode for slave node - Protected against VBAT shorts - Protected against loss of ground - High current drive • TXD and LIN Bus Dominant Time-Out Function • Two Low-Power Modes - Transmitter Off mode: 90 µA (typical) - Power Down mode: 4.5 µA (typical) • Output Indicating Internal Reset State (POR or Sleep Wake) • MCP2050 On-Chip Voltage Regulator - Output voltage of 5.0V or 3.3V with 70 mA capability and tolerances of ±3% over operating temperature range - Internal short-circuit current limit - Only external filter and load capacitors needed • Programmable Windowed Watchdog Timer (WWDT) - External resistor programmable from 7 ms to 140 ms - Disabled by connecting the WWDTSELECT pin to VREG or let the pin float • Ratiometric Output of VBAT Voltage Scaled to VREG • Automatic Thermal Shutdown • High Electromagnetic Immunity (EMI), Low Electromagnetic Emission (EME) • Robust ESD Performance: ±15 kV for LBUS and VBB pin (IEC61000-4-2) • Transient Protection for LBUS and VBB Pins in Automotive Environment (ISO7637) 2012-2014 Microchip Technology Inc. • Meets Stringent Automotive Design Requirements Including “OEM Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications”, Version 1.3, May 2012 • Multiple Package Options Including Small 5x5 QFN Description: The MCP2050 provides a bidirectional, half-duplex communication physical interface to meet the LIN bus specification Revision 2.1 and SAE J2602. The device incorporates a voltage regulator with 5V or 3.3V 70 mA regulated power supply output. The on-chip WWDT allows users to adjust the size of the reset window by using an external resistor. The ratiometric VBAT pin scales down VBAT to the range of VREG so it can be monitored by an A/D converter. The device has been designed to meet the stringent quiescent current requirements of the automotive industry and will survive +43V load dump transients, and double battery jumps. MCP2050 family members: - MCP2050-500, 14-pin, LIN driver with 5.0V regulator - MCP2050-330, 14-pin, LIN driver with 3.3V regulator - MCP2050-500, 20-pin QFN, LIN driver with 5.0V regulator - MCP2050-330, 20-pin QFN, LIN driver with 3.3V regulator DS20002299C-page 1 MCP2050 Package Types 5 16 RESET 17 1 2 3 4 VBAT RATIO EP 21 NC LBUS VSS 8 9 10 RXD CS/LWAKE VREG TXD 15 14 13 12 11 WWDTTRIG WWDTSELECT FAULT/TXE VBB NC NC NC 11 10 9 8 NC NC 4 5 6 7 WWDTRESET WWDTTRIG WWDTSELECT FAULT/TXE VBB LBUS VSS 20 14 13 12 6 7 TXD RESET NC 1 2 3 19 18 VBAT RATIO RXD CS/LWAKE VREG WWDTRESET NC MCP2050 5 x 5 QFN* MCP2050 PDIP, SOIC * Includes Exposed Thermal Pad (EP), see Table 1-2. Block Diagram 4.2V WWDTTRIG Programmable Windowed Watchdog WWDTselect Short-Circuit Protection VREG RESET Thermal Protection Voltage Regulator VREG Internal Circuits 4.2V VREG Wake-Up Logic and Power Control WWDTRESET VBB Ratiometric Reference Bus Wakeup RXD CS/LWAKE ~30 kΩ Slope Control LBUS TXD Bus Dominant Timer FAULT/TXE VSS VBB Thermal and Short-Circuit Protection DS20002299C-page 2 VREG VBATRATIO 300Ω 2012-2014 Microchip Technology Inc. MCP2050 1.0 FUNCTION DESCRIPTION The MCP2050 provides a physical interface between a microcontroller and a LIN half-duplex bus. It is intended for automotive and industrial applications with serial bus baud rates up to 20 kbaud. This device will translate the CMOS/TTL logic levels to LIN logic levels, and vice versa. The device offers optimum EMI and ESD performance; it can withstand high voltage on the LIN bus. The device supports two low-power modes to meet automotive industry power consumption requirements. The MCP2050 also provides a +5V or 3.3V 70 mA regulated power output. FIGURE 1-1: POR(2) VREG OFF RX OFF TX OFF 1.1 Modes of Operation The MCP2050 works in five modes: Power-On Reset mode, Power-Down mode, Ready mode, Operation mode, and Transmitter Off mode. For an overview of all operational modes, please refer to Table 1-1. For the operational mode transition, please refer to Figure 1-1. STATE DIAGRAM VBB > VON READY VREG ON RX ON TX OFF CS/LWAKE = 1& FAULT/TXE = 0 CS/LWAKE = 1 OR Voltage Rising Edge on LBUS CS/LWAKE = 1 & FAULT/TXE = 1 (3) & TXD = 1& VREG_OK = 1 (1) CS/LWAKE = 1& FAULT/TXE = 1 (3)& TXD = 1 TX OFF VREG ON RX ON TX OFF CS/LWAKE = 0 POWER-DOWN VREG OFF RX OFF TX OFF OPERATION VREG ON RX ON TX ON CS/LWAKE = 1& FAULT/TXE = 0 CS/LWAKE = 0 Note 1: VREG_OK: Regulator Output Voltage > 0.8VREG_NOM. 2: If the voltage on pin VBB falls below VOFF, the device will enter Power-On Reset mode from all other modes, which is not shown in the figure. 3: FAULT/TXE = 1 represents input and no fault conditions. FAULT/TXE = 0 represents input low or a fault condition. Refer to Table 1-3. 2012-2014 Microchip Technology Inc. DS20002299C-page 3 MCP2050 1.1.1 POWER-ON-RESET MODE Upon application of VBB, or whenever the voltage on VBB is below the threshold of regulator turn-off voltage VOFF (typically. 4.50V), the device enters Power-On Reset mode (POR). During this mode, the device maintains the digital section in a reset mode and waits until the voltage on pin VBB rises above the threshold of regulator turn-on voltage VON (typically 5.75V) to enter into Ready mode. In Power-On-Reset mode, the LIN physical layer and voltage regulator are disabled, and RESET output is forced to low. 1.1.2 READY MODE The device enters Ready mode from POR mode after the voltage on VBB rises above the threshold of regulator turn-on voltage VON or from Power-Down mode when a remote or local wake-up event happens. Upon entering Ready mode, the voltage regulator and receiver section of the transceiver are powered up. The transmitter remains in off state. The device is ready to receive data but not to transmit. In order to minimize the power consumption, the regulator operates in a reduced-power mode. It has a lower GBW product and thus is slower. However, the 70 mA drive capability is unchanged. The device stays in Ready mode until the output of the voltage regulator has stabilized and the CS/LWAKE pin is high (‘1’). 1.1.3 OPERATION MODE If VREG is OK (VREG > 0.8 VREG_NOM), CS/LWAKE pin, FAULT/TXE pin and TXD pin are high, the part enters the Operation mode from either Ready or Transmitter Off mode. In this mode, all internal modules are operational. The internal pull-up resistor between LBUS and VBB is connected only in this mode. The device goes into the Power-Down mode at the falling edge on CS/LWAKE; or to the Transmitter Off mode at the falling on FAULT/TXE while CS/LWAKE stays high. 1.1.4 TRANSMITTER OFF MODE In Transmitter Off mode, the receiver is enabled but the LBUS transmitter is off. It is a lower-power mode. In order to minimize the power consumption, the window watchdog timer is disabled and the regulator operates in a reduced-power mode. It has a lower GBW product and thus is slower. However, the 70 mA drive capability is unchanged. The transmitter may be re-enabled whenever the FAULT/TXE signal returns high, by removing the internal fault condition and the CPU returning the FAULT/TXE high. The transmitter will not be enabled even if the FAULT/TXE pin is brought high externally, when the internal fault is still present. However, externally forcing the FAULT/TXE high, while the internal fault is still present, should be avoided since this will induce high current and power dissipation in the FAULT/TXE pin. The transmitter is also turned off whenever the voltage regulator is unstable or recovering from a fault. This prevents unwanted disruption of the bus during times of uncertain operation. 1.1.5 POWER-DOWN MODE In Power-Down mode, the transceiver and the voltage regulator are both off. Only the Bus Wake-up section and the CS/LWAKE pin wake-up circuits are in operation. This is the lowest-power mode. If any bus activity (e.g. a BREAK character) occurs during Power-Down mode, the device will immediately enter Ready mode and enable the voltage regulator. Then, once the regulator output has stabilized (approximately 0.3 ms to 1.2 ms) it goes to Operation mode. Refer to Section 1.1.6 “Remote Wake-up” for more details. The part will also enter Ready mode from Power-Down mode, followed by Operation mode, if the CS/LWAKE pin becomes active high (‘1’). 1.1.6 REMOTE WAKE-UP The remote wake-up sub module observes the LBUS in order to detect bus activity. In Power-Down mode, normal LIN recessive/dominant threshold is disabled, and the LIN bus Wake-Up Voltage Threshold VWK(LBUS) is used to detect bus activities. Bus activity is detected when the voltage on the LBUS falls below the LIN bus Wake-Up Voltage Threshold VWK(LBUS) (approximately 3.4V) for at least tBDB (a typical duration of 80 µs) followed by a rising edge. Such a condition causes the device to leave Power-Down mode DS20002299C-page 4 2012-2014 Microchip Technology Inc. MCP2050 . TABLE 1-1: State OVERVIEW OF OPERATIONAL MODES Transmitter Receiver Internal Voltage Watch Dog Wake Module Regulator Timer Operation Comments PoR Off Off Off Off Off Proceed to Ready mode after VBB>VON. — Ready Off On Off On On If CS/LWAKE high, then proceed to Operation or Transmitter Off mode. Bus Off state Operation On On Off On On If CS/LWAKE low level, then proceed to Power-Down. If FAULT/TXE low level, then Transmitter-Off mode. Normal Operation mode Power-Down Off Off On Activity Detect Off Off On LIN bus rising edge or CS/LWAKE high level, proceed to READY mode. LowestPower mode Transmitter Off Off On Off On Off If CS/LWAKE low level, then proceed to Power down. If FAULT/TXE high, then Operation mode. Bus Off state, Lower-Power mode 1.2 1.2.1 Windowed Watchdog Reset The Watchdog Timer monitors for activity on the Windowed Watchdog Timer Trigger input pin WWDTTRIG. The WWDTTRIG pin is expected to be strobed within a given time frame. When this time frame has expired without an edge transition on the WWDTTRIG pin, the WWDTRESET pin is driven active (low) to reset the system. This feature is enabled by connecting a resistor between the WWDTSELECT pin and VSS. Monitoring is then done by requiring the host processor to force a falling edge transition on the WWDTTRIG pin within a predetermined time frame (TWD). WWDT DURING INITIAL POWER-UP The WWDTRESET is driven high after a power-on reset. The Watchdog Timer begins counting at this point, awaiting an edge on WWDTTRIG pin. Note that there is no window enabled, yet. If no falling edge is detected on the WWDTTRIG pin before the timer expires, the WWDTRESET is pulse low and the timer is restarted. When a trigger edge on the WWDTTRIG pin is seen, the window is enabled and the timer is reset. The start time of the trigger window is fixed at 50% of the total watchdog period, after the last trigger. The length of the window is determined by the value of the resistor on pin WWDTSELECT. The Watchdog Timer is disabled if WWDTSELECT is floating. FIGURE 1-2: WWDTRESET DURING INITIAL POWER-UP Internal reset WWDTRESET tPOWERUP tWDRST tPOWERUP tWDRST tPOWERUP Figure 1-2 shows the behavior of the WWDTRESET pin after a system reset with no trig at all. If no trig is given during the power-up window, WWDTRESET is reset low for the time tWDRST. Duration for tPOWERUP and tWDRST are: • tPOWERUP = 0.8 ms x (RWWDTSELECT+1) typical • tWDRST = 150 μs typical • RWWDTSELECT is in kΩ The power-up window length tPOWERUP duration is determined by the value of the resistor connected between pin WWDTSELECT and pin VSS, while the reset pulse duration is about 150 μs. Once a trig is asserted, the power-up sequence “stops” and the normal behavior begins. 2012-2014 Microchip Technology Inc. DS20002299C-page 5 MCP2050 1.2.2 WINDOWED WATCHDOG BEHAVIOR EQUATION 1-1: After windowed watchdog begins its normal behavior, three different cases can appear. tWLENGTH = (0.175 ms × RWWDTSELECT) + 1.2 typical • A pulse (falling edge) on the WWDTTRIG pin is detected within the trigger window; the watchdog timer will be reset, and a new watchdog period will begin; WWDTRESET pin remains high (Figure 1-3.) tWDRST = 150 μs typical RWWDTSELECT is in kΩ; its value ranges from 33 kΩ to 680 kΩ and window length ranges from 7 ms to 120 ms typical. • A pulse (falling edge) on the WWDTTRIG pin is detected before the trigger window (too early trigger); WWDTRESET is asserted (low) immediately after the falling edge is detected for approximately tWDRST; the counter is reset and the next watchdog period begins at the rising edge of the voltage on WWDTRESET pin (Figure 1-12). If the WWDTSELECT pin is floating, the watchdog is disabled and the WWDTRESET remains high. • No pulse on the WWDTTRIG pin is detected during the whole watchdog window (no trigger); WWDTRESET is asserted (low) for approximately tWDRST when the timer has expired; the counter is reset and the next watchdog period begins at the rising edge of the voltage on WWDTRESET pin (Figure 1-5). The trigger window is between 50% to 100% of the watchdog window length, tWLENGTH. The window length is determined by the external resistor between WWDTSELECT pin and VSS. FIGURE 1-3: CORRECT TRIGGER Window length Next period 50% TWD Too early Trigger window Earliest trigger point Lastest trigger point 1 WWDTTRIG 0 1 WWDTRESET New period begins Window length 50% Too early DS20002299C-page 6 Trigger window 2012-2014 Microchip Technology Inc. MCP2050 FIGURE 1-4: TOO EARLY TRIGGER Window length Next period 50% TWD Too early Trigger window Earliest trigger point Lastest trigger point 1 WWDTTRIG 0 1 tWDRST WWDTRESET 0 New period begins Window length 50% Too early FIGURE 1-5: Trigger window NO TRIGGER Window length Next period 50% TWD Too early Trigger window Earliest trigger point Lastest trigger point 1 No trigger, timer expired WWDTTRIG 1 WWDTRESE T tWDRST 0 Window length New period begins 50% Too early 2012-2014 Microchip Technology Inc. Trigger window DS20002299C-page 7 MCP2050 1.3 Pin Descriptions Please refer to Table 1-2 for the pinout overview. TABLE 1-2: PINOUT DESCRIPTIONS Devices PIN Name Function PIN Type 14-Pin PDIP, SOIC 5 x 5 QFN VBATRATIO 1 18 Analog Output RXD 2 1 Output CS/LWAKE 3 2 VREG 4 3 Output TXD 5 4 Input, HV-tolerant RESET 6 5 Output NC 7 6,9,10,11, 16,19,20 Not Connected Normal Operation VBATRATIO = VBAT/24 × VREG Receive Data Output TTL Input, HV-tolerant Chip Select and Local Wake-up Input Voltage Regulator Output Transmit Data Input Reset Output — VSS 8 8 Power Ground LBUS 9 7 I/O, HV LIN Bus VBB 10 12 Power Battery FAULT/TXE 11 13 I/O, HV-tolerant WWDTSELECT 12 14 Input A Resistor between this pin and Ground determines the Watchdog Window length WWDTTRIG 13 15 Input Windowed Watchdog Trigger Input WWDTRESET 14 17 Output, HV-tolerant Windowed Watchdog Reset Output EP — 21 1.3.1 Exposed Thermal Pad Exposed Thermal Pad can be left unconnected, (EP) or connected to the ground. VBATRATIO This is an analog output pin that reflects the voltage at the VBAT pin. It is scaled by VREG such that: VBATRATIO = VBAT/24 × VREG 0 <= VBATRATIO <= VREG The resistive divider and the output driver are switched off during Power-Down mode in order to reduce power consumption. 1.3.2 RXD Receive Data Output pin. The RXD pin is a standard CMOS output pin and it follows the state of the LBUS pin. 1.3.3 Fault Detect Output/Transmitter Enable Input CS/LWAKE Chip Select and Local Wake-Up Input pin (TTL level, high voltage tolerant). This pin controls the device state transition. Refer to Figure 1-1. An internal pull-down resistor will keep the CS/LWAKE pin low to ensure that no disruptive data will be present on the bus while the microcontroller is executing a Power-on Reset and I/O initialization sequence. When CS/LWAKE is ‘1’, a weak pull-down (~600 kΩ) is used to reduce current. When CS/LWAKE is ‘0’ a stronger pull-down (~300 kΩ) is used to maintain the logic level. This pin may also be used as a local wake-up input (see Figure 1-12). The microcontroller will set the I/O pin to control the CS/LWAKE. An external switch, or other source, can then wake-up both the transceiver and the microcontroller. Note: CS/LWAKE should NOT be tied directly to pin VREG as this could force the MCP2050 into Operation Mode before the microcontroller is initialized. If CS/LWAKE = 1, the device can work in Operation mode (FAULT/TXE = 1) or Transmitter Off mode (FAULT/TXE = 0). If CS/LWAKE = 0, the device can work in Power-Down mode or Ready mode. DS20002299C-page 8 2012-2014 Microchip Technology Inc. MCP2050 1.3.4 VREG Positive Supply Voltage Regulator Output pin. An onchip LDO gives +5.0 or +3.3V 70 mA regulated voltage on this pin. 1.3.5 TXD Transmit Data Input pin (TTL level, HV compliant, adaptive pull-up). The transmitter reads the data stream on TXD pin and sends it to LIN bus. The LBUS pin is low (dominant) when TXD is low, and high (recessive) when TXD is high. The Transmit Data Input pin has an internal adaptive pull-up to an internally-generated 4.2V (approximate). When TXD is ‘0’, a weak pull-up (~900 kΩ) is used to reduce current. When TXD is ‘1’ a stronger pull-up (~300 kΩ) is used to maintain the logic level. A series reverse-blocking diode allows applying TXD input voltages greater than the internally generated 4.2V and renders TXD pin HV compliant up to 30V (see the Block Diagram on page 2). 1.3.6 RESET Reset Output pin. This pin is open drain with ~90 kΩ pull-up to VREG. It indicates the internal voltage has reached a valid, stable level. As long as the internal voltage is valid (above 0.8VREG), this pin will remain high (‘1’); otherwise the RESET pin switches to low (‘0’). 1.3.7 VSS 1.3.10 FAULT/TXE Fault Detect Output/Transmitter Enable Input pin. The output section is HV tolerant open drain (up to 30V). The input section is identical with TXD section (TTL level, HV compliant, adaptive pull-up). The internal pullup resistor may be too weak for some applications. An external 10kΩ pull-up resistor is recommended to ensure a logic high level. Its state is defined as shown in Table 1-3. The device is placed in Transmitter Off mode whenever this pin is low (‘0’), either from an internal fault condition or by external drive. If CS/LWAKE is high (‘1’), the FAULT/TXE signals a mismatch between the TXD input and the LBUS level. This can be used to detect a bus contention. Since the bus exhibits a propagation delay, the sampling of the internal compare is debounced to eliminate false faults. After the device wakes up, the FAULT/TXE indicates what wakes the device if CS/LWAKE remains low (‘0’) (refer to Table 1-3). The FAULT/TXE pin sampled at a rate faster than every 10 µs. 1.3.11 WWDTSELECT This is an analog input pin that sets the open window time to accept a trigger reset. A resistor between this pin and VSS sets this time. The equation to determine the value of the resistor can be found in Section 1.2.2 “Windowed Watchdog Behavior”. Ground pin. 1.3.12 1.3.8 This is an input pin to reset the Windowed Watchdog Timer. A high-to-low transition during the open window time will reset the timer and prevent the WWDT from timing out. The pin has an internal adaptive pull-up to an internally-generated 4.2V (approximate.). LBUS LBUS is a bidirectional LIN bus Interface pin and is controlled by the signal TXD. It has an open collector output with a current limitation. To reduce electromagnetic emission, the slopes during signal changes are controlled, and the LBUS pin has corner-rounding control for both falling and rising edges. The internal LIN receiver observes the activities on LIN bus, and generates the output signal RXD that follows the state of the LBUS. A first degree 160 kHz, low-pass input filter optimizes electromagnetic immunity. 1.3.9 VBB Battery Positive Supply Voltage pin. An external diode is connected in series to prevent the device from being reversely powered (refer Figure 1-12). WWDTTRIG When WWDTTRIG is ‘0’, a weak pull-up (~800 kΩis connectedto reduce current. When WWDTTRIG is ‘1’, the pull-up is stronger to maintain the logic level. 1.3.13 WWDTRESET WWDTRESET is an open-drain output pin. This pin is asserted low when the internal Windowed Watchdog Timer has expired or an attempt was made to clear the timer before the window has opened. 1.3.14 EP It is recommended to connect this pad to VSS to enhance electromagnetic immunity and thermal resistance. 2012-2014 Microchip Technology Inc. DS20002299C-page 9 MCP2050 TABLE 1-3: FAULT/TXE TRUTH TABLE FAULT/TXE TXD In RXD Out LIN BUS I/O Thermal Override L H VBB OFF H L FAULT, TXD driven low, LBUS shorted to VBB (Note 1), or LBUS/TXD permanent dominant detected, and transmit time-out shutdown. H H VBB OFF H H OK External Input Definition Driven Output CS = 1 L L GND OFF H H OK H L GND OFF H H OK, data is being received from LBUS x x VBB ON H L FAULT, transceiver in thermal shutdown x x VBB x L x NO FAULT, the CPU is commanding the transceiver to turn off the transmitter driver CS = 0 after a wake-up x x x x x L Wake-up from LIN bus activity x x x x x H Wake-up from POR Legend: x = don’t care Note 1: The FAULT/TXE is valid after approximately 25 µs after TXD falling edge. This is to eliminate false fault reporting during bus propagation delays. FIGURE 1-6: VBATRATIO OUTPUT RANGE VBATRATIO .75VREG VREG/2 .25VREG 0 VBB 6V Note 1: DS20002299C-page 10 12V 18V 24V Linear range of VBATRATIO is between VBB = 6.0-18.0V. 2012-2014 Microchip Technology Inc. MCP2050 1.4 1.4.1 1.4.3 Fail-Safe Features GENERAL FAIL-SAFE FEATURES • An internal pull-down resistor on the CS/LWAKE pin disables the transmitter if the pin is floating. • An internal pull-up resistor on the TXD pin places TXD in high, thus the LBUS is recessive if the TXD pin is floating. • High-Impedance and low leakage current on LBUS during loss of power or ground. • The current limit on LBUS protects the transceiver from being damaged if the pin is shorted to VBB. 1.4.2 TXD/LBUS TIME-OUT TIMER LIN bus can be driven to a dominant level either from TXD pin or externally. An internal timer deactivates the LBUS transmitter if a dominant status (low) on LIN bus lasts longer than Bus Dominant Time-Out Time tTO(LIN) (approximately 20 ms); at the same time, RXD output is put in recessive (high), FAULT/TXE is also driven to low and the internal LIN pull-up resistor is disconnected. The timer is reset on any recessive LBUS status or POR mode. The recessive status on LBUS can be caused either by the bus being externally pulled up or by TXD pin being returned high. THERMAL PROTECTION The thermal protection circuit monitors the die temperature and is able to shut down the LIN transmitter and voltage regulator. There are three causes for a thermal overload. A thermal shut down can be triggered by any one, or a combination of, the following thermal overload conditions. • Voltage regulator overload • LIN bus output overload • Increase in die temperature due to increase in environment temperature The recovery time from the thermal shutdown is equal to adequate cooling time. Driving the TXD and checking the RXD pin makes it possible to determine whether there is a bus contention (TXD = high, RXD = low) or a thermal overload condition (TXD = low, RXD = high). FIGURE 1-7: THERMAL SHUTDOWN STATE DIAGRAMS LIN bus shorted to VBB Output Overload Voltage Regulator Shutdown Operation Mode Transmitter Shutdown Temp < SHUTDOWNTEMP Temp < SHUTDOWNTEMP 2012-2014 Microchip Technology Inc. DS20002299C-page 11 MCP2050 1.5 Internal Voltage Regulator The regulator overload current limit is approximately 250 mA. The regulator output voltage VREG is monitored. If output voltage VREG is lower than VSD, the voltage regulator will turn off. After a recovery time of about 3 ms, the VREG will be checked again. If there is no short circuit, (VREG > VSD) then the voltage regulator remains on. Note: The MCP2050 has a positive regulator capable of supplying +5.0V or +3.3V at up to 70 mA of load current with tolerances of ±3% over the entire operating temperature range of -40°C to +125°C. The regulator uses an LDO design, is short-circuit-protected and will turn the regulator output off if its output falls below the Shutdown Voltage Threshold VSD. With a load current of 70 mA, the minimum input-tooutput voltage differential required for the output to remain in regulation is typically +0.5V (+1V maximum over the full operating temperature range). Quiescent current is less than 100 µA with a full 70 mA load current when the input-to-output voltage differential is greater than +3.00V. The regulator requires an external output bypass capacitor for stability. See Figure 2-1 for correct capacity and ESR for stable operation. Regarding the correlation between VBB, VREG and IDD, refer to Figure 1-9 and Figure 1-10. When the input voltage (VBB) drops below the differential needed to provide stable regulation, the voltage regulator output VREG will track the input down to approximately VOFF. The regulator will turn off the output at this point. This will allow PIC® microcontrollers, with internal POR circuits, to generate a clean arming of the Power-on Reset trip point. The MCP2050 will then monitor VBB and turn on the regulator when VBB is above the threshold of regulator turn-on voltage VON. Under specific ambient temperature and battery voltage range, the voltage regulator can output as high as 150 mA current. Warning: In worst-case scenarios, the ceramic capacitor may derate by 50%, based on tolerance, voltage and temperature. Therefore, in order to ensure stability, ceramic capacitors smaller than 10 µF may require a small series resistance to meet the ESR requirements, as shown in Table 1-4. TABLE 1-4: For current load capability of the voltage regulator, refer to Figure 1-9 and Figure 1-10. In Power-Down mode, the VBB monitor is turned off. FIGURE 1-8: A ceramic capacitor of at least 10 µF, or a tantalum capacitor of at least 2.2 µF is recommended for stability. Note: RECOMMENDED SERIES RESISTANCE FOR CERAMIC CAPACITORS Resistance Capacitor 1 1 µF 0.47 2.2 µF 0.22 4.7 µF 0.1 6.8 µF VOLTAGE REGULATOR BLOCK DIAGRAM Pass Element VREG Sampling Network VBB Fast Transient Loop Buffer VSS VREF DS20002299C-page 12 2012-2014 Microchip Technology Inc. MCP2050 FIGURE 1-9: VOLTAGE REGULATOR OUTPUT ON POWER-ON RESET VBB V 8 Minimum VBB to maintain regulation VON 6 VOFF 4 2 0 t VREG V 5 VREG-NOM 4 3 2 1 0 Note 1: 2: 3: 4: 2012-2014 Microchip Technology Inc. t (4) (1) (2) (3) Start-Up, VBB < VON, regulator off. VBB > VON, regulator on. VBB minimum VBB to maintain regulation. VBB < VOFF, regulator will turn off. DS20002299C-page 13 MCP2050 FIGURE 1-10: VOLTAGE REGULATOR OUTPUT ON OVER CURRENT SITUATION IREG mA lLIM 0 t VREG 6 5 V VREG-NOM 4 VSD 3 2 1 0 Note 1: 2: 1.6 1.6.1 (1) (2) IREG less than lLIM, regulator on. After IREG exceeds lLIM, the voltage regulator output will be reduced until VSD is reached. Optional External Protection REVERSE BATTERY PROTECTION An external reverse-battery-blocking diode should be used to provide polarity protection (see Figure 1-12). 1.6.2 t TRANSIENT VOLTAGE PROTECTION (LOAD DUMP) An external 43V transient suppressor (TVS) diode, between VBB and ground, with a transient protection resistor (RTP) in series with the battery supply and the VBB pin protects the device from power transients and ESD events greater than 43V (see Figure 1-12). The maximum value for the RTP protection resistor depends on two parameters: the minimum voltage the part will start at, and the impacts of this RTP resistor on the VBB value, thus on the Bus recessive level and slopes. Equation 1-4 provides a max RTP value according to the maximum relative variation the user can accept on the slope when IREG varies. Since both Equation 1-2 and Equation 1-3 must be fulfilled, the maximum allowed value for RTP is thus the smaller of the two values found when solving Equation 1-2 and Equation 1-3. Usually Equation 1-2 gives the higher constraint (smaller value) for RTP as shown in the following example where VBATmin is 8V. However, the user needs to check that the value found with Equation 1-2 also fulfills Equation 1-3 and Equation 1-4. While this protection is optional, it should be considered as good engineering practice. This leads to a set of three equations to fulfill. Equation 1-2 provides a max RTP value according to the minimum battery voltage the user wants the part to start at. Equation 1-3 provides a max RTP value according to the maximum error on the recessive level thus VBB since the part uses VBB as the reference value for the recessive level. DS20002299C-page 14 2012-2014 Microchip Technology Inc. MCP2050 EQUATION 1-2: V BATmin – 5.5V R TP ------------------------------------250mA The following formula gives an indication of the minimum value of CBAT using RTOT and L: EQUATION 1-5: 5.5V = VOFF + 1.0V 250 mA is the peak current at power-on when VBB =5.5V Assume VBATMIN = 8V. Equation 1-2 shows 10Ω EQUATION 1-3: V RECESSIVE R TP ---------------------------------I REGMAX Where: L = Inductor (measured in mH) RTOT = RLINE + RTP (measured in ) Equation 1-5 allows lower CBAT/CREG values than the 10x ratio we recommend. Assume that we have a good quality VBAT connection with RTOT = 0.1 and L = 0.1 mH. Solving the equation gives CBAT/CREG = 1. Where: VRECESSIVE = Maximum variation tolerated on the recessive level Assume ∆VRECCESSIVE = 1V and IREGMAX = 50 mA Equation 1-3 shows 20Ω EQUATION 1-4: Slope V BATMIN – 1V R TP ----------------------------------------------------------------I REGMAX Where: Slope = Maximum variation tolerated on the slope level IREGMAX = Maximum current the current will provide to the load VBATMIN > VOFF + 1.0V If we increase RTOT up to 1 the result becomes CBAT/CREG = 1.4. However, if the connection is highly resistive or highly inductive (poor connection), the CBAT/CREG ratio greatly increases. TABLE 1-5: CBAT/CREG RATIO BY VBAT CONNECTION TYPE Connection Type RTOT L CBAT/CREG Ratio Good 0.1 0.1 mH 1 Typical 1 0.1 mH 1.4 Highly inductive 0.1 1 mH 7 Highly resistive 10 0.1 mH 7 Figure 1-11 shows the minimum recommended CBAT/CREG ratio as a function of the impedance of the VBAT connection. FIGURE 1-11: MINIMUM RECOMMENDED CBAT/CREG RATIO Assume ∆Slope = 15%, VBATMIN = 8V and IREGMAX = 50 mA. Equation 1-3 shows 20Ω CBAT/CREG Ratio as Function of the VBAT Line Impedance CBAT CAPACITOR Selecting CBAT = 10 x CREG is recommended. However, this leads to a high-value capacitor. Lower values for CBAT capacitor can be used with respect to some rules. In any case, the voltage at the VBB pin should remain above VOFF when the device is turned on. The current peak at start-up (due to the fast charge of the CREG and CBAT capacitors) may induce a significant drop on the VBB pin. This drop is proportional to the impedance of the VBAT connection (see Figure 1-12). 10 RBAT = 10 RBAT = 4 CBAT/CREG 1.6.3 2 2 100L + R TOT ----------------------------------2 RTOT 2 1 + L + ------------100 C BAT -------------- = C REG RBAT = 2 RBAT = 1 RBAT = 0.3 RBAT = 0.1 1 0.1 1 VBAT Line Inductance [mH] The VBAT connection is mainly inductive and resistive. Therefore, it can be modeled as a resistor (RTOT) in series with an inductor (L). RTOT and L can be measured. 2012-2014 Microchip Technology Inc. DS20002299C-page 15 MCP2050 1.7 Typical Applications FIGURE 1-12: TYPICAL APPLICATION CIRCUIT VBAT VBAT RTP 220 kΩ 43V(5) CREG WAKE-UP VDD VREG TXD TXD (6) RXD I/O VBB 1 kΩ RXD VBATRATIO A/D MCU Master Node Only VBB CBAT LIN Bus LBUS CS/LWAKE (3) I/O FAULT/TXE I/O WWDTTRIG MMBZ27V (4) 220 pF WWDTRESET IRQ RESET RESET VSS (6) WWDTSELECT VSS 100 nF Note 1: CREG, the load capacitor, should be ceramic or tantalum rated for extended temperatures, 1.0-22 µF. See Figure 2-1 for selecting the correct ESR. 2: CBAT is the filter capacitor for the external voltage supply. It’s typically 10 · CREG, with no ESR restriction. See Figure 1-11 to select the minimum recommended value for CBAT. The RTP value is added to the line resistance. 3: This diode is only needed if CS/LWAKE is connected to VBAT supply. 4: ESD protection diode. 5: This component is for additional load dump protection. 6: An external 10 kΩ resistor is recommended for some applications. DS20002299C-page 16 2012-2014 Microchip Technology Inc. MCP2050 FIGURE 1-13: TYPICAL LIN NETWORK CONFIGURATION 40m + Return LIN bus 1 kΩ VBB LIN bus MCP2050 LIN bus MCP2050 Slave 1 (MCU) LIN bus MCP202XA LIN bus MCP2003 Slave 2 (MCU) Slave n <16 (MCU) Master (MCU) 1.8 ICSP™ Considerations The following should be considered when the MCP2050 is connected to pins supporting in-circuit programming: • Power used for programming the microcontroller can be supplied from the programmer, or from the MCP2050. • The voltage on the VREG pin should not exceed the maximum value of VREG as shown in Section 2.3, DC Specifications. 2012-2014 Microchip Technology Inc. DS20002299C-page 17 MCP2050 2.0 ELECTRICAL CHARACTERISTICS 2.1 Absolute Maximum Ratings† VIN DC Voltage on RXD, and RESET ................................................................................................ -0.3V to VREG + 0.3 VIN DC Voltage on TXD, CS/LWAKE, FAULT/TXE......................................................................................... -0.3 to + 40V VBB Battery Voltage, continuous, non-operating (Note 1)............................................................................ -0.3 to + 40V VBB Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s) (Note 2) ..................... -0.3 to + 43V VBB Battery Voltage, transient ISO 7637 Test 1 ..................................................................................................... -100V VBB Battery Voltage, transient ISO 7637 Test 2a .....................................................................................................+75V VBB Battery Voltage, transient ISO 7637 Test 3a ................................................................................................... -150V VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+100V VLBUS Bus Voltage, continuous ..................................................................................................................... -18 to + 30V VLBUS Bus Voltage, transient (Note 3) .......................................................................................................... -27 to + 43V ILBUS Bus Short-Circuit Current Limit ....................................................................................................................200 mA ESD protection on LIN, VBB (IEC 61000-4-2) (Note 4) ......................................................................................... ±15 KV ESD protection on LIN, VBB (Human Body Model) (Note 5) ................................................................................... ±8 KV ESD protection on all other pins (Human Body Model) (Note 5) ............................................................................ ±4 KV ESD protection on all pins (Charge Device Model) (Note 6).................................................................................±1500V ESD protection on all pins (Machine Model) (Note 7).............................................................................................±200V Maximum Junction Temperature ............................................................................................................................. 150C Storage Temperature..................................................................................................................................-65 to + 150C † NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Note 1: LIN 2.x compliant specification. 2: SAE J2602-2 compliant specification. 3: ISO 7637/1 load dump compliant (t < 500 ms). 4: According to IEC 61000-4-2, 330 ohm, 150 pF and Tranceiver EMC Test Specifications [2] to [4] 5: According to AEC-Q100-002/JESD22-A114 6: According to AEC-Q100-011B 7: According to AEC-Q100-003/JESD22-A115 2.2 Nomenclature used in this document Some terms and names used in this data sheet deviate from those referred to in the LIN specifications. Equivalent values are shown below. LIN 2.1 Name Term used in the following tables VBAT not used VSUP VBB Supply voltage at device pin VBUS_LIM ISC Current Limit of Driver VBUSREC VIH(LBUS) Recessive state VBUSDOM VIL(LBUS) Dominant state DS20002299C-page 18 Definition ECU operating voltage 2012-2014 Microchip Technology Inc. MCP2050 2.3 DC Specifications DC Specifications Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V, TA = -40°C to +125°C CREG = 10 µF Sym. Min. Typ. Max. Units Conditions IBBQ — — 200 µA IOUT = 0 mA, LBUS recessive VREG = 5.0V — — 200 µA IOUT = 0 mA, LBUS recessive VREG = 3.3V — — 250 µA IOUT = 0 mA, LBUS recessive VREG = 5.0V Power VBB Quiescent Operating Current VBB Quiescent Operating Current with Watchdog Enabled IBBQWDT 250 VBB READY Current VBB Ready Current WWDT Enabled IBBRD IBBRDWDT IOUT = 0 mA, LBUS recessive VREG = 3.3V — — 100 µA IOUT = 0 mA, LBUS recessive VREG = 5.0V — — 100 µA IOUT = 0 mA, LBUS recessive VREG = 3.3V — — 150 µA With voltage regulator on, transmitter off, receiver on, FAULT/TXE = VIL, CS = VIH,VREG = 5.0V 150 VBB Transmitter-Off Current with Watchdog Disabled VBB Power-Down Current VBB Current with VSS Floating Note 1: 2: 3: IBBTO With voltage regulator on, transmitter off, receiver on, FAULT/TXE = VIL, CS = VIH,VREG = 3.3V — — 100 µA With voltage regulator on, transmitter off, receiver on, FAULT/TXE = VIL, CS = VIH,VREG = 5.0V — — 100 µA With voltage regulator on, transmitter off, receiver on, FAULT/TXE = VIL, CS = VIH,VREG = 3.3V IBBPD — 4.5 8 µA With voltage regulator powered-off, receiver on and transmitter off, FAULT/TXE = VIH, TXD = VIH, CS = VIL) IBBNOGND -1 — 1 mA VBB = 12V, GND to VBB, VLIN = 0-18V Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0, VLBUS = VBB). Characterized, not 100% tested. In Power-Down mode, normal LIN recessive/dominant threshold is disabled; VWK(LBUS) is used to detect bus activities. 2012-2014 Microchip Technology Inc. DS20002299C-page 19 MCP2050 2.3 DC Specifications (Continued) DC Specifications Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V, TA = -40°C to +125°C CREG = 10 µF Sym. Min. Typ. Max. Units Conditions High-Level Input Voltage (TXD, FAULT/TXE, WWDTTRIG) VIH 2.0 — VREG +0.3 V Low-Level Input Voltage (TXD, FAULT/TXE, WWDTTRIG) VIL -0.3 — 0.8 V High-Level Input Current (TXD, FAULT/TXE, WWDTTRIG) IIH -2.5 — 0.4 µA Input voltage = 4.0V. ~800 kΩ internal adaptive pull-up Low-Level Input Current (TXD, FAULT/TXE, WWDTTRIG) IIL -10 — — µA Input voltage = 0.5V. ~800 kΩ internal adaptive pull-up High-Level Input Voltage (CS/LWAKE) VIH 2.0 — VBB V Through a current-limiting resistor Low-Level Input Voltage (CS/LWAKE) VIL -0.3 — 0.8 V High-Level Input Current (CS/LWAKE) IIH — — 8.0 µA Input voltage = 0.8VREG ~1.3 MΩ internal pulldown to VSS Low-Level Input Current (CS/LWAKE) IIL — — 5.0 µA Input voltage = 0.2VREG ~1.3 MΩ internal pulldown to VSS Low-Level Output Voltage (RXD) VOLRXD — — 0.2VREG V IOL = 2 mA High-Level Output Voltage (RXD) VOHRXD 0.8VREG — — V IOH = 2 mA Low-Level Output Voltage (FAULT/TXE) VOLOD — 1.0 V IOL = 4 mA Low-Level Output Voltage (RESET) VOLRST — 1.0 V IOL = 4 mA Microcontroller Interface Note 1: 2: 3: — Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0, VLBUS = VBB). Characterized, not 100% tested. In Power-Down mode, normal LIN recessive/dominant threshold is disabled; VWK(LBUS) is used to detect bus activities. DS20002299C-page 20 2012-2014 Microchip Technology Inc. MCP2050 2.3 DC Specifications (Continued) DC Specifications Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V, TA = -40°C to +125°C CREG = 10 µF Sym. Min. High-Level Input Voltage VIH(LBUS) 0.6 VBB Low-Level Input Voltage VIL(LBUS) -8 Typ. Max. Units Conditions — — V Recessive state — 0.4 VBB V Dominant state Bus Interface VHYS — — 0.175 VBB V Low-Level Output Current Input Hysteresis IOL(LBUS) 40 — 200 mA Output voltage = 0.1 VBB, VBB = 12V Pull-Up Current on Input IPU(LBUS) -180 — -72 µA ~30 kΩ internal pull-up @ VIH (LBUS) = 0.7 VBB, VBB=12V (Note 1) VIH(LBUS) – VIL(LBUS) Short-Circuit Current Limit ISC 50 — 200 mA High-Level Output Voltage VOH(LBUS) 0.8 VBB — VBB V Driver Dominant Voltage V_LOSUP — — 1.1 V VBB = 7.3V, RLOAD = 1000Ω Driver Dominant Voltage V_HISUP — — 1.2 V VBB = 18V, RLOAD = 1000Ω Input Leakage Current (at the receiver during dominant bus level) IBUS_PAS_ -1 — — mA Driver off, VBUS = 0V, VBB = 12V Input Leakage Current (at the receiver during recessive bus level) IBUS_PAS_ -20 — 20 µA Driver off, 8V < VBB < 18V 8V < VBUs < 18V VBUS VBB Leakage Current IBUS_NO_G (disconnected from ground) ND -10 — +10 µA GNDDEVICE = VBB, 0V < VBUS < 18V, VBB = 12V Leakage Current (disconnected from VBB) IBUS_NO_P -10 — +10 µA VBB = GND, 0 < VBUS < 18V Receiver Center Voltage VBUS_CNT 0.475 VBB 0.5 VBB 0.525 VBB V VBUS_CNT = (VIL (LBUS) + VIH (LBUS))/2 RSLAVE 20 30 47 kΩ (Note 2) 50 pF (Note 2) — — 3.4 V Wake up from PowerDown mode (Note 3) Slave Termination Capacitance of slave node Wake-Up Voltage Threshold on LIN Bus Note 1: 2: 3: DOM REC WR CSLAVE VWK(LBUS) Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0, VLBUS = VBB). Characterized, not 100% tested. In Power-Down mode, normal LIN recessive/dominant threshold is disabled; VWK(LBUS) is used to detect bus activities. 2012-2014 Microchip Technology Inc. DS20002299C-page 21 MCP2050 2.3 DC Specifications (Continued) DC Specifications Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V, TA = -40°C to +125°C CREG = 10 µF Sym. Min. Typ. Max. Units Conditions Voltage Regulator – 5.0V VREG 4.85 5.00 5.15 V Line Regulation Output Voltage Range VOUT1 — 10 50 mV IOUT = 1 mA, 6.0V < VBB < 18V Load Regulation VOUT2 — 10 50 mV 5 mA < IOUT <70 mA 6.0V < VBB < 12V PSRR — — 50 dB 1 VPP @10-20 kHz ILOAD = 20 mA Output Noise Voltage eN — — 100 Shutdown Voltage Threshold VSD 3.5 — 4.0 V Input Voltage to Turn Off Output VOFF 3.9 — 4.5 V Input Voltage to Turn On Output VON 5.25 — 6.0 V Output Voltage VREG 3.20 3.30 3.40 V Line Regulation VOUT1 — 10 50 mV IOUT = 1 mA, 6.0V < VBB < 18V Load Regulation VOUT2 — 10 50 mV 5 mA < IOUT < 70 mA, 6.0V < VBB < 12V PSRR — — 50 dB 1 VPP @10-20 kHz, ILOAD = 20 mA Output Noise Voltage eN — — 100 Shutdown Voltage VSD 2.5 — 2.7 Power Supply Ripple Reject 0 mA < IOUT < 70 mA µVRMS 10 Hz – 40 MHz CFILTER = 10 µf, CBP = 0.1 µf, ILOAD = 20 mA See Figure 1-10 (Note 2) Voltage Regulator – 3.3V Power Supply Ripple Reject Note 1: 2: 3: 0 mA < IOUT < 70 mA µVRMS 10 Hz – 40 MHz /Hz CFILTER = 10 µf, CBP = 0.1 µf, ILOAD = 20 mA V See Figure 1-10 (Note 2) Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0, VLBUS = VBB). Characterized, not 100% tested. In Power-Down mode, normal LIN recessive/dominant threshold is disabled; VWK(LBUS) is used to detect bus activities. DS20002299C-page 22 2012-2014 Microchip Technology Inc. MCP2050 FIGURE 2-1: ESR CURVES FOR LOAD CAPACITOR SELECTION ESR Curves 10 Instable Unstable Stable only ESR [ohm] 1 with Tantalum or Electrolytic cap. Stable with Tantalum, Electrolytic and Ceramic cap. Unstable Instable 0.1 0.01 Instable Unstable 0.001 0.1 1 10 100 1000 Load Capacitance Load Capacitor [uF] Note 1: The graph shows the minimum capacitance after de-rating due to tolerance, temperature and voltage 2012-2014 Microchip Technology Inc. DS20002299C-page 23 MCP2050 2.4 AC Specifications AC CHARACTERISTICS Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for VBB = 6.0V to 18.0V; TA = -40°C to +125°C Sym. Min. Typ. Max. Units Test Conditions Bus Interface - Constant Slope Time Parameters (DC specifications are for a VBB range of 6.0 to 18.0V) Slope Rising and Falling Edges tSLOPE 3.5 — 22.5 µs 7.3V <= VBB <= 18V Propagation Delay of Transmitter tTRANSPD — — 5.0 µs tTRANSPD = max (tTRANSPDR or tTRANSPDF) Propagation Delay of Receiver tRECPD — — 6.0 µs tRECPD = max (tRECPDR or tRECPDF) tRECSYM -2.0 — 2.0 µs trecsym = max (tRECPDF – tRECPDR) RRXD 2.4 kΩto VCC, CRXD 20pF tTRANSSYM -2.0 — 2.0 µs tTRANSSYM = max (tTRANSPDF tTRANSPDR) Bus Dominant Time-Out Time tTO(LIN) — 25 — mS Time to Sample of FAULT/TXE for Bus Conflict Reporting tFAULT — — 32.5 µs Duty Cycle 1 @ 20.0 kbit/sec 0.396 — — %tBIT CBUS;RBUS conditions: 1 nF; 1 kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω THREC(MAX) = 0.744 x VBB, THDOM(MAX) = 0.581 x VBB, VBB =7.0V - 18V; tBIT = 50 µs. D1 = tBUS_REC(MIN) / 2 x tBIT) Duty Cycle 2 @ 20.0 kbit/sec — — 0.581 %tBIT CBUS;RBUS conditions: 1 nF; 1 kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω THREC(MAX) = 0.284 x VBB, THDOM(MAX) = 0.422 x VBB, VBB =7.6V - 18V; tBIT = 50 µs. D2 = tBUS_REC(MAX) / 2 x tBIT) Duty Cycle 3 @ 10.4 kbit/sec 0.417 — — %tBIT CBUS;RBUS conditions: 1 nF; 1 kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω THREC(MAX) = 0.778 x VBB, THDOM(MAX) = 0.616 x VBB, VBB =7.0V - 18V; tBIT = 96 µs. D3 = tBUS_REC(MIN) / 2 x tBIT) Duty Cycle 4 @ 10.4 kbit/sec — — 0.590 %tBIT CBUS;RBUS conditions: 1 nF; 1 kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω THREC(MAX) = 0.251 x VBB, THDOM(MAX) = 0.389 x VBB, VBB =7.6V - 18V; tBIT = 96 µs. D4 = tBUS_REC(MAX) / 2 x tBIT) Symmetry of Propagation Delay of Receiver Rising Edge w.r.t. Falling Edge Symmetry of Propagation Delay of Transmitter Rising Edge w.r.t. Falling Edge DS20002299C-page 24 tFAULT = max (tTRANSPD + tSLOPE + tRECPD) 2012-2014 Microchip Technology Inc. MCP2050 2.4 AC Specifications (Continued) AC CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, all limits are specified for VBB = 6.0V to 18.0V; TA = -40°C to +125°C Parameter Sym. Min. Typ. Max. Units Test Conditions tBDB 30 80 250 µs tBACTIVE 35 — 200 µs Voltage Regulator Enabled to Ready tVEVR 300 — 1200 µs Chip Select to Ready Mode tCSR — — 230 µs Chip Select to Power-Down tCSPD — — 300 µs tSHUTDOWN 20 — 100 µs VREG OK detect to RESET inactive tRPU — — 60.0 µs VREG not OK detect to RESET active tRPD — — 60.0 µs Reset Pulse Length tWDRST — 150 — µs -40/+100% Power-Up Watchdog Window Length tPOWERUP — 27.2 — ms ±15% RWWDTSELECT = 33 kΩ (Note 2, Note 3) Watchdog Window Length tWLENGTH 5.95 7 8.05 ms ±15% RWWDTSELECT = 33 kΩ (Note 4, Note 5) 102 120 138 ms ±15% RWWDTSELECT = 680 kΩ (Note 4, Note 5) Voltage Regulator Bus Activity Debounce time Bus Activity to Voltage Regulator Enabled Short-Circuit to Shutdown (Note 1) (Note 2) RESET Timing WWDT Note 1: 2: 3: 4: 5: 2.5 Time depends on external capacitance and load. Test condition: CREG = 4.7uF, no resistor load. Characterized, not 100% tested. tPOWERUP = 0.8 ms × (RWWDTSELECT+1); R in kΩ. tWLENGTH = (0.175 ms × RWWDTSELECT) + 1.2 ±15%; R in kΩ. Characterized; tested for RWWDTSELECT = 33 kΩ and 680 kΩ Thermal Specifications Parameter Symbol Typ Max Units Recovery Temperature RECOVERY +140 — C Shutdown Temperature SHUTDOWN +150 — C tTHERM 1.5 5.0 ms Short Circuit Recovery Time Test Conditions Thermal Package Resistances Thermal Resistance, 14L-PDIP JA 70 — C/W Thermal Resistance, 14L-SOIC JA 90.8 — C/W Thermal Resistance, 20L-QFN JA 44.6 — C/W Note 1: The maximum power dissipation is a function of TJMAX, JA and ambient temperature TA. The maximum allowable power dissipation at an ambient temperature is PD = (TJMAX - TA)JA. If this dissipation is exceeded, the die temperature will rise above 150C and the MCP2050 will go into thermal shutdown. 2012-2014 Microchip Technology Inc. DS20002299C-page 25 MCP2050 2.6 Typical Performance Curves Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 200 200 180 180 160 160 140 120 VBB = 6V IBBQ (μA) IBBQ (μA) Note: Unless otherwise indicated, VBB = 6.0V to 18.0V; TA = -40°C to +125°C VBB = 12V 100 140 120 VBB = 6V 100 VBB = 12V VBB = 18V VBB = 18V 80 80 -40 -25 -10 5 20 35 50 65 Temperature(°C) 80 -40 -25 -10 95 110 125 FIGURE 2-2: Typical IBBQ vs. Temperature – 5.0V. 95 110 125 100 90 70 VBB = 6V 60 IBBTO (μA) 80 IBBTO (μA) 80 FIGURE 2-5: Typical IBBQ vs. Temperature – 3.3V. 90 80 VBB = 6V -40 -25 -10 95 110 125 FIGURE 2-3: Typical IBBTO vs. Temperature – 5.0V. 5 5 4.8 4.8 IPD (μA) 5.2 4.6 VBB = 6V VBB = 12V 4.2 5 20 35 50 65 Temperature(°C) 80 95 110 125 FIGURE 2-6: Typical IBBTO vs. Temperature – 3.3V. 5.2 4.4 VBB = 12V 50 50 5 20 35 50 65 Temperature(°C) 70 VBB = 18V VBB = 18V -40 -25 -10 80 60 VBB = 12V IPD (μA) 5 20 35 50 65 Temperature(°C) 4.6 4.4 VBB=6V VBB=12V 4.2 VBB = 18V VBB=18V 4 4 -40 -25 -10 5 20 35 50 65 Temperature(°C) 80 FIGURE 2-4: Typical IPD vs. Temperature – 5.0V. DS20002299C-page 26 95 110 125 -40 -25 -10 5 20 35 50 65 Temperature(°C) 80 95 110 125 FIGURE 2-7: Typical IPD vs. Temperature – 3.3V. 2012-2014 Microchip Technology Inc. MCP2050 3.5 6 3 5 2.5 VREG (V) VREG (V) 4 3 2 -40°C +25°C 1 +125°C FIGURE 2-8: 12V. 1 -40°C +25°C +90°C +125°C 0 0 50 1.5 0.5 +90°C 0 2 100 150 IREG (mA) 200 250 300 5.0 VREG vs. IREG at VBB = 2012-2014 Microchip Technology Inc. 0 FIGURE 2-9: 12V. 50 100 150 IREG (mA) 200 250 300 3.3V VREG vs. IREG at VBB = DS20002299C-page 27 MCP2050 2.7 Timing Diagrams and Specifications FIGURE 2-10: BUS TIMING DIAGRAM TXD 50% 50% LBUS .95VLBUS .50VBB .05VLBUS tTRANSPDR tTRANSPDF tRECPDF 0.0V tRECPDR RXD 50% Internal TXD/RXD Compare Match 50% Match Match Match Match FAULT Sampling tFAULT tFAULT FAULT/TXE Output FIGURE 2-11: Stable Hold Value Stable Hold Value Stable REGULATOR BUS WAKE TIMING DIAGRAM LBUS VWK(LBUS) tBDB tVEVR tBACTIVE VREG-NOM VREG DS20002299C-page 28 2012-2014 Microchip Technology Inc. MCP2050 FIGURE 2-12: CS/LWAKE, REGULATOR AND RESET TIMING DIAGRAM CS/LWAKE tCSR tVEVR VREG-NOM VREG tRPD tRPU tCSPD RESET 2012-2014 Microchip Technology Inc. DS20002299C-page 29 MCP2050 3.0 PACKAGING INFORMATION 3.1 Package Marking Information Example 14-Lead PDIP (300 mil) MCP2050-500 3 E/P e^^ 1429256 Example 14-Lead SOIC (.150”) MCP2050-500 E/SL e^^ 3 1429256 20-Lead QFN (5x5x0.9 mm) PIN 1 Example PIN 1 MCP2050 500E/MQ 3 e^^ 1429256 Legend: XX...X Y YY WW NNN e3 * Note: DS20002299C-page 30 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2012-2014 Microchip Technology Inc. MCP2050 )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RSWR6HDWLQJ3ODQH $ ± ± 0ROGHG3DFNDJH7KLFNQHVV $ %DVHWR6HDWLQJ3ODQH $ ± ± 6KRXOGHUWR6KRXOGHU:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' 7LSWR6HDWLQJ3ODQH / /HDG7KLFNQHVV F E E H% ± ± 8SSHU/HDG:LGWK /RZHU/HDG:LGWK 2YHUDOO5RZ6SDFLQJ %6& 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKWKHKDWFKHGDUHD 6LJQLILFDQW&KDUDFWHULVWLF 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6&%DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2012-2014 Microchip Technology Inc. DS20002299C-page 31 MCP2050 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002299C-page 32 2012-2014 Microchip Technology Inc. MCP2050 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012-2014 Microchip Technology Inc. DS20002299C-page 33 MCP2050 )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ DS20002299C-page 34 2012-2014 Microchip Technology Inc. MCP2050 20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-120A 2012-2014 Microchip Technology Inc. DS20002299C-page 35 MCP2050 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002299C-page 36 2012-2014 Microchip Technology Inc. MCP2050 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) Device Tape and Reel Option –X Temperature Range /XX Package Examples: a) MCP2050-330E/P: b) MCP2050-330E/MQ: Device: MCP2050: LIN Transceiver with Voltage Regulator MCP2050T: LIN Transceiver with Voltage Regulator (Tape and Reel) (SOIC and QFN) c) MCP2050T-330E/MQ: d) MCP2050-330E/SL: Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: E Package: MQ = 20-Lead Plastic Quad Flat, No Lead Package – 5x5x0.9 mm Body (QFN) P = 14-Lead Plastic Dual In-Line – 300 mil Body (PDIP) = -40°C to +125°C e) MCP2050T-330E/SL: f) MCP2050-500E/P: g) MCP2050-500E/MQ: SL = 14-Lead Plastic Small Outline – Narrow, 3.90 mm Body (SOIC) h) MCP2050T-500E/MQ: i) MCP2050-500E/SL: j) MCP2050T-500E/SL: Note 1: 2012-2014 Microchip Technology Inc. 3.3V, Extended Temperature, 14-LD PDIP Package 3.3V, Extended Temperature, 20-LD QFN Package Tape and Reel, 3.3V, Extended Temperature, 20-LD QFN Package 3.3V, Extended Temperature, 14-LD SOIC Package Tape and Reel, 3.3V, Extended Temperature, 14-LD SOIC Package 5.0V, Extended Temperature, 14-LD PDIP Package 5.0V, Extended Temperature, 20-LD QFN Package Tape and Reel, 5.0V, Extended Temperature, 20-LD QFN Package 5.0V, Extended Temperature, 14-LD SOIC Package Tape and Reel, 5.0V, Extended Temperature, 14-LD SOIC package Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DS20002299C-page 37 MCP2050 APPENDIX A: REVISION HISTORY Revision D (September 2014) The following is the list of modifications: 1. 2. 3. 4. 5. 6. Added Exposed Thermal Pad pin on QFN and in Section 1.3, Pin Descriptions. Updated Figure 1-7. Added note in Figure 2-1. Added AC parameter for WWDT in Section 2.4, AC Specifications. Created new Section 2.6, Typical Performance Curves. Fixed minor typographical errors. Revision C (August 2012) The following is the list of modifications: 1. Removed two notes in Section 2.4 “AC Specifications”. Revision B (April 2012) The following is the list of modifications: 1. 2. 3. Corrected a label in Figure 1-12. Corrected a label in Figure 1-13. Updated the Product Identification System page. Revision A (March 2012) Original release of this document. DS20002299C-page 38 2012-2014 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2012-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63276-639-7 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2012-2014 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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