AD AD8228ARMZ-RL1 Low gain drift precision instrumentation amplifier Datasheet

Low Gain Drift
Precision Instrumentation Amplifier
AD8228
CONNECTION DIAGRAM
Easy to use
Pin strappable gains of 10 and 100
Wide power supply range: ±2.3 V to ±18 V
DC specifications (B Grade, G = 10)
2 ppm/°C gain drift
0.02% gain error
50 μV maximum input offset voltage
0.8 μV/°C maximum input offset drift
0.6 nA maximum input bias current
100 dB CMRR
AC specifications
650 kHz, –3 dB bandwidth (G = 10)
2 V/μs slew rate
Low noise
8 nV/√Hz, @ 1 kHz (G = 100)
0.3 μV p-p from 0.1 Hz to 10 Hz (G = 100)
APPLICATIONS
Weigh scales
Industrial process controls
Bridge amplifiers
Precision data acquisition systems
Medical instrumentation
Strain gages
Transducer interfaces
–IN 1
8 +VS
G1 2
7 VOUT
G2 3
6 REF
+IN 4
5 –VS
AD8228
TOP VIEW
(Not to Scale)
07035-001
FEATURES
Figure 1.
Table 1. Instrumentation Amplifiers by Category
General
Purpose
AD82201
AD8221
AD8222
AD82241
AD8228
1
Zero
Drift
AD82311
AD85531
AD85551
AD85561
AD85571
Military
Grade
AD620
AD621
AD524
AD526
AD624
Low
Power
AD6271
AD6231
High Speed
PGA
AD8250
AD8251
AD8253
Rail-to-rail output.
GENERAL DESCRIPTION
The AD8228 is a high performance instrumentation amplifier
with very high gain accuracy. Because all gain setting resistors
are internal and laser trimmed, gain accuracy and gain drift
are better than can be achieved with typical instrumentation
amplifiers.
The AD8228 operates on both single and dual supplies. Because
the part can operate on supplies up to ±18 V, it is well suited for
applications where high common-mode input voltages are
encountered. The AD8228 is available in 8-lead MSOP and
SOIC packages.
Low voltage offset, low offset drift, low gain drift, high gain
accuracy, and high CMRR make this part an excellent choice
in applications that demand the best dc performance possible,
such as bridge signal conditioning.
Performance is specified over the entire industrial temperature
range of −40°C to +85°C for all grades. Furthermore, the AD8228
is operational from −40°C to +125°C. For a pin-compatible amplifier with similar specifications, but with a gain range of 1 to 1000,
see the AD8221.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD8228* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
Reference Materials
View a parametric search of comparable parts
Technical Articles
• High-performance Adder Uses Instrumentation Amplifiers
Evaluation Kits
• AD62x, AD822x, AD842x Series InAmp Evaluation Board
Documentation
Application Notes
• AN-1401: Instrumentation Amplifier Common-Mode
Range: The Diamond Plot
Data Sheet
• AD8228: Low Gain Drift Precision Instrumentation
Amplifier Data Sheet
Technical Books
• A Designer's Guide to Instrumentation Amplifiers, 3rd
Edition, 2006
User Guides
• UG-261: Evaluation Boards for the AD62x, AD822x and
AD842x Series
Design Resources
•
•
•
•
AD8228 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
Discussions
View all AD8228 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
number
Tools and Simulations
• AD8228 SPICE Macro-Model
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.
AD8228
TABLE OF CONTENTS
Features .............................................................................................. 1
Architecture ................................................................................ 16
Applications....................................................................................... 1
Setting the Gain .......................................................................... 16
General Description ......................................................................... 1
Common-Mode Input Voltage Range ..................................... 16
Connection Diagram ....................................................................... 1
Reference Terminal .................................................................... 17
Revision History ............................................................................... 2
Layout .......................................................................................... 17
Specifications..................................................................................... 3
Input Protection ......................................................................... 18
Gain = 10 ....................................................................................... 3
Radio Frequency Interference (RFI) ........................................ 18
Gain = 100 ..................................................................................... 5
Applications Information .............................................................. 19
Absolute Maximum Ratings............................................................ 7
Differential Drive ....................................................................... 19
Thermal Resistance ...................................................................... 7
Precision Strain Gage................................................................. 19
ESD Caution.................................................................................. 7
Driving a Differential ADC ...................................................... 19
Pin Configuration and Function Descriptions............................. 8
Outline Dimensions ....................................................................... 20
Typical Performance Characteristics ............................................. 9
Ordering Guide .......................................................................... 21
Theory of Operation ...................................................................... 16
REVISION HISTORY
7/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD8228
SPECIFICATIONS
GAIN = 10
VS = ±15 V, VREF = 0 V, TA = 25°C, RL = 2 kΩ, all specifications referred to input, unless otherwise noted.
Table 2.
Parameter
COMMON-MODE REJECTION RATIO
CMRR DC to 60 Hz with 1 kΩ
Source Imbalance
CMRR at 2 kHz
NOISE
Voltage Noise
Current Noise
VOLTAGE OFFSET
Offset
Over Temperature
Average TC
Offset vs. Supply (PSR)
INPUT CURRENT
Input Bias Current
Over Temperature
Average TC
Input Offset Current
Over Temperature
Average TC
REFERENCE INPUT
RIN
IIN
Voltage Range
Gain to Output
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
Settling Time 0.01%
Settling Time 0.001%
Slew Rate
GAIN
Gain Error
Gain Nonlinearity
RL = 10 kΩ
RL = 2 kΩ
Gain vs. Temperature
INPUT
Input Impedance
Differential
Common Mode
Input Operating Voltage Range 1
Over Temperature
Input Operating Voltage Range1
Over Temperature
Conditions
(Gain = 10)
Min
VCM = −10 V to +10 V
94
100
dB
VCM = −10 V to +10 V
VIN+ = VIN− = VREF = 0 V
90
100
dB
f = 1 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 0.1 Hz to 10 Hz
Referred to input,
VS = ±5 V to ±15 V
A Grade
Typ
Max
Min
B Grade
Typ
15
0.5
40
6
104
120
0.5
T = −40°C to +85°C
T = −40°C to +85°C
1
0.2
T = −40°C to +85°C
T = −40°C to +85°C
1
VIN+ = VIN− = VREF = 0 V
20
50
2
nV/√Hz
μV p-p
fA/√Hz
pA p-p
50
100
0.8
μV
μV
μV/°C
dB
1.5
2.0
0.6
1
nA
nA
pA/°C
nA
nA
pA/°C
120
0.4
1
0.1
0.6
0.8
0.4
0.6
1
1 ± 0.0001
1 ± 0.0001
kΩ
μA
V
V/V
650
6
9
2.5
650
6
9
2.5
kHz
μs
μs
V/μs
−VS
10 V step
10 V step
106
60
+VS
20
50
Unit
15
0.5
40
6
90
180
1.5
T = −40°C to +85°C
T = −40°C to +85°C
Max
−VS
2
60
+VS
VOUT = −10 V to +10 V
0.07
3
3
1
10
10
10
3
3
1
100||2
100||2
VS = ±2.3 V to ±5 V
T = −40°C to +85°C
VS = ±5 V to ±18 V
T = −40°C to +85°C
−VS + 1.9
−VS + 2.0
−VS + 1.9
−VS + 2.0
Rev. 0 | Page 3 of 24
0.02
%
10
10
2
ppm
ppm
ppm/°C
+VS − 1.1
+VS − 1.2
+VS − 1.2
+VS − 1.2
GΩ||pF
GΩ||pF
V
V
V
V
100||2
100||2
+VS − 1.1
+VS − 1.2
+VS − 1.2
+VS − 1.2
−VS + 1.9
−VS + 2.0
−VS + 1.9
−VS + 2.0
AD8228
Parameter
OUTPUT
Output Swing
Over Temperature
Output Swing
Over Temperature
Short-Circuit Current
POWER SUPPLY
Operating Range
Quiescent Current
Over Temperature
TEMPERATURE RANGE
Specified Performance
Operating Range 2
Conditions
(Gain = 10)
RL = 10 kΩ
VS = ±2.3 V to ±5 V
T = −40°C to +85°C
VS = ±5 V to ±18 V
T = –40°C to +85°C
Min
A Grade
Typ
−VS + 1.1
−VS + 1.4
−VS + 1.2
−VS + 1.6
Max
Min
+VS − 1.2
+Vs − 1.3
+VS − 1.4
+VS − 1.5
−VS + 1.1
−VS + 1.4
−VS + 1.2
−VS + 1.6
18
VS = ±2.3 V to ±18 V
±2.3
0.85
1
T = −40°C to +85°C
−40
−40
1
B Grade
Typ
Max
Unit
+VS − 1.2
+VS − 1.3
+VS − 1.4
+VS − 1.5
V
V
V
V
mA
±18
1
1.2
V
mA
mA
+85
+125
°C
°C
18
±18
1
1.2
±2.3
+85
+125
−40
−40
0.85
1
Operating near the input voltage range limit may reduce the available output range. See Figure 10 and Figure 11 for the input common-mode range vs. output
voltage.
2
See the Typical Performance Characteristics section for expected operation between 85°C to 125°C.
Rev. 0 | Page 4 of 24
AD8228
GAIN = 100
VS = ±15 V, VREF = 0 V, TA = 25°C, RL = 2 kΩ, all specifications referred to input, unless otherwise noted.
Table 3.
Parameter
COMMON-MODE REJECTION RATIO
CMRR DC to 60 Hz with 1 kΩ
Source Imbalance
CMRR at 2 kHz
NOISE
Voltage Noise
Current Noise
VOLTAGE OFFSET
Offset
Over Temperature
Average TC
Offset vs. Supply (PSR)
INPUT CURRENT
Input Bias Current
Over Temperature
Average TC
Input Offset Current
Over Temperature
Average TC
REFERENCE INPUT
RIN
IIN
Voltage Range
Gain to Output
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
Settling Time 0.01%
Settling Time 0.001%
Slew Rate
GAIN
Gain Error
Gain Nonlinearity
RL = 10 kΩ
RL = 2 kΩ
Gain vs. Temperature
INPUT
Input Impedance
Differential
Common Mode
Input Operating Voltage Range1
Over Temperature
Input Operating Voltage Range1
Over Temperature
Conditions
(Gain = 100)
Min
VCM = −10 V to +10 V
114
120
dB
VCM = −10 V to +10 V
VIN+ = VIN− = VREF = 0 V
100
105
dB
f = 1 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 0.1 Hz to 10 Hz
Referred to input,
VS = ±5 V to ±15 V
A Grade
Typ
Max
Min
B Grade
Typ
8
0.3
40
6
118
140
0.5
T = −40°C to +85°C
T = −40°C to +85°C
1
0.2
T = −40°C to +85°C
T = −40°C to +85°C
1
VIN+ = VIN− = VREF = 0 V
20
50
2
nV/√Hz
μV p-p
fA/√Hz
pA p-p
50
80
0.5
μV
μV
μV/°C
dB
1.5
2.0
0.6
1
nA
nA
pA/°C
nA
nA
pA/°C
140
0.4
1
0.1
0.6
0.8
0.4
0.6
1
1 ± 0.0001
1 ± 0.0001
kΩ
μA
V
V/V
110
13
15
2.5
110
13
15
2.5
kHz
μs
μs
V/μs
−VS
10 V step
10 V step
124
60
+VS
20
50
Unit
8
0.3
40
6
90
140
0.9
T = −40°C to +85°C
T = −40°C to +85°C
Max
−VS
2
60
+VS
VOUT = −10 V to +10 V
0.1
5
15
1
15
45
10
5
15
1
100||2
100||2
VS = ±2.3 V to ±5 V
T = −40°C to +85°C
VS = ±5 V to ±18 V
T =−40°C to +85°C
−VS + 1.9
−VS + 2.0
−VS + 1.9
−VS + 2.0
Rev. 0 | Page 5 of 24
0.05
%
15
45
2
ppm
ppm
ppm/°C
+VS − 1.1
+VS − 1.2
+VS − 1.2
+VS − 1.2
GΩ||pF
GΩ||pF
V
V
V
V
100||2
100||2
+VS − 1.1
+VS − 1.2
+VS − 1.2
+VS − 1.2
−VS + 1.9
−VS + 2.0
−VS + 1.9
−VS + 2.0
AD8228
Parameter
OUTPUT
Output Swing
Over Temperature
Output Swing
Over Temperature
Short-Circuit Current
POWER SUPPLY
Operating Range
Quiescent Current
Over Temperature
TEMPERATURE RANGE
Specified Performance
Operating Range 2
Conditions
(Gain = 100)
RL = 10 kΩ
VS = ±2.3 V to ±5 V
T = −40°C to +85°C
VS = ±5 V to ±18 V
T = −40°C to +85°C
Min
A Grade
Typ
−VS + 1.1
−VS + 1.4
−VS + 1.2
−VS + 1.6
Max
Min
+VS − 1.2
+Vs − 1.3
+VS − 1.4
+VS − 1.5
−VS + 1.1
−VS + 1.4
−VS + 1.2
−VS + 1.6
18
VS = ±2.3 V to ±18 V
±2.3
0.85
1
T = −40°C to +85°C
−40
−40
1
B Grade
Typ
Max
Unit
+VS − 1.2
+VS − 1.3
+VS − 1.4
+VS − 1.5
V
V
V
V
mA
±18
1
1.2
V
mA
mA
+85
+125
°C
°C
18
±18
1
1.2
±2.3
+85
+125
−40
−40
0.85
1
Operating near the input voltage range limit may reduce the available output range. See Figure 12 and Figure 13 for the input common-mode range vs. output
voltage.
2
See the Typical Performance Characteristics section for expected operation between 85°C to 125°C.
Rev. 0 | Page 6 of 24
AD8228
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Output Short-Circuit Current
Input Voltage (Common Mode)
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range1
Maximum Junction Temperature
ESD
Human Body Model
Charge Device Model
1
THERMAL RESISTANCE
Rating
±18 V
Indefinite
±VS
±VS
−65°C to +150°C
−40°C to +125°C
140°C
θJA is specified for a device in free air.
Table 5.
Package
8-Lead MSOP, 4-Layer JEDEC Board
8-Lead SOIC, 4-Layer JEDEC Board
ESD CAUTION
2 kV
1 kV
Temperature range for specified performance is −40°C to +85°C. See the
Typical Performance Characteristics section for expected operation from
85°C to 125°C.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 7 of 24
θJA
135
121
Unit
°C/W
°C/W
AD8228
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–IN 1
8 +VS
G1 2
7 VOUT
G2 3
6 REF
AD8228
5 –VS
TOP VIEW
(Not to Scale)
07035-004
+IN 4
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2, 3
4
5
6
7
8
Mnemonic
−IN
G1, G2
+IN
−VS
REF
VOUT
+VS
Description
Negative Input.
Gain Pins. Short together for a gain of 100. Leave unconnected for a gain of 10.
Positive Input.
Negative Supply.
Reference.
Output.
Positive Supply.
Rev. 0 | Page 8 of 24
AD8228
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.
MEAN: –5.5
SD: 12.4
70
MEAN: 0.20
SD: 0.12
100
60
80
HITS
HITS
50
40
30
60
40
20
20
–100
–50
0
50
G10 SYSTEM VOS RTI @ 15V (µV)
100
0
07035-043
0
Figure 3. Typical Distribution of Input Offset Voltage (G = 10)
1.5
100
MEAN: 0.29
SD: 0.27
80
50
40
60
HITS
HITS
–0.5
0
0.5
1.0
G100 SYSTEM VOS DRIFT RTI (µV)
Figure 6. Typical Distribution of Input Offset Voltage Drift (G = 100)
MEAN: –0.079
SD: 0.27
60
–1.0
07035-047
10
30
40
20
–1.0
–0.5
0
0.5
G10 SYSTEM VOS DRIFT RTI (µV)
1.0
1.5
0
–3
07035-045
0
–1.5
–2
–1
0
1
CMRR G100 RTI (µV/V)
2
3
07035-048
20
10
Figure 7. Typical Distribution for CMR (G = 100)
Figure 4. Typical Distribution of Input Offset Voltage Drift (G = 10)
MEAN: 7.1
SD: 10.1
MEAN: 0.42
SD: 0.08
120
80
100
60
HITS
HITS
80
40
60
40
20
–100
–50
0
50
G100 SYSTEM VOS RTI @ 15V (µV)
100
0
07035-046
0
–0.5
0
0.5
1.0
NEG IBIAS CURRENTS ±15V (nA)
Figure 8. Typical Distribution of Input Bias Current
Figure 5. Typical Distribution of Input Offset Voltage (G = 100)
Rev. 0 | Page 9 of 24
1.5
07035-049
20
AD8228
5
INPUT COMMON-MODE VOLTAGE (V)
4
80
HITS
60
40
0
–0.6
–0.4
–0.2
0
0.2
IOS @ 15V (nA)
0.4
0.6
07035-050
20
VS = ±5V
3
2
1
0
VS = ±2.5V
–1
–2
–3
–4
–5
–5
–4
–3
–2
–1
0
1
2
OUTPUT VOLTAGE (V)
3
4
5
07035-035
MEAN: –0.097
SD: 0.07
Figure 12. Input Common-Mode Voltage vs. Output Voltage,
VS = ±2.5 V, ±5 V; G = 100
Figure 9. Typical Distribution of Input Offset Current
5
15
2
1
0
VS = ±2.5V
–1
–2
–3
–4
–4
–3
–2
–1
0
1
2
OUTPUT VOLTAGE (V)
3
4
5
0
–5
–10
–10
–5
0
5
OUTPUT VOLTAGE (V)
10
15
Figure 13. Input Common-Mode Voltage vs. Output Voltage,
VS = ±15 V, G = 100
0.60
15
0.55
10
INPUT BIAS CURRENT (nA)
VS = ±15V
5
0
–5
–10
+IN IBIAS, ±15V SUPPLIES
0.50
–IN IBIAS, ±15V SUPPLIES
0.45
0.40
+IN IBIAS, ±5V SUPPLIES
0.35
–IN IBIAS, ±5V SUPPLIES
0.30
0.25
–10
–5
0
5
OUTPUT VOLTAGE (V)
10
15
0.20
–15
07035-034
INPUT COMMON-MODE VOLTAGE (V)
5
–15
–15
Figure 10. Input Common-Mode Voltage vs. Output Voltage,
VS = ±2.5 V, ±5 V; G =10
–15
–15
VS = ±15V
Figure 11. Input Common-Mode Voltage vs. Output Voltage,
VS = ±15 V, G = 10
–10
–5
0
5
COMMON-MODE VOLTAGE (V)
10
Figure 14. Input Bias Current vs. Common-Mode Voltage
Rev. 0 | Page 10 of 24
15
07035-051
–5
–5
10
07035-036
INPUT COMMON-MODE VOLTAGE (V)
VS = ±5V
3
07035-033
INPUT COMMON-MODE VOLTAGE (V)
4
2.00
160
1.75
140
NEGATIVE PSRR (dB)
1.50
1.25
1.00
0.75
0.50
G = 100
120
G = 10
100
80
60
0
0.01
0.1
1
WARM-UP TIME (Minutes)
10
20
0.1
Figure 15. Change in Input Offset Voltage vs. Warm-Up Time
1
10
100
1k
FREQUENCY (Hz)
10k
100k
1M
07035-013
40
0.25
07035-002
CHANGE IN INPUT OFFSET VOLTAGE (µV)
AD8228
Figure 18. Negative PSRR vs. Frequency
4
70
3
60
+IN IBIAS
1
0
–1
–IN IBIAS
G = 100
40
GAIN (dB)
IOS
30
G = 10
20
10
0
–2
–10
–3
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
–30
100
1k
Figure 16. Input Bias Current and Offset Current vs. Temperature
10M
150
140
100
G = 100
G = 10
GAIN ERROR (µV/V)
120
G = 10
100
80
60
50
0
G = 100
–50
–100
40
100
1k
10k
FREQUENCY (Hz)
100k
1M
–150
–45 –30 –15
07035-012
POSITIVE PSRR (dB)
1M
Figure 19. Gain vs. Frequency
160
20
10
10k
100k
FREQUENCY (Hz)
07035-019
–20
07035-052
–4
–40
–20
0
15 30 45 60 75
TEMPERATURE (°C)
90
Figure 20. Gain Error vs. Temperature
Figure 17. Positive PSRR vs. Frequency, RTI
Rev. 0 | Page 11 of 24
105 120 135
07035-007
INPUT BIAS CURRENT (nA)
50
2
AD8228
140
+VS – 0
G = 100
INPUT VOLTAGE LIMIT (V)
REFERRED TO SUPPLY VOLTAGES
+VS – 0.4
120
CMRR (dB)
G = 10
100
80
60
+VS – 0.8
+VS – 1.2
+VS – 1.6
+VS – 2.0
–VS + 2.0
–VS + 1.6
–VS + 1.2
–VS + 0.8
1
10
100
1k
FREQUENCY (Hz)
10k
100k
1M
–VS + 0
07035-039
0
5
10
SUPPLY VOLTAGE (±V)
15
20
Figure 24. Input Voltage Limit vs. Supply Voltage
Figure 21. CMRR vs. Frequency, RTI
140
+VS – 0
+VS – 0.4
OUTPUT VOLTAGE LIMIT (V)
REFERRED TO SUPPLY VOLTAGES
G = 100
120
G = 10
CMRR (dB)
0
07035-014
–VS + 0.4
40
100
80
60
+VS – 0.8
RL = 10kΩ
+VS – 1.2
+VS – 1.6
RL = 2kΩ
+VS – 2.0
–VS + 2.0
–VS + 1.6
RL = 2kΩ
–VS + 1.2
–VS + 0.8
RL = 10kΩ
0
1
10
100
1k
FREQUENCY (Hz)
10k
100k
1M
–VS + 0
07035-040
40
0
5
10
SUPPLY VOLTAGE (±V)
15
20
Figure 25. Output Voltage Swing vs. Supply Voltage
Figure 22. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance
30
20
VS = ±15V
15
25
OUTPUT VOLTAGE (V p-p)
5
0
–5
–10
15
10
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
0
1
10
100
LOAD RESISTANCE (Ω)
1k
Figure 26. Output Voltage Swing vs. Load Resistance
Figure 23. CMR vs. Temperature
Rev. 0 | Page 12 of 24
10k
07035-020
–20
–40
20
5
–15
07035-008
CMR (µV/V)
10
07035-015
–VS + 0.4
AD8228
1k
+VS –0
VOLTAGE NOISE RTI (nV/√Hz)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGE
–1
–2
–3
+3
+2
100
G = 10
10
G = 100
0
1
2
3
4
5
6
7
8
OUTPUT CURRENT (mA)
9
10
11
12
1
07035-021
–VS +0
1
100
1k
FREQUENCY (Hz)
10k
100k
Figure 30. Voltage Noise Spectral Density vs. Frequency
–10
–8
–6
–4
–2
0
2
4
OUTPUT VOLTAGE (V)
6
8
10
1s/DIV
07035-016
0.2µV/DIV
07035-023
ERROR (10ppm/DIV)
Figure 27. Output Voltage Swing vs. Output Current, G = 1
10
07035-022
+1
Figure 28. Gain Nonlinearity, G = 10, RL = 10 kΩ
Figure 31. 0.1 Hz to 10 Hz RTI Voltage Noise, G=10
–8
–6
–4
–2
0
2
4
OUTPUT VOLTAGE (V)
6
8
10
100
10
1
1
10
100
FREQUENCY (Hz)
1k
Figure 32. Current Noise Spectral Density vs. Frequency
Figure 29. Gain Nonlinearity, G = 100, RL = 10 kΩ
Rev. 0 | Page 13 of 24
10k
07035-030
–10
07035-029
ERROR (10ppm/DIV)
CURRENT NOISE (fA/ Hz)
1000
AD8228
5pA/DIV
5V/DIV
20µs/DIV
Figure 33. 0.1 Hz to 10 Hz Current Noise
07035-026
1s/DIV
07035-031
0.002%/DIV
Figure 36. Large Signal Pulse Response and Settling Time (G = 100)
30
VS = ±15V
20
15
G = 10, 100
20mV/DIV
10
5
10k
100k
FREQUENCY (Hz)
1M
07035-024
4µs/DIV
0
1k
07035-027
OUTPUT VOLTAGE (V p-p)
25
Figure 34. Large Signal Frequency Response
Figure 37. Small Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF
5V/DIV
07035-025
20µs/DIV
4µs/DIV
Figure 35. Large Signal Pulse Response and Settling Time (G = 10)
07035-028
20mV/DIV
0.002%/DIV
Figure 38. Small Signal Response, G = 100, RL = 2 kΩ, CL = 100 pF
Rev. 0 | Page 14 of 24
AD8228
15
20.0
G = 10
RL = 10kΩ
G = 100
RL = 10kΩ
SETTLING TIME (µs)
0.001% SETTLING TIME
0.01% SETTLING TIME
5
0.001% SETTLING TIME
15.0
12.5
0
0
5
10
15
OUTPUT VOLTAGE STEP SIZE (V p-p)
20
10.0
Figure 39. Settling Time vs. Step Size, G = 10
0
5
10
15
OUTPUT VOLTAGE STEP SIZE (V p-p)
Figure 40. Settling Time vs. Step Size, G = 100
Rev. 0 | Page 15 of 24
20
07035-042
0.01% SETTLING TIME
07035-041
SETTLING TIME (µs)
17.5
10
AD8228
THEORY OF OPERATION
I
I
VBIAS
IB COMPENSATION
A1
IB COMPENSATION
A2
C1
10kΩ
C2
+VS
10kΩ
R1
22kΩ
–IN
600Ω
Q1
R2
22kΩ
+VS
V1
–VS
+VS
R3
4.889kΩ
+VS
Q2
–VS
10kΩ
600Ω
REF
+IN
V2
–VS
–VS
G1 G2
–VS
+VS
07035-018
+VS
OUTPUT
A3
10kΩ
GAIN R4 –VS
SET 489Ω
Figure 41. Simplified Schematic
ARCHITECTURE
SETTING THE GAIN
The AD8228 is based on the classic three op amp topology. This
topology has two stages: a preamplifier to provide differential
amplification, followed by a difference amplifier to remove the
common-mode voltage. Figure 41 shows a simplified schematic
of the AD8228.
The AD8228 can be configured for a gain of 10 or 100 with no
external components. Leave Pin 2 and Pin 3 open for a gain of 10;
short Pin 2 and Pin 3 together for a gain of 100 (see Figure 42).
The second stage is a difference amplifier, composed of A3 and
four 10 kΩ resistors. The purpose of this stage is to remove the
common-mode signal from the amplified differential signal.
The AD8228 does not depend on external resistors. Much of the
dc performance of precision circuits depends on the accuracy and
matching of resistors. The resistors on the AD8228 are laid out to
be tightly matched. The resistors of each part are laser trimmed
and tested for their matching accuracy. Because of this trimming
and testing, the AD8228 can guarantee high accuracy for specifications such as gain drift, common-mode rejection (CMRR),
and gain error.
G = 100
PIN 2 AND PIN 3 SHORTED
+VS
–IN
1
8
–IN
2
3
+IN
+VS
AD8228
6
4
5
7
VOUT
2
3
+IN
8
1
AD8228
–VS
VOUT
6
4
REF
7
5
REF
–VS
07035-003
The first stage is composed of the A1 and A2 amplifiers, the Q1
and Q2 input transistors, and the R1 through R4 resistors. The
feedback loop of A1, R1, and Q1 ensures that the V1 voltage is
a constant diode drop below in the negative input voltage.
Similarly, V2 is kept a constant diode drop below the positive
input. Therefore, a replica of the differential input voltage is
placed across either R3 (when the gain pins are left open) or
R3||R4 (when the gain pins are shorted). The current that flows
across this resistance must also flow through the R1 and R2
resistors, creating a gained differential signal between the A2
and A1 outputs. Note that, in addition to a gained differential
signal, the original common-mode signal, shifted a diode drop
down, is also still present.
G = 10
PIN 2 AND PIN 3 OPEN
Figure 42. Setting the Gain
The transfer function with Pin 2 and Pin 3 open is
VOUT = 10 × (VIN+ − VIN−) + VREF
The transfer function with Pin 2 and Pin 3 shorted is
VOUT = 100 × (VIN+ − VIN−) + VREF
COMMON-MODE INPUT VOLTAGE RANGE
The three op amp architecture of the AD8228 applies gain and
then removes the common-mode voltage. Therefore, internal
nodes in the AD8228 experience a combination of both the
gained signal and the common-mode signal. This combined
signal can be limited by the voltage supplies even when the
individual input and output signals are not. Figure 10 through
Figure 13 show the allowable common-mode input voltage
ranges for various output voltages and supply voltages.
Rev. 0 | Page 16 of 24
AD8228
REFERENCE TERMINAL
Common-Mode Rejection Ratio over Frequency
The output voltage of the AD8228 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to level-shift
the output so that the AD8228 can drive a single-supply ADC. The
REF pin is protected with ESD diodes and should not exceed
either +VS or −VS by more than 0.3 V.
The AD8228 has a higher CMRR over frequency than typical
in-amps, which gives it greater immunity to disturbances such
as line noise and its associated harmonics. The AD8228 pinout
was designed so that the board designer can take full advantage
of this performance with a well-implemented layout.
For best performance, source impedance to the REF terminal
should be kept below 1 Ω. As shown in Figure 41, the reference
terminal, REF, is at one end of a 10 kΩ resistor. Additional impedance at the REF terminal adds to this 10 kΩ resistor and results
in amplification of the signal connected to the positive input.
The amplification from the additional RREF can be computed by
2 × (10 kΩ + RREF )
20 kΩ + RREF
Only the positive signal path is amplified; the negative path is
unaffected. This uneven amplification degrades the CMRR of
the amplifier.
REF
Power Supplies
CORRECT
AD8228
A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect performance. See the PSRR performance curves in Figure 17 and Figure 18
for more information.
AD8228
REF
V
V
A 0.1 μF capacitor should be placed as close as possible to each
supply pin. As shown in Figure 45, a 10 μF tantalum capacitor
can be used farther away from the part. In most cases, it can be
shared by other precision integrated circuits.
+
OP1177
07035-005
–
Parasitic capacitance at the gain setting pins can also affect
CMRR over frequency. If the board design has a component at
the gain setting pins (for example, a switch or jumper), the part
should be chosen so that the parasitic capacitance is as small as
possible.
+VS
Figure 43. Driving the Reference
LAYOUT
0.1µF
The AD8228 is a high precision device. To ensure optimum
performance at the PCB level, care must be taken in the design
of the board layout. The AD8228 pins are arranged in a logical
manner to aid in this task.
+IN
+VS
7
VOUT
G2 3
6
REF
+IN 4
5
–VS
LOAD
REF
AD8228
TOP VIEW
(Not to Scale)
0.1µF
07035-044
8
G1 2
VOUT
AD8228
–IN
–IN 1
10µF
–VS
10µF
07035-006
INCORRECT
Poor layout can cause some of the common-mode signal to be
converted to a differential signal before it reaches the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other. To keep CMRR across
frequency high, input source impedance and capacitance of each
path should be closely matched. Additional source resistance in
the input path (for example, for input protection) should be placed
close to the in-amp inputs, which minimizes their interaction
with parasitic capacitance from the PCB traces.
Figure 45. Supply Decoupling, REF, and Output Referred to Local Ground
Figure 44. Pinout Diagram
Rev. 0 | Page 17 of 24
AD8228
References
The output voltage of the AD8228 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.
For applications where the AD8228 encounters extreme overload
voltages, such as cardiac defibrillators, external series resistors
and low leakage diode clamps such as the BAV199L, the FJH1100s,
or the SP720 should be used.
Input Bias Current Return Path
Large Differential Voltages When G = 100
The input bias current of the AD8228 must have a return path
to common. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 46.
When operating at a gain of 100, large differential input voltages
can cause more than 6 mA of current to flow into the inputs.
This condition occurs when the voltage between +IN and –IN
exceeds 5 V. This is true for differential voltages of either polarity.
INCORRECT
The maximum allowed differential voltage can be increased by
adding an input protection resistor in series with each input.
The value of each protection resistor should be
CORRECT
+VS
+VS
RPROTECT = (VDIFF_MAX − 5 V)/6 mA
AD8228
RADIO FREQUENCY INTERFERENCE (RFI)
AD8228
REF
REF
–VS
RF rectification is often a problem when amplifiers are used in
applications having strong RF signals. The disturbance can appear
as a small dc offset voltage. High frequency signals can be filtered
with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 47. The filter limits the
input signal bandwidth, according to the following relationship:
–VS
TRANSFORMER
TRANSFORMER
+VS
+VS
FilterFrequencyDIFF =
AD8228
REF
REF
FilterFrequencyCM =
10MΩ
–VS
where CD ≥ 10 CC.
–VS
THERMOCOUPLE
+15V
THERMOCOUPLE
+VS
+VS
C
0.1µF
C
CC
R
1
fHIGH-PASS = 2πRC
AD8228
CD
REF
–VS
CAPACITIVELY COUPLED
CC
All terminals of the AD8228 are protected against ESD (1 kV,
human body model). In addition, the input structure allows for
dc overload conditions of about 3.5 V beyond the supplies.
Input Voltages Beyond the Rails
For larger input voltages, an external resistor should be used in
series with each input to limit current during overload conditions.
The AD8228 can safely handle a continuous 6 mA current. The
limiting resistor can be computed from
6 mA
10µF
–15V
INPUT PROTECTION
V IN − V SUPPLY
1nF
0.1µF
Figure 46. Creating an IBIAS Path
R LIMIT ≥
REF
–IN
4.02kΩ
07035-009
–VS
VOUT
AD8228
10nF
R
R
CAPACITIVELY COUPLED
+IN
4.02kΩ
AD8228
C
REF
10µF
1nF
R
C
1
2 πRCC
07035-010
AD8228
1
2πR(2CD + CC )
Figure 47. RFI Suppression
CD affects the difference signal, and CC affects the common-mode
signal. Values of R and CC should be chosen to minimize RFI.
Mismatch between the R × CC at the positive input and the R × CC
at the negative input degrades the CMRR of the AD8228. By using
a value of CD one magnitude larger than CC, the effect of the
mismatch is reduced, and performance is improved.
− 600 Ω
Rev. 0 | Page 18 of 24
AD8228
APPLICATIONS INFORMATION
DIFFERENTIAL DRIVE
PRECISION STRAIN GAGE
Figure 48 shows how to configure the AD8228 for differential
output. The advantage of this circuit is that the dc differential
accuracy depends on the AD8228 and not on the op amp or the
resistors. This circuit takes advantage of the precise control the
AD8228 has of its output voltage relative to the reference voltage.
The ideal equation for the differential output is as follows:
The low offset and high CMRR over frequency of the AD8228
make it an excellent candidate for bridge measurements. As shown
in Figure 49, the bridge can be connected directly to the inputs
of the amplifier.
5V
10µF
Op amp dc performance and resistor matching determine the
dc common-mode output accuracy. However, because commonmode errors are likely to be rejected by the next device in the
signal chain, these errors typically have little effect on overall
system accuracy. The ideal equation for the common-mode
output is as follows:
VOUT + + VOUT −
2
+
AD8228
–
2.5V
Figure 49. Precision Strain Gage
DRIVING A DIFFERENTIAL ADC
+OUT
Figure 50 shows how the AD8228 can be used to drive a
differential ADC. The AD8228 is configured with an op amp and
two resistors for differential drive. The 510 Ω resistors and 2200
pF capacitors isolate the instrumentation amplifier from the
switching transients produced by the switched capacitor front
end of a typical SAR converter. These components between the
ADC and the amplifier also create a filter at 142 kHz, which
provides antialiasing and noise filtering. The advantage of this
configuration is that it uses less power than a dedicated ADC
driver: the AD8641 typically consumes 200 μA, and the current
through the two 10 kΩ resistors is 250 μA at full output voltage.
–OUT
With the AD7688, this configuration gives excellent dc performance and a THD of 71 dB (10 kHz input). For applications that
need better distortion performance, a dedicated ADC driver, such
as the ADA4941-1 or ADA4922-1, is recommended.
+IN
AD8228
–IN
VREF
07035-017
+
–
AD8641
10kΩ
350Ω
–IN
= VREF
10kΩ
350Ω
+IN
For best ac performance, an op amp with at least 3 MHz gain
bandwidth product and 2 V/μs slew rate is recommended.
REF
350Ω
Figure 48. Differential Output Using an Op Amp
+8V
0.1µF
VIN
VOUT
ADR435
+8V
10µF
X5R
0.1µF
GND
10kΩ
+5V
0.1µF
10kΩ
0.1µF
+IN
510Ω
AD8228
–IN
–8V
REF 10kΩ
0.1µF
–8V
IN+
0.1µF
AD7688
AD8641
10kΩ
REF VDD
0.1µF
IN–
GND
0.1µF
+8V
510Ω
0.1µF
Figure 50. Driving a Differential ADC
Rev. 0 | Page 19 of 24
07035-032
VCM_OUT =
350Ω
07035-011
VDIFF_OUT = VOUT+ − VOUT− = Gain × (VIN+ − VIN−)
0.1µF
AD8228
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.80
0.60
0.40
8°
0°
0.23
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 51. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 52. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. 0 | Page 20 of 24
012407-A
4.00 (0.1574)
3.80 (0.1497)
AD8228
ORDERING GUIDE
Model
AD8228ARMZ 1
AD8228ARMZ-RL1
AD8228ARMZ-R71
AD8228ARZ1
AD8228ARZ-RL1
AD8228ARZ-R71
AD8228BRMZ1
AD8228BRMZ-RL1
AD8228BRMZ-R71
AD8228BRZ1
AD8228BRZ-RL1
AD8228ARZ-R71
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
Z = RoHS Compliant Part.
Rev. 0 | Page 21 of 24
PackageOption
RM-8
RM-8
RM-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
Branding
Y16
Y16
Y16
Y1M
Y1M
Y1M
AD8228
NOTES
Rev. 0 | Page 22 of 24
AD8228
NOTES
Rev. 0 | Page 23 of 24
AD8228
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07035-0-7/08(0)
Rev. 0 | Page 24 of 24