FEDL2280XFULL-04 Issue Date: Nov.16, 2009 ML22808/ML22804/ML22802-XXX ML22P808/ML22P804/ML22P802 LAPIS Semiconductor ADPCM Algorithm-Based Speech Synthesis LSI GENERAL DESCRIPTION The ML22808/ML22804/ML22802-xxx are speech synthesis LSI devices that have P2ROM for storing voice data. The voice output component has an ADPCM2 decoder to enable high speech quality, a D/A converter, and a low-pass filter. It is easy to configure a speech synthesizer by connecting a power amplifier and a CPU externally. The ML22808/ML22804/ML22802-xxx allow selection of a playback method from among the 8-bit PCM, non-linear 8-bit PCM, 16-bit PCM, and 4-bit ADPCM2 algorithms and enable volume control. The ML22808/ML22804/ML22802-xxx, supported by the ROM codes, are the products in which written speech data is included. The ML22P808/ML22P804/ML22P802 are OTP products in which speech data can be easily written by the user using a dedicated writer. These devices are suitable for applications in developing products, manufacturing of a wide variety of products in small quantities, and requiring quick turn around. • Capacity of the internal memory device and the maximum vocal reproduction time (when 4-bit ADPCM2 algorithm used) Product name ROM capacity ML22808-XXX/ML22P808 ML22804-XXX/ML22P804 ML22802-XXX/ML22P802 8 Mbits 4 Mbits 2 Mbits Maximum vocal reproduction time (sec) FSAM = 4.0 kHz FSAM = 8.0 kHz FSAM = 16 kHz 524 262 131 262 131 65 131 65 32 • Speech synthesis method: • • • • • • • • • • • • • An algorithm can be specified for each phrase from among the following: 4-bit ADPCM2 8-bit Nonlinear PCM 8-bit PCM/16-bit PCM Sampling frequency: A fsam value can be specified fro each phrase. 4.0/8.0/16.0 kHz, 5.3/10.7 kHz, 6.4/12.8 kHz Built-in low-pass filter and 12-bit D/A converter CPU command interface: 3-wired serial / clock synchronous Maximum number of phrases: 256 phrases, from 00h to FFh (per bank) Memory bank switching: Enabled between bank 1 and bank 4 using the SEL0 and SEL1 pins Memory bank selecting: Selectable between bank 1 and bank 4 by setting the SEL0 and SEL1 pins (Other than ML22802/ML22P802) Selectable between bank1 and bank 2 (ML22802/ML22P802) Volume control: Can be adjusted in 16 levels or set to OFF Repeat function: LOOP command Source oscillation frequency: 4.096 MHz Power supply voltage: 2.7 to 3.6 V Operating temperature range: -20 to +85°C Package: 30-pin plastic SSOP (SSOP30-P-56-0.65-K) Product name: ML22P808MB, ML22P804MB, ML22P802MB ML22808-xxxMB, ML22804-xxxMB, ML22802-xxxMB (xxx indicates a ROM code number) 1/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX The table below summarizes the differences between the ML2216 and the ML2280X. Item CPU interface Playback method Maximum number of phrases Sampling frequency (kHz) Clock frequency D/A converter Low-pass filter Speaker driving amplifier Edit ROM Volume control Silence insertion Repeat function Interval at which a seam is silent during continuous playback (*1) Memory bank switching Package ML2216 Serial 4-bit ADPCM2 8-bit straight PCM 8-bit non-linear PCM 16-bit straight PCM 256 4.0/5.3/6.4/ 8.0/10.7/12.8 16.0 4.096 MHz (has a crystal oscillator circuit built-in) Current-type 12-bit 3D comb filter Built-in type; 0.3W (at 8Ω, VDD=5V) Yes 16 levels Yes 20 to 1024 ms (4 ms steps) Yes ML2280X Serial 4-bit ADPCM2 8-bit straight PCM 8-bit non-linear PCM 16-bit straight PCM 256 up to 1024 (per bank) 4.0/5.3/6.4/ 8.0/10.7/12.8 16.0 4.096 MHz (has a crystal oscillator circuit built-in) Current-type 12-bit 3D comb filter Yes 16 levels Yes 20 to 1024 ms (4 ms steps) Yes No No No 44-pin QFP Yes 30-pin SSOP No *1: Continuous playback as shown below is possible. 1 phrase 1 phrase No silence interval 2/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX BLOCK DIAGRAM ML22808/ML22804/ML22P808/ML22P804: 19-/20-bit Multiplexer Address Controller 4-/8-Mbit ROM VPP DVDD PVDD DGND PGND Phrase Address Latch 19-/20-bit Address Counter ADPCM Synthesizer CS SCK PCM Synthesizer DI BUSY NCR DIPH SEL0 I/O Interface LPF Timing Controller SEL1 12-bit DAC TEST0 TEST1 RESET OSC TESTO1 TESTO2 XT XT AOUT AV DD AGND 3/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX ML22802/ML22P802: Address Controller 18-bit Multiplexer 2-Mbit ROM VPP DVDD PVDD DGND PGND Phrase Address Latch 18-bit Address Counter ADPCM Synthesizer CS SCK PCM Synthesizer DI BUSY NCR DIPH SEL I/O Interface LPF Timing Controller TEST0 12-bit DAC TEST1 RESET TESTO1 OSC TESTO2 XT XT AOUT AVDD AGND 4/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX PIN CONFIGURATION (TOP VIEW) ML22808/ML22804/ML22P808/ML22P804: XT XT TEST0 TEST1 DGND DIPH SEL0 SEL1 CS SCK DI BUSY NCR RESET NC 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DVDD AVDD AOUT NC AGND VPP PGND TESTO1 PVDD NC NC PGND TESTO0 NC NC NC: No Connection 30-Pin Plastic SSOP 5/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX ML22802/ML22P802: XT XT TEST0 TEST1 DGND DIPH SEL TEST2 CS SCK DI BUSY NCR RESET NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DVDD AVDD AOUT NC AGND VPP PGND TESTO1 PVDD NC NC PGND TESTO0 NC NC NC: No Connection 30-Pin Plastic SSOP 6/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX PIN DESCRIPTION Pin Symbol Type 1 XT I 2 XT O 3 4 5 TEST0 TEST1 DGND I I — 6 DIPH I 7 (SEL) SEL0 I 8 (TEST2) SEL1 I 9 CS I 10 11 SCK DI I I 12 BUSY O 13 NCR O 14 RESET I 18 19,24 TESTO0 PGND O — 22 PVDD — 23 TESTO1 O Description Connects to a crystal or a ceramic resonator. A feedback resistor of around 1 MΩ is built in between this XT pin and XT pin. When using an external clock, input the clock from this pin. If a crystal or a ceramic resonator is used, connect it as close to the LSI as possible. Connects to a crystal or a ceramic resonator. When using an external clock, leave this pin open. If a crystal or a ceramic resonator is used, connect it as close to the LSI as possible Input pin for testing. Tie this pin at a “L” level (DGND level). Input pin for testing. Tie this pin at a “L” level (DGND level). Digital ground pin. Pin for choosing between rising edges and falling edges as to the edges of the SCK pulses used for shifting serial data input to the DI pin into the inside of the LSI. When this pin is at a “L” level, DI input data is shifted into the LSI on the rising edges of the SCK clock pulses; when this pin is at a “H” level, DI input data is shifted into the LSI on the falling edges of the SCK clock pulses. Memory bank selecting pin. Enabled when memory bank selecting is specified at the time the PUP1 or PUP2 command is input. Do not change during speech playback (when the BUSY pin is at “L”) ML22808/ML22804/ML22P808/ML22P804: Memory bank selecting pin. Enabled when memory bank selecting is specified at the time the PUP1 or PUP2 command is input. Do not change during speech playback (when the BUSY pin is at “L”) ML22802/ML22P802: Input pin for testing. Tie this pin at “L” (DGND level). Chip select input pin. A “L” level on this pin enables the serial interface. Serial clock input pin. Serial data input pin. Pin that outputs a signal that indicates the phrase playback status. If the LSI is playing a phrase, this pin outputs a “L” level. If the LSI is in a standby state, this pin outputs a “H” level. Pin that outputs a signal that indicates whether command input is enabled or disabled. If command input is enabled, this pin outputs a “H” level. If command input is disabled, this pin outputs a “L” level. During a reset input, the entire circuit is stopped and enters a power down state. Upon power-on, input a “L” level to this pin. Put this pin into a “H” level after the power supply voltage is stabilized. Output pin for testing. Leave this pin open. Ground pin for the internal P2ROM. Power supply pin for the internal P2ROM. Connect a capacitor of 0.1 μF or more between this pin and PGND. Output pin for testing. Leave this pin open. 7/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX Pin Symbol Type 25 VPP I 26 28 AGND AOUT — O 29 AVDD — 30 DVDD — Description VPP power supply pin used for writing data to the internal P2ROM. Tie this pin at the DGND level. Analog ground pin. Playback signal output pin. Analog power supply pin. Connect a capacitor of 0.1 μF or more between this pin and PGND. Digital power supply pin. Connect a capacitor of 0.1 μF or more between this pin and PGND. Note: The pin names in the parentheses are applied to ML22802/ML22P802. 8/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX ABSOLUTE MAXIMUM RATINGS Parameter Digital power supply voltage Analog power supply voltage Symbol (DGND = PGND = AGND = 0 V) Rating Unit Condition DVDD, PVDD –0.3 to +5.0 V –0.3 to +5.0 V –0.3 to DVDD+0.3 V 1.3 W Ta = 25°C AVDD Input voltage VIN Power dissipation PD Ta = 25°C When a JEDEC2-layer board is mounted ISC — 10 mA TSTG — –55 to +150 °C Output short-circuit current Storage temperature RECOMMENDED OPERATING CONDITIONS Parameter Digital power supply voltage Analog power supply voltage Operating temperature Master clock frequency External crystal oscillator capacitance (DGND = PGND = AGND = 0 V) Range Unit Symbol Condition DVDD, PVDD — 2.7 to 3.6 V AVDD — 2.7 to 3.6 V TOP — -20 to +85 Typ. Max. °C fOSC — Cd, Cg — Min. 3.5 4.096 4.5 15 30 45 MHz pF 9/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX ELECTRICAL CHARACTERISTICS DC Characteristics Parameter “H” input voltage “L” input voltage “H” output current 1 “H” output current 2 (*1) “L” output current 1 “L” output current 2 (*1) “H” input current 1 “H” input current 2 (*2) “L” input current 1 “L” input current 2 (*2) “H” output leakage current (*3) “L” output leakage current (*3) Supply current during playback Power-down supply current DVDD = PVDD = AVDD = 2.7 to 3.6 V, DGND = PGND = AGND = 0 V, Ta = -20 to +85°C Symbol Condition Min. Typ. Max. Unit 0.86 × VIH — — — V VDD 0.14 × VIL — — — V VDD VOH1 IOH = −1 mA VDD – 0.4 — — V VOH2 IOH = −100 µA VDD – 0.4 — — V VOL1 IOL = 2 mA — — 0.4 V VOL2 IOL = 100 µA — — 0.4 V IIH1 VIH = DVDD — — 10 µA IIH2 VIH = DVDD 0.3 2.0 15 µA IIL1 VIL = DGND –10 — — µA IIL2 VIL = DGND –15 −2.0 –0.3 µA ILOH VIH = DVDD — — 10 µA ILOL VIL = DGND –10 — — µA IDD fOSC = 4.096 MHz No output load — — 10 mA IDDS Ta = -20 to +85°C — 1 20 µA Note: The input voltages and input currents apply to all the input pins except the XT pin. The output voltages apply to all the output pins except the AOUT pin. *1: Applies to the XT pin. *2: Applies to the XT pin. *3: Applies to the TESTO0 and TESTO1 pins. Analog Section Characteristics DVDD = PVDD = AVDD = 2.7 to 3.6 V, DGND = PGND = AGND = 0 V, Ta = -20 to +85°C Parameter Symbol Condition Min. Typ. Max. Unit During silence 5 — — kΩ AOUT output load resistance RLAO playback AOUT output voltage range VAOUT No output load 0.07 × AVDD — 0.64 × AVDD V 10/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX AC Characteristics DVDD = AVDD = 2.7 to 3.6 V, DGND = PGND = AGND = 0 V, Ta = -20 to +85°C Parameter Symbol Condition Min. Typ. Max. Unit Master clock duty cycle fduty — 40 50 60 % RESET input pulse width tRST — 1 — — μs SCK setup time for falling edge of CS tCKS — 200 — — ns SCK hold time for falling edge of CS tCKH — 200 — — ns Data setup time for rising edge of SCK tDIS1 DIPH = “L” 50 — — ns Data hold time for rising edge of SCK tDIH1 DIPH = “L” 50 — — ns Data setup time for rising edge of SCK tDIS2 DIPH = “H” 50 — — ns Data hold time for rising edge of SCK tDIH2 DIPH = “H” 50 — — ns SCK “H” level pulse width tSCKH — 200 — — ns SCK “L” level pulse width tSCKL — 200 — — ns NCR output delay time for rising edge of SCK tDN1 DIPH = “L” — — 150 ns NCR output delay time for falling edge of SCK tDN2 DIPH = “H” — — 150 ns BUSY output delay time for rising edge of SCK tDB1 DIPH = “L” — — 150 ns BUSY output delay time for falling edge of SCK tDB2 DIPH = “H” — — 150 ns SEL0 and SEL1 setup time for falling edge of Memory bank 1 — — μs tSB function used BUSY (*4) SEL0 and SEL1 hold time for falling edge of Memory bank 1 — — μs tBS function used BUSY (*4) fOSC = 4.096 MHz; At STOP, SLOOP, 6 — — μs Command input interval time tINT CLOOP or VOL command input fOSC = 4.096 MHz; During continuous — — 10 ms Command input enable time tcm playback; At SLOOP input “L” level output time of NCR and BUSY at tPUP1 When a 4.096 MHz 1.9 2.0 2.1 ms PUP1 command input external clock is “L” level output time of NCR and BUSY at input tPUP2 65 66 67 ms PUP2 command input “L” level output time of NCR and BUSY at tPD1 — — 6 μs PDWN1 command input fOSC = 4.096 MHz “L” level output time of NCR and BUSY at tPD2 63 64 65 ms PDWN2 command input NCR “L” level output time 1 (*1) tNCR1 fOSC = 4.096 MHz — — 6 μs fOSC = 4.096 MHz; After phrase data — 4.125 4.38 ms NCR “L” level output time 2 (*2) tNCR2 input by the PLAY command BUSY “L” level output time (*3) tBSY fOSC = 4.096 MHz — — 6 μs Note: Output pin load capacitance = 55 pF (Max) *1: Applies to cases where a command is input except after a PUP1, PUP2, PDWN1, PDWN2, SLOOP, or CLOOP command input or except after a phrase data input by the PLAY command. *2: Indicates the time when the sampling frequency of the phrase played last was 4 kHz. For any other sampling frequency, the NCR “L” output time 2 is proportional to that sampling frequency. After reset release, a sampling freuency is set to 4 kHz. 11/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX *3: *4: Applies to when a command is input except after a PUP1, PUP2, PDWN1, PDWN2, SLOOP, or CLOOP command input or except after a phrase data input by the PLAY command, providing no phrase is being played. For ML22802/ML22P802, applied to the SEL pin. 12/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX TIMING DIAGRAMS Serial CPU Interface Timing (When DIPH = “L”) CS VIH VIL tESCK tCSH tSCKH VIH SCK VIL tDIS1 tDIH1 tSCKL VIH DI VIL tDN1 VOH NCR VOL BUSY VOH tDB1 VOL Serial CPU Interface Timing (When DIPH = “H”) CS VIH VIL tESCK tCSH tSCKL VIH SCK VIL tDIS1 tDIH1 tSCKH VIH DI VIL tDN1 VOH NCR VOL BUSY VOH tDB1 VOL 13/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX Power-On Timing VDD VDD tRST RESET VIH Processing reset VIL Power down Status Oscillation is stopped at power-on. Power-Up Timing • PUP1 command input CS SCK DI NCR VOH VOL tPUP1 BUSY VOH VOL Oscillation stopped XT•XT Oscillating 1V AOUT Status GND Power down Oscillation stabilized Awaiting command 14/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX • PUP2 command input CS SCK DI NCR VOH VOL tPUP2 BUSY VOH VOL Oscillation stopped XT•XT Oscillating 1V AOUT GND Power down Status Suppressing pop noise Awaiting command Oscillation stabilized Power-Down Timing • PDWN1 command input CS SCK DI NCR VOH VOL tPD1 BUSY VOH VOL XT•XT Oscillation stopped Oscillating 1V AOUT Status GND Awaiting command Command is being processed Power down 15/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX • PDWN2 command input CS SCK DI NCR VOH VOL tPD2 BUSY XT•XT VOH VOL Oscillation stopped Oscillating 1V AOUT Status GND Pop noise is being suppressed Awaiting command Power down Command is being processed • RESET input RESET tRST BUSY XT•XT Oscillating AOUT Status Note: Oscillation stopped GND Playing Power down The same timing applies in cases where the RESET signal is input during waiting for command. T 16/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX • Playback Timing by the PLAY Command PLAY command st 1 byte PLAY command nd 2 byte CS SCK DI tSB tBS SEL1 SEL0 tNCR1 NCR tNCR2 VOH VOL (*1) tBSY BUSY VOH VOL 1V AOUT Status Command standby Awaiting command Address is being controlled Playing Awaiting command Command is being processed Length of a “L” interval of BUSY is = tNCR2 + voice reproduction time length. Note: • Playback Stop Timing STOP command CS SCK DI tNCR1 NCR VOH VOL BUSY VOH VOL 1V AOUT Status Playing Awaiting command Command is being processed 17/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX • Continuous Playback Timing by the PLAY Command PLAY command 1st byte PLAY command 2nd byte PLAY command 2nd byte CS SCK tcm DI tNCR1 tNCR2 NCR (*1) VOH VOL BUSY 1V AOUT Status Playing phrase 1 Awaiting command Address is being controlled *1: Playing phrase 2 Address is being controlled The “L” level period of the NCR pin during playback varis depending on the timing at which the PLAY command is input. • Silence Insertion Timing by the MUON Command MUON command MUON command 1st byte 2nd byte PLAY command 2nd byte PLAY command PLAY command 1st byte 2nd byte CS SCK tcm DI tNCR2 NCR tNCR1 tNCR1 (*1) VOH (*1) VOL BUSY AOUT Status 1V Awaiting command Playing Silence is being inserted Playing Address is being controlled Waiting for silence insertion to be finished *1: The “L” level period of the NCR pin during playback or silence insertion operation varis depending on the timing at which the MUON command is input. 18/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX • Repeat Playback Set/Release Timing by the SLOOP and CLOOP Commands CS VIH SLOOP command PLAY command 2nd byte VIL CLOOP command tINT SCK DI tcm tNCR2 NCR VOH VOL BUSY 1V AOUT Status Awaiting command Playing Address is being controlled Address is being controlled Playing Awaiting command Command is being processed • Volume Change Timing by the VOL Command VOL command CS SCK DI tNCR1 NCR VOH VOL tBSY BUSY VOH VOL Status Awaiting command Awaiting command Command is being processed 19/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX FUNCTIONAL DESCRIPTION Serial CPU Interface Command data can be input through the DI pin by signals input through the CS and SCK pins. Setting the CS pin to a “L” level enables the serial CPU interface. After the CS pin is set to a “L” level, the command data, which is synchronized with the SCK clock signal, is input through the DI pin from the MSB. The command data input through the DI pin is shifted into the LSI on the rising or falling edges of the SCK clock pulses and the command is executed by the rising or falling edge of the eighth pulse of the SCK clock. Choosing between rising edges and falling edges of the clock pulses input through the SCK pin is determined by the signal input through the DIPH pin: - When the DIPH pin is at a “L” level, the data input through the DI pin is shifted into the LSI on the rising edges of the SCK clock pulses. - When the DIPH pin is at a “H” level, the data input through the DI pin is shifted into the LSI on the falling edges of the SCK clock pulses. It is possible to input command data in the LSI even by holding the CS pin continuously at a “L” level. However, if unexpected pulses caused by noise are induced through the SCK pin, SCK clock pulses are incorrectly counted. As a result, command data cannot be input correctly. Setting the CS pin to a “H” level returns the count of the SCK clock pulses to the initial state. Command and Data Input Timings • SCK rising edge operation (when DIPH pin = “L” level) CS SCK D7 DI D6 D5 D4 D3 D2 D1 (MSB) D0 (LSB) CS SCK DI D7 D6 D5 D4 D3 D2 D1 (MSB) D0 (LSB) • SCK falling edge operation (when DIPH pin = “H” level) CS SCK D7 DI D6 D5 D4 D3 D2 D1 (MSB) D0 (LSB) CS SCK DI D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) 20/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX Command List Each command is configured in 1-byte (8-bit) units. command by two bytes each. Each of the PLAY and MUON command forms one Command D7 D6 D5 D4 D3 D2 D1 D0 PUP1 0 0 0 0 ⎯ ⎯ S1 S0 PUP2 0 0 0 1 ⎯ ⎯ S1 S0 PDWN1 0 0 1 0 ⎯ ⎯ ⎯ ⎯ PDWN2 0 0 1 1 ⎯ ⎯ ⎯ ⎯ 0 1 0 0 ⎯ ⎯ ⎯ ⎯ F7 F6 F5 F4 F3 F2 F1 F0 0 1 1 0 ⎯ ⎯ ⎯ ⎯ 0 1 1 1 ⎯ ⎯ ⎯ ⎯ M7 M6 M5 M4 M3 M2 M1 M0 SLOOP 1 0 0 0 ⎯ ⎯ ⎯ ⎯ CLOOP 1 0 0 1 ⎯ ⎯ ⎯ ⎯ VOL 1 0 1 0 V3 V2 V1 V0 PLAY STOP MUON S1, S0 F7–F0 M7–M0 V3–V0 Description Instantly shifts the device currently powered down to a command wait state. Suppresses pop noise and shifts the device currently powered down to a command wait state. Instantly shifts the device from a command wait state to a power down state. Suppresses pop noise and shifts the device from a command wait state to a power down state. Phrase-specified playback start command. Use the data of the 2nd byte to specify a phrase number. Playback stop command. Inserts silence. Use the data of the 2nd byte to specify the length of silence. Command for setting the repeat playback mode. Enabled during playback. Command for releasing the repeat playback mode. If the STOP command is input, repeat playback mode is released automatically. Volume setting command. : Number of memory banks (*) : Phrase address : Length of silence period : Sound volume * S0 is fixed to “0” for ML22802/ML22P802. 21/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX Power Down Function This LSI has the power down function. When in a power down state, all the circuits including the oscillator circuit stop operating, thus minimizing the supply current. When supplying an external clock to the XT pin, tie the pin at a “L” level during power down. The figure below shows a equivalent circuit to an oscillator circuit. Power down signal Master clock inside the LSI (During power down = “L”) approx. 1 MΩ XT XT The Initial Status at Reset Input and the Status at Power Down of Output Pins The status of relative output pins at reset input and power down is shown below. Digital output pin State NCR BUSY “H” level “H” level Analog output pin State AOUT GND level Voice Synthesis Algorithm The ML22804/ML22808-xxx contain four algorithm types to match the characteristic of playback voice: 4-bit ADPCM2 algorithm, 8-bit straight ADPCM2 algorithm, 8-bit non-linear PCM algorithm, and 16-bit straight PCM algorithm. Key feature of each algorithm is described in the table below. Voice synthesis algorithm Applied waveform 4-bit ADPCM2 Normal voice waveform 8-bit Nonlinear PCM High-frequency components inclusive sound effect etc. 8-bit PCM 16-bit PCM Feature LAPIS Semiconductor ’s specific speech synthesis algorithm of improved waveform follow-up with improved 4-bit ADPCM. Algorithm, which plays back mid-range of waveform as 10-bit equivalent voice quality. Normal 8-bit PCM algorithm Normal 16-bit PCM algorithm 22/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX Memory Allocation and Creating Voice Data The ROM is partitioned into four data areas: voice (i.e., phrase) control area, test area, voice area, and edit ROM area. The voice control area manages the ROM’s voice data. It contains data for controlling the start/stop addresses of voice data for 256 phrases, use/non-use of the edit ROM function and so on. The test area contains data for testing. The voice area contains actual waveform data. The edit ROM area contains data for effective use of voice data. For the details, refer to the section of “Edit ROM Function.” No edit ROM area is available unless the edit ROM is used. The ROM data is created using a dedicated tool. ROM address (ML22808/ML22804/ML22802-XXX, ML22P808/ML22P804/ML22P802) 0x00000 Voice control area (Fixed16 Kbits) 0x007FF 0x00800 0x00807 0x00808 Test area Voice area Max: 0xFFFFF Max: 0xFFFFF Edit ROM area Depends on creation of ROM data. Playback Time and Memory Capacity The playback time depends upon the memory capacity, sampling frequency, and playback method. The equation showing the relationship is given below. The equation below gives the playback time when the edit ROM function is not used. (Bit length is 2 bits for 2-bit ADPCM2; 4 bits for 4-bit ADPCM2; 8 bits for PCM.) Example : Let the sampling frequency be 16 kHz and 4-bit ADPCM2 algorithm. approx. 65 seconds, as shown below. Playback time = 1.024 × (4096 – 16) (Kbit) 16 (kHz) × 4 (bit) Then the playback time is ≅ 65 (sec) 23/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX Edit ROM Function The edit ROM function makes it possible to play back multiple phrases in succession. The following functions are set using the edit ROM function: • Continuous playback: There is no limit to the number of times a continuous playback can be specified. It depends on the memory capacity only. 20 to 1024 ms • Silence insertion function: Using the edit ROM function enables an effective use of the memory capacity of voice ROM. Below is an example of the ROM configuration in the case of using the edit ROM function. Example 1: Phrases Using the Edit ROM Function Phrase 1 A B D Phrase 2 A C D Phrase 3 E B D Phrase 4 E C D Phrase 5 A B D Silence E C Example 2: Example of ROM Data Where Contents of Example 1 Are Stored in ROM Address control area A B C D E F Editing area 24/41 D FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX Memory Bank Selecting Function Using the memory bank selecting function, the internal ROM area in the ML22808/ML22804/ML22P808/ ML22P804 can be divided into up to four areas. If four banks are used, up to 1024 phrases can be played back since each bank is capable of up to 256 phrases. Using the memory bank selecting function, the internal ROM area in the MLl22802/ML22P802 can be divided into up to two areas. If two banks are used, up to 512 phrases can be played back because each bank is capable of up to 256 phrases. Using this function, it is possible to put together multiple ROM codes into one code. In the case of the ML22808/ML22804/ML22P808/ML22P804, the memory is used by setting the SEL1 and SEL0 pins and in the case of the ML22802/ML22P802, the memory is used by setting the SEL pin, as shown in the tables below. In addition, when playing phrases, it is necessary to specify the number of memory banks by PUP1 or PUP2. “⎯“ in the tables below means Don’t Care, whether 0 or 1. Note that, if the memory bank selecting fnction is used, it is necessary to divide data when ROM data is created and store the divided data in the specified area in advance. For one memory banks: SEL1 ⎯ SEL0 ⎯ ML22P808/ML22808-XXX 00000h -FFFFFh ML22P804/ML22804-XXX 00000h – 7FFFFh SEL ⎯ ML22P802/ML22802-XXX 00000h – 3FFFFh ML22P804/ML22804-XXX 00000h – 3FFFFh 40000h – 7FFFFh SEL 0 1 ML22P802/ML22802-XXX 00000h – 1FFFFh 20000h – 3FFFFh For two memory banks: SEL1 ⎯ ⎯ SEL0 0 1 ML22P808/ML22808-XXX 00000h – 7FFFFh 80000h – FFFFFh For four memory banks: SEL1 0 0 1 1 SEL0 0 1 0 1 ML22P808/ML22808-XXX 00000h–3FFFFh 40000h–7FFFFh 80000h–BFFFFh C0000h–FFFFFh ML22P804/ML22804-XXX 00000h–1FFFFh 20000h–3FFFFh 40000h–5FFFFh 60000h–7FFFFh Shown below is an example of memory division for the M22808 (8 Mbits). 0–3FFFFh Bank 1 Capacity: 8 Mbits Max. number of phrases: 256 Bank 1 Capacity: 4 Mbits Max. number of phrases: 256 40000–7FFFFh Bank 2 Capacity: 4 Mbits Max. number of phrases: 256 80000–BFFFFh C0000–FFFFFh Number of memory divisions: 1 8-Mbit × 1 area Bank 1 Capacity: 2 Mbits Max. number of phrases: 256 Bank 2 Capacity: 2 Mbits Max. number of phrases: 256 Bank 3 Capacity: 2 Mbits Max. number of phrases: 256 Bank 4 Capacity: 2 Mbits Max. number of phrases: 256 Number of memory divisions: 2 Number of memory divisions: 4 4-Mbit × 2 areas 2-Mbit × 4 areas 25/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX Command Function Descriptions 1. PUP1 command • command 0 0 0 0 ⎯ ⎯ S1 S0 PUP1 command is used to shift the ML22804/ML22808-xxx from power down state to the command standby state. In the power down state, any command input other than PUP1 and PUP2 will be ignored. The ML22804/ML22808-xxx enters the power down state in any of the following conditions: 1) When power is turned on 2) At RESET input 3) When both NCR and BUSY go to a “H” level after inputting the power down command. The relationship between S1/S0 and the memory bank is as follows. S1 S0 0 0 0 1 1 0 1 1 ML22808/ML22804/ML22P808/ML22P804 Uses the entire space of the internal memory as one area. Divides the internal memory into two areas to select the memory areas with the SEL0 pin. Divides the internal memory into four areas to select the memory areas with the SEL0 and SEL1 pins. Setting prohibited ML22802/ML22P802 Uses the entire space of the internal memory. Setting prohibited (fix S0 to “0”) Divides the internal memory into two areas to select the memory areas with the SEL pin. Setting prohibited (Fix S0 to “0”.) CS SCK DI NCR BUSY XT•XT Oscillation stopped Oscillating 1V AOUT Status GND Power down Oscillation stabilized Awaiting command The oscillation starts when the PUP1 command is input and, after an elapse of about 2 ms oscillation stabilization time, the AOUT output abruptly changes from GND level to approx. 1 V level. Therefore, this abrupt change in AOUT output will cause generation of pop noise if the AOUT output is not processed outside. To suppress pop noise, input the PUP2 command. Any command that is input during oscillation stabilization will be ignored. However, if a “L” level is input to the RESET pin, the device enters the power down state immediately. 26/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX 2. PUP2 command • command 0 0 0 1 ⎯ ⎯ S1 S0 PUP2 command is used to shift the ML22804/ML22808-xxx from the power down state to the command standby state. In the power down state, any command input other than PUP1 and PUP2 will be ignored. The ML22804/ML22808-xxx enters the power down state in any of the following conditions: 1) When power is turned on 2) At RESET input 3) When both NCR and BUSY go to a “H” level after inputting the power down command. The relationship between S1/S0 and the memory bank is as follows. S1 0 S0 0 0 1 1 0 1 1 ML22808/ML22804/ML22P808/ML22P804 Uses the entire space of the internal memory. Divides the internal memory into two areas to switch the memory areas with the SEL0 pin. Divides the internal memory into four areas to switch the memory areas with the SEL0 and SEL1 pins. Setting prohibited (Operation is the same as above.) ML22802/ML22P802 Uses the entire space of the internal memory. Setting prohibited (fix S0 to “0”) Divides the internal memory into two areas to select the memory areas with the SEL pin. Setting prohibited (Fix S0 to “0”.) CS SCK DI NCR BUSY Oscillation stopped XT•XT Oscillating 1V AOUT Status GND Power down Pop noise is being suppressed Awaiting command Oscillation stabilized The oscillation starts when the PUP2 command is input and, after an elapse of about 2 ms oscillation stabilization time, the AOUT output gradually changes from GND level to approx. 1 V level in about 64 ms. Any command that is input during oscillation stabilization will be ignored. However, if a “L” level is input to the RESET pin, the device enters the power down state immediately. T 27/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX 3. PDWN1 command • command 0 0 1 0 ⎯ ⎯ ⎯ ⎯ The PDWN1 command is used to shift the ML22804/ML22808-xxx from a command wait state (both NCR and BUSY are “H”) to a power down state. However, this command is disabled during playback. To resume playback after the ML22804/ML22808-xxx has shifted to the power down state, first input the PUP1 or PUP2 command and then input the PLAY command. CS SCK DI NCR BUSY XT•XT Oscillation stopped Oscillating 1V AOUT Status GND Awaiting command Command is being processed Power down After the PDWN1 command is input and after an elapse of command processing time, the oscillation stops and the AOUT output abruptly changes from approx. 1 V level to GND level. This abrupt change in the AOUT output will cause generation of pop noise if the AOUT output is not processed outside. To suppress pop noise, input the PDWN2 command. 28/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX 4. PDWN2 command • command 0 0 1 1 ⎯ ⎯ ⎯ ⎯ The PDWN2 command is used to shift the ML22804/ML22808-xxx from a command wait state (both NCR and BUSY are “H”) to a power down state. However, this command is disabled during playback. To resume playback after the ML22804/ML22808-xxx has shifted to the power down state, first input the PUP1 or PUP2 command and then input the PLAY command. CS SCK DI NCR BUSY XT•XT Oscillation stopped Oscillating 1V AOUT Status GND Awaiting command Pop noise is being suppressed Power down Command is being processed After the PDWN1 command is input and after an elapse of command processing time, the oscillation stops and the AOUT output gradually changes from approx. 1 V level to GND level in about 64 ms. Any command that is input while pop noise is being suppressed will be ignored. However, if a “L” level is input to the RESET pin, the device enters the power down state immediately. 29/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX 5. PLAY command • command 0 F7 1 F6 0 F5 0 F4 ⎯ F3 ⎯ F2 ⎯ F1 ⎯ F0 1st byte 2nd byte The PLAY command is a 2-byte command. Set the playback phrase using the second byte of this command. The PLAY command can be input when the NCR signal is at a “H” level. Since it is possible to specify the playback phrase (F7 to F0) at the time of creating the ROM that stores voice data, set the phrase that was set when the ROM was created. Figure below shows the timing of phrase (F7 to F0 = 01H) playback. PLAY command st 1 byte PLAY command nd 2 byte CS SCK DI NCR BUSY AOUT Status 1V Awaiting command Awaiting command Address is being controlled Playing Awaiting command Command is being processed When the 1st byte of the PLAY command is input, the device enters a state in which it waits for the 2nd byte to be input after the elapse of the command processing time. When the 2nd byte of PLAY command is input, after an elapse of the command processing time, the device starts reading from the ROM the address information of the phrase to be played. Thereafter, playback operation starts, the playback is performed up to the specified ROM address, and then the playback ends automatically. The NCR1 signal is at a “L” level during address control, and goes “H” when the address control is finished and playback is started. When this NCR signal goes “H”, then it is possible to input the PLAY command for the next playback phrase. During address control, the BUSY signal is at a “L” level during playback and goes “H” when playback is finished. Whether the playback is going on can be known by the BUSY signal. Time Required for Address Control The time required for controlling the address of the playback phrase after input of the PLAY command is the time of 16 to 17 periods of the sampling frequency of the the phrase that was played last. After power is turned on or after RESET is input, it is the time of 16 to 17 periods of 4 kHz sampling frequency. 30/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX PLAY Command Input Timing for Continuous Playback The diagram below shows the PLAY command input timing in cases where one phrase is played and then the next phrase is played in succession. PLAY command 2nd byte PLAY command PLAY command 1st byte 2nd byte CS SCK tcm DI NCR BUSY AOUT Status 1V Awaiting command Address is being controlled Playing phrase 1 Waiting for address control Playing phrase 2 Address is being controlled As shown in the diagram above, if continuous playback is carried out, input the PLAY command for the second phrase within 10 ms (tcm) after NCR goes “H”. This will make it possible to start playing the second phrase immediately after the playback of the first phrase finishes. Phrases can thus be played back continuously without inserting silence between phrases. 31/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX 6. STOP command • command 0 1 1 0 ⎯ ⎯ ⎯ ⎯ The STOP command is used to stop playback. When speech synthesis processing stops, the AOUT output becomes 1/4VDD and the NCR and BUSY signals go “H”. Although it is possible to input the STOP command regardless of the status of NCR during playback, a prescribed command interval time needs taking. Note that STOP command input during power down, shifting to power up, and shifting to power down will be ignored. STOP command CS SCK DI NCR BUSY 1V AOUT Status Playing Awaiting command Command is being processed Because the AOUT output abruptly changes to approx. 1 V level after the STOP command is input, pop noise may be generated. To prevent pop noise, input the STOP command after gradually decreasing the volume by the VOL command. 32/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX 7. MUON command • command 0 M7 1 M6 1 M5 1 M4 ⎯ M3 ⎯ M2 ⎯ M1 ⎯ M0 1st byte 2nd byte The MUON command is a 2-byte command. This command is used to insert silence between the two playback phrases. The MUON command is enabled when the NCR signal is at a “H” level. Set the silence time length using the second byte of this command. As the silence length (M7 to M0), a value between 4 ms and 1024 ms can be set in 4 ms intervals (252 steps in total). The equation to set the silence time length is shown below. The silence length (M7-M0) must be set to 04h or higher. tmu = (27×(M7) + 26×(M6) + 25×(M5) + 24×(M4) + 23×(M3) + 22×(M2) + 21×(M1) + 20×(M0) + 1) × 4ms The timing diagram shown below is a case of inserting a silence of 20 ms between the repetitions of a phrase of (F7–F0) = 01h. PLAY command 2nd byte MUON command 1st byte MUON command 2nd byte PLAY command PLAY command st nd 1 byte 2 byte CS SCK tcm tcm Playing Silence is being inserted DI NCR BUSY AOUT Status 1V Awaiting command Address is being controlled Waiting for playback to be finished Playing Waiting for silence insertion to be finished When the PLAY command is input, the address control of phrase 1 ends, the phrase playback starts, and the NCR signal goes “H” level. Input the MUON command after this NCR signal changes to the “H” level. After the MUON command input, the NCR signal remains “L” up to the end of phrase 1 playback, and the device enters a state waiting for the phrase 1 playback to end. When the phrase 1 playback finishes, the silence playback starts, and NCR1 signal goes “H” level. After this NCR signal has changed to the “H” level, re-input the PLAY command in order to play phrase 1. After the PLAY command input, the NCR signal once again returns to “L” level and the device enters the state waiting for the end of silence playback. When the silence playback finishes and then the phrase 1 playback starts, the NCR signal goes “H”, and the device enters a state in which it is possible to input the next PLAY or MUON command. The BUSY signal remains “L” until the end of a series of playback. 33/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX 8. SLOOP command • command 1 0 0 0 ⎯ ⎯ ⎯ ⎯ The SLOOP command is used to set repeat playback mode. The CLOOP command is used to release repeat playback mode. Since the SLOOP command is valid only during playback, be sure to input the SLOOP command while the NCR signal is at a “H” level after the PLAY command is input. The NCR signal remains “L” during repeat playback mode. Once repeat playback mode is set, the current phrase is repeatedly played back until the repeat playback setting is released by SLOOP command or until playback is stopped by the STOP command. In the case of a phrase using the edit function, the edited phrase is repeatedly played back. Since repeat playback mode is released when playback is stopped by the STOP command, input the SLOOP command once again if desired to repeat the playback. Following shows the SLOOP command input timing. PLAY command 2nd byte SLOOP command CLOOP command CS SCK DI NCR tcm BUSY AOUT Status 1V Awaiting command Address is being controlled Playing Address is being controlled Playing Awaiting command Command is being processed Effective Range of SLOOP Command Input After the PLAY command is input, input the SLOOP command within 10 ms (tcm) after NCR goes “H”. This will enable the SLOOP command, so that repeat playback will be carried out. 34/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX 9. CLOOP command • command 1 0 0 1 ⎯ ⎯ ⎯ ⎯ The CLOOP command releases repeat playback mode. When repeat playback mode is released, NCR goes “H”. It is possible to input the CLOOP command regardless of the NCR status during playback, but a prescribed command interval needs taking. CLOOP Command Input Timing Depending on the timing of the CLOOP command input during repeat playback, the repeat playback will end either at the end of the currently playing phrase or after one more repetition of the phrase. The repeat playback will end at the currently playing phrase at the CLOOP command input timing shown in the table below. Playback method CLOOP input timing Amount of remaining voice data in the phrase being played 4-bit ADPCM2 8-bit nonlinear/straight PCM 16-bit straight PCM 35 samples or more 18 samples or more 18 samples or more In 4-bit ADPCM2, if the CLOOP command is input 35 or more samples earlier than the time when playback of 1 phrase ends, repeat playback will end with that phrase. If the command is input after the amount of remaining voice data becomes less than 35 samples, playback of the phrase will be repeated once more. 1 phrase 1 phrase 35 samples If the command is input at this timing, playback of the phrase will be repeated once more. In 8-bit nonlinear/straight PCM or 16-bit straight PCM, if the CLOOP command is input 18 or more samples earlier than the time when playback of 1 phrase ends, repeat playback will end with that phrase. If the command is input after the amount of remaining voice data becomes less than 18 samples, playback of the phrase will be repeated once more. 1 phrase 18 samples If the command is input at this timing, playback will end with this phrase. 35/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX 10. VOL command • command 1 0 1 0 V3 V2 V1 V0 The VOL command is used to adjust the playback volume. Although it is possible to input the VOL command regardless of the status of the NCR signal, a prescribed command interval time needs taking. Note that VOL command input during power down, shifting to power up, and shifting to power down will be ignored. The volume can be set in 16 steps, as shown in the table below. The initial value after reset release is set to 0 dB. During power down or at the time of input of the STOP command, the value set by the VOL command will be retained. V3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 V2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 V1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 V0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Volume 0 dB −0.63 dB −1.31 dB −2.05 dB −2.85 dB −3.74 dB −4.73 dB −5.85 dB −7.13 dB −8.64 dB −10.45 dB −12.76 dB −15.92 dB −20.90 dB −33.98 dB OFF 36/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX Power Supply Wiring The power supplies of this LSI are divided into the following three: • Digital power supply (DVDD) • ROM power supply (PVDD) • Analog power supply (AVDD) As shown in the figure below, supply DVDD, PVDD, and AVDD from the same power supply, and separate them into analog and digital power supplies in the wiring. When power supply voltage = 3 V ML22808/ML22804/ML22802-XXX/ ML22P808/ML22P804/ML22P802-XXX DVDD DGND PVDD PGND AVDD AGND 3V 37/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX APPLICATION CIRCUITS • ML22808/ML22804/ML22P808/ML22P804 MCU RESET CS SCK DI NCR BUSY AOUT Speaker amplifier DIPH SEL1 SEL0 TEST0,1 VPP 33pF XT DVDD PVDD AVDD 3.3V 4.096MHz XT 33pF DGND PGND AGND • ML22802/ML22P802 MCU RESET CS SCK DI NCR BUSY AOUT Speaker amplifier DIPH SEL 33pF TEST0,1, 2 VPP DVDD PVDD AVDD XT 4.096MHz XT 33pF 3.3V DGND PGND AGND 38/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX PACKAGE DIMENSIONS (Unit: mm) SSOP30-P-56-0.65-K Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5μm) 0.19 TYP. 5/Dec. 5, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 39/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX REVISION HISTORY Document No. Date FEDL2280XFULL-01 Sep. 29, 2006 FEDL2280XFULL-02 Apr. 09, 2007 FEDL2280XFULL-03 Dec.25.2007 FEDL2280XFULL-04 Nov. 11, 2009 Page Previous Current Edition Edition Description – – Final edition 1 – – Final edition 2 – 1 to 8, 11, 20, 22, 24 to 26, and 36 – 18 – 22 – 41 1,9 to 11, 41 The product names (ML22802 and ML22P808/ ML22P804/ML22P802) have been added. Volume Change Timing by the VOL Channel in the “TIMING DIAGRAMS” Section has been modified. The explanation for POWER down was modified. Operating temperature was expanded. Change the item of “NOTICE” 40/41 FEDL2280XFULL-04 ML22808/ML22804/Ml22802-XXX NOTICE No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from LAPIS Semiconductor upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. 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