ECMF2-0730V12M12 Common mode filter with ESD protection for USB2.0 interface Datasheet - production data VBUS high power TVS diode: – VRM = 13.2 V – IPP (8/20 µs): 70 A Very low PCB space consumption Thin package: 0.55 mm max Lead free package High reduction of parasitic elements through integration Complies with following standards 4)1/ PP[PP Figure 1. Pin configuration (top view) 9%86 9%86 9%86 IEC61000-4-2 level 4: – +/-15 kV (air discharge) – +/-8 kV (contact discharge) Applications *1' Mobile phone, smartphone *1' Phablet *1' , 2 , 2 ,' *1' Tablet Portable devices Description The ECMF2-0730V12M12 is a highly integrated common mode filter designed to suppress EMI/RFI common mode noise on LTE, GSM and GPS band. The device integrates a high power TVS to protect the VBUS line against surge. 9%86SLQDQGPXVWEH FRQQHFWHFWHGWRJHWKHURQWKH3&% Features High common mode attenuation from 0.65 GHz to 3 GHz: – -18 dB at 0.7 GHz – -30 dB at 0.9 GHz – -25 dB at 1.5 GHz – -20 dB at 2.4 GHz – -17 dB at 3 GHz March 2016 This is information on a product in full production. DocID028573 Rev 1 1/14 www.st.com Characteristics 1 ECMF2-0730V12M12 Characteristics Table 1. Absolute maximum rating (Tamb = 25 °C) Symbol VPP Parameter Value Unit I1, I2, O1, O2, ID IEC61000-4-2 contact discharge IEC61000-4-2 air discharge 8 15 kV VBUS IEC61000-4-2 contact discharge IEC61000-4-2 air discharge 30 30 kV Peak pulse voltage IPP Peak pulse current (8/20 µs) 70 A PPP Peak pulse power (8/20 µs) 1500 W IRMS Maximum RMS current 100 mA TOP Operating temperature -40 to +85 °C 125 °C -65 to +150 °C 260 °C Tj Maximum junction temperature Tstg Storage temperature range TL Maximum lead temperature for soldering during 10 s Figure 2. VBUS pins electrical characteristics (definitions) , 6\PERO3DUDPHWHU ,) 9%5 %UHDNGRZQYROWDJH ,50 /HDNDJHFXUUHQW 950 6WDQGRIIYROWDJH 9&/ &ODPSLQJYROWDJH 9) 9&/ 9%5 950 ,50 ,33 3HDNSXOVHFXUUHQW ,) )RUZDUGFXUUHQW 9) )RUZDUGYROWDJH 5' '\QDPLFLPSHGDQFH 2/14 DocID028573 Rev 1 6ORSH 5' ,33 9 ECMF2-0730V12M12 Characteristics Figure 3. I1, I2 and ID pins electrical characteristics (definitions) 6\PERO 3DUDPHWHU 9%5 %UHDNGRZQYROWDJH ,50 /HDNDJHFXUUHQW 950 6WDQGRIIYROWDJH Table 2. Electrical characteristics (Tamb = 25°C) Symbol Test conditions Min. Typ. Max. Unit Data Lines VBR IR = 1 mA IRM VRM = 3 V per line RDC DC serial resistance 5.5 Ω Differential mode cut-off frequency at -3 dB 1.2 GHz Fc 5 V 100 nA ID VBR IR = 1 mA IRM VRM = 3 V 5 V 100 nA VBUS VBR IR = 1 mA 13.5 IRM VRM = 13.2 V 0.1 1 µA VCL IPP = 60 A - 8/20 μs 21 23 V RD 8/20 µs 0.1 DocID028573 Rev 1 V Ω 3/14 14 Characteristics ECMF2-0730V12M12 Figure 4. Differential mode attenuation versus frequency (Z0 diff = 100 Ω) Figure 5. Common mode attenuation versus frequency (Z0 com = 50 Ω) 6'' G% 6&& G% )+] 0 0 0 * )+] 0 0 * 0 Figure 6. Return loss versus frequency (Z0 com = 50 Ω) * Figure 7. Return loss versus frequency (Z0 com = 50 Ω) 6'' G% 6'' G% )+] )+] 0 0 0 0 * * 0 ,2 0 0 0 * * ,2 Figure 8. USB2.0 (480 Mbps) eye diagram without device 4/14 * ,2 ,2 Figure 9. USB2.0 (480 Mbps) eye diagram with device DocID028573 Rev 1 ECMF2-0730V12M12 Characteristics Figure 10. Data lines ESD response to IEC 61000-4-2 (+8 kV contact discharge) 9GLY Figure 11. Data lines ESD response to IEC 61000-4-2 (-8 kV contact discharge) 9GLY 933(6'SHDNYROWDJH 9 &/&ODPSLQJYROWDJHDWQV 9 &/&ODPSLQJYROWDJHDWQV 9 &/&ODPSLQJYROWDJHDWQV 9 9 9 9 9 9 9 9 933(6'SHDNYROWDJH 9&/&ODPSLQJYROWDJHDWQV 9&/&ODPSLQJYROWDJHDWQV 9 &/&ODPSLQJYROWDJHDWQV QVGLY Figure 12. ID ESD response to IEC 61000-4-2 (+8kV contact discharge) QVGLY Figure 13. ID ESD response to IEC 61000-4-2 (-8kV contact discharge) 9GLY 9GLY 933(6'SHDNYROWDJH 9&/&ODPSLQJYROWDJHDWQV 9&/&ODPSLQJYROWDJHDWQV 9 &/&ODPSLQJYROWDJHDWQV 9 9 9 9 9 933(6'SHDNYROWDJH 9 &/&ODPSLQJYROWDJHDWQV 9 &/&ODPSLQJYROWDJHDWQV 9 &/&ODPSLQJYROWDJHDWQV 9 QVGLY Figure 14. VBUS ESD response to IEC 61000-4-2 (+30kV contact discharge) 9GLY 9 QVGLY 9 Figure 15. VBUS ESD response to IEC 61000-4-2 (-30kV contact discharge) 9GLY 933(6'SHDNYROWDJH 9 &/&ODPSLQJYROWDJHDWQV 9 &/&ODPSLQJYROWDJHDWQV 9 &/&ODPSLQJYROWDJHDWQV 9 9 9 9 9 9 P9 9 933(6'SHDNYROWDJH 9&/&ODPSLQJYROWDJHDWQV 9&/&ODPSLQJYROWDJHDWQV 9 &/&ODPSLQJYROWDJHDWQV QVGLY DocID028573 Rev 1 QVGLY 5/14 14 Characteristics ECMF2-0730V12M12 Figure 16. VBUS peak pulse power dissipation versus initial junction temperature (maximum value) Figure 17. VBUS peak pulse power versus exponential pulse duration (maximum value) 333 : 333 : 7MLQLWLDO & V 7M & Figure 18. VBUS peak pulse current versus clamping voltage (maximum value) WS V Figure 19. VBUS leakage current versus junction temperature (typical value) ,5 Q$ ,33 $ V 7MLQLWLDO & 9&/ 9 7M & 6/14 DocID028573 Rev 1 ECMF2-0730V12M12 2 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. µQFN-12L package information Figure 20. µQFN-12L package outline H E DocID028573 Rev 1 / / 7\S $ $ $ ( ' / 2.1 7/14 14 Package information ECMF2-0730V12M12 Table 3. µQFN-12L package mechanical data Dimensions Ref. Inches(1) Millimeters Typ. Min. Max. Typ. Min. Max. A 0.50 0.45 0.55 0.0197 0.0177 0.0217 A1 0.02 0.00 0.05 0.0008 0.0000 0.0020 A3 0.127 b 0.20 0.15 0.25 0.0079 0.0060 0.0099 D 2.60 2.55 2.65 0.0102 0.0100 0.1043 E 1.35 1.30 1.40 0.0531 0.0512 0.0551 e 0.40 L1 0.45 0.35 0.55 0.0177 0.0138 0.0217 L2 0.842 0.742 0.942 0.0331 0.0292 0.0371 L3 0.253 0.153 0.353 0.0099 0.0060 0.0139 0.0050 0.0157 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 21. Footprint Figure 22. Marking 0 Note: The marking codes can be rotated by 90 ° or 180 ° to differentiate assembly location. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose 8/14 DocID028573 Rev 1 ECMF2-0730V12M12 Package information Figure 23. Tape and reel outline 'RWLGHQWLI\LQJ3LQ $ORFDWLRQ $OOGLPHQVLRQVDUHW\SLFDOYDOXHVLQPP 8VHUGLUHFWLRQRIXQUHHOLQJ DocID028573 Rev 1 9/14 14 Recommendation on PCN assembly ECMF2-0730V12M12 3 Recommendation on PCN assembly 3.1 Stencil opening design 3.1.1 General recommendation on stencil opening design 1. Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 24. Stencil opening recommendation / 7 2. : General design rule Stencil thickness (T) = 75 ~ 125 µm $VSHFWUDWLR $VSHFWDUHD 3.1.2 : 7 /[: 7 /: Reference design 1. Stencil opening thickness: 100 µm 2. Stencil opening for leads: opening to footprint ratio is 90%. Figure 25. Recommended stencil window position 10/14 DocID028573 Rev 1 ECMF2-0730V12M12 3.2 3.3 3.4 Recommendation on PCN assembly Solder paste 1. Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004. 2. "No clean" solder paste recommended. 3. Offers a high tack force to resist component displacement during PCB movement. 4. Use solder paste with fine particles: powder particle size 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away DocID028573 Rev 1 11/14 14 Recommendation on PCN assembly 3.5 ECMF2-0730V12M12 Reflow profile Figure 26. ST ECOPACK® recommended soldering profile for PCB mounting & 7HPSHUDWXUH & &V &V VHF PD[ &V &V &V 7LPH V Note: Minimize air convection currents in the reflow oven to avoid component movement. 3.5.1 General advice about reflow conditions: For each individual board, the appropriate heat profile has to be adjusted experimentally. The proposed profiles are just starting points. In every case, the following precautions have to be considered: - Always preheat the device. The purpose of this step is to minimize the rate of temperature rise to less than 2 °C per second in order to minimize thermal shock on the component. - Dry out sections ensure that the solder paste is fully dried before starting reflow step. Also, this step allows the temperature gradient on the board to be evened out. - Peak temperature should be at least 30 °C higher than the melting point of the chosen solder alloy to ensure the reflow quality. In any case the peak temperature should not exceed 260 °C. 12/14 DocID028573 Rev 1 ECMF2-0730V12M12 4 Ordering information Ordering information Figure 27. Ordering information scheme (&0) 9 0 )XQFWLRQ (6'&RPPRQ0RGH)LOWHU 1XPEHURIOLQHV ODQH 5HMHFWLRQUDQJH )URP 0+]WR *+] 9HUVLRQ9 9 9%86VXUJHSURWHFWLRQ,' (6'SURWHFWLRQ 'LIIHUHQWLDOEDQGZLGWK *+] 3DFNDJH 0 4)1/ Table 4. Ordering information 5 Order code Marking Package Weight Base qty. Delivery mode ECMF2-0730V12M12 M4 µQFN-12L 5.3 mg 3000 Tape and reel Revision history Table 5. Document revision history Date Revision 01-Mar-2016 1 Changes Initial release. DocID028573 Rev 1 13/14 14 ECMF2-0730V12M12 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 14/14 DocID028573 Rev 1