STMicroelectronics M48TY-70MH1 3.3v-5v timekeeper controller Datasheet

M48T201Y
M48T201V
5.0 or 3.3V TIMEKEEPER® Supervisor
FEATURES SUMMARY
■
■
■
■
■
■
■
■
■
■
CONVERTS LOW POWER SRAM INTO
NVRAMs
YEAR 2000 COMPLIANT
BATTERY LOW FLAG
INTEGRATED REAL TIME CLOCK, POWERFAIL CONTROL CIRCUIT, BATTERY AND
CRYSTAL
WATCHDOG TIMER
CHOICE OF WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48T201Y: VCC = 4.5 to 5.5V
4.1V ≤ VPFD ≤ 4.5V
– M48T201V: VCC = 3.0 to 3.6V
2.7V ≤ VPFD ≤ 3.0V
MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode.)
PROGRAMMABLE ALARM OUTPUT
ACTIVE IN THE BATTERY BACKED-UP
MODE
PACKAGING INCLUDES A 44-LEAD SOIC
AND SNAPHAT® TOP (to be ordered
separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT® TOP
WHICH CONTAINS THE BATTERY AND
CRYSTAL
September 2004
Figure 1. Package
SNAPHAT (SH)
Crystal/Battery
44
1
SOH44 (MH)
44-pin SOIC
1/33
M48T201Y, M48T201V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2.
Table 1.
Figure 3.
Figure 4.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.......
.......
.......
.......
......
......
......
......
......
......
......
......
.....4
.....4
.....5
.....6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Address Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. GCON Timing When Switching Between RTC and External SRAM . . . . . . . . . . . . . . . . . . 8
Figure 6. READ Cycle Timing: RTC and External RAM Control Signals . . . . . . . . . . . . . . . . . . . . . 9
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. WRITE Cycle Timing: RTC & External RAM Control Signals . . . . . . . . . . . . . . . . . . . . . 11
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Alarm Interrupt Reset Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10.RSTIN1 and RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/33
M48T201Y, M48T201V
Table 9. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. Power Down/Up Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16.SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Outline . . . . . . . . . . . . . . 28
Table 15. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Mechanical Data . . . . . . 28
Figure 17.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 29
Table 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 29
Figure 18.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 30
Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 30
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18. Ordering Information Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 19. SNAPHAT® Battery Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/33
M48T201Y, M48T201V
DESCRIPTION
The M48T201Y/V are self-contained devices that
include a real time clock (RTC), programmable
alarms, a watchdog timer, and a square wave output which provides control of up to 512K x 8 of external low-power static RAM. Access to all RTC
functions and the external RAM is the same as
conventional bytewide SRAM. The 16 TIMEKEEPER® registers offer year, month, date, day,
hour, minute, second, calibration, alarm, century,
watchdog, and square wave output data. Externally attached static RAMs are controlled by the
M48T201Y/V via the GCON and ECON signals.
The 44-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct connection to a separate SNAPHAT® housing containing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery damage due to the high
temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent
reverse insertion. The SOIC and battery packages
are shipped separately in plastic anti-static tubes
or in Tape & Reel form. For the 44-lead SOIC, the
battery/crystal package (e.g., SNAPHAT) part
number is “M4Txx-BR12SH” (see Table
19., page 31).
Caution: Do not place the SNAPHAT battery/crystal top in conductive foam as this will drain the lithium button-cell battery.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A18
DQ0-DQ7
VCC
19
8
A0-A18
W
M48T201Y
M48T201V
G
RSTIN1
Reset 1 Input
RSTIN2
Reset 2 Input
RST
Reset Output (Open Drain)
WDI
Watchdog Input
IRQ/FT
E
Chip Enable Input
RST
G
Output Enable Input
GCON
W
WRITE Enable Input
ECON
ECON
RAM Chip Enable Output
RAM Enable Output
RSTIN1
SQW
GCON
RSTIN2
VOUT
IRQ/FT
VSS
AI02240
4/33
Data Inputs / Outputs
DQ0-DQ7
WDI
E
Address Inputs
Interrupt / Frequency Test Output
(Open Drain)
SQW
Square Wave Output
VOUT
Supply Voltage Output
VCC
Supply Voltage
VSS
Ground
NC
Not Connected Internally
M48T201Y, M48T201V
Figure 3. SOIC Connections
RSTIN1
RSTIN2
RST
NC
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
WDI
GCON
DQ0
DQ1
DQ2
VSS
44
1
2
43
42
3
41
4
5
40
6
39
7
38
8
37
9
36
10
35
11
34
M48T201Y
12 M48T201V 33
13
32
14
31
15
30
16
29
28
17
27
18
26
19
25
20
24
21
22
23
VCC
VOUT
SQW
IRQ/FT
A17
A15
A13
A8
A9
A11
G
W
NC
A10
E
ECON
DQ7
DQ6
DQ5
DQ4
DQ3
NC
AI02241
5/33
M48T201Y, M48T201V
Figure 4. Hardware Hookup
A0-Axx
A0-A18
32,768 Hz
CRYSTAL
VOUT
VCC
0.1µF
5V
LITHIUM
CELL
E2(1)
M48T201Y/V
VCC
0.1µF
CMOS
SRAM
E
ECON
W
W
G
WDI
GCON
RSTIN1
RST
RSTIN2
IRQ/FT
VSS
E
SQW
DQ0-DQ7
G
VSS
DQ0-DQ7
AI00604
Note: 1. If the second chip enable pin (E2) is unused, it should be tied to VOUT.
6/33
M48T201Y, M48T201V
OPERATION
Automatic backup and write protection for an external SRAM is provided through VOUT, ECON, and
GCON pins. (Users are urged to insure that voltage
specifications, for both the SUPERVISOR chip
and external SRAM chosen, are similar.) The
SNAPHAT® containing the lithium energy source
is used to retain the RTC and RAM data in the absence of VCC power through the VOUT pin. The
chip enable output to RAM (ECON) and the output
enable output to RAM (GCON) are controlled during power transients to prevent data corruption.
The date is automatically adjusted for months with
less than 31 days and corrects for leap years (valid
until 2100). The internal watchdog timer provides
programmable alarm windows.
The nine clock bytes (7FFFFh-7FFF9h and
7FFF1h) are not the actual clock counters, they
are memory locations consisting of BiPORT™
READ/WRITE memory cells within the static RAM
array. Clock circuitry updates the clock bytes with
current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory
array. Byte 7FFF8h is the clock control register.
This byte controls user access to the clock information and also stores the clock calibration setting.
Byte 7FFF7h contains the watchdog timer setting.
The watchdog timer can generate either a reset or
an interrupt, depending on the state of the Watchdog Steering Bit (WDS). Bytes 7FFF6h-7FFF2h
include bits that, when programmed, provide for
clock alarm functionality. Alarms are activated
when the register content matches the month,
date, hours, minutes, and seconds of the clock
registers. Byte 7FFF1h contains century information. Byte 7FFF0h contains additional flag information pertaining to the watchdog timer, the alarm
condition, the battery status and square wave output operation. 4 bits are included within this register (RS0-RS3) that are used to program the
Square Wave Output Frequency (see Table
7., page 18). The M48T201Y/V also has its own
Power-Fail Detect circuit. This control circuitry
constantly monitors the supply voltage for an out
of tolerance condition. When VCC is out of tolerance, the circuit write protects the TIMEKEEPER ®
register data and external SRAM, providing data
security in the midst of unpredictable system operation. As VCC falls below the Battery Back-up
Switchover Voltage (VSO), the control circuitry automatically switches to the battery, maintaining
data and clock operation until valid power is restored.
Address Decoding
The M48T201Y/V accommodates 19 address
lines (A0-A18) which allow direct connection of up
to 512K bytes of static RAM. Regardless of SRAM
density used, timekeeping, watchdog, alarm, century, flag, and control registers are located in the
upper RAM locations. All TIMEKEEPER registers
reside in the upper RAM locations without conflict
by inhibiting the GCON (output enable RAM) signal
during clock access. The RAM's physical locations
are transparent to the user and the memory map
looks continuous from the first clock address to the
upper most attached RAM addresses.
Table 2. Operating Modes
Mode
VCC
Deselect
WRITE
READ
4.5V to 5.5V
or
3.0V to 3.6V
READ
E
G
W
DQ7-DQ0
Power
VIH
X
X
High-Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High-Z
Active
Deselect
VSO to VPFD (min)(1)
X
X
X
High-Z
CMOS Standby
Deselect
≤ VSO(1)
X
X
X
High-Z
Battery Back-Up
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage
1. See Table 14., page 27 for details.
7/33
M48T201Y, M48T201V
READ Mode
The M48T201Y/V executes a READ Cycle whenever W (WRITE Enable) is high and E (Chip Enable) is low. The unique address specified by the
address inputs (A0-A18) defines which one of the
on-chip TIMEKEEPER® registers or external
SRAM locations is to be accessed. When the address presented to the M48T201Y/V is in the
range of 7FFFFh-7FFF0h, one of the on-board
TIMEKEEPER registers is accessed and valid
data will be available to the eight data output drivers within tAVQV after the address input signal is
stable, providing that the E and G access times
are also satisfied. If they are not, then data access
must be measured from the latter occurring signal
(E or G) and the limiting parameter is either tELQV
for E or tGLQV for G rather than the address access
time. When one of the on-chip TIMEKEEPER registers is selected for READ, the GCON signal will
remain inactive throughout the READ Cycle.
When the address value presented to the
M48T201Y/V is outside the range of TIMEKEEPER registers, an external SRAM location will be
selected. In this case the G signal will be passed
to the GCON pin, with the specified delay times of
tAOEL or tOERL.
Figure 5. GCON Timing When Switching Between RTC and External SRAM
ADDRESS
7FFF0h - 7FFFFh
RTC
00000h - 7FFEFh
7FFF0h - 7FFFFh
External SRAM
RTC
00000h - 7FFEFh
External SRAM
G
GCON
tAOEL
tAOEH
tOERL
tRO
E
AI02333
8/33
M48T201Y, M48T201V
Figure 6. READ Cycle Timing: RTC and External RAM Control Signals
READ
tAVAV
READ
WRITE
tAVAV
tAVAV
ADDRESS
tELQV
tAVQV
tAVWL
tWHAX
E
tELQX
tGLQV
G
tRO
GCON
ECON
tEPD
W
tWLWH
tGLQX
tAXQX
tGHQZ
DQ0-DQ7
DATA OUT
VALID
DATA OUT
VALID
DATA IN
VALID
AI02334
9/33
M48T201Y, M48T201V
Table 3. READ Mode AC Characteristics
Symbol
M48T201Y
M48T201V
–70
–85
(1)
Parameter
Min
Max
Min
Unit
Max
tAVAV
READ Cycle Time
tAVQV
Address Valid to Output Valid
70
85
ns
tELQV
Chip Enable Low to Output Valid
70
85
ns
tGLQV
Output Enable Low to Output Valid
25
35
ns
70
85
ns
tELQX(2)
Chip Enable Low to Output Transition
5
5
ns
tGLQX(2)
Output Enable Low to Output Transition
0
0
ns
tEHQZ(2)
Chip Enable High to Output Hi-Z
20
25
ns
tGHQZ(2)
Output Enable High to Output Hi-Z
20
25
ns
tAXQX
Address Transition to Output Transition
tAOEL
External SRAM Address to GCON Low
20
30
ns
tAOEH
SUPERVISOR SRAM Address to GCON High
20
30
ns
tEPD
E to ECON Low or High
10
15
ns
tOERL
G Low to GCON Low
15
20
ns
tRO
G High to GCON High
10
15
ns
5
5
ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF.
10/33
M48T201Y, M48T201V
WRITE Mode
The M48T201Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are low
state after the address inputs are stable. The start
of a WRITE is referenced from the latter occurring
falling edge of W or E. A WRITE is terminated by
the earlier rising edge of W or E. The addresses
must be held valid throughout the cycle. E or W
must return high for a minimum of tEHAX from Chip
Enable or tWHAX from WRITE Enable prior to the
initiation of another READ or WRITE Cycle. Datain must be valid tDVWH prior to the end of WRITE
and remain valid for tWHDX afterward. G should be
kept high during WRITE Cycles to avoid bus con-
tention; although, if the output bus has been activated by a low on E and G a low on W will disable
the outputs tWLQZ after W falls.
When the address value presented to the
M48T201Y/V during the WRITE is in the range of
7FFFFh-7FFF0h, one of the on-board TIMEKEEPER® registers will be selected and data will
be written into the device. When the address value
presented to M48T201Y/V is outside the range of
TIMEKEEPER registers, an external SRAM location is selected.
Figure 7. WRITE Cycle Timing: RTC & External RAM Control Signals
WRITE
WRITE
READ
tAVAV
tAVAV
tAVAV
ADDRESS
tAVEH
tAVEL
tAVWH
tELEH
tEHAX
tWHAX
tAVQV
E
tEPD
ECON
tEPD
tGLQV
G
tEHDX
tRO
GCON
tAVWL
tWLWH
tWHQX
tWLQZ
W
tEHQZ
DQ0-DQ7
DATA OUT
VALID
tDVEH
DATA IN
VALID
tDVWH
tWHDX
DATA IN
VALID
DATA OUT
VALID
AI02336
11/33
M48T201Y, M48T201V
Table 4. WRITE Mode AC Characteristics
Symbol
M48T201Y
M48T201V
–70
–85
(1)
Parameter
Min
Max
Min
Unit
Max
tAVAV
WRITE Cycle Time
70
85
ns
tAVWL
Address Valid to WRITE Enable Low
0
0
ns
tAVEL
Address Valid to Chip Enable Low
0
0
ns
tWLWH
WRITE Enable Pulse Width
45
55
ns
tELEH
Chip Enable Low to Chip Enable High
50
60
ns
tWHAX
WRITE Enable High to Address Transition
0
0
ns
tEHAX
Chip Enable High to Address Transition
0
0
ns
tDVWH
Input Valid to WRITE Enable High
25
30
ns
tDVEH
Input Valid to Chip Enable High
25
30
ns
tWHDX
WRITE Enable High to Input Transition
0
0
ns
tEHDX
Chip Enable High to Input Transition
0
0
ns
tWLQZ(2,3)
WRITE Enable Low to Output High-Z
tAVWH
Address Valid to WRITE Enable High
55
65
ns
tAVEH
Address Valid to Chip Enable High
55
65
ns
WRITE Enable High to Output Transition
5
5
ns
tWHQX(2,3)
20
25
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
12/33
ns
M48T201Y, M48T201V
Data Retention Mode
With valid VCC applied, the M48T201Y/V can be
accessed as described above with READ or
WRITE cycles. Should the supply voltage decay,
the M48T201Y/V will automatically deselect, write
protecting itself (and any external SRAM) when
VCC falls between VPFD (max) and VPFD (min).
This is accomplished by internally inhibiting access to the clock registers via the E signal. At this
time, the Reset pin (RST) is driven active and will
remain active until VCC returns to nominal levels.
External RAM access is inhibited in a similar manner by forcing ECON to a high level. This level is
within 0.2V of the VBAT. ECON will remain at this
level as long as VCC remains at an out-of-tolerance condition. When VCC falls below the level of
the battery (VBAT), power input is switched from
the VCC pin to the SNAPHAT® battery and the
clock registers are maintained from the attached
battery supply. External RAM is also powered by
the SNAPHAT battery. All outputs except GCON,
ECON, RST, IRQ/FT and VOUT, become high impedance. The VOUT pin is capable of supplying
100µA of current to the attached memory with less
than 0.3V drop under this condition. On power up,
when VCC returns to a nominal value, write protection continues for 200ms (max) by inhibiting ECON.
The RST signal also remains active during this
time (see Figure 15., page 27).
Note: Most low power SRAMs on the market today can be used with the M48T201Y/V TIMEKEEPER® SUPERVISOR. There are, however
some criteria which should be used in making the
final choice of an SRAM to use.
The SRAM must be designed in a way where the
chip enable input disables all other inputs to the
SRAM. This allows inputs to the M48T201Y/V and
SRAMs to be “Don't care” once VCC falls below
VPFD (min). The SRAM should also guarantee
data retention down to VCC = 2.0V. The chip enable access time must be sufficient to meet the
system needs with the chip enable (and output enable) output propagation delays included.
13/33
M48T201Y, M48T201V
CLOCK OPERATION
TIMEKEEPER ® Registers
The M48T201Y/V offers 16 internal registers
which contain TIMEKEEPER®, Alarm, Watchdog,
Flag, and Control data (see Table 5., page 15).
These registers are memory locations which contain external (user accessible) and internal copies
of the data (usually referred to as BiPORT™
TIMEKEEPER cells). The external copies are independent of internal functions except that they
are updated periodically by the simultaneous
transfer of the incremented internal copy. TIMEKEEPER and Alarm Registers store data in BCD.
Control, Watchdog and Flags (Bits D0 to D3) Registers store data in Binary Format.
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. The BiPORT TIMEKEEPER
cells in the RAM array are only data registers and
not the actual clock counters, so updating the registers can be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register (7FFF8h). As
long as a '1' remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and time that were
current at the moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in
progress. Updating occurs approximately 1 second after the READ Bit is reset to a '0.'
14/33
Setting the Clock
Bit D7 of the Control Register (7FFF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24-hour BCD
format (see Table 5., page 15).
Resetting the WRITE Bit to a '0' then transfers the
values of all time registers (7FFFFh-7FFF9h,
7FFF1h) to the actual TIMEKEEPER counters and
allows normal operation to resume. After the
WRITE Bit is reset, the next clock update will occur
approximately one second later.
Note: Upon power-up following a power failure,
both the WRITE Bit and the READ Bit will be reset
to '0.'
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is located at Bit D7 within the Seconds Register
(7FFF9h). Setting it to a '1' stops the oscillator.
When reset to a '0,' the M48T201Y/V oscillator
starts within one second.
Note: It is not necessary to set the WRITE Bit
when setting or resetting the FREQUENCY TEST
Bit (FT) or the STOP Bit (ST).
M48T201Y, M48T201V
Table 5. TIMEKEEPER® Register Map
Data
Address
D7
7FFFFh
D6
D5
D4
D3
D2
10 Years
D0
Year
Year
00-99
Month
Month
01-12
Date: Day of Month
Date
01-31
Day
01-07
Hours (24 Hour Format)
Hours
00-23
7FFFEh
0
0
7FFFDh
0
0
7FFFCh
0
FT
7FFFBh
0
0
7FFFAh
0
10 Minutes
Minutes
Minutes
00-59
7FFF9h
ST
10 Seconds
Seconds
Seconds
00-59
7FFF8h
W
R
S
7FFF7h
WDS
BMB4
BMB3
BMB2
7FFF6h
AFE
SQWE
ABE
Al.10M
7FFF5h
RPT4
RPT5
7FFF4h
RPT3
0
7FFF3h
RPT2
7FFF2h
RPT1
7FFF1h
7FFF0h
0
D1
Function/Range
BCD Format
10 M
10 Date
0
0
10 Hours
0
Day
Calibration
BMB1
RB1
RB0
Watchdog
Alarm Month
Al. Month
01-12
Al. 10 Date
Alarm Date
Al. Date
01-31
Al. 10 Hours
Alarm Hours
Al. Hours
00-23
Alarm 10 Minutes
Alarm Minutes
Al. Minutes
00-59
Alarm 10 Seconds
Alarm Seconds
Al. Seconds
00-59
100 Years
Century
00-99
1000 Years
WDF
BMB0
Control
AF
Keys: S = Sign Bit
FT = Frequency Test Bit
R = READ Bit
W = WRITE Bit
ST = Stop Bit
0 = Must be set to '0'
WDS = Watchdog Steering Bit
AF = Alarm Flag
BL = Battery Low Flag
0
BL
RS3
RS2
RS1
RS0
Flags
SQWE = Square Wave Enable Bit
BMB0-BMB4 = Watchdog Multiplier Bits
RB0-RB1 = Watchdog Resolution Bits
AFE = Alarm Flag Enable Flag
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog Flag
RS0-RS3 = SQW Frequency
15/33
M48T201Y, M48T201V
Setting the Alarm Clock
Registers 7FFF6h-7FFF2h contain the alarm settings. The alarm can be configured to go off at a
prescribed time on a specific month, day of month,
hour, minute, or second or repeat every month,
day of month, hour, minute, or second.
It can also be programmed to go off while the
M48T201Y/V is in the battery back-up to serve as
a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 6 shows the possible configurations. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
Note: User must transition address (or toggle chip
enable) to see Flag Bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
tion activates the IRQ/FT pin. To disable alarm,
write ’0’ to the Alarm-Date register and RPT1-5.
The IRQ/FT output is cleared by a READ to the
Flags Register as shown in Figure 8. A subsequent READ of the Flags Register is necessary to
see that the value of the Alarm Flag has been reset to '0.'
The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE Bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T201Y/V was in the deselect mode
during power-up. Figure 9., page 17 illustrates the
back-up mode alarm timing.
Figure 8. Alarm Interrupt Reset Waveforms
ADDRESS 7FFF0h
A0-A18
15ns Min
ACTIVE FLAG BIT
IRQ/FT
HIGH-Z
AI02331
Table 6. Alarm Repeat Modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
1
1
1
1
1
Once per Second
1
1
1
1
0
Once per Minute
1
1
1
0
0
Once per Hour
1
1
0
0
0
Once per Day
1
0
0
0
0
Once per Month
0
0
0
0
0
Once per Year
16/33
M48T201Y, M48T201V
Figure 9. Back-up Mode Alarm Waveforms
tREC
VCC
VPFD (max)
VPFD (min)
VSO
AFE bit/ABE bit
AF bit in Flags Register
IRQ/FT
HIGH-Z
HIGH-Z
AI03520
Watchdog Timer
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address
7FFF7h. Bits BMB4-BMB0 store a binary multiplier
and the two lower order bits RB1-RB0 select the
resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The
amount of time-out is then determined to be the
multiplication of the five-bit multiplier value with the
resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M48T201Y/V sets the WDF
(Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by
reading the Flag Register (Address 7FFF0h).
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a '0', the watchdog will activate the IRQ/FT pin
when timed-out. When WDS is set to a '1,' the
watchdog will output a negative pulse on the RST
pin for tREC. The Watchdog register and the AFE,
SQWE, ABE, and FT Bits will reset to a '0' at the
end of a Watchdog time-out when the WDS Bit is
set to a '1.'
The watchdog timer can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or
2. the microprocessor can perform a WRITE of
the Watchdog Register.
The time-out period then starts over. The WDI pin
should be tied to VSS if not used. The watchdog
will be reset on each transition (edge) seen by the
WDI pin.
In order to perform a software reset of the watchdog timer, the original time-out period can be written into the Watchdog Register, effectively
restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
7FFF0h).
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied.
Note: The user must transition the address (or
toggle chip enable) to see the Flag Bit change.
17/33
M48T201Y, M48T201V
Square Wave Output
The M48T201Y/V offers the user a programmable
square wave function which is output on the SQW
pin. RS3-RS0 Bits located in 7FFF0h establish the
square wave output frequency. These frequencies
are listed in Table 7. Once the selection of the
SQW frequency has been completed, the SQW
pin can be turned on and off under software control with the Square Wave Enable Bit (SQWE) located in Register 7FFF6h.
Table 7. Square Wave Output Frequency
Square Wave Bits
18/33
Square Wave
RS3
RS2
RS1
RS0
Frequency
Units
0
0
0
0
Hi-Z
-
0
0
0
1
32.768
kHz
0
0
1
0
8.192
kHz
0
0
1
1
4.096
kHz
0
1
0
0
2.048
kHz
0
1
0
1
1.024
kHz
0
1
1
0
512
Hz
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
M48T201Y, M48T201V
Reset Inputs (RSTIN1 & RSTIN2)
The M48T201Y/V provides two independent inputs which can generate an output reset. The duration and function of these resets is identical to a
reset generated by a power cycle. Figure 10 and
Table 8 illustrate the AC reset characteristics of
this function. Pulses shorter than tR1 and tR2 will
not generate a reset condition. RSTIN1 and
RSTIN2 are each internally pulled up to VCC
through a 100KΩ resistor.
Power-on Reset
The M48T201Y/V continuously monitors VCC.
When VCC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for tREC after VCC passes VPFD (max).
The RST pin is an open drain output and an appropriate pull-up resistor to VCC should be chosen to
control rise time.
Figure 10. RSTIN1 and RSTIN2 Timing Waveforms
RSTIN1
RSTIN2
tR2
Hi-Z
Hi-Z
RST
tR1
tR1HRZ
tR2HRZ
AI01679
Table 8. Reset AC Characteristics
Symbol
Parameter(1)
Min
Max
Unit
tR1
RSTIN1 Low to RST Low
50
200
ns
tR2
RSTIN2 Low to RST Low
20
100
ms
tR1HRZ(2)
RSTIN1 High to RST Hi-Z
40
200
ms
tR2HRZ(2)
RSTIN2 High to RST Hi-Z
40
200
ms
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF (see Figure 14., page 25).
19/33
M48T201Y, M48T201V
Calibrating the Clock
The M48T201Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are factory calibrated at 25°C and
tested for accuracy. Clock accuracy will not exceed ±35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about
±1.53 minutes per month. When the Calibration
circuit is properly employed, accuracy improves to
better than +1/–2 ppm at 25°C.
The oscillation rate of crystals changes with temperature (see Figure 11., page 21). The
M48T201Y/V design employs periodic counter
correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure
12., page 21.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The Calibration bits occupy the five lower order
bits (D4-D0) in the Control Register 7FFF8h.
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign Bit;
'1' indicates positive calibration, '0' indicates negative calibration (see Figure 12., page 21). Calibration occurs within a 64 minute cycle. The first 62
minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened
by 256 oscillator cycles. If a binary '1' is loaded into
the register, only the first 2 minutes in the 64
minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that
the oscillator is running at exactly 32,768Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
20/33
which corresponds to a total range of +5.5 or –2.75
minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T201Y/V may require. The first involves setting the clock, letting it
run for a month and comparing it to a known accurate reference and recording deviation over a fixed
period of time. Calibration values, including the
number of seconds lost or gained in a given period, can be found in the STMicroelectronics Application
Note
AN934,
“TIMEKEEPER ®
CALIBRATION.” This allows the designer to give
the end user the ability to calibrate the clock as the
environment requires, even if the final product is
packaged in a non-user serviceable enclosure.
The designer could provide a simple utility that accesses the Calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz, when the
Stop Bit (ST, D7 of 7FFF9h) is '0,' the Frequency
Test Bit (FT, D6 of 7FFFCh) is '1,' the Alarm Flag
Enable Bit (AFE, D7 of 7FFF6h) is '0,' and the
Watchdog Steering Bit (WDS, D7 of 7FFF7h) is '1'
or the Watchdog Register (7FFF7h=0) is reset.
Note: A 4-second settling time must be allowed
before reading the 512Hz output.
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124Hz would indicate a +20 ppm oscillator
frequency error, requiring a –10 (WR001010) to be
loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency Test output frequency.
The IRQ/FT pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500-10kΩ resistor is recommended in order
to control the rise time. The FT Bit is cleared on
power-down.
M48T201Y, M48T201V
Figure 11. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
∆F = -0.038 ppm (T - T )2 ± 10%
0
F
C2
–120
T0 = 25 °C
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
Figure 12. Calibration Waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
21/33
M48T201Y, M48T201V
Battery Low Warning
The M48T201Y/V automatically performs battery
voltage monitoring upon power-up and at factoryprogrammed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 7FFF0h, will be asserted if the battery
voltage is found to be less than approximately
2.5V. The BL Bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next
power-up sequence or the next scheduled 24-hour
interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5V and may not be able to maintain
data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT® top
may be replaced while VCC is applied to the device.
Note: This will cause the clock to lose time during
the interval the battery/crystal is removed.
The M48T201Y/V only monitors the battery when
a nominal VCC is applied to the device. Thus applications which require extensive durations in the
battery back-up mode should be powered-up periodically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
Initial Power-on Defaults
Upon application of power to the device, the following register bits are set to a '0' state: WDS;
BMB0-BMB4; RB0-RB1; AFE; ABE; SQWE; W; R;
FT (see Table 9).
Table 9. Default Values
W
R
FT
AFE
ABE
SQWE
WATCHDOG
Register(1)
Initial Power-up
(Battery Attach for SNAPHAT)(2)
0
0
0
0
0
0
0
RESET(3)
0
0
0
0
0
0
0
Power-down(4)
0
0
0
1
1
1
0
Condition
Note: 1.
2.
3.
4.
22/33
WDS, BMB0-BMB4, RB0, RB1.
State of other control bits undefined.
State of other control bits remains unchanged.
Assuming these bits set to '1' prior to power-down.
M48T201Y, M48T201V
VCC Noise And Negative Going Transients
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure
13) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values
below VSS by as much as one volt. These negative
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, STMicroelectronics recommends connecting a schottky diode from VCC to
VSS (cathode connected to VCC, anode to VSS).
Schottky diode 1N5817 is recommended for
through hole and MBRS120T3 is recommended
for surface mount.
Figure 13. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI00605
23/33
M48T201Y, M48T201V
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 10. Absolute Maximum Ratings
Symbol
TA
TSTG
TSLD(1)
Parameter
Value
Unit
0 to 70
°C
SNAPHAT®
–40 to 85
°C
SOIC
–55 to 125
°C
260
°C
–0.3 to VCC + 0.3
V
M48T201Y
–0.3 to 7.0
V
M48T201V
–0.3 to 4.6
V
Ambient Operating Temperature
Storage Temperature
Lead Solder Temperature for 10 seconds
VIO
Input or Output Voltage
VCC
Supply Voltage
IO(2)
Output Current
20
mA
Power Dissipation
1
W
PD
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
24/33
M48T201Y, M48T201V
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 11. DC and AC Measurement Conditions
Parameter
M48T201Y
M48T201V
Unit
4.5 to 5.5
3.0 to 3.6
V
0 to 70
0 to 70
°C
Load Capacitance (CL)
100
50
pF
Input Rise and Fall Times
≤5
≤5
ns
0 to 3
0 to 3
V
1.5
1.5
V
VCC Supply Voltage
Ambient Operating Temperature
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note: Output High Z is defined as the point where data is no longer driven.
Figure 14. AC Testing Load Circuit
645Ω
DEVICE
UNDER
TEST
CL = 100pF
CL includes JIG capacitance
1.75V
AI04764
Notes:Excluding open-drain output pin; 50pF for M48T201V.
Table 12. Capacitance
Symbol
CIN
COUT(3)
Parameter(1,2)
Min
Max
Unit
Input Capacitance
10
pF
Input/Output Capacitance
10
pF
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C; f = 1MHz.
3. Outputs deselected.
25/33
M48T201Y, M48T201V
Table 13. DC Characteristics
Sym
Parameter
Test Condition
(1)
Min
ILI(2)
Input Leakage Current
ILO(3)
Output Leakage Current
M48T201Y
M48T201V
–70
–85
Typ
Max
Min
Typ
Unit
Max
0V ≤ VIN ≤ VCC
±1
±1
µA
0V ≤ VOUT ≤ VCC
±1
±1
µA
10
mA
ICC
Supply Current
ICC1
Supply Current (Standby)
TTL
E = VIH
5
3
mA
ICC2
Supply Current (Standby)
CMOS
E = VCC –0.2
3
2
mA
800
nA
100
nA
Outputs open
8
Battery Current OSC ON
575
VCC = 0V
15
4
800
575
IBAT
Battery Current OSC
OFF
VIL
Input Low Voltage
–0.3
0.8
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC +
0.3
2.0
VCC +
0.3
V
100
Output Low Voltage
IOL = 2.1mA
0.4
0.4
V
Output Low Voltage
(open drain)(4)
IOL = 10mA
0.4
0.4
V
Output High Voltage
IOH = –1.0mA
2.4
VOHB(5) VOH Battery Back-up
IOUT2 = –1.0µA
2.0
IOUT1(6) VOUT Current (Active)
VOUT1 > VCC –0.3
IOUT2
VOUT Current (Battery
Back-up)
VOUT2 > VBAT –0.3
VPFD
Power-fail Deselect
Voltage
VSO
Battery Back-up
Switchover Voltage
3.0
VPFD –
100mV
V
VBAT
Battery Voltage
3.0
3.0
V
VOL
VOH
Note: 1.
2.
3.
4.
5.
4.1
2.4
3.6
4.35
V
3.6
V
100
70
mA
100
100
µA
3.0
V
4.5
2.0
2.7
2.9
Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
RSTIN1 and RSTIN2 internally pulled-up to VCC through 100KΩ resistor. WDI internally pulled-down to VSS through 100KΩ resistor.
Outputs deselected.
For IRQ/FT & RST pins (Open Drain).
Conditioned outputs (ECON - GCON) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage currents
will reduce battery life.
6. External SRAM must match TIMEKEEPER SUPERVISOR chip VCC specification.
26/33
M48T201Y, M48T201V
Figure 15. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
INPUTS
VALID
OUTPUTS
VALID
tRB
tREC
VALID
DON'T CARE
HIGH-Z
VALID
RST
AI03519
Table 14. Power Down/Up Mode AC Characteristics
Parameter(1)
Symbol
tF(2)
VPFD (max) to VPFD (min) VCC Fall Time
tFB(3)
VPFD (min) to VSS VCC Fall Time
tR
tREC
tRB
Min
Max
Unit
300
µs
M48T201Y
10
µs
M48T201V
150
µs
VPFD (min) to VPFD (max) VCC Rise Time
10
µs
VPFD (max) to RST High
40
VSS to VPFD (min) VCC Rise Time
5
200
ms
µs
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
27/33
M48T201Y, M48T201V
PACKAGE MECHANICAL INFORMATION
Figure 16. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 15. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Mechanical Data
mm
inches
Symb
Typ
Min
A
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.46
0.014
0.018
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
44
e
CP
28/33
Max
0.81
0.032
44
0.10
0.004
M48T201Y, M48T201V
Figure 17. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
A1
A2
A3
A
eA
B
L
eB
D
E
SHTK-A
Note: Drawing is not to scale.
Table 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
9.78
Max
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
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M48T201Y, M48T201V
Figure 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A1
A2
A3
A
eA
B
L
eB
D
E
SHTK-A
Note: Drawing is not to scale.
Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data
mm
inches
Symb
Typ
Min
A
Typ
Min
10.54
Max
0.415
A1
8.00
8.51
0.315
.0335
A2
7.24
8.00
0.285
0.315
A3
30/33
Max
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
.0710
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
M48T201Y, M48T201V
PART NUMBERING
Table 18. Ordering Information Example
Example:
M48T
201Y
–70
MH
1
TR
Device Type
M48T
Supply and Write Protect Voltage
201Y = VCC = 4.5 to 5.5V; VPFD = 4.1V to 4.5V
201V = VCC = 3.0 to 3.6V; VPFD = 2.7V to 3.0V
Speed
–70 = 70ns (for M48T201Y)
–85 = 85ns (for M48T201V)
Package
MH(1) = SOH44
Temperature Range
1 = 0 to 70°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The SOIC package (SOH44) requires the battery package (SNAPHAT ®) which is ordered separately under the part number
“M4Txx-BR12SH” in plastic tube or “M4Txx-BR12SHTR” in Tape & Reel form.
Note: 1. Caution: Do not place the SNAPHAT battery package “M4Txx-BR12SH” in conductive foam as it will drain the lithium button-cell
battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Table 19. SNAPHAT® Battery Table
Part Number
Description
Package
M4T28-BR12SH
Lithium Battery (48mAh) SNAPHAT
SH
M4T32-BR12SH
Lithium Battery (120mAh) SNAPHAT
SH
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M48T201Y, M48T201V
REVISION HISTORY
Table 20. Document Revision History
Date
Rev. #
Revision Details
November 1999
1.0
First Issue
10-May-01
2.0
Reformatted; added Industrial temperature (Table 10, 13, 3, 4, 14)
14-May-01
2.1
Corrected table footnote (Table 14)
30-May-01
2.2
Change “Controller” references to “SUPERVISOR”
01-Aug-01
2.3
Formatting changes from recent document review findings; E2 added to Hookup (Figure
4)
08-Aug-01
2.4
Improve text in “Setting the Alarm Clock” section
18-Dec-01
2.5
Added IBAT values for Industrial Temperature device (Table 13)
13-May-02
2.6
Modify reflow time and temperature footnote (Table 10)
16-Jul-02
2.7
Update DC Characteristics, footnotes (Table 13)
27-Mar-03
3.0
v2.2 template applied; update test condition (Table 13)
24-Sep-04
4.0
Reformatted, remove Industrial Temperature (Ambient Operating) references (Table 3, 4,
8, 10, 13, 14, 18)
M48T201, M48T201Y, M48T201V, 48T201, 48T201Y, 48T201V, T201, T201Y, T201V, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER,
TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,
NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,
NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, RTC, RTC, RTC, RTC, RTC, RTC, RTC,
RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC,
RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,
Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,
Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,
Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog,
Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog,
Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI,
PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO,
PFO, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover,
Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator,
Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC,
SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V,
5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V
32/33
M48T201Y, M48T201V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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