AD ADM8324 Supervisory circuits with windowed watchdog and manual reset in 5-lead sot-23 Datasheet

Supervisory Circuits with Windowed
Watchdog and Manual Reset in 5-Lead SOT-23
ADM8323/ADM8324
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
ADM8323
VCC
VCC
RESET
GENERATOR
VREF
MR
RESET
DEBOUNCE
WINDOWED
WATCHDOG
DETECTOR
GND
11802-001
Windowed watchdog, 8 timeout options
26 reset threshold options
2.5 V to 5 V in 100 mV increments
4 reset timeout options
1 ms, 20 ms, 140 ms, and 1120 ms (minimum)
Manual reset input
Open-drain or push-pull RESET outputs
Low power consumption
Specified over wide temperature range (−40°C to +125°C)
Qualified for automotive applications
5-lead SOT-23 package
WDI
Figure 1.
ADM8324
APPLICATIONS
Automotive
Microprocessor systems
Computers
Controllers
Intelligent instruments
Portable equipment
VCC
RESET
GENERATOR
VREF
MR
RESET
DEBOUNCE
GND
WDI
11802-002
WINDOWED
WATCHDOG
DETECTOR
Figure 2.
GENERAL DESCRIPTION
The ADM8323/ADM8324 are supervisory circuits that monitor
power supply voltage levels and code execution integrity in
microprocessor-based systems. An on-chip watchdog timer
checks for activity within a preset timeout window. A reset
signal can also be asserted by an external push-button switch
through a manual reset input. The RESET output is either pushpull (ADM8323) or open-drain (ADM8324).
pulse. The watchdog timeout is measured from the last falling
edge of the watchdog input (WDI). There are eight different
watchdog windows available, as shown in Table 5.
A watchdog failure results in a low output on the RESET pin.
A failure can be triggered either by a fast watchdog error
(watchdog pulses too close together) or by a slow watchdog
error (no watchdog pulse within the timeout period). This
effectively gives a window in which to observe the watchdog
The ADM8323/ADM8324 are available in a 5-lead SOT-23
package and typically consume only 10 μA, making them
suitable for use in low power portable applications.
Rev. 0
Each device is available in a choice of 26 reset threshold options
from 2.5 V to 5 V in 100 mV increments. There are also four
reset timeout options of 1 ms, 20 ms, 140 ms, and 1120 ms
(minimum).
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ADM8323/ADM8324
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Push-Pull RESET Output .......................................................... 10
Applications ....................................................................................... 1
Open-Drain RESET Output ..................................................... 10
Functional Block Diagrams ............................................................. 1
Manual Reset Input .................................................................... 10
General Description ......................................................................... 1
Windowed Watchdog Input ...................................................... 10
Revision History ............................................................................... 2
Applications Information .............................................................. 11
Specifications..................................................................................... 3
Watchdog Input Current ........................................................... 11
Absolute Maximum Ratings............................................................ 5
Negative Going VCC Transients................................................. 11
ESD Caution .................................................................................. 5
Ensuring RESET Valid to VCC = 0 V ........................................ 11
Pin Configuration and Function Descriptions ............................. 6
Options ............................................................................................ 12
Typical Performance Characteristics ............................................. 7
Outline Dimensions ....................................................................... 13
Theory of Operation ...................................................................... 10
Ordering Guide .......................................................................... 13
Circuit Description..................................................................... 10
Automotive Products ................................................................. 14
REVISION HISTORY
10/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
ADM8323/ADM8324
SPECIFICATIONS
VCC = (VTH + 1.5%) to 5.5 V, TA = −40°C to +125°C, unless otherwise noted. Typical values are at TA = 25°C.
Table 1.
Parameter
SUPPLY
VCC Operating Voltage Range 1
VCC that Guarantees Valid Output
Supply Current
RESET THRESHOLD VOLTAGE 2
RESET THRESHOLD TEMPERATURE COEFFICIENT
RESET THRESHOLD HYSTERESIS
RESET TIMEOUT PERIOD
Reset Timeout Option A
Reset Timeout Option B
Reset Timeout Option C
Reset Timeout Option D
VCC TO RESET DELAY, tRD
PUSH-PULL OUTPUT (ADM8323)
RESET Output Voltage
Min
Typ
Max
Unit
5.5
V
10
10
VTH
VTH
20
2.5 × VTH
20
18
VTH + 1%
VTH + 1.5%
µA
µA
V
V
ppm/°C
mV
1.4
28
200
1600
90
1.8
36
260
2080
ms
ms
ms
ms
µs
VCC falling at 1 mV/µs
100
V
V
V
V
V
V
ns
VCC ≥ 0.9 V, ISINK = 25 µA
VCC ≥ 1.2 V, ISINK = 100 µA
VCC ≥ 2.7 V, ISINK = 1.2 mA
VCC ≥ 4.5 V, ISINK = 3.2 mA
VCC ≥ 2.7 V, ISOURCE = 500 µA
VCC ≥ 4.5 V, ISOURCE = 800 µA
From 10% to 90% VCC, CL = 5 pF, VCC = 3.3 V
0.2
0.2
0.2
0.3
1
V
V
V
V
µA
VCC ≥ 0.9 V, ISINK = 25 µA
VCC ≥ 1.2 V, ISINK = 100 µA
VCC ≥ 2.7 V, ISINK = 1.2 mA
VCC ≥ 4.5 V, ISINK = 3.2 mA
0.9
0.9
VTH − 1%
VTH − 1.5%
VCC = 5.5 V, WDI = 0 V
VCC = 3.6 V, WDI = 0 V
TA = 25°C
TA = −40°C to +125°C
See Table 4
1
20
140
1120
0.2
0.2
0.2
0.3
0.9 × VCC
0.9 × VCC
50
RESET Rise Time
OPEN-DRAIN OUTPUT (ADM8324)
RESET Output Voltage
Open-Drain Reset Output Leakage Current
WATCHDOG INPUT
Watchdog Timeout Period (Fast), tWD-FAST
Watchdog Timeout Option A
Watchdog Timeout Option B
Watchdog Timeout Option C
Watchdog Timeout Option D
Watchdog Timeout Option E
Watchdog Timeout Option F
Watchdog Timeout Option G
Watchdog Timeout Option H
Watchdog Timeout Period (Slow), tWD-SLOW
Watchdog Timeout Option A
Watchdog Timeout Option B
Watchdog Timeout Option C
Watchdog Timeout Option D
Watchdog Timeout Option E
Watchdog Timeout Option F
Watchdog Timeout Option G
Watchdog Timeout Option H
Test Conditions/Comments
See Table 5
1
10
10
10
10
16
27
512
1.5
15
15
15
15
24
41
768
ms
ms
ms
ms
ms
ms
ms
ms
10
100
300
10
60
44
76
1.24
15
150
450
15
90
66
114
1.86
ms
ms
ms
sec
sec
ms
ms
sec
Rev. 0 | Page 3 of 16
ADM8323/ADM8324
Parameter
WDI Pulse Width
WDI Glitch Immunity
WDI Input Threshold
WDI Input Current
Data Sheet
Min
200
1
2
Max
100
0.3 × VCC
−1
MANUAL RESET INPUT
VIL
VIH
MR Input Pulse Width
MR Glitch Rejection
MR Pull-Up Resistance
MR to Reset Delay
Typ
0.35
−0.35
0.7 × VCC
1
0.8
2.0
1
35
100
75
350
125
Unit
ns
ns
V
µA
µA
V
V
µs
ns
kΩ
ns
Test Conditions/Comments
VIL = 0.3 × VCC, VIH = 0.7 × VCC
VWDI = VCC
VWDI = 0 V
VCC = 5 V
The device switches from undervoltage reset to normal operation when 1.5 V < VCC < 2.5 V.
The device monitors VCC through an internal factory trimmed voltage divider, which programs the nominal reset threshold. Factory trimmed reset thresholds are
available in approximately 100 mV increments from 2.5 V to 5 V.
Rev. 0 | Page 4 of 16
Data Sheet
ADM8323/ADM8324
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter
VCC
All Other Pins
Output Current (RESET)
Operating Temperature Range
Storage Temperature Range
θJA Thermal Impedance, SOT-23
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
−0.3 V to +6 V
−0.3 V to (VCC + 0.3 V)
20 mA
−40°C to +125°C
−65°C to +150°C
270°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
300°C
215°C
220°C
Rev. 0 | Page 5 of 16
ADM8323/ADM8324
Data Sheet
RESET 1
GND 2
MR 3
ADM8323/
ADM8324
TOP VIEW
(Not to Scale)
5
VCC
4
WDI
11802-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. ADM8323/ADM8324 Pin Configuration
Table 3. ADM8323/ADM8324 Pin Function Descriptions
Pin No.
1
Mnemonic
RESET
2
3
GND
MR
4
5
WDI
VCC
Description
Active Low Reset Output. Asserted whenever VCC is below the reset threshold, VTH. This pin is a push-pull
output stage for the ADM8323 and an open-drain output stage for the ADM8324.
Ground.
Manual Reset Input. This is an active low input that, when forced low for greater than the glitch filter time,
generates a reset. It features a 75 kΩ internal pull-up resistor.
Watchdog Input. Generates a reset if the WDI pulse is not within the watchdog window.
Power Supply Voltage Being Monitored.
Rev. 0 | Page 6 of 16
Data Sheet
ADM8323/ADM8324
TYPICAL PERFORMANCE CHARACTERISTICS
14
100
13
90
12
80
VCC TO RESET DELAY (µs)
VCC = 5.0V
11
10
VCC = 3.0V
8
VCC = 1.5V
7
6
5
4
3
70
VTH = 5V
60
VTH = 2.93V
50
VTH = 2.5V
40
30
20
11802-106
2
1
10
0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 130
0
–40
–20
0
TEMPERATURE (°C)
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 4. Supply Current (ICC) vs. Temperature
11802-109
ICC (µA)
9
Figure 7. VCC to Reset Delay vs. Temperature
35
500
450
30
400
PROPAGATION DELAY
ICC (µA)
25
20
15
10
VTH = 2.5V
350
VTH = 2.93V
300
250
VTH = 5V
200
150
100
11802-107
0
0
50
0
–40
0.3 0.9 1.1 1.5 1.8 2.1 2.7 3.0 3.6 3.9 4.2 4.5 4.8 5.1 5.4
–20
0
VCC (V)
40
60
80
100
120
TEMPERATURE (°C)
Figure 8. Manual Reset to Reset Propagation Delay vs. Temperature
Figure 5. Supply Current (ICC) vs. Supply Voltage (VCC)
1.05
1.20
1.04
NORMALIZED RESET TIMEOUT
1.15
1.03
1.02
1.01
1.00
0.99
0.98
0.97
1.10
1.05
1.00
0.95
0.90
0.95
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
120
0.80
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 9. Normalized Reset Timeout vs. Temperature
Figure 6. Normalized Reset Threshold vs. Temperature
Rev. 0 | Page 7 of 16
11802-111
0.85
0.96
11802-108
NORMALIZED RESET THRESHOLD
20
11802-110
5
ADM8323/ADM8324
Data Sheet
WDI
1.15
1.10
2
RESET
1.05
1.00
1
11802-115
0.95
11802-112
0.90
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 130
CH1 2.0V
M 4.0ms 125kS/s 8.0µs/pt
A CH2 1.48V
CH2 2.0V
TEMPERATURE (°C)
Figure 13. Slow Watchdog Timeout Period, Watchdog Timeout Option A
160
MAXIMUM TRANSIENT DURATION (µs)
1.15
1.10
1.05
1.00
0.95
11802-113
NORMALIZED WATCHDOG TIMEOUT (ms)
1.20
RESET ASSERTED ABOVE CURVE
140
VTH = 2.93V
120
VTH = 5V
100
80
VTH = 4.63V
60
40
20
0
10
0.90
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 130
100
Figure 11. Normalized Watchdog Timeout vs. Temperature, Slow Timeout
Figure 14. Maximum VCC Transient Duration vs. Reset Threshold Overdrive
MR MINIMUM PULSE WIDTH (ns)
WDI
2
RESET
11802-114
1
CH1 2.0V
CH2 2.0V
1000
OVERDRIVE VOLTAGE (mV)
TEMPERATURE (°C)
11802-116
Figure 10. Normalized Watchdog Timeout vs. Temperature, Fast Timeout
M400µs 1.25MS/s 800ns/pt
A CH1 1.48V
850
840
830
820
810
800
790
780
770
760
750
740
730
720
710
700
690
680
670
660
650
–40
VTH = 2.93V
VTH = 2.5V
VTH = 5V
–20
0
20
40
60
TEMPERATURE (°C)
Figure 12. Fast Watchdog Timeout Period, Watchdog Timeout Option A
Rev. 0 | Page 8 of 16
80
100
120
11802-117
NORMALIZED WATCHDOG TIMEOUT (ms)
1.20
Figure 15. Manual Reset (MR) Minimum Pulse Width vs. Temperature
Data Sheet
ADM8323/ADM8324
3.5
0.308
ISINK = 3.2mA
ISINK = 800µA
3.0
RESET VOLTAGE (V)
0.208
0.158
0.108
0.058
2.5
2.0
1.5
1.0
0.5
1.5
1.7
1.9
2.1
2.3
2.5
2.7
0
1.1
11802-119
1.3
2.9
VCC VOLTAGE (V)
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
VCC VOLTAGE (V)
Figure 16. RESET Open-Drain VOL Voltage vs. VCC Voltage (VTH = 3 V)
11802-121
RESET VOLTAGE (V)
0.258
0.008
1.1
ISOURCE = 3.2mA
ISOURCE = 800µA
Figure 18. RESET Push-Pull VOH Voltage vs. VCC Voltage (VTH = 3 V)
25
0.30
ISINK = 3.2mA
ISINK = 800µA
24
0.25
RESET RISE TIME (ns)
0.20
0.15
0.10
22
21
20
19
18
0.05
0
1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9
VCC VOLTAGE (V)
16
2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4
VCC VOLTAGE (V)
Figure 19. RESET Push-Pull Rise Time vs. VCC Voltage
Figure 17. RESET Push-Pull VOL Voltage vs. VCC Voltage (VTH = 4 V)
Rev. 0 | Page 9 of 16
11802-122
17
11802-120
RESET VOLTAGE (V)
23
ADM8323/ADM8324
Data Sheet
THEORY OF OPERATION
CIRCUIT DESCRIPTION
The ADM8323/ADM8324 provide microprocessor supply
voltage supervision by controlling the microprocessor reset input.
Code execution errors are avoided during power-up, powerdown, and brownout conditions by asserting a reset signal when
the supply voltage is below a preset threshold and by allowing
supply voltage stabilization with a fixed timeout reset pulse
after the supply voltage rises above the threshold. In addition,
problems with microprocessor code execution can be monitored
and corrected with a windowed watchdog timer. If the user
detects a problem with system operation, a manual reset input is
available to reset the microprocessor, for example, by means of
an external push-button switch.
PUSH-PULL RESET OUTPUT
The ADM8323 features an active low push-pull reset output.
The reset signal is guaranteed to be valid for VCC down to 0.9 V.
The reset output is asserted when VCC is below the reset threshold (VTH), when MR is driven low, or when WDI is not serviced
within the watchdog timeout window. Reset remains asserted for
the duration of the reset active timeout period (tRP) after VCC
rises above the reset threshold, after MR transitions from low to
high, or after the watchdog timer fault occurs. Figure 20
illustrates the behavior of the reset output.
the MR input, and fast, negative going transients of up to 100 ns
(typical) are ignored. A 0.1 µF capacitor between MR and ground
provides additional noise immunity.
WINDOWED WATCHDOG INPUT
The ADM8323/ADM8324 feature a windowed watchdog timer
that monitors microprocessor activity. A timer circuit is cleared
with every high-to-low logic transition on the watchdog input pin
(WDI), which detects pulses as short as 200 ns. If this watchdog
pulse does not occur within the defined time window, a reset
asserts. Failure of the microprocessor to toggle WDI within the
watchdog window, therefore, indicates a code execution error,
and the reset pulse generated restarts the microprocessor in a
known state.
As well as logic transitions on WDI, the watchdog timer is also
cleared by a reset assertion due to an undervoltage condition on
VCC or due to MR being pulled low. When a reset is asserted, the
watchdog timer is cleared and does not begin counting again
until the reset deassserts. The windowed watchdog timer cannot
be disabled.
All WDI input pulses are ignored while a reset is asserted. After
the reset deasserts, the first WDI falling edge is ignored for the
fast fault condition.
tWDI < tWD-FASTmin
VCC
VCC
VTH
VTH
1V
0V
Figure 20. Reset Timing Diagram
RESET
OPEN-DRAIN RESET OUTPUT
The ADM8324 has an active low, open-drain reset output. This
output structure requires an external pull-up resistor to connect
the reset output to a voltage rail no higher than Vcc. Use a
resistor that complies with the logic low and logic high voltage
level requirements of the microprocessor while supplying input
current and leakage paths on the RESET line. A 10 kΩ resistor
is adequate in most situations.
11802-010
WDI
tRP
Figure 21. Watchdog Fast Timeout Fault
tWDI > tWD-SLOWmax
WDI
tRP
RESET
MANUAL RESET INPUT
11802-011
tRD
Figure 22. Watchdog Slow Timeout Fault
The ADM8323/ADM8324 feature a manual reset input (MR),
which when driven low, asserts the reset output. When MR
transitions from low to high, the reset output remains asserted
for the duration of the reset active timeout period before
deasserting. The MR input has a 75 kΩ, internal pull-up resistor
so that the input is always high when unconnected. An external
push-button switch can be connected between MR and ground
so that the user can generate a reset. Debounce circuitry for this
purpose is integrated on chip. Noise immunity is provided on
tWD-FASTmax < tWDI< tWD-SLOWmin
WDI
11802-012
tRP
0V
11802-009
VCC
RESET
RESET
Rev. 0 | Page 10 of 16
Figure 23. Normal Watchdog Operation
Data Sheet
ADM8323/ADM8324
APPLICATIONS INFORMATION
WATCHDOG INPUT CURRENT
ENSURING RESET VALID TO VCC = 0 V
There is no way to disable the windowed watchdog functionality. Do not leave the WDI pin floating because this is not a valid
mode of operation. If the WDI pin is not in a defined state at
startup, this can lead to high supply current until the microprocessor is enabled and takes control of the WDI pin. A solution to
this is to add a 100 kΩ pull-up or pull-down resistor on the
WDI pin to hold it in a defined state until the microprocessor is
enabled.
The reset output is guaranteed valid for VCC as low as 0.9 V.
However, by using an external resistor with the push-pull
configured reset output on the ADM8323, a valid output for VCC
as low as 0 V is possible. For this active low reset output, a resistor
connected between RESET and ground pulls the output low
when it is unable to sink current. Use a large resistance, such as
100 kΩ, so that it does not overload the reset output when VCC
is above 0.9 V.
VCC
NEGATIVE GOING VCC TRANSIENTS
ADM8323
RESET
100kΩ
11802-013
To avoid unnecessary resets caused by fast power supply transients,
the ADM8323/ADM8324 are equipped with glitch rejection
circuitry. The typical performance characteristic in Figure 14
plots VCC transient duration vs. reset threshold overdrive. The
curves show combinations of reset threshold overdrive and
duration for which a reset is not generated for 5 V, 4.63 V, and
2.93 V reset threshold devices. For example, with the 2.93 V
threshold, a transient that goes 100 mV below the threshold and
lasts 80 µs typically does not cause a reset, but if the transient is
any larger in reset threshold overdrive or duration, a reset
generates. An optional 0.1 µF bypass capacitor mounted near
VCC provides additional glitch rejection.
Figure 24. Ensuring RESET Valid to VCC = 0 V
VCC
RESET
ADM8323
WDI
MICROPROCESSOR
I/O
11802-014
MR
RESET
Figure 25. ADM8323 Typical Application Circuit
Rev. 0 | Page 11 of 16
ADM8323/ADM8324
Data Sheet
OPTIONS
Table 4. Reset Timeout Options
Suffix
A
B
C
D
Minimum
1
20
140
1120
Typical
1.4
28
200
1600
Maximum
1.8
36
260
2080
Unit
ms
ms
ms
ms
Minimum
10
100
300
10
60
44
76
1.24
Slow
Unit
ms
ms
ms
sec
sec
ms
ms
sec
Table 5. Watchdog Timeout Options
Suffix
A
B
C
D
E
F
G
H
Maximum
1.5
15
15
15
15
24
41
768
Fast
Unit
ms
ms
ms
ms
ms
ms
ms
ms
Table 6. Reset Voltage Threshold Options
Reset Threshold Number
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Minimum
4.950
4.851
4.752
4.653
4.584
4.455
4.346
4.257
4.158
4.059
3.960
3.861
3.762
3.663
3.564
3.465
3.366
3.267
3.168
3.049
2.970
2.901
2.772
2.673
2.604
2.475
TA = 25°C
Typical
5.000
4.900
4.800
4.700
4.630
4.500
4.390
4.300
4.200
4.100
4.00
3.900
3.800
3.700
3.600
3.500
3.400
3.300
3.200
3.080
3.000
2.930
2.800
2.700
2.630
2.500
Maximum
5.050
4.949
4.848
4.747
4.676
4.545
4.434
4.343
4.242
4.141
4.040
3.939
3.838
3.737
3.636
3.535
3.434
3.333
3.232
3.111
3.030
2.959
2.828
2.727
2.656
2.525
TA = −40°C to +125°C
Minimum
Maximum
4.925
5.075
4.826
4.974
4.728
4.872
4.629
4.771
4.560
4.700
4.432
4.568
4.324
4.456
4.235
4.365
4.137
4.263
4.038
4.162
3.940
4.060
3.841
3.959
3.743
3.857
3.644
3.756
3.546
3.654
3.447
3.553
3.349
3.451
3.250
3.350
3.152
3.248
3.033
3.127
2.955
3.045
2.886
2.974
2.758
2.842
2.659
2.741
2.590
2.670
2.462
2.538
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Table 7. Standard Models
Model
ADM8323WCC29ARJZR7
ADM8323WCC46ARJZR7
ADM8324WCA29ARJZR7
ADM8324WCA46ARJZR7
Reset Threshold (V)
2.93
4.63
2.93
4.63
Maximum Fast Timeout (ms)
15
15
1.5
1.5
Rev. 0 | Page 12 of 16
Minimum Slow Timeout (ms)
300
300
10
10
Minimum Reset Timeout (ms)
140
140
140
140
Data Sheet
ADM8323/ADM8324
OUTLINE DIMENSIONS
3.00
2.90
2.80
5
1.70
1.60
1.50
4
1
2
3.00
2.80
2.60
3
0.95 BSC
1.90
BSC
1.45 MAX
0.95 MIN
0.15 MAX
0.05 MIN
0.50 MAX
0.35 MIN
0.20 MAX
0.08 MIN
10°
5°
0°
SEATING
PLANE
0.60
BSC
0.55
0.45
0.35
COMPLIANT TO JEDEC STANDARDS MO-178-AA
11-01-2010-A
1.30
1.15
0.90
Figure 26. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
ADM83
W
ARJZR7
ORDERING QUANTITY
R7: 3000-PIECE REEL, RoHS COMPLIANT
GENERIC NUMBER
(23 OR 24)
Z: RoHS COMPLIANT
W: AUTOMOTIVE QUAL
PACKAGE CODE
RJ: 5-LEAD SOT-23
RESET TIMEOUT PERIOD
A: 1ms (MIN)
B: 20ms (MIN)
C: 140ms (MIN)
D: 1120ms (MIN)
TEMPERATURE RANGE
A: –40°C TO +125°C
11802-016
RESET THRESHOLD NUMBER
(25 TO 50)
WINDOWED WATCHDOG
TIMEOUT PERIOD (A-H)
Figure 27. Ordering Code Structure
ORDERING GUIDE
Model 1, 2, 3, 4
ADM8323WxxxxARJZR7
ADM8324WxxxxARJZR7
Temperature Range
−40°C to +125°C
−40°C to +125°C
Ordering Quantity 5
3,000
3,000
Package Description
5-Lead SOT-23
5-Lead SOT-23
Complete the ordering code by inserting reset timeout, watchdog timeout, and reset threshold suffixes from Table 4 to Table 6.
Contact sales for the availability of nonstandard models. See Table 7 for a list of standard models.
3
Z = RoHS Compliant Part.
4
W = Qualified for Automotive Applications.
5
A minimum of 12,000 (four reels) must be ordered for nonstandard models.
1
2
Rev. 0 | Page 13 of 16
Package Option
RJ-5
RJ-5
Branding
LNO
LMU
ADM8323/ADM8324
Data Sheet
AUTOMOTIVE PRODUCTS
The ADM8323W/ADM8324W model are available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models.
Rev. 0 | Page 14 of 16
Data Sheet
ADM8323/ADM8324
NOTES
Rev. 0 | Page 15 of 16
ADM8323/ADM8324
Data Sheet
NOTES
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11802-0-10/13(0)
Rev. 0 | Page 16 of 16