Renesas ISL62391C High-efficiency, triple-output system power supply controller for notebook computer Datasheet

DATASHEET
ISL62391, ISL62392, ISL62391C, ISL62392C
FN6666
Rev 8.00
August 25, 2015
High-Efficiency, Triple-Output System Power Supply Controller for Notebook
Computers
The ISL62391, ISL62392, ISL62391C and ISL62392C
controller generate supply voltages for battery-powered
systems. It includes two pulse-width modulation (PWM)
controllers, adjustable from 0.6V to 5.5V, and a linear
regulator (LDO3) that generates a fixed 3.3V and can deliver
up to 100mA. The ISL62391, ISL62392, ISL62391C and
ISL62392C include on-board power-up sequencing, a
power-good (PGOOD) output, digital soft-start, and internal
soft-stop output discharge that prevents negative voltages on
shutdown.
Features
The patented R3 PWM control scheme provides a low jitter
system with fast response to load transients. Light-load
efficiency is improved with period-stretching discontinuous
conduction mode (DCM) operation. To eliminate noise in audio
frequency applications, an ultrasonic DCM mode is included,
which limits the minimum switching frequency to 28kHz.
• Internal Soft-Start and Soft-Stop Output Discharge
The ISL62391, ISL62391C and ISL62392, ISL62392C are
identical except for how their overvoltage protection is
handled. The ISL62391 and ISL62391C utilize a tri-state
overvoltage scheme, whereas the ISL62392 and ISL62392C
employ a soft-crowbar method.
• Thermal Monitor and Protection
The ISL62391, ISL62392, ISL62391C and ISL62392C are
available in a 28 Ld 4x4 TQFN package and operate over
the extended temperature range (-40°C to +100°C).
• High Performance R3 Technology
• Fast Transient Response
• ±1% Output Voltage Accuracy
• 2 Fully Programmable Switch-Mode Power Supplies
• Programmable Switching Frequency
• Fixed 3.3V LDO Output
• Wide Input Voltage Range: 5.5V to 25V
• Full and Ultrasonic Pulse-Skipping Mode
• Power-Good Indicator
• Overvoltage, Undervoltage and Overcurrent Protection
• Pb-Free (RoHS Compliant)
Applications
• Notebook and Sub-Notebook Computers
• PDAs and Mobile Communication Devices
• 3-Cell and 4-Cell Li+ Battery-Powered Devices
Pinout
FN6666 Rev 8.00
August 25, 2015
FB2
VOUT2
ISEN2
OCSET2
EN2
PHASE2
UGATE2
ISL62391, ISL62392, ISL62391C, ISL62392C
(28 LD 4X4 TQFN)
TOP VIEW
28
27
26
25
24
23
22
PGOOD
1
21
BOOT2
FSET2
2
20
LGATE2
FCCM
3
19
PGND
VCC
4
18
PVCC
LDO3EN
5
17
VIN
FSET1
6
16
LDO3
FB1
7
15
LGATE1
9
10
11
12
13
ISEN1
OCSET1
EN1
PHASE1
UGATE1
14
BOOT1
8
VOUT1
CENTER PAD:
GND
Page 1 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Ordering Information
PART NUMBER
(Notes 1, 2)
PART MARKING
TEMP RANGE (°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL62391HRTZ (Note 3)
623 91HRTZ
-10 to +100
28 Ld 4x4 TQFN
L28.4x4
ISL62392HRTZ (Note 3)
623 92HRTZ
-10 to +100
28 Ld 4x4 TQFN
L28.4x4
ISL62391CHRTZ (No longer available or
supported)
62391C HRTZ
-10 to +100
28 Ld 4x4 TQFN
L28.4x4
ISL62392CHRTZ
62392C HRTZ
-10 to +100
28 Ld 4x4 TQFN
L28.4x4
ISL62391IRTZ (Note 3)
623 91IRTZ
-40 to +100
28 Ld 4x4 TQFN
L28.4x4
ISL62392IRTZ (Note 3)
623 92IRTZ
-40 to +100
28 Ld 4x4 TQFN
L28.4x4
ISL62391CIRTZ (No longer available or
supported)
62391C IRTZ
-40 to +100
28 Ld 4x4 TQFN
L28.4x4
ISL62392CIRTZ
62392C IRTZ
-40 to +100
28 Ld 4x4 TQFN
L28.4x4
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
3. Not Recommended for New Designs. No Recommended Replacement.
FN6666 Rev 8.00
August 25, 2015
Page 2 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Absolute Maximum Ratings
Thermal Information
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
VCC, PGOOD, PVCC to GND . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
EN1, 2, LDO3EN . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC +0.3V
VOUT1,2, FB1,2, FSET1,2 . . . . . . . . . . . . -0.3V to GND, VCC +0.3V
PHASE1,2 to GND . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V
(<100ns Pulse Width, 10µJ) . . . . . . . . . . . . . . . . . . . . . . . . . -5.0V
BOOT1,2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
BOOT1,2 to PHASE1,2 . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
UGATE1,2 . . . . . . . . . . . . (DC) -0.3V to PHASE1,2, BOOT1,2 +0.3V
(<200ns Pulse Width, 20µJ) . . . . . . . . . . . . . . . . . . . . . . . . -4.0V
LGATE1,2 . . . . . . . . . . . . . . . . . . . (DC) -0.3V to GND, PVCC +0.3V
(<100ns Pulse Width, 4µJ) . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V
LDO3 Current (Internal Regulator) Continuous . . . . . . . . . +100mA
Thermal Resistance (Typical, Notes 4, 5) JA (°C/W)
JC (°C/W)
TQFN Package . . . . . . . . . . . . . . . . . .
37
3.5
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55C to +150°C
Operating Temperature Range
ISL62391IRTZ). . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +100°C
ISL62392IRTZ). . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +100°C
Operating Temperature Range
ISL62391HRTZ) . . . . . . . . . . . . . . . . . . . . . . . . . .-10C to +100°C
ISL62392HRTZ) . . . . . . . . . . . . . . . . . . . . . . . . . .-10C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range
ISL62391IRTZ). . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
ISL62392IRTZ). . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Ambient Temperature Range
ISL62391HRTZ) . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
ISL62392HRTZ) . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Supply Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . 5.5V to 25V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VIN = 12V, EN = VCC, TA = -40°C to +100°C, unless otherwise noted. Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range.
PARAMETER
CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
LINEAR REGULATOR
VIN Power-on Reset
Rising Threshold
5.3
5.4
5.5
V
Hysteresis
20
80
150
mV
VIN Shutdown Supply Current
EN1 = EN2 = LDO3EN = 0
6
15
µA
VIN Standby Supply Current
EN1 = EN2 = 0, LDO3EN = 1
150
250
µA
LDO3 Output Voltage
I_LDO3 = 100mA
3.25
3.3
3.35
V
I_LDO3 = 0mA
3.25
3.3
3.35
V
LDO3 Short-Circuit Current
LDO3 = GND
LDO3EN Input Voltage
Rising edge
1.1
2.5
V
Falling edge
0.94
1.06
V
-1
1
µA
60

LDO3EN Input Leakage Current
LDO3EN = 0 or VCC
LDO3 Discharge ON-resistance
LDO3EN = 0
180
36
PVCC POR Threshold
4.2
SMPS2 to PVCC Switchover Threshold
SMPS2 to PVCC Switchover Resistance
mA
4.63
VOUT2 to PVCC, VOUT2 = 5V
V
4.8
4.93
V
2.5
3.2

MAIN SMPS CONTROLLERS
VCC Input Bias Current
EN1 = EN2 = 1, FB1 = FB2 = 0.65V
VCC Start-up Voltage
EN1 = EN2 = LDO3EN = GND
FN6666 Rev 8.00
August 25, 2015
2
3.45
3.6
mA
3.75
V
Page 3 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Electrical Specifications
VIN = 12V, EN = VCC, TA = -40°C to +100°C, unless otherwise noted. Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range. (Continued)
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
Rising Edge
4.33
4.50
4.55
V
Rising Edge (ISL62391HRTZ, ISL62392HRTZ,
TA = -10°C to +100°C)
4.35
4.50
4.55
V
Falling Edge
4.08
4.20
4.30
V
Falling Edge (ISL62391HRTZ, ISL62392HRTZ,
TA = -10°C to +100°C)
4.10
4.20
4.30
V
PARAMETER
VCC POR Threshold
CONDITIONS
Reference Voltage
0.6
V
Regulation Accuracy
VOUT regulated to 0.6V
-1
1
%
FB Input Bias Current
FB = 0.6V
-12
30
nA
FB = 0.6V (ISL62391HRTZ, ISL62392HRTZ,
TA = -10°C to +100°C)
-10
30
nA
200
600
kHz
12
%
Frequency Range
Frequency Set Accuracy
FSW = 300kHz (Note 6)
-12
VOUT Voltage Adjust Range
VIN 6V for VOUT = 5.5V
0.6
5.5
V
VOUT Soft-discharge Resistance
14
50

PGOOD Pull-down Impedance
32
50

0
1
PGOOD Leakage Current
PGOOD = VCC
Maximum PGOOD Sink Current
PGOOD Soft-start Delay
(From first EN = 1 to PGOOD = 1)
5
µA
mA
EN1 = EN2 = 1
2.20
2.75
3.70
ms
EN1 = 1, EN2 = Floating or EN1 = Floating, EN2 =1
4.50
5.60
7.60
ms
EN1 = 1, EN2 = Floating or EN1 = Floating, EN2 =1
(ISL62391HRTZ, ISL62392HRTZ, TA = -10°C to
+100°C)
4.50
5.60
7.50
ms
1.5

UGATE Pull-up ON-resistance
200mA source current
1.0
UGATE Source Current
UGATE-PHASE = 2.5V
2.0
UGATE Pull-down ON-resistance
250mA source current
1.0
UGATE Sink Current
UGATE-PHASE = 2.5V
2.0
LGATE Pull-up ON-resistance
250mA source current
1.0
A
1.5

A
1.5

0.9

LGATE Source Current
LGATE-PGND = 2.5V
2.0
LGATE Pull-down ON-resistance
250mA source current
0.5
A
LGATE Sink Current
LGATE-PGND = 2.5V
4.0
A
UGATE to LGATE Deadtime
UG falling to LG rising, no load
21
ns
LGATE to UGATE Deadtime
LG falling to UG rising, no load
21
ns
Bootstrap Diode Forward Voltage
2mA forward diode current
0.58
V
Bootstrap Diode Reverse Leakage Current
VR = 25V
0.2
FCCM Input Voltage
Low Level (DCM enabled)
Float Level (audio filter enabled)
1.9
High Level (forced CCM)
2.4
FCCM Input Leakage Current
FCCM = GND or VCC
-2
Audio Filter Switching Frequency
FCCM floating
EN Input Voltage
Low Level (Clear fault level/SMPS off)
FN6666 Rev 8.00
August 25, 2015
1
0.8
V
2.1
V
V
2
28
Float Level (Delayed start)
1.9
High Level (SMPS on)
2.4
µA
µA
kHz
0.8
V
2.1
V
V
Page 4 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Electrical Specifications
VIN = 12V, EN = VCC, TA = -40°C to +100°C, unless otherwise noted. Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range. (Continued)
PARAMETER
CONDITIONS
EN Input Leakage Current
EN = GND or VCC
ISEN Input Impedance
EN = VCC
MIN
(Note 7)
TYP
-3.5
MAX
(Note 7)
UNITS
3.5
µA
600
k
ISEN Input Leakage Current
EN = GND
0.1
µA
OCSET Input Impedance
EN = VCC
600
k
OCSET Input Leakage Current
EN = GND
0.1
µA
OCSET Current Source
EN = VCC
8.7
10.0
10.5
µA
9
10.0
10.5
µA
-1.75
0.0
1.75
mV
80.9
84
87
%
Falling edge, referenced to FB (ISL62391HRTZ,
ISL62392HRTZ, TA = -10°C to +100°C)
81
84
87
%
Rising edge, referenced to FB
113
116
120
%
Falling edge, referenced to FB
99.5
103
106
%
EN = VCC (ISL62391HRTZ, ISL62392HRTZ,
TA = -10°C to +100°C)
OCP (OCSET-ISEN) Threshold
UVP Threshold
OVP Threshold
OTP Threshold
Falling edge, referenced to FB
Rising edge
150
Falling edge
135
°C
NOTES:
6. FSW accuracy reflects IC tolerance only; it does not include frequency variation due to VIN, VOUT, LOUT, ESRCOUT, or other application specific
parameters.
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN6666 Rev 8.00
August 25, 2015
Page 5 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Functional Pin Description
PIN
NAME
FUNCTION
1
PGOOD
Open-drain power-good status outputs. Connect to VCC through a 100k resistor. Output will be high when all outputs are
within regulation with no faults detected.
2
FSET2
Frequency control input for SMPS2. Connect a resistor to ground to program the switching frequency. The pin output is
a pulsed current and requires a decoupling capacitor to average the signal.
3
FCCM
Logic input to control efficiency mode. Logic high forces continuous conduction mode (CCM). Logic low allows full
discontinuous conduction mode (DCM). Float this pin for ultrasonic DCM operation.
4
VCC
5
LDO3EN
6
FSET1
7
FB1
8
VOUT1
SMPS1 output voltage sense input. Used for soft-discharge.
9
ISEN1
SMPS1 DCR current sense input. Used for overcurrent protection and R3 regulation.
10
OCSET1
11
EN1
12
PHASE1
SMPS1 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS
source, the synchronous NMOS drain, and the output inductor for SMPS1.
13
UGATE1
High-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 switching FET.
14
BOOT1
SMPS1 bootstrap input for the switching NMOS gate drivers. Connect to SMPS1 PHASE with a ceramic capacitor of 0.22µF.
15
LGATE1
Low-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 synchronous FET.
16
LDO3
17
VIN
18
PVCC
5V power source for SMPS gate drive current. Bypass to ground with a 4.7µF ceramic capacitor.
19
PGND
Power ground for SMPS1 and SMPS2. This provides a return path for synchronous FET switching currents.
20
LGATE2
Low-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 synchronous FET.
21
BOOT2
SMPS2 bootstrap input for the switching NMOS gate drivers. Connect to SMPS2 PHASE with a ceramic capacitor of 0.22µF.
22
UGATE2
High-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 switching FET.
23
PHASE2
SMPS2 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS
source, the synchronous NMOS drain, and the output inductor for SMPS2.
24
EN2
25
OCSET2
26
ISEN2
SMPS2 DCR current sense input. Used for overcurrent protection and R3 regulation.
27
VOUT2
SMPS2 output voltage sense input. Used for soft-discharge and switchover for PVCC 5V LDO.
28
FB2
SMPS2 feedback input used for output voltage programming and regulation.
Bottom
Pad
GND
Analog ground for analog and logic signals.
FN6666 Rev 8.00
August 25, 2015
Analog power supply input for reference voltages and currents. Bypass to ground with a 1µF ceramic capacitor near the IC.
Logic input for enabling and disabling the LDO3 linear regulator. Positive logic input.
Frequency control input for SMPS1. Connect a resistor to ground to program the switching frequency. The pin output is
a pulsed current and requires a decoupling capacitor to average the signal.
SMPS1 feedback input used for output voltage programming and regulation.
Input from DCR current-sensing network used to program the overcurrent shutdown threshold for SMPS1.
Logic input to enable and disable SMPS1. A logic high will immediately enable SMPS1. Floating this pin will enable
SMPS1 only after SMPS2 has been enabled and achieved regulation. A logic low disables SMPS1.
3.3V linear regulator output, capable of providing 100mA continuous current. Bypass to ground with a 4.7µF ceramic capacitor.
Feed-forward input for line voltage transient compensation. Connect to the power train input voltage.
Logic input to enable and disable SMPS2. A logic high will immediately enable SMPS2. Floating this pin will enable
SMPS2 only after SMPS1 has been enabled and achieved regulation. A logic low disables SMPS2.
Input from DCR current-sensing network used to program the overcurrent shutdown threshold for SMPS2.
Page 6 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Typical Application Circuits
The typical application circuits generate the 5V/8A and 3.3V/8A (system regulator), or 1.05V/15A and 1.5V/15A (chip set) supplies
in a notebook computer. The input supply (VBAT) range is 5.5V to 25V.
VBAT
4x10µF
BO OT1
0.22µF
4.7µH
3 .3 V
330µF
IRF7821
V IN
BOO T2
UGATE1
UGATE2
PHASE1
PHASE2
LGATE1
LG ATE2
OCSET1
OCSET2
0.22µF
IRF7821
5V
330µF
14k 0.022µF
0.022µF 14k
IRF7832
IRF7832
14k
4.7µH
750
45.3k
1200pF
14k
IS E N 1
IS E N 2
VOUT1
VOUT2
68.1k
1200pF
FB2
FB1
9.09k
ISL62391, ISL62392
ISL62391C, ISL62392C
10k
750
100k
PGOOD
LDO3
4.7µF
PVCC
EN1
EN2
LD O 3EN
FCCM
FSET1
FSET2
PVCC
1µF
VCC
1µF
PGND
0.01µF
24.3k
PAD
19.6k
0.01µF
FIGURE 1. TYPICAL SYSTEM REGULATOR APPLICATION CIRCUIT WITH INDUCTOR DCR CURRENT SENSE
VBAT
BO OT1
4x10µF
0.22µF
4.7µH
3 .3 V
0.001
330µF
1k
V IN
BO O T2
IRF7821
IRF7821
UG ATE1
UG ATE2
PHASE1
PHASE2
4.7µH
5V
0.001
IRF7832
IRF7832
1k
0.22µF
LGATE1
LG ATE2
OCSET1
OCSET2
330µF
1k
1k
750
750
1200pF 45.3k
IS E N 1
IS E N 2
VO UT1
VOUT2
FB1
1200pF
FB2
9.09k
ISL62391, ISL62392
ISL62391C, ISL62392C
10k
68.1k
100k
PGOOD
PVCC
EN1
EN2
3 .3 V
LDO 3
LDO 3EN
4.7µF
FCCM
FSET1
FSET2
PVCC
1µF
1µF
VCC
PGND
GND
24.3k
19.6k
0.01µF
0.01µF
FIGURE 2. TYPICAL SYSTEM REGULATOR APPLICATION CIRCUIT WITH RESISTOR SENSE
FN6666 Rev 8.00
August 25, 2015
Page 7 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Typical Application Circuits (Continued)
VBAT
4x10µF
BO O T1
0.22µF
IRF7821
2x
2.2µH
1 .0 5 V
2x330µF
V IN
BO O T2
UG ATE1
UGATE2
PHASE1
PHASE2
0.22µF
IRF7821
2x
0.022µF 14k
IRF7832
2x
14k
590
LGATE2
OCSET1
OCSET2
14k
2x
IRF7832
1 .5 V
2x330µF
0.022µF
14k
36.5k
1800pF
LGATE1
2.2µH
IS E N 1
IS E N 2
VO UT1
VOUT2
36.5k
1800pF
FB2
FB1
24.3k
ISL62391, ISL62392
ISL62391C, ISL62392C
48.7k
590
100k
PGOOD
LDO3
4.7µF
PVCC
EN1
EN2
LDO 3EN
FCCM
FSET1
FSET2
PVCC
1µF
VCC
1µF
PGND
17.4k
PAD
14k
0.01µF
0.01µF
FIGURE 3. TYPICAL CHIP SET APPLICATION CIRCUIT WITH INDUCTOR DCR CURRENT SENSE
VBAT
BO OT1
4x10µF
0.22µF
2x
2.2µH
1 .0 5 V
0.001
2x330µF
1k
BO O T2
IRF7821
UG ATE1
UGATE2
PHASE1
PHASE2
IRF7832
2x
1k
0.22µF
2x
2.2µH
0.001
2x330µF
IRF7832
LGATE1
LG ATE2
OCSET1
OCSET2
1 .5 V
2x
1k
1k
590
590
1800pF
V IN
IRF7821
36.5k
IS E N 1
IS E N 2
VOUT1
VOUT2
FB1
36.5k
FB2
24.3k
ISL62391, ISL62392
ISL62391C, ISL62392C
48.7k
1800pF
100k
PGOOD
PVCC
EN1
EN2
3 .3 V
LDO3
LDO 3EN
4.7µF
FCCM
FSET1
FSET2
PVCC
1µF
1µF
VCC
PGND
17.4k
GND
14k
0.01µF
0.01µF
FIGURE 4. TYPICAL CHIP SET APPLICATION CIRCUIT WITH RESISTOR SENSE
FN6666 Rev 8.00
August 25, 2015
Page 8 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Block Diagram
VIN
VOUT2*
FSET1/2
4.8V
5V
LDO
FB1/2
R3
MODULATOR
VREF
PVCC
0.6V
BOOT1/2
FCCM
PWM
VOUT1/2
UGATE
DRIVER
UGATE1/2
PHASE1/2
SOFT DISCHARGE
LGATE
DRIVER
LGATE1/2
PGND
EN1
PGOOD
START-UP
AND
SHUTDOWN
LOGIC
EN2
LDO3EN
VCC
BIAS AND
REFERENCE
10µA
OCSET1/2
OCP
T-PAD
PROTECTION LOGIC
OVP/UVP/OCP/OTP
ISEN1/2
VREF + 16%
PVCC
UVP
3.3V
LDO
FB1/2
LDO3
OVP
VREF - 16%
THERMAL
MONITOR
SOFT DISCHARGE
*In addition to being used for regulation, VOUT2 will also provide power for PVCC when it is programmed to 5V.
FN6666 Rev 8.00
August 25, 2015
Page 9 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Typical Performance Curves
100
95
100
VIN = 7V
95
90
VIN = 12V
85
EFFICIENCY (%)
EFFICIENCY (%)
VIN = 7V
90
VIN = 19V
80
75
70
65
80
70
65
60
55
55
1.00
10.00
VIN = 19V
75
60
50
0.10
VIN = 12V
85
50
0.01
0.10
1.00
FIGURE 5. CHANNEL 1 EFFICIENCY AT VO = 3.3V, DEM
OPERATION. HIGH-SIDE 1xIRF7821,
rDS(ON) = 9.1m; LOW-SIDE 1xIRF7832,
rDS(ON) = 4m; L = 4.7µH, DCR = 14.3m; CCM
FSW = 270kHz
10.00
IOUT (A)
IOUT (A)
FIGURE 6. CHANNEL 2 EFFICIENCY AT VO = 5V, DEM
OPERATION. HIGH-SIDE 1xIRF7821,
rDS(ON) = 9.1m; LOW-SIDE 1xIRF7832,
rDS(ON) = 4m; L = 4.7µH, DCR = 14.3m; CCM
FSW = 330kHz
VO1
VO1
FB1
FB1
PGOOD
PGOOD
PHASE1
FIGURE 7. POWER-ON, VIN = 12V, LOAD = 5A, VO = 3.3V
VO1
FB1
PGOOD
PHASE1
FIGURE 8. POWER-OFF, VIN = 12V, IO = 5A, VO = 3.3V
VO1
FB1
PGOOD
EN1
EN1
FIGURE 9. ENABLE CONTROL, EN1 = HIGH, VIN = 12V,
VO = 3.3V, IO = 5A
FN6666 Rev 8.00
August 25, 2015
FIGURE 10. ENABLE CONTROL, EN1 = LOW, VIN = 12V,
VO = 3.3V, IO = 5A
Page 10 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Typical Performance Curves (Continued)
VO1
PHASE1
VO2
PHASE2
FIGURE 11. CCM STEADY-STATE OPERATION, VIN = 12V,
VO1 = 3.3V, IO1 = 5A, VO2 = 5V, IO2 = 5A
VO1
VO1
PHASE1
VO2
PHASE2
FIGURE 12. DCM STEADY-STATE OPERATION, VIN = 12V,
VO1 = 3.3V, IO1 = 0. 2A, VO2 = 5V, IO2 = 0.2A
VO1
PHASE1
PHASE1
VO2
PHASE2
FIGURE 13. AUDIO FILTER OPERATION, VIN = 12V,
VO1 = 3.3V, VO2 = 5V, NO LOAD
IO1
FIGURE 14. TRANSIENT RESPONSE, VIN = 12V, VO = 3.3V,
IO = 0.1A/8.1A @ 2.5A/µs
VO1
VO1
PHASE1
IO1
FIGURE 15. LOAD INSERTION RESPONSE, VIN = 12V,
VO = 3.3V, IO = 0.1A/8.1A @ 2.5A/µs
FN6666 Rev 8.00
August 25, 2015
PHASE1
IO1
FIGURE 16. LOAD RELEASE RESPONSE, VIN = 12V,
VO = 3.3V, IO = 0.1A/8.1A @ 2.5A/µs
Page 11 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Typical Performance Curves (Continued)
EN1
EN2
VO1
VO1
VO2
VO2
FIGURE 17. DELAYED START, VIN = 12V, VO1 = 3.3V, VO2 = 5V,
EN2 = FLOAT, NO LOAD
VO1
FIGURE 18. DELAYED START, VIN = 12V, VO1 = 3.3V, VO2 = 5V,
EN1 = FLOAT, NO LOAD
VO1
PGOOD
IO1
VO2
PGOOD
FIGURE 19. DELAYED START, VIN = 12V, VO1 = 3.3V, VO2 = 5V,
EN1 = 1, EN2 = FLOAT, NO LOAD
VO1
UGATE1-PHASE1
FIGURE 20. OVERCURRENT PROTECTION, VIN = 12V,
VO = 3.3V
VO1
UGATE1-PHASE1
LGATE1
LGATE1
PGOOD
PGOOD
FIGURE 21. CROWBAR OVERVOLTAGE PROTECTION,
VIN = 12V, VO = 3.3V, NO LOAD
FN6666 Rev 8.00
August 25, 2015
FIGURE 22. TRI-STATE OVERVOLTAGE PROTECTION,
VIN = 12V, VO = 3.3V, NO LOAD
Page 12 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Theory of Operation
Three Output Controller
The ISL62391, ISL62392, ISL62391C and ISL62392C generate
three regulated output voltages. Two are produced with switchmode power supplies (SMPS), and the third by a low dropout
linear regulator (LDO). An additional 5V LDO (PVCC) is used to
power the chip during operation, allowing the ISL62391,
ISL62392, ISL62391C and ISL62392C to regulate all outputs
from a single power source (VIN) with no need for a separate
quiescent supply. This makes the ISL62391, ISL62392,
ISL62391C and ISL62392C an ideal choice as system regulator
for notebook PCs. Because the two SMPS channels are
identical and almost entirely independent, all conclusions drawn
apply to both channels unless otherwise noted.
(EQ. 3)
V W = g m  V OUT   1 – D   R W
The frequency can be expressed in Equation 4:
Modulator and Switching Frequency
The ISL62391, ISL62392, ISL62391C and ISL62392C
modulator feature Intersil’s R3 technology, a hybrid of fixed
frequency PWM and variable frequency hysteretic control.
Intersil’s R3 technology can simultaneously affect the PWM
switching frequency and PWM duty cycle in response to input
voltage and output load transients. The R3 modulator
synthesizes an AC signal, VR, which is an analog
representation of the output inductor ripple current. The dutycycle of VR is the result of charge and discharge current
through a ripple capacitor, CR. The current through CR is
provided by a transconductance amplifier that measures the
VIN and VO pin voltages. The positive slope of VR can be
written as Equation 1:
(EQ. 1)
V RPOS = g m   V IN – V OUT 
The negative slope of VR can be written as Equation 2:
V RNEG = g m  V OUT
(EQ. 2)
Where gm is the gain of the transconductance amplifier.
RIPPLE CAPACITOR VOLTAGE CR
A window voltage VW is referenced with respect to the error
amplifier output voltage VCOMP, creating an envelope into
which the ripple voltage VR is compared. The amplitude of VW
is set by a resistor, RW, connected across the FSET and GND
pins. The VR, VCOMP, and VW signals feed into a window
comparator in which VCOMP is the lower threshold voltage and
VW is the higher threshold voltage. Figure 23 shows PWM
pulses being generated as VR traverses the VW and VCOMP
thresholds. The PWM switching frequency is proportional to
the slew rates of the positive and negative slopes of VR; it is
inversely proportional to the voltage between VW and VCOMP.
Equation 3 illustrates how to calculate the window size based
on output voltage and frequency set resistor.
WINDOW VOLTAGE VW
(WRT VCOMP)
1
F SW = -----------------K  RW
(EQ. 4)
Inverting Equation 4 allows easy selection of RW for a desired
FSW:
1
R W = --------------------K  F SW
(EQ. 5)
For Equations 3 through 5:
gm = 1.66µs
K = 1.7 x 10-10 (±20%)
D = VOUT/VIN
Power-On Reset
The ISL62391, ISL62392, ISL62391C and ISL62392C are
disabled until the voltage at the VIN pin has increased above
the rising power-on reset (POR) threshold. Conversely, the
controller will be disabled when the voltage at the VIN pin
decreases below the falling POR threshold.
In addition to VIN POR, the PVCC pin is also monitored. If its
voltage falls below 4.2V, the SMPS outputs will be shut down.
This ensures that there is sufficient BOOT voltage to enhance
the upper MOSFET.
EN, Soft-Start and PGOOD
ERROR AMPLIFIER
VOLTAGE VCOMP
PWM
FIGURE 23. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
FN6666 Rev 8.00
August 25, 2015
The ISL62391, ISL62392, ISL62391C and ISL62392C use a
digital soft-start circuit to ramp the output voltage of each
SMPS to the programmed regulation setpoint at a predictable
slew rate. The slew rate of the soft-start sequence has been
selected to limit the in-rush current through the output
capacitors as they charge to the desired regulation voltage.
When the EN pins are pulled above their rising thresholds, the
PGOOD Soft-Start Delay, tSS, starts and the output voltage
begins to rise. The FB pin ramps to 0.6V in approximately 1.5ms
and the PGOOD pin goes to high impedance approximately
1.25ms after the FB pin voltage reaches 0.6V.
Page 13 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
1.5ms
VO
tSOFTSTART
VCC AND PVCC
EN
above the 4.2V VCC POR threshold, VCC will switchover to
PVCC internally.
After VIN is applied, the VCC start-up 3.6V voltage can be used
as the logic high signal of any of EN1, EN2 and LDO3EN to
enable PVCC if there is no other power supply on the board.
MOSFET Gate-Drive Outputs LGATE and UGATE
FB
PGOOD
2.75ms
PGOOD DELAY
FIGURE 24. SOFT-START SEQUENCE FOR ONE SMPS
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. It is an undefined impedance if VIN
is not above the rising POR threshold or below the POR falling
threshold. When a fault is detected, the ISL62391, ISL62392,
ISL62391C and ISL62392C will turn on the open-drain NMOS,
which will pull PGOOD low with a nominal impedance of 32
This will flag the system that one of the output voltages is out of
regulation.
Separate enable pins allow for full soft-start sequencing.
Because low shutdown quiescent current is necessary to
prolong battery life in notebook applications, the PVCC 5V LDO
is held off until any of the three enable signals (EN1, EN2 or
LDO3EN) are pulled high. Soft-start of all outputs will only start
until after PVCC is above the 4.2V POR threshold. In addition to
user-programmable sequencing, the ISL62391, ISL62392,
ISL62391C and ISL62392C include a pre-programmed
sequential SMPS soft-start feature. Table 1 shows the SMPS
enable truth table.
The ISL62391, ISL62392, ISL62391C and ISL62392C have
internal gate-drivers for the high-side and low-side N-Channel
MOSFETs. The low-side gate-drivers are optimized for low
duty-cycle applications where the low-side MOSFET
conduction losses are dominant, requiring a low r DS(ON)
MOSFET. The LGATE pull-down resistance is small in order to
clamp the gate of the MOSFET below the VGS(th) at turn-off. The
current transient through the gate at turn-off can be considerable
because the gate charge of a low r DS(ON) MOSFET can be large.
Adaptive shoot-through protection prevents a gate-driver output
from turning on until the opposite gate-driver output has fallen
below approximately 1V. The dead-time shown in Figure 25 is
extended by the additional period that the falling gate voltage
stays above the 1V threshold. The typical dead-time is 21ns. The
high-side gate-driver output voltage is measured across the
UGATE and PHASE pins while the low-side gate-driver output
voltage is measured across the LGATE and PGND pins. The
power for the LGATE gate-driver is sourced directly from the
PVCC pin. The power for the UGATE gate-driver is sourced from
a “boot” capacitor connected across the BOOT and PHASE pins.
The boot capacitor is charged from the 5V PVCC supply through
a “boot diode” each time the low-side MOSFET turns on, pulling
the PHASE pin low. The ISL62391, ISL62392, ISL62391C and
ISL62392C have integrated boot diodes connected from the
PVCC pins to BOOT pins.
TABLE 1. SMPS ENABLE SEQUENCE LOGIC
EN1
EN2
0
0
All SMPS outputs OFF
0
FLOAT
All SMPS outputs OFF
0
1
SMPS1 OFF, SMPS2 ON
FLOAT
0
All SMPS outputs OFF
FLOAT
FLOAT
All SMPS outputs OFF
FLOAT
1
SMPS1 enables after SMPS2 is in regulation
1
0
SMPS1 ON, SMPS2 OFF
1
FLOAT
1
1
tLGFUGR
START-UP SEQUENCE
tUGFLGR
50%
UGATE
LGATE
50%
SMPS2 enables after SMPS1 is in regulation
All SMPS outputs ON simultaneously
FIGURE 25. LGATE AND UGATE DEAD-TIME
VCC
The VCC nominal operation voltage is 5V. If EN1, EN2 and
LDO3EN are all logic low, the VCC start-up voltage is 3.6V
when VIN is applied on ISL62391, ISL62392, ISL62391C and
ISL62392C. PVCC is held off until any of the three enable
signals (EN1, EN2 or LDO3EN) is pulled high. When PVCC is
FN6666 Rev 8.00
August 25, 2015
Diode Emulation
FCCM is a logic input that controls the power state of the
ISL62391, ISL62392, ISL62391C and ISL62392C. If forced
high, the ISL62391, ISL62392, ISL62391C and ISL62392C will
operate in forced continuous-conduction-mode (CCM) over the
entire load range. This will produce the best transient response
Page 14 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
to all load conditions, but will have increased light-load power
loss. If FCCM is forced low, the ISL62391, ISL62392,
ISL62391C and ISL62392C will automatically operate in Diode
Emulation Mode (DEM) at light load to optimize efficiency in the
entire load range. The transition is automatically achieved by
detecting the load current and turning off LGATE when the
inductor current reaches 0A.
allow DEM at light loads, but will prevent the switching
frequency from going below ~28kHz to prevent noise injection
to the audio band. A timer is reset each PWM pulse. If the
timer exceeds 30µs, LGATE is turned on, causing the ramp
voltage to reduce until another UGATE is commanded by the
voltage loop.
Positive-going inductor current flows from either the source of
the high-side MOSFET, or the drain of the low-side MOSFET.
Negative-going inductor current flows into the drain of the lowside MOSFET. When the low-side MOSFET conducts positive
inductor current, the phase voltage will be negative with
respect to the GND and PGND pins. Conversely, when the
low-side MOSFET conducts negative inductor current, the
phase voltage will be positive with respect to the GND and
PGND pins. The ISL62391, ISL62392, ISL62391C and
ISL62392C monitor the phase voltage when the low-side
MOSFET is conducting inductor current to determine its
direction.
The overcurrent protection (OCP) setpoint is programmed with
resistor, ROCSET, that is connected across the OCSET and
PHASE pins.
When the output load current is greater than or equal to ½ the
inductor ripple current, the inductor current is always positive,
and the converter is always in CCM. The ISL62391, ISL62392,
ISL62391C and ISL62392C minimize the conduction loss in
this condition by forcing the low-side MOSFET to operate as a
synchronous rectifier.
When the output load current is less than ½ the inductor ripple
current, negative inductor current occurs. Sinking negative
inductor through the low-side MOSFET lowers efficiency
through unnecessary conduction losses. The ISL62391,
ISL62392, ISL62391C and ISL62392C automatically enter
DEM after the PHASE pin has detected positive voltage and
LGATE was allowed to go high for 8 consecutive PWM
switching cycles. The ISL62391, ISL62392, ISL62391C and
ISL62392C will turn off the low-side MOSFET once the phase
voltage turns positive, indicating negative inductor current. The
ISL62391, ISL62392, ISL62391C and ISL62392C will return to
CCM on the following cycle after the PHASE pin detects
negative voltage, indicating that the body diode of the low-side
MOSFET is conducting positive inductor current.
Efficiency can be further improved with a reduction of
unnecessary switching losses by reducing the PWM frequency.
It is characteristic of the R3 architecture for the PWM
frequency to decrease while in diode emulation. The extent of
the frequency reduction is proportional to the reduction of load
current. Upon entering DEM, the PWM frequency makes an
initial step-reduction because of a 33% step-increase of the
window voltage V W.
Because the switching frequency in DEM is a function of load
current, very light load conditions can produce frequencies well
into the audio band. This can be problematic if audible noise is
coupled into audio amplifier circuits. To prevent this from
occurring, the ISL62391, ISL62392, ISL62391C and
ISL62392C allow the user to float the FCCM input. This will
FN6666 Rev 8.00
August 25, 2015
Overcurrent Protection
L
DCR
IL
PHASE1
+
ROCSET
ISL62391,
ISL62392
10µA
OCSET1
+ VROCSET
VDCR
CSEN
VO
_
CO
_
RO
ISEN1
FIGURE 26. OVERCURRENT-SET CIRCUIT
Figure 26 shows the overcurrent-set circuit for SMPS1. The
inductor consists of inductance L and the DC resistance
(DCR). The inductor DC current IL creates a voltage drop
across DCR, which is given by Equation 6:
(EQ. 6)
V DCR = I L  DCR
The ISL62391, ISL62392, ISL62391C and ISL62392C sink a
10µA current into the OCSET1 pin, creating a DC voltage drop
across the resistor ROCSET, which is given by Equation 7:
(EQ. 7)
V ROCSET = 10A  R OCSET
Resistor RO is connected between the ISEN1 pin and the
actual output voltage of the converter. During normal
operation, the ISEN1 pin is a high impedance path, therefore
there is no voltage drop across RO. The DC voltage difference
between the OCSET1 pin and the ISEN1 pin can be
established using Equation 8:
V OCSET1 – V ISEN1 = I L  DCR – 10A  R OCSET
(EQ. 8)
The ISL62391, ISL62392, ISL62391C and ISL62392C monitor
the OCSET1 pin and the ISEN1 pin voltages. Once the
OCSET1 pin voltage is higher than the ISEN1 pin voltage for
more than 10µs, the ISL62391, ISL62392, ISL62391C and
ISL62392C declare an OCP fault. The value of ROCSET is then
written as Equation 9:
I OC  DCR
R OCSET = --------------------------10A
(EQ. 9)
Page 15 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Where:
- ROCSET () is the resistor used to program the
overcurrent setpoint
- IOC is the output current threshold that will activate the
OCP circuit
- DCR is the inductor DC resistance
For example, if IOC is 20A and DCR is 4.5m, the choice of
ROCSET is ROCSET = 20A x 4.5m/10µA = 9k
Resistor ROCSET and capacitor CSEN form an R-C network to
sense the inductor current. To sense the inductor current
correctly, not only in DC operation but also during dynamic
operation, the R-C network time constant ROCSET-CSEN
needs to match the inductor time constant L/DCR. The value of
CSEN is then written as Equation 10:
L
C SEN = ----------------------------------------R OCSET  DCR
(EQ. 10)
For example, if L is 1.5µH, DCR is 4.5m, and ROCSET is 9k
the choice of CSEN = 1.5µH/(9kx 4.5m) = 0.037µF
Upon converter start-up, the CSEN capacitor bias is 0V. To
prevent false OCP during this time, a 10µA current source
flows out of the ISEN1 pin, generating a voltage drop on the
RO resistor, which should be chosen to have the same
resistance as ROCSET. When the PGOOD pin goes high, the
ISEN1 pin current source will be removed.
When an OCP fault is declared, the PGOOD pin will pull-down
to 32and latch-off the converter. The fault will remain latched
until the EN pin has been pulled below the falling EN threshold
voltage, or until VIN has decayed below the falling POR
threshold.
When using a discrete current sense resistor, inductor
time-constant matching is not required. Equation 7 remains
unchanged, but Equation 8 is modified in Equation 11:
V OCSET1 – V ISEN1 = I L  R SENSE – 10A  R OCSET
(EQ. 11)
Furthermore, Equation 9 is changed in Equation 12:
I OC  R SENSE
R OCSET = ------------------------------------10A
Although latched, the ISL62392 and ISL62392C LGATE gatedriver output will retain the ability to toggle the low-side
MOSFET on and off in response to the output voltage
transversing the OVP rising and falling thresholds. The LGATE
gate-driver will turn on the low-side MOSFET to discharge the
output voltage, thus protecting the load from potentially
damaging voltage levels. The LGATE gate-driver will turn off the
low-side MOSFET once the FB pin voltage is lower than the
falling overvoltage threshold for more than 2µs. The falling
overvoltage threshold is typically 106% of the reference voltage,
or 1.06*0.6V = 0.636V. This soft-crowbar process repeats as
long as the output voltage fault is present, allowing the ISL62392
and ISL62392C to protect against persistent overvoltage
conditions.
Undervoltage Protection
The UVP fault detection circuit triggers after the FB pin voltage is
below the undervoltage threshold for more than 2µs. The
undervoltage threshold is typically 86% of the reference voltage,
or 0.86*0.6V = 0.516V. If a UVP fault is declared, the PGOOD
pin will pull-down with 32and latch-off the converter. The fault
will remain latched until the EN pin has been pulled below the
falling enable threshold, or if VIN has decayed below the falling
POR threshold.
Programming the Output Voltage
When the converter is in regulation, there will be 0.6V between
the FB and GND pins. Connect a two-resistor voltage divider
across the OUT and GND pins with the output node connected
to the FB pin, as shown in Figure 27. Scale the voltage-divider
network such that the FB pin is 0.6V with respect to the GND
pin when the converter is regulating at the desired output
voltage. The output voltage can be programmed from 0.6V to
5.5V.
Programming the output voltage is written as Equation 13:
(EQ. 12)
Where RSENSE is the series power resistor for sensing
inductor current. For example, with an RSENSE = 1m and an
OCP target of 10A, ROCSET = 1k
Overvoltage Protection
The OVP fault detection circuit triggers after the FB pin voltage
is above the rising overvoltage threshold for more than 2µs.
The FB pin voltage is 0.6V in normal operation. The rising
overvoltage threshold is typically 116% of that value, or
1.16*0.6V = 0.696V.
For ISL62391, ISL62392, ISL62391C and ISL62392C, when an
OVP fault is declared, the PGOOD pin will pull-down with 32
and latch-off the converter. The OVP fault will remain latched
FN6666 Rev 8.00
August 25, 2015
until the EN pin has been pulled below the falling EN threshold
voltage, or until VIN has decayed below the falling POR
threshold. During the latch condition, the ISL62391 and
ISL62391C will tri-state the PHASE node by turning both
UGATE and LGATE off until the latch is cleared.
R TOP 

V OUT = V REF   1 + -----------------------------
R

BOTTOM
(EQ. 13)
Where:
- VOUT is the desired output voltage of the converter
- The voltage to which the converter regulates the FB pin is
the VREF (0.6V)
- RTOP is the voltage-programming resistor that connects
from the FB pin to the converter output. In addition to
setting the output voltage, this resistor is part of the loop
compensation network
- RBOTTOM is the voltage-programming resistor that
connects from the FB pin to the GND pin
Choose RTOP first when compensating the control loop, and
then calculate RBOTTOM according to Equation 14:
Page 16 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
V REF  R
TOP
R BOTTOM = ------------------------------------V OUT – V REF
(EQ. 14)
General Application Design Guide
Compensation Design
Figure 27 shows the recommended Type-II compensation circuit.
The FB pin is the inverting input of the error amplifier. The COMP
signal, the output of the error amplifier, is inside the chip and
unavailable to users. CINT is a 100pF capacitor integrated inside
the IC that connects across the FB pin and the COMP signal.
RTOP, RFB, CFB and CINT form the Type-II compensator. The
frequency domain transfer function is given by Equation 15:
1 + s   R TOP + R FB   C
FB
G COMP  s  = ------------------------------------------------------------------------------------------s  R TOP  C INT   1 + s  R FB  C 
CFB
RFB
VO
FB
EA
RBOTTOM
COMP
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as
Equation 16:
VO
D = --------V IN
RTOP
-
This design guide is intended to provide a high-level explanation
of the steps necessary to design a single-phase power
converter. It is assumed that the reader is familiar with many of
the basic skills and techniques referenced in the following
section. In addition to this guide, Intersil provides complete
reference designs that include schematics, bills of materials, and
example board layouts.
Selecting the LC Output Filter
(EQ. 15)
FB
CINT = 100pF
power dissipation. The outputs will remain off until the junction
temperature has fallen below +135°C.
+
REF
ISL62391, ISL62392
FIGURE 27. COMPENSATION REFERENCE CIRCUIT
The LC output filter has a double pole at its resonant frequency
that causes rapid phase change. The R3 modulator used in the
ISL62391, ISL62392, ISL62391C and ISL62392C make the LC
output filter resemble a first order system in which the closed loop
stability can be achieved with the recommended Type-II
compensation network. Intersil provides a PC-based tool
(example page is shown later) that can be used to calculate
compensation network component values and help simulate
the loop frequency response.
3.3V Linear Regulator
In addition to the two SMPS outputs, the ISL62391, ISL62392,
ISL62391C and ISL62392C also provide a fixed 3.3V LDO output
(LDO3) capable of sourcing 100mA continuous current. LDO3
draws its power from PVCC and can be independently enabled
from both SMPS channels.
LDO3 also has a current limit feature with a nominal level of
180mA. Currents in excess of the limit will cause the LDO3
voltage to drop dramatically, limiting the power dissipation.
(EQ. 16)
The output inductor peak-to-peak ripple current is written as
Equation 17:
VO   1 – D 
I PP = -----------------------------f SW  L
A typical step-down DC/DC converter will have an IP-P of 20%
to 40% of the maximum DC output load current. The value of
IP-P is selected based upon several criteria, such as MOSFET
switching loss, inductor core loss, and the resistive loss of the
inductor winding. The DC copper loss of the inductor can be
estimated by Equation 18:
P COPPER = I LOAD
2

(EQ. 18)
DCR
Where ILOAD is the converter output DC current.
The copper loss can be significant so attention has to be given
to the DCR selection. Another factor to consider when
choosing the inductor is its saturation characteristics at
elevated temperature. A saturated inductor could cause
destruction of circuit components, as well as nuisance OCP
faults.
A DC/DC buck regulator must have output capacitance CO into
which ripple current IP-P can flow. Current IP-P develops a
corresponding ripple voltage VP-P across CO, which is the sum
of the voltage drop across the capacitor ESR and of the voltage
change stemming from charge moved in and out of the
capacitor. These two voltages are written as Equation 19:
V ESR = I P-P  E SR
Thermal Monitor and Protection
and Equation 20:
LDO3 and PVCC LDOs can dissipate non-trivial power inside the
ISL62391, ISL62392, ISL62391C and ISL62392C at high inputto-output voltage ratios and full load conditions. To protect the
silicon, ISL62391, ISL62392, ISL62391C and ISL62392C
continually monitor the die temperature. If the temperature
exceeds +150°C, all outputs will be turned off to sharply curtail
I P-P
V C = ----------------------------8  CO  f
FN6666 Rev 8.00
August 25, 2015
(EQ. 17)
(EQ. 19)
(EQ. 20)
SW
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled to
reduce the total ESR until the required VP-P is achieved. The
inductance of the capacitor can cause a brief voltage dip if the
Page 17 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
load transient has an extremely high slew rate. Low inductance
capacitors should be considered in this scenario. A capacitor
dissipates heat as a function of RMS current and frequency. Be
sure that IP-P is shared by a sufficient quantity of paralleled
capacitors so that they operate below the maximum rated RMS
current at fSW. Take into account that the rated value of a
capacitor can fade as much as 50% as the DC voltage across it
increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25x greater than the
maximum input voltage, while a voltage rating of 1.5x is a
preferred rating. Figure 28 is a graph of the input RMS ripple
current (normalized relative to output load current) as a function
of duty cycle and is adjusted for a converter efficiency of 80%.
The ripple current calculation is written as Equation 21:
2
I IN_RMS NORMALIZED =
2
x
 D – D  +  D  ------ 
 12 
(EQ. 21)
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum VDS rating that exceeds the sum of the upper
voltage tolerance of the input power source and the voltage
spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low gate charge so that the
device spends the least amount of time dissipating power in
the linear region. Unlike the low-side MOSFET, which has the
drain-source voltage clamped by its body diode during turn off,
the high-side MOSFET turns off with a VDS of approximately
VIN - VOUT, plus the spike across it. The preferred low-side
MOSFET emphasizes low r DS(ON) when fully saturated to
minimize conduction loss. It should be noted that this is an
optimal configuration of MOSFET selection for low duty cycle
applications (D < 50%). For higher output, low input voltage
solutions, a more balanced MOSFET selection for high- and
low-side devices may be warranted.
For the low-side (LS) MOSFET, the power loss can be assumed
to be conductive only and is written as Equation 23:
Where:
- IMAX is the maximum continuous ILOAD of the converter
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a percentage
of IMAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account the
efficiency of the converter which is written as Equation 22.
VO
D = -------------------------V IN  EFF
(EQ. 22)
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain of
the high-side MOSFET and the source of the low-side
MOSFET.
2
P CON_LS  I LOAD  r DS  ON _LS   1 – D 
(EQ. 23)
For the high-side (HS) MOSFET, the conduction loss is written
as Equation 24:
P CON_HS = I LOAD
2

r DS  ON _HS  D
(EQ. 24)
For the high-side MOSFET, the switching loss is written as
Equation 25:
V IN  I VALLEY  t ON  f
V IN  I PEAK  t OFF  f
SW
SW
P SW_HS = ----------------------------------------------------------------- + ------------------------------------------------------------2
2
(EQ. 25)
NORMALIZED INPUT RMS RIPPLE CURRENT
Where:
- IVALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- IPEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- tON is the time required to drive the device into saturation
- tOFF is the time required to drive the device into cut-off
0.60
0.55
0.50
0.45
0.40
0.35
0.30
x=1
x = 0.75
x = 0.50
x = 0.25
x=0
0.25
0.20
0.15
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as Equation
26:
0.10
Qg
C BOOT = -----------------------V BOOT
0.05
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
(EQ. 26)
1.0
DUTY CYCLE
FIGURE 28. NORMALIZED RMS INPUT CURRENT
FN6666 Rev 8.00
August 25, 2015
Page 18 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Where:
- Qg is the total gate charge required to turn on the
high-side MOSFET
- VBOOT, is the maximum allowed voltage decay across
the boot capacitor each time the high-side MOSFET is
switched on
As an example, suppose the high-side MOSFET has a total
gate charge Qg, of 25nC at VGS = 5V, and a VBOOT of
200mV. The calculated bootstrap capacitance is 0.125µF; for a
comfortable margin, select a capacitor that is double the
calculated capacitance. In this example, 0.22µF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of the
PCB and weak analog or logic signals are on the top layer of
the PCB. The ground-plane layer should be adjacent to the top
layer to provide shielding. The ground plane layer should have
an island located under the IC, the compensation components,
and the FSET components. The island should be connected to
the rest of the ground plane layer at one point.
VIAS TO
VIAS TO
GROUND
GROUND
PLANE
GND
GND
PLANE
VOUT
INDUCTOR
INDUCTOR
HIGH-SIDE
HIGH-SIDE
MOSFETS
MOSFETS
PHASE
PHASE
NODE
NODE
VIN
VIN
L2
PIN 18 (PVCC)
PIN 4 (VCC)
L2 U2
ISL6239
Ci
LINE OF SYMMETRY
Ci
L1 U1
PGND PLANE
PHASE PLANES
VOUT PLANES
VIN PLANE
L1
Co
FIGURE 30. SYMMETRIC LAYOUT GUIDE
VIN (Pin 17)
The VIN pin should be connected close to the drain of the highside MOSFET, using a low resistance and low inductance path.
VCC (Pin 4)
OUTPUT
OUTPUT
CAPACITORS
CAPACITORS
SCHOTTKY
SCHOTTKY
DIODE
DIODE
LOW-SIDE
LOW-SIDE
MOSFETS
MOSFETS
INPUT
INPUT
CAPACITORS
CAPACITORS
FIGURE 29. TYPICAL POWER COMPONENT PLACEMENT
Because there are two SMPS outputs and only one PGND pin,
the power train of both channels should be laid out
symmetrically. The line of bilateral symmetry should be drawn
through pins 4 and 18. This layout approach ensures that the
controller does not favor one channel over another during
critical switching decisions. Figure 29 illustrates one example
of how to achieve proper bilateral symmetry.
Signal Ground and Power Ground
The bottom of the ISL62391, ISL62392, ISL62391C and
ISL62392C TQFN package is the signal ground (GND)
terminal for analog and logic signals of the IC. Connect the
GND pad of the ISL62391, ISL62392, ISL62391C and
ISL62392C to the island of ground plane under the top layer
using several vias for a robust thermal and electrical
conduction path. Connect the input capacitors, the output
capacitors, and the source of the lower MOSFETs to the power
ground plane.
PGND (Pin 19)
This is the return path for the pull-down of the LGATE low-side
MOSFET gate driver. Ideally, PGND should be connected to
the source of the low-side MOSFET with a low-resistance, lowinductance path.
FN6666 Rev 8.00
August 25, 2015
Co
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
PVCC (Pin 18)
For best performance, place the decoupling capacitor very
close to the PVCC and respective PGND pin, preferably on the
same side of the PCB as the ISL62391, ISL62392, ISL62391C
and ISL62392C ICs.
EN (Pins 11 and 24), and PGOOD (Pin 1)
These are logic signals that are referenced to the GND pin.
Treat as a typical logic signal.
OCSET (Pins 10 and 25) and ISEN (Pins 9 and 26)
For DCR current sensing, the current-sense network,
consisting of ROCSET and CSEN, needs to be connected to the
inductor pads for accurate measurement. Connect ROCSET to
the phase-node side pad of the inductor, and connect CSEN to
the output side pad of the inductor. The ISEN resistor should
also be connected to the output pad of the inductor with a
separate trace. Connect the OCSET pin to the common node
of node of ROCSET and CSEN.
For resistive current sensing, connect ROCSET from the
OCSET pin to the inductor side of the resistor pad. The ISEN
resistor should be connected to the VOUT side of the resistor
pad.
In both current-sense configurations, the resistor and capacitor
sensing elements, with the exclusion of the current sense
power resistor, should be placed near the corresponding IC
pin. The trace connections to the inductor or sensing resistor
should be treated as Kelvin connections.
Page 19 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
FB (Pins 7 and 28), and VOUT (Pins 8 and 27)
The VOUT pin is used to generate the R3 synthetic ramp
voltage and for soft-discharge of the output voltage during
shutdown events. This signal should be routed as close to the
regulation point as possible. The input impedance of the FB pin
is high, so place the voltage programming and loop
compensation components close to the VOUT, FB, and GND
pins, keeping the high impedance trace short.
FSET (Pins 2 and 6)
This pin requires a quiet environment. The resistor RFSET and
capacitor CFSET should be placed directly adjacent to this pin.
Keep fast moving nodes away from this pin.
LGATE (Pins 15 and 20)
The signal going through this trace is both high dv/dt and high
di/dt, with high peak charging and discharging current. Route
this trace in parallel with the trace from the PGND pin. These
two traces should be short, wide, and away from other traces.
There should be no other weak signal traces in proximity with
these traces on any layer.
FN6666 Rev 8.00
August 25, 2015
BOOT (Pins 14 and 21), UGATE (Pins 13 and 22), and
PHASE (Pins 12 and 23)
The signals going through these traces are both high dv/dt and
high di/dt, with high peak charging and discharging current.
Route the UGATE and PHASE pins in parallel with short and
wide traces. There should be no other weak signal traces in
proximity with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across the
drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
Page 20 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
CHANGE
August 25, 2015
FN6666.8
Updated Ordering Information table on page 2.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing L28.4X4 to the latest revision.
-Revision 0 to Revision 1 changes - Added +/- 0.05 tolerances to each dimension in Top View and Bottom
View. Added 2 degrees to Bottom view pin 1 index area dimension
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2008-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6666 Rev 8.00
August 25, 2015
Page 21 of 22
ISL62391, ISL62392, ISL62391C, ISL62392C
Package Outline Drawing
L28.4x4
28 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 6/15
A
2.50 ±0.05
PIN #1 INDEX AREA
CHAMFER
0.400 ±0.05 x 45° ±2°
0.40 ±0.05
22
28
1
2.50 ±0.05
4.00 ±0.05
21
0.40 ±0.05
15
3.20 ±0.05
B
PIN 1
INDEX AREA
0.4 x 6 = 2.40 REF
4.00 ±0.05
7
0.10
2x
14
8
0.4 x 6 = 2.40 REF
3.20 ±0.05
TOP VIEW
0.20 ±0.05
0.10 M C A B
BOTTOM VIEW
SEE DETAIL X''
0.10 C
(3.20)
PACKAGE
OUTLINE
C
MAX. 0.80
(28x 0.20)
0.00 - 0.05
0.20 REF
SEATING PLANE
0.08 C
(3.20)
(2.50)
SIDE VIEW
(0.40)
(0.40)
C
0.20 REF
5
0 ~ 0.05
(2.50)
(28x 0.60)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Controlling dimensions are in mm.
Dimensions in ( ) are for reference only.
2. Unless otherwise specified, tolerance : Decimal ±0.05
Angular ±2°
3. Dimensioning and tolerancing conform to AMSE Y14.5M-1994.
4. Bottom side Pin#1 ID is diepad chamfer as shown.
5. Tiebar shown (if present) is a non-functional feature.
FN6666 Rev 8.00
August 25, 2015
Page 22 of 22