ON NSVMUN5312DW1T3G Complementary bias resistor transistor Datasheet

MUN5312DW1,
NSBC124EPDXV6,
NSBC124EPDP6
Complementary Bias
Resistor Transistors
R1 = 22 kW, R2 = 22 kW
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NPN and PNP Transistors with Monolithic
Bias Resistor Network
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base-emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space.
PIN CONNECTIONS
(3)
(2)
R1
•
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
S and NSV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC-Q101 Qualified and PPAP Capable*
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
R2
Q1
Q2
R2
Features
•
•
•
•
(4)
R1
(5)
(6)
MARKING DIAGRAMS
6
1
(TA = 25°C both polarities Q1 (PNP) & Q2 (NPN), unless otherwise noted)
Rating
Max
Unit
VCBO
50
Vdc
Collector-Emitter Voltage
VCEO
50
Vdc
IC
100
mAdc
Input Forward Voltage
VIN(fwd)
40
Vdc
Input Reverse Voltage
VIN(rev)
10
Vdc
Collector Current − Continuous
1
SOT−963
CASE 527AD
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
12 M G
G
SOT−563
CASE 463A
R
Symbol
12 M G
G
SOT−363
CASE 419B
MAXIMUM RATINGS
Collector-Base Voltage
(1)
1
12/R
M
G
MG
G
= Specific Device Code
= Date Code*
= Pb-Free Package
Package
Shipping†
MUN5312DW1T1G,
SMUN5312DW1T1G*
SOT−363
3,000 / Tape & Reel
(Note: Microdot may be in either location)
NSVMUN5312DW1T3G*
SOT−363
10,000 / Tape & Reel
*Date Code orientation may vary depending upon manufacturing location.
MUN5312DW1T2G,
NSVMUN5312DW1T2G*
SOT−363
3,000 / Tape & Reel
NSBC124EPDXV6T1G
SOT−563
4,000 / Tape & Reel
NSBC124EPDXV6T5G
SOT−563
8,000 / Tape & Reel
NSBC124EPDP6T5G
SOT−963
8,000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and
tape sizes, please refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 3
1
Publication Order Number:
DTC124EP/D
MUN5312DW1, NSBC124EPDXV6, NSBC124EPDP6
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
187
256
1.5
2.0
mW
MUN5312DW1 (SOT−363) ONE JUNCTION HEATED
Total Device Dissipation
TA = 25°C
(Note 1)
(Note 2)
Derate above 25°C
(Note 1)
(Note 2)
Thermal Resistance,
Junction to Ambient
PD
(Note 1)
(Note 2)
RqJA
mW/°C
670
490
°C/W
250
385
2.0
3.0
mW
MUN5312DW1 (SOT−363) BOTH JUNCTION HEATED (Note 3)
PD
Total Device Dissipation
(Note 1)
TA = 25°C
(Note 2)
Derate above 25°C
(Note 1)
(Note 2)
Thermal Resistance,
Junction to Ambient
(Note 2)
RqJA
(Note 1)
Thermal Resistance,
Junction to Lead (Note 1)
(Note 2)
RqJL
Junction and Storage Temperature Range
TJ, Tstg
mW/°C
°C/W
493
325
°C/W
188
208
−55 to +150
°C
357
2.9
mW
mW/°C
NSBC124EPDXV6 (SOT−563) ONE JUNCTION HEATED
PD
Total Device Dissipation
(Note 1)
TA = 25°C
Derate above 25°C
(Note 1)
Thermal Resistance,
Junction to Ambient
RqJA
(Note 1)
°C/W
350
NSBC124EPDXV6 (SOT−563) BOTH JUNCTION HEATED (Note 3)
PD
Total Device Dissipation
(Note 1)
TA = 25°C
Derate above 25°C
(Note 1)
Thermal Resistance,
Junction to Ambient
500
4.0
RqJA
(Note 1)
Junction and Storage Temperature Range
TJ, Tstg
mW
mW/°C
°C/W
250
−55 to +150
°C
231
269
1.9
2.2
MW
NSBC124EPDP6 (SOT−963) ONE JUNCTION HEATED
PD
Total Device Dissipation
(Note 4)
TA = 25°C
(Note 5)
Derate above 25°C
(Note 4)
(Note 5)
Thermal Resistance,
Junction to Ambient
(Note 5)
RqJA
(Note 4)
mW/°C
°C/W
540
464
NSBC124EPDP6 (SOT−963) BOTH JUNCTION HEATED (Note 3)
PD
Total Device Dissipation
(Note 4)
TA = 25°C
(Note 5)
Derate above 25°C
(Note 4)
(Note 5)
Thermal Resistance,
Junction to Ambient
(Note 5)
339
408
2.7
3.3
RqJA
(Note 4)
Junction and Storage Temperature Range
1.
2.
3.
4.
5.
TJ, Tstg
FR−4 @ Minimum Pad.
FR−4 @ 1.0 × 1.0 Inch Pad.
Both junction heated values assume total power is sum of two equally powered channels.
FR−4 @ 100 mm2, 1 oz. copper traces, still air.
FR−4 @ 500 mm2, 1 oz. copper traces, still air.
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2
MW
mW/°C
°C/W
369
306
−55 to +150
°C
MUN5312DW1, NSBC124EPDXV6, NSBC124EPDP6
ELECTRICAL CHARACTERISTICS (TA = 25°C both polarities Q1 (PNP) & Q2 (NPN), unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
−
−
100
−
−
500
−
−
0.2
50
−
−
50
−
−
60
100
−
−
−
0.25
−
−
1.2
1.2
−
−
−
−
1.9
2.0
−
−
−
−
0.2
4.9
−
−
Unit
OFF CHARACTERISTICS
Collector-Base Cutoff Current
(VCB = 50 V, IE = 0)
ICBO
Collector-Emitter Cutoff Current
(VCE = 50 V, IB = 0)
ICEO
Emitter-Base Cutoff Current
(VEB = 6.0 V, IC = 0)
IEBO
nAdc
nAdc
mAdc
Collector-Base Breakdown Voltage
(IC = 10 mA, IE = 0)
V(BR)CBO
Collector-Emitter Breakdown Voltage (Note 6)
(IC = 2.0 mA, IB = 0)
V(BR)CEO
Vdc
Vdc
ON CHARACTERISTICS
hFE
DC Current Gain (Note 6)
(IC = 5.0 mA, VCE = 10 V)
Collector-Emitter Saturation Voltage (Note 6)
(IC = 10 mA, IB = 0.3 mA)
VCE(sat)
Input Voltage (Off)
(VCE = 5.0 V, IC = 100 mA) (NPN)
(VCE = 5.0 V, IC = 100 mA) (PNP)
Vi(off)
Input Voltage (On)
(VCE = 0.2 V, IC = 5.0 mA) (NPN)
(VCE = 0.2 V, IC = 5.0 mA) (PNP)
Vi(on)
Output Voltage (On)
(VCC = 5.0 V, VB = 2.5 V, RL = 1.0 kW)
VOL
Output Voltage (Off)
(VCC = 5.0 V, VB = 0.5 V, RL = 1.0 kW)
VOH
V
Vdc
Vdc
Vdc
Vdc
Input Resistor
R1
15.4
22
28.6
Resistor Ratio
R1/R2
0.8
1.0
1.2
kW
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Pulsed Condition: Pulse Width = 300 ms, Duty Cycle ≤ 2%.
PD, POWER DISSIPATION (mW)
400
350
300
250
200
(1) SOT−363; 1.0 × 1.0 Inch Pad
(2) SOT−563; Minimum Pad
(3) SOT−963; 100 mm2, 1 oz. Copper Trace
(1) (2) (3)
150
100
50
0
−50
−25
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
Figure 1. Derating Curve
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3
MUN5312DW1, NSBC124EPDXV6, NSBC124EPDP6
1000
1
VCE = 10 V
IC/IB = 10
25°C
hFE , DC CURRENT GAIN
VCE(sat) , COLLECTOR-EMITTER VOLTAGE (V)
TYPICAL CHARACTERISTICS − NPN TRANSISTOR
MUN5312DW1, NSBC124EPDXV6
150°C
0.1
TA=-55°C
0.01
25°C
0
10
20
30
40
IC, COLLECTOR CURRENT (mA)
-55°C
100
10
1
0.001
50
1
10
IC, COLLECTOR CURRENT (mA)
Figure 2. VCE(sat) vs. IC
100
Figure 3. DC Current Gain
3.2
100
f = 10 kHz
IE = 0 A
TA = 25°C
2.4
150°C
25°C
TA=-55°C
IC, COLLECTOR CURRENT (mA)
2.8
2.0
1.6
1.2
0.8
0.4
10
1
0.1
0.01
VO = 5 V
0
0
10
20
30
40
VR, REVERSE VOLTAGE (V)
0.001
50
0
Figure 4. Output Capacitance
1
2
3
4
5
6
7
Vin, INPUT VOLTAGE (V)
VO = 0.2 V
10
TA=-55°C
1
150°C
0.1
0
25°C
10
8
9
Figure 5. Output Current vs. Input Voltage
100
V in , INPUT VOLTAGE (V)
Cob, OUTPUT CAPACITANCE (pF)
TA=150°C
20
30
IC, COLLECTOR CURRENT (mA)
40
Figure 6. Input Voltage vs. Output Current
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4
50
10
MUN5312DW1, NSBC124EPDXV6, NSBC124EPDP6
1000
1
VCE = 10 V
IC/IB = 10
TA=150°C
25°C
150°C
hFE , DC CURRENT GAIN
VCE(sat) , COLLECTOR-EMITTER VOLTAGE (V)
TYPICAL CHARACTERISTICS − PNP TRANSISTOR
MUN5312DW1, NSBC124EPDXV6
0.1
TA=-55°C
0.01
0.001
10
10
IC, COLLECTOR CURRENT (mA)
10
IC, COLLECTOR CURRENT (mA)
Figure 7. VCE(sat) vs. IC
Figure 8. DC Current Gain
30
20
40
1
50
100
10
9
IC, COLLECTOR CURRENT (mA)
7
6
5
4
3
2
1
0
10
10
TA=-55°C
1
0.1
0.01
VO = 5 V
0.001
50
20
30
40
VR, REVERSE VOLTAGE (V)
0
Figure 9. Output Capacitance
1
2
3
4
5
6
7
Vin, INPUT VOLTAGE (VOLTS)
VO = 0.2 V
10
TA=-55°C
150°C
25°C
0.1
0
8
9
Figure 10. Output Current vs. Input Voltage
100
1
100
25°C
150°C
f = 10 kHz
lE = 0 A
TA = 25°C
8
V in , INPUT VOLTAGE (V)
Cob, OUTPUT CAPACITANCE (pF)
-55°C
1
0
0
25°C
100
10
20
30
IC, COLLECTOR CURRENT (mA)
40
Figure 11. Input Voltage vs. Output Current
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5
50
10
MUN5312DW1, NSBC124EPDXV6, NSBC124EPDP6
1000
1
IC/IB = 10
VCE = 10 V
hFE, DC CURRENT GAIN
VCE(sat), COLLECTOR−EMITTER VOLTAGE (V)
TYPICAL CHARACTERISTICS − NPN TRANSISTOR
NSBC124EPDP6
25°C
0.1
150°C
−55°C
0.01
150°C
100
−55°C
10
1
0
30
10
20
40
IC, COLLECTOR CURRENT (mA)
1
10
IC, COLLECTOR CURRENT (mA)
0.1
50
Figure 12. VCE(sat) vs. IC
100
Figure 13. DC Current Gain
100
2.4
IC, COLLECTOR CURRENT (mA)
f = 10 kHz
IE = 0 A
TA = 25°C
2.0
1.6
1.2
0.8
0.4
0
0
10
20
30
40
VR, REVERSE VOLTAGE (V)
150°C
−55°C
10
1
0.1
VO = 5 V
0.01
50
25°C
0
2
4
6
8
10
12
Vin, INPUT VOLTAGE (V)
100
25°C
10
−55°C
150°C
1
VO = 0.2 V
0.1
0
14
Figure 15. Output Current vs. Input Voltage
Figure 14. Output Capacitance
Vin, INPUT VOLTAGE (V)
Cob, OUTPUT CAPACITANCE (pF)
25°C
10
20
30
40
IC, COLLECTOR CURRENT (mA)
Figure 16. Input Voltage vs. Output Current
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6
50
16
MUN5312DW1, NSBC124EPDXV6, NSBC124EPDP6
1
1000
25°C
IC/IB = 10
25°C
hFE, DC CURRENT GAIN
VCE(sat), COLLECTOR−EMITTER VOLTAGE (V)
TYPICAL CHARACTERISTICS − PNP TRANSISTOR
NSBC124EPDP6
150°C
0.1
−55°C
100
−55°C
10
VCE = 10 V
1
0.01
0
10
20
30
40
0.1
50
10
1
100
IC, COLLECTOR CURRENT (mA)
IC, COLLECTOR CURRENT (mA)
Figure 17. VCE(sat) vs. IC
Figure 18. DC Current Gain
7
100
6
IC, COLLECTOR CURRENT (mA)
f = 10 kHz
IE = 0 A
TA = 25°C
5
4
3
2
1
0
150°C
−55°C
10
25°C
1
0.1
VO = 5 V
0.01
0
10
20
30
40
0
50
2
4
6
8
10
12
VR, REVERSE VOLTAGE (V)
Vin, INPUT VOLTAGE (V)
Figure 19. Output Capacitance
Figure 20. Output Current vs. Input Voltage
100
Vin, INPUT VOLTAGE (V)
Cob, OUTPUT CAPACITANCE (pF)
150°C
25°C
10
−55°C
150°C
1
VO = 0.2 V
0.1
0
10
20
30
40
IC, COLLECTOR CURRENT (mA)
Figure 21. Input Voltage vs. Output Current
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7
50
14
MUN5312DW1, NSBC124EPDXV6, NSBC124EPDP6
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
2X
aaa H D
D
A
D
6
5
GAGE
PLANE
4
L
L2
E1
E
1
2
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
H
DETAIL A
3
aaa C
2X
bbb H D
2X 3 TIPS
e
B
6X
ddd
TOP VIEW
DIM
A
A1
A2
b
C
D
E
E1
e
L
L2
aaa
bbb
ccc
ddd
b
A2
M
C A-B D
DETAIL A
A
6X
ccc C
A1
SIDE VIEW
C
SEATING
PLANE
c
MILLIMETERS
MIN
NOM MAX
−−−
−−−
1.10
0.00
−−−
0.10
0.70
0.90
1.00
0.15
0.20
0.25
0.08
0.15
0.22
1.80
2.00
2.20
2.00
2.10
2.20
1.15
1.25
1.35
0.65 BSC
0.26
0.36
0.46
0.15 BSC
0.15
0.30
0.10
0.10
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
6X
6X
0.30
0.66
2.50
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
8
INCHES
NOM MAX
−−− 0.043
−−− 0.004
0.035 0.039
0.008 0.010
0.006 0.009
0.078 0.086
0.082 0.086
0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.006 BSC
0.006
0.012
0.004
0.004
MIN
−−−
0.000
0.027
0.006
0.003
0.070
0.078
0.045
MUN5312DW1, NSBC124EPDXV6, NSBC124EPDP6
PACKAGE DIMENSIONS
SOT−563, 6 LEAD
CASE 463A
ISSUE F
D
−X−
6
5
1
2
A
L
4
E
−Y−
3
b
e
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE MATERIAL.
DIM
A
b
C
D
E
e
L
HE
HE
C
5 PL
6
0.08 (0.003)
M
X Y
MILLIMETERS
MIN
NOM MAX
0.50
0.55
0.60
0.17
0.22
0.27
0.08
0.12
0.18
1.50
1.60
1.70
1.10
1.20
1.30
0.5 BSC
0.10
0.20
0.30
1.50
1.60
1.70
SOLDERING FOOTPRINT*
0.3
0.0118
0.45
0.0177
1.35
0.0531
1.0
0.0394
0.5
0.5
0.0197 0.0197
SCALE 20:1
mm Ǔ
ǒinches
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
9
INCHES
NOM MAX
0.021 0.023
0.009 0.011
0.005 0.007
0.062 0.066
0.047 0.051
0.02 BSC
0.004 0.008 0.012
0.059 0.062 0.066
MIN
0.020
0.007
0.003
0.059
0.043
MUN5312DW1, NSBC124EPDXV6, NSBC124EPDP6
PACKAGE DIMENSIONS
SOT−963
CASE 527AD
ISSUE E
X
Y
D
6
5
4
1
2
3
HE
E
DIM
A
b
C
D
E
e
HE
L
L2
C
SIDE VIEW
TOP VIEW
e
6X
6X
6X L2
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
A
L
MILLIMETERS
MIN
NOM
MAX
0.34
0.37
0.40
0.10
0.15
0.20
0.07
0.12
0.17
0.95
1.00
1.05
0.75
0.80
0.85
0.35 BSC
0.95
1.00
1.05
0.19 REF
0.05
0.10
0.15
b
0.08 X Y
BOTTOM VIEW
RECOMMENDED
MOUNTING FOOTPRINT*
6X
6X
0.35
0.20
PACKAGE
OUTLINE
1.20
0.35
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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ON Semiconductor Website: www.onsemi.com
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DTC124EP/D