FEDL610Q380FULL-01 Issue Date: Mar 9, 2012 ML610Q380/ML610Q383 ML610Q384/ML610Q385 8-bit Microcontroller with Voice Output Function I GENERAL DESCRIPTION Equipped with a 8-bit CPU nX-U8/100, the ML610Q380/383/384/385 is a high-performance 8-bit CMOS microcontroller that integrates a wide variety of peripherals such as 12-bit A/D converter, timer, PWM, synchronous serial port, UART, I２C bus interface (master), Battery level detect circuit, LCD driver, voice output function and speaker amplifier. The nX-U8/100 CPU is capable of executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel processing by the 3-stage pipelined architecture. In addition, it has an on-chip debugging function, which allows software debugging/rewriting with the LSI mounted on the board. FEATURES • CPU − 8-bit RISC CPU (CPU name: nX-U8/100) − Instruction system:16-bit instructions − Instruction set:Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on − On-Chip debug function − Minimum instruction execution time Approx 30.5 μs (at 32.768kHz system clock) Approx 0.122 μs (at 8.192MHz system clock)＠DVDD = 2.2 to 5.5V • Internal memory − Has 128-Kbyte flash ROM(64K × 16-bit) built in. (1K byte of test domain that it cannot be used is included) − Has 2-Kbyte RAM (2048 × 8 bits) built in. − Has maximum of 16-Mbit P2ROM (only ML610Q383/384/385) P2ROM capacity: ML610Q383 (4M bit), ML610Q384 (8M bit), and ML610Q385 (16M bit) • Interrupt controller − 2 non-maskable interrupt sources (Internal source: 1, External source: 1) − 24 maskable interrupt sources (Internal source: 20, External source: 4) • Time base counter − Low-speed time base counter × 1 channel − High-speed time base counter × 1 channel • Watchdog timer − Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second − Free running − Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) • Timers − 8 bits × 6ch (16-bit configuration available) 1/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 • PWM − Resolution 16 bits × 2 channel(IGBT control) • Voice output function − Voice synthesis method: 4-bit ADPCM2 / 8bit non-linear PCM / straight 8-bit PCM / straight 16-bit PCM − Sampling frequency: 6.4/8/10.7/12.8/16/21.3/25.6/32 kHz • D/A converter − 12-bit D/A converter • Speaker amplifier output power − 0.6W(at 5V) − Thermal detection circuit − Disconnection detection circuit • Synchronous serial port − 2ch ( For ML610Q383/384/385, SSIO1 is used for P2ROM access inside a chip.) − Master/slave selectable − LSB first/MSB first selectable − 8-bit length/16-bit length selectable • UART − Half-duplex − TXD/RXD × 2 channels − Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits − Positive logic/negative logic selectable − Built-in baud rate generator • I2C bus interface − Master function only − Fast mode (400kbit/s@4MHz), Standard mode (100kbit/s@4MHz) • Successive approximation type A/D converter − 10-bit A/D converter − Input: 8ch （Maximum） − Conversion time: 12.75μs per channel • General-purpose ports ×45（Maximum） − Non-maskable interrupt input port × 1ch − Input-only port × 6ch − Output-only port × 4ch (including secondary functions) − Input/output × 18ch (including secondary functions) − Input/output × 16ch (including LCD driver functions) • LCD driver − 96 dots max. (24 seg × 4 com), 1/1 to 1/4 duty − Frame frequency selecable (approx. 64Hz, 73Hz, 85Hz, 102Hz, 32Hz, 128Hz, 171Hz, and 256Hz) − LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable • Power supply voltage detect function − Judgment voltages: One of 4 levels − Judgment accuracy: ±2% (Typ.) 2/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 • Reset − Reset through the RESET_N pin − Reset by the watchdog timer (WDT) overflow • Clock − Low-speed clock (This LSI can not guarantee the operation withoug low-speed clock) Crystal oscillation (32.768 kHz) or Built-in RC oscillation (32.7kHz) − High-speed clock Built-in oscillation (8.192MHz), Crystal/Ceramic oscillation (8MHz), external clock • Power management − HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states). − STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are stopped.) − Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) − Block control function: Operation of an intact functional block circuit is powerd down. (register reset and clock stop) • Shipment − 80-pin QFP (P-QFP80-1414-0.80-TK9-MC) ML610Q380-xxxGA (blank product: ML610Q380-NNNGA) ML610Q383-xxxGA (blank product: ML610Q383-NNNGA) ML610Q384-xxxGA (blank product: ML610Q384-NNNGA) ML610Q385-xxxGA (blank product: ML610Q385-NNNGA) xxx: ROM code number • Guaranteed operating range − Operating temperature: −40°C to 70°C − Operating voltage: DVDD = P5VDD=2.2V to 5.5V, SPVDD = 4.5V to 5.5V, VREF = 4.5V to 5.5V 3/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 BLOCK DIAGRAM Block diagram of ML610Q380 Figure 1-1 is a block diagram of the ML610Q380. Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding port. CPU (nX-U8/100) Large Model EPSW1-3 GREG 0-15 PSW Timing Controller On-Chip ICE ALU XT0 XT1 OSC0* OSC1* LSCLK* OUTCLK* VDDL SG AOUT ECSR1-3 LR DSR/CSR EA PC SP Instruction Decoder P5VDD VDD VSS RESET_N TEST0 TEST1_N ELR1-3 Instruction Register Data-bus RESET & TEST RAM 2048byte OSC Interrupt Controller INT 4 POWER INT 6 INT 1 VOICECNT Program Memory （Flash） 128Kbyte BUS Controller INT 2 INT 2 INT 1 TBC INT 2 8bit Timer ×6 INT 5 SSIO SCK0*1, SCK1*1 SIN0*1, SIN1*1 SOUT0*1, SOUT1*1 UART RXD0*1, RXD1*1 TXD0*1, TXD1*1 I2C PWM INT WDT GPIO BLD VREF PWM4*1 PWM5*1 PW45EV0*1 PW45EV1*1 NMI P00 to P03 P10 to P11 P20 to P23 P34 to P35 P40 to P43 P44 to P47*3 P50 to P53 PC0 to PC7*2 PD0 to PD7*2 SPEAKER AMP VDD VSS AIN0 to AIN3*3 AIN4 to AIN7*3 SDA*1 SCL*1 P30 to P33*3 SPVDD SPVSS SPP SPM SG SPIN VPP INT 1 10bit-ADC *1 Secondary or tertiary function *2 Select I/O port or LCD driver *3 Select I/O port or A/D converter input LCD Driver LCD Drive Voltage COM0 to COM3 SEG0 to SEG7 SEG8 to SEG23*2 VL1, VL2, VL3 4/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 Block diagram of ML610Q383/384/385 Figure 1-2 is a block diagram of the ML610Q383/384/385. Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding port. EPSW1～3 PSW CPU (nX-U8/100) Large d ELR1～3 GREG 0～15 LR Timing Controller On-Chip ICE EA ALU Instruction Decoder Instruction Register Data-bus XT0 XT1 OSC0* OSC1* LSCLK* OUTCLK* VDDL VDDR RESET & TEST OSC Interrupt Controller INT 4 INT 6 INT 1 SG AOUT SPVDD SPVSS VOICECNT SPP SPM SG SPIN VDD VSS SPEAKER AMP VREF AIN0 to AIN3*3 PVPP AIN4 to AIN7 PSO PSCK 16Mbit PSI P2ROM PCSB RAM 2048byte INT 1 POWER PC INT Program Memory （Flash） 128Kbyte BUS Controller INT 2 INT 2 INT 1 TBC INT 2 8bit Timer ×6 INT 5 WDT INT 1 DSR/CSR SP DVDD VSS RESET_N TEST0 TEST1_N ECSR1～3 VPP SSIO SCK0*1, SCK1*4 SIN0*1, SIN1*4 SOUT0*, SOUT1*4 UART RXD0*1, RXD1*1 TXD0*1, TXD1*1 I2C PWM GPIO BLD SDA*1 SCL*1 PWM4*11 PWM5* PW45EV0*1 PW45EV1*1 NMI P00 to P03 P10 to P11 P20 to P23 P30 to P33*3 P34 to P35 P40 to P43 P44 to P47*3 PC0 to PC7*2 PD0 to PD7*2 10bit-ADC ＊3 *1 P50(SIN1) *1 P51(SCK1) GPIO *1 P52(SOUT1) *1 P53 LCD Driver LCD Drive Voltage COM0 to COM3 SEG0 to SEG7 *2 SEG8 to SEG23 VL1, VL2, VL3 *1 Secondary or tertiary function *2 Select I/O port or LCD driver *3 Select I/O port or A/D converter input *4 For P2ROM 5/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 PIN CONFIGURATION (ML610Q383/384/385) SG TEST1_N TEST0 NMI PD7/SEG23 PD6/SEG22 PD5/SEG21 PD4/SEG20 PD3/SEG19 PD2/SEG18 PD1/SEG17 PD0/SEG16 PC7/SEG15 PC6/SEG14 PC5/SEG13 PC4/SEG12 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SPVSS SPVDD SPIN AOUT ML610Q380 QFP package product P33/AIN3 SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 VL3 VL2 VL1 P52/SOUT1 RESET_N VSS DVDD VDDL XT0 XT1 VPP P10/OSC0 P11/OSC1 P51/SCK1 P02/INT2 P03/INT3 VREF P30/AIN0 P31/AIN1 P32/AIN2 PC3/SEG11 PC2/SEG10 PC1/SEG9 PC0/SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (NC) P5VDD P00/INT0 P01/INT1 P45/AIN5 P46/AIN6 P47/AIN7 P34/PWM4 P35/PWM5 P40/SDA P41/SCL P42/RXD0 P43/TXD0 P50/SIN1 P53/TXD1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 P44/AIN4 SPM SPP P20/LED0 P21/LED1 P22/LED2 P23/LED3 VSS NC: No Connection 6/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 SG TEST1_N TEST0 NMI PD7/SEG23 PD6/SEG22 PD5/SEG21 PD4/SEG20 PD3/SEG19 PD2/SEG18 PD1/SEG17 PD0/SEG16 PC7/SEG15 PC6/SEG14 PC5/SEG13 PC4/SEG12 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SPVSS SPVDD SPIN AOUT ML610Q383/384/385 QFP package product P33/AIN3 SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 VL3 VL2 VL1 TEST02 RESET_N VSS DVDD VDDL XT0 XT1 VPP P10/OSC0 P11/OSC1 TEST01 P02/INT2 P03/INT3 VREF P30/AIN0 P31/AIN1 P32/AIN2 PC3/SEG11 PC2/SEG10 PC1/SEG9 PC0/SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 1 2 3 4 V L6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PVPP VDDR P00/INT0 P01/INT1 P45/AIN5 P46/AIN6 P47/AIN7 P34/PWM4 P35/PWM5 P40/SDA P41/SCL P42/RXD0 P43/TXD0 TEST00 TEST03 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 P44/AIN4 SPM SPP P20/LED0 P21/LED1 P22/LED2 P23/LED3 VSS 7/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 LIST OF PINS Pin No. Primary function Pin name I/O 12,67 Vss ⎯ 13 DVDD ⎯ 14 VDDL ⎯ 60 SPVSS ⎯ 59 SPVDD ⎯ P5VDD*1 ⎯ VDDR*2 ⎯ Secondary function Pin name I/O Negative power supply pin ⎯ Positive power supply pin Description Tertiary function Description Pin name I/O Description ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 70 PVPP 17 VPP ⎯ Power supply for internal logic (internally generated) Negative power supply pin for built-in speaker amplifier Positive power supply pin for built-in speaker amplifier For P50 to P53 power supply pin For P2ROM SIOport power supply pin High voltage power supply pin of data to building P2ROM Power supply pin for Flash ROM ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 22 VL1 ⎯ Power supply pin for LCD bias ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 23 VL2 ⎯ Power supply pin for LCD bias ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 24 VL3 ⎯ Power supply pin for LCD bias ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 54 TEST0 I/O Input/output pin for testing ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 55 TEST1_N I/O Input/output pin for testing ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 11 15 RESET_N I Reset input pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ XT0 I Low-speed clock oscillation pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Low-speed clock oscillation pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ LINE output Analog input to the built-in speaker amplifier Reference power supply pin of the built-in speaker amplifier Positive output pin of the built-in speaker amplifier Negative output pin of the built-in speaker amplifier Reference power supply pin of Successive-approximation type ADC Input port, non-maskable interrupt Input port / External interrupt / PW45EV0 input Input port / External interrupt Input port / External interrupt UART0 data input Input port / External interrupt / UART1 data input ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 71 16 *2 ⎯ 57 XT1 AOUT O O 58 SPIN I 56 SG O 62 SPP O 61 SPM O 76 VREF I 53 NMI I 72 P00/EXI0/ PW45EV0 I 73 P01/EXI1 I 74 P02/EXI2/ RXD0 I 75 P03/EXI3/ RXD1 I 18 P10 I Input port OSC0 I 19 P11 I Input port OSC1 O O Output port / LED drive LSCLK O O Output port / LED drive OUTCLK O O Output port / LED drive ⎯ ⎯ ⎯ TM9OUT O Timer9 output O Output port / LED drive ⎯ ⎯ ⎯ TMBOUT O TimerB output 63 64 65 66 P20/ LED0 P21/ LED1 P22/ LED2 P23/ LED3 High-speed clock oscillation pin High-speed clock oscillation pin Low-speed clock output Low-speed clock output 8/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 Pin No. Primary function Pin name I/O Secondary function Pin name I/O type ⎯ type Description I/O Description ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ type ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ type ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PWM4 O PWM4 output PWM5 O SIN0 I SCK0 I/O SOUT0 O PWM5 output SSIO0 data input SSIO0 synchronous clock input/output SSIO0 data output PWM4 O PWM4 output SIN0 I SSIO0 data input Description 77 P30/ PW45EV1 /AIN0 I/O 78 P31/AIN1 I/O 79 P32/AIN2 I/O 80 P33/AIN3 I/O 5 P34 I/O Input/output port / PW45EV1 input / Successive approximation ADC input Input/output port / Successive approximation ADC input Input/output port / Successive approximation ADC input Input/output port / Successive approximation ADC input Input/output port ⎯ ⎯ 6 P35 I/O Input/output port ⎯ ⎯ 7 P40 I/O Input/output port SDA I/O 8 P41 I/O Input/output port SCL I/O 9 P42 I/O Input/output port RXD0 I 10 P43 I/O Input/output port TXD0 O ⎯ ⎯ 1 P44/ T0P4CK/ AIN4 2 P45/ T1P5CK/ AIN5 I 3 P46/ T8ACK/ AIN6 I 4 P47/ T9BCK/ AIN7 I 68 20 P50*1 TESTO0*2 P51*1 TESTO1*2 I I/O I/O Input port / Timer0 external clock input / PWM4 external clock input/ Successive approximation type ADC input Input port / Timer1 external clock input / PWM5 external clock input/ Successive approximation type ADC input Input port / Timer8 external clock input / TimerA external clock input / Successive approximation type ADC input Input port / Timer9 external clock input / TimerB external clock input / Successive approximation type ADC input Input/output port Input/output port Tertiary function Pin name ⎯ I2C data input/output I2C clock input/output UART0 data input UART0 data output ⎯ ⎯ ⎯ ⎯ SCK0 I/O SSIO0 synchronous clock input/output ⎯ ⎯ ⎯ SOUT0 O SSIO0 data output ⎯ ⎯ ⎯ PWM5 O PWM5 output ⎯ ⎯ ⎯ SIN1 I ⎯ ⎯ ⎯ SCK1 I/O RXD1 I SOUT1 O ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SSIO1 data input SSIO1 synchronous clock input/output SSIO1 data output 28 27 P52*1 TESTO2*2 P53*1 TESTO3*2 COM0 COM1 26 COM2 O LCD common pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 25 COM3 O LCD common pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 29 SEG0 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 30 SEG1 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 31 SEG2 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 32 SEG3 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 21 69 I/O Input/output port I/O Input/output port TXD1 O O O LCD common pin LCD common pin ⎯ ⎯ ⎯ ⎯ UART1 data input UART1 data input ⎯ ⎯ 9/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 Pin No. Primary function Pin name I/O 33 SEG4 O 34 SEG5 35 36 Secondary function Pin name I/O LCD segment pin ⎯ O LCD segment pin SEG6 O SEG7 O Tertiary function Description Pin name I/O Description ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Description 37 PC0 I/O Input/output port SEG8 O 38 PC1 I/O Input/output port SEG9 O 39 PC2 I/O Input/output port SEG10 O 40 PC3 I/O Input/output port SEG11 O 41 PC4 I/O Input/output port SEG12 O 42 PC5 I/O Input/output port SEG13 O 43 PC6 I/O Input/output port SEG14 O 44 PC7 I/O Input/output port SEG15 O 45 PD0 I/O Input/output port SEG16 O 46 PD1 I/O Input/output port SEG17 O 47 PD2 I/O Input/output port SEG18 O 48 PD3 I/O Input/output port SEG19 O 49 PD4 I/O Input/output port SEG20 O 50 PD5 I/O Input/output port SEG21 O 51 PD6 I/O Input/output port SEG22 O 52 PD7 I/O Input/output port SEG23 O LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin *1：It applies to ML610Q380.、*2：It applies to ML610Q383/384/385. 10/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 Supplementation: Only ML610Q383/384/385. ( ML610Q380 doesn't correspond.) P50 to P53 is connected with building P2ROM by the inside of the chip into, and each function exists. (The external pin name becomes TESTO0 to TESTO3. Please give the external terminal processing to me as an opening.) Connected with P2ROM content is shown as follows. The pins of built-in P2ROM PSO PSCK PSI PCSB Explanation Serial-data output connected with P50/SIN1 (Tertiary functional) inside. Serial-data output connected with P51/SCK1 (Tertiary functional) inside Serial-data input connected with P52/SOUT1 (Tertiary functional) inside Chip select input connected with P53 (Primary functional) inside 11/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 PIN DESCRIPTION Pin name Primary/ Secondary Logic Negative power supply pin — — I/O Description Power supply VSS — DVDD — Positive power supply pin — — VDDL — Positive power supply pin for internal logic (internally generated). Connect capacitors (CL) (see Measuring Circuit 1) between this pin and VSS . — — SPVSS — Negative power supply pin for built-in speaker amplifier — — SPVDD — Positive power supply pin for built-in speaker amplifier — — P5VDD — Port5 IF power supply pin.(Only ML610Q380) — — — — — — supply the power supply of the SPI memory when you connect the SPI memory with external.Besides, supply the same level as DVDD. VDDR P2ROM built in Positive power supply(Inner generation) pin. (Only ML610Q383/384/385)Connect capacitors (CR) (see Measuring Circuit 1) between this pin and VSS . PVPP — High voltage power supply pin of the data write to building P2ROM into. Besides, fix at the VSS level. VPP — Power supply pin for programming Flash ROM. — — VL1 — Power supply pins for LCD bias (external input) — — VL2 — Power supply pins for LCD bias (external input) — — VL3 — Power supply pins for LCD bias (external input) — — Test TEST0 I/O Input/output pin for testing. Has a pull-down resistor built in. — Positive TEST1_N I/O Input/output pin for testing. Has a pull-up resistor built in. — Negative — Negative — — — — Secondary — Secondary — System RESET_N I XT0 I XT1 O OSC0 I OSC1 O LSCLK O OUTCLK O Reset input pin. When this pin is set to a “L” level, the device is placed in system reset mode and the internal circuit is initialized. If after that this pin is set to a “H” level, program execution starts. This pin has a pull-up resistor built in. Crystal connection pin for low-speed clock. A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to this pin. Capacitors CDL and CGL are connected across this pin and VSS as required. External input pin for high-speed clock. This function is allocated to the secondary function of the P10 pin. Low-speed clock output. This function is allocated to the secondary function Secondary of the P20 pin. High-speed clock output. This function is allocated to the secondary Secondary function of the P21 pin. — — General-purpose input port P00 to P03 I P10 to P11 I General-purpose input ports. Provided with a secondary function for each port. Cannot be used as ports if their secondary functions are used. Primary Positive Primary Positive General-output input port P20 to P23 O General-purpose output ports.Provided with a secondary function for each port. Cannot be used as ports if their secondary functions are used. 12/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 Primary/ Pin name I/O Description Secondary/ Logic Tertiary General-purpose input/output port P30 to P35 P40 to P47 I/O General-purpose input/output ports.Provided with a secondary function for each port. Cannot be used as ports if their secondary functions are used. P50 to P53 PC0 to PC7 PD0 to PD7 Primary Positive I/O General-purpose input/output ports.Provided with a LCD segment for each port. Cannot be used as ports if LCD segment are used. UART O UART0 data output pin. Allocated to the secondary function of the P43 pin. Secondary Positive RXD0 I UART0 data input pin. Allocated to the primary function of the P02 pin and the secondary function of the P42 pin. Secondary Positive TXD1 O UART1 data output pin. Allocated to the secondary function of the P53 pin. Secondary Positive I UART1 data input pin. Allocated to the primary function of the P03 pin and the secondary function of the P52 pin. Secondary Positive TXD0 RXD1 2 I C bus interface 2 SDA SCL I C data input/output pin. This pin is used as the secondary function of the I/O P40 pin. This pin has an NMOS open drain output. When using this pin as 2 a function of the I C, externally connect a pull-up resistor. 2 I C clock output pin. This pin is used as the secondary function of the P41 I/O pin. This pin has an NMOS open drain output. When using this pin as a 2 function of the I C, externally connect a pull-up resistor. Secondary Positive Secondary Positive Synchronous serial (SSIO) SIN0 SCK0 SOUT0 SIN1 SCK1 SOUT1 Synchronous serial data input pin. Allocated to the tertiary function of the P40 pin and P44 pin. Synchronous serial clock input/output pin. Allocated to the tertiary function I/O of the P41 pin and P45 pin. I Synchronous serial data output pin. Allocated to the tertiary function of the P42 pin and P46 pin. Synchronous serial data input pin. Allocated to the tertiary function of the I P50 pin . Synchronous serial clock input/output pin. Allocated to the tertiary function I/O of the P51 pin. Synchronous serial data output pin. Allocated to the tertiary function of the O P52 pin. O Tertiary Positive Tertiary — Tertiary Positive Tertiary Positive Tertiary — Tertiary Positive PWM PWM4 O PWM4 output pin. Allocated to the tertiary function of the P34 and P43 pins. Tertiary Positive PWM5 O PWM5 output pin. Allocated to the tertiary function of the P35and P47 pins. Tertiary Positive T0P4CK I External clock input pin for timer 0 and PWM4. Allocated to the primary function of the P44 pin. Primary — T1P5CK I External clock input pin for timer 1 and PWM5. Allocated to the primary function of the P45 pin. Primary — I Control start /stop pin for PWM4 and PWM5. Allocated to the primary function of the P00 pin and P30 pin. Primary — PW45EV0 PW45EV1 13/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 Primary/ Pin name I/O Description Secondary/ Logic Tertiary External interrupt NMI I External non-maskable interrupt input pin. The interrupt occurs on both the rising and falling edges. Primary Positive/ Negative EXI0–EXI3 I External maskable interrupt input pins. It is possible, for each bit, to specify whether the interrupt is enabled and select the interrupt edge by software. Allocated to the primary function of the P00–P03 pins. Primary Positive/ Negative Primary — Primary — Primary — Primary — Tertiary Positive Tertiary Positive Primary Positive/ Negative Timer T0P4CK I T1P5CK I T8ACK I T9BCK I TM9OUT O TMBOUT O External clock input pin for timer 0 and PWM4. Allocated to the primary function of the P44 pin. External clock input pin for timer 1 and PWM5. Allocated to the primary function of the P45 pin. External clock input pin for timer 8 and timer A. Allocated to the primary function of the P46 pin. External clock input pin for timer 9 and timer B. Allocated to the primary function of the P47 pin. Timer9 overflow output pin. Allocated to the secondary function of the P22 pin. TimerB overflow output pin. Allocated to the secondary function of the P23 pin. LED drive LED0-LED3 O Pins for LED driving. Allocated to the primary function of the P20–P23 pins. Voice output function O LINE output pin. The case of built-in speaker amplifier use, connect with the SPIN pin. — — SPIN I Analog input pin of the internal speaker amplifier. — — SG O Reference voltage output pin of the internal speaker amplifier. — — SPP O Positive output pin of the internal speaker amplifier. — — SPM O Negative output pin of the internal speaker amplifier. — — — — AOUT Successive-approximation type A/D converter VREF I AIN0–AIN7 I Reference power supply pin for successive approximation type A/D converter. Analog inputs to Ch0–Ch7 of the successive-approximation type A/D converter. Allocated to the secondary function of the P30 to P33 and P44 to P47 pins. LCD driver COM0 to COM3 O LCD common output pins. — — SEG0 to SEG7 O LCD segment output pins. — — SEG8 to SEG23 O LCD segment output pins. Allocated to the secondary function of the PC0 to PC7 and PD0 to PD7 pins. — — 14/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 TERMINATION OF UNUSED PINS How to Terminate Unused Pins Pin VPP RESET_N TEST0 TEST1_N VREF SPVDD SPVSS *1 P5VDD AOUT SPIN SG SPP SPM P00 to P03 P10 to P11 P20 to P23 P30 to P33 (AIN0 to AIN3) P34 to P35 P40 to P43 P44 to P47 (AIN4 to AIN7) P50 to P53 COM0 to COM3 SEG0 to SEG7 PC0 to PC7 （SEG8 to15） PD0 to PD7 （SEG16 to 23） Recommended pin termination open open open open Connect to DVDD Connect to DVDD Connect to DVSS Connect to DVDD open open open open open Connect DVDD or VSS Connect DVDD or VSS open open open open open open open open open open Note: *1. Only ML610Q380 is applied. For unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance inputs and left open, the supply current may become excessively large. Therefore, it is recommended to configure those pins as either inputs with a pull-down resistor/pull-up resistor or outputs. 15/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (VSS = SPVSS = 0V) Parameter Symbol Condition Rating Unit Power supply voltage 1 DVDD Ta = 25°C −0.3 to +7.0 V Power supply voltage 2 Power supply voltage 3 Power supply voltage 4 Power supply voltage 5 SPVDD VPP VL1 VL2 Ta = 25°C Ta = 25°C Ta = 25°C Ta = 25°C −0.3 to +7.0 −0.3 to +9.5 −0.3 to +2.33 −0.3 to +4.66 V V V V Power supply voltage 6 VL3 Ta = 25°C −0.3 to +7.0 V Power supply voltage 7 P5VDD Ta=25℃ -0.3～+7.0 V VREF Ta = 25°C −0.3 to DVDD+0.3 V VAI Ta = 25°C −0.3 to DVDD+0.3 V Reference voltage Analog input voltage VIN Ta = 25°C −0.3 to DVDD+0.3 V Output voltage VOUT −0.3 to DVDD+0.3 V Output current 1 IOUT1 −12 to +11 mA Output current 2 IOUT2 Ta = 25°C Port3,4,5,C,D,COM,SEG, Ta = 25°C Port2,9 Ta = 25°C −12 to +20 mA Power dissipation PD Ta = 25°C 1 W Storage temperature TSTG ― −55 to +150 °C Input voltage Recommended Operating Conditions (VSS = SPVSS = 0V) Parameter Symbol Condition Range Unit °C TOP ― −40 to +70 DVDD ― 2.2 to 5.5 Operating voltage P5VDD ― 2.2 to 5.5 V Operating frequency (CPU) Low-speed crystal oscillation frequency Capacitor externally connected to DVDD pin Capacitor externally connected to SPVDD pin Capacitor externally connected to VPP pin Capacitor externally connected to Vref pin SPVDD fOP fXTL CV CSV C1 CAV CDL ― ― ― ― ― ― ― Use 32.768KHz Crystal Oscillator DT-26S (DAISHINKU CORP.) 4.5 to 5.5 30k to 8.4M 32.768k 10±30% 1±30% 1±30% 1±30% 12 to 25 Hz Hz μF μF μF μF fXTH ― 8M/8.192M Hz CDH CGH ― ― 47±30% 47±30% pF Capacitor externally connected to VDDL pin CL ― 10±30% μF Capacitor externally connected to VDDR pin CR ― 1±30% μF Capacitor externally connected to VL1,2,3 pin CL1,2,3 ― 0.22±30% μF CAOSP ― 0.022±30% μF CSG ― 0.1±30% μF Operating temperature Low-speed crystal oscillation external capacitor High-speed crystal/ceramic oscillation frequency High-speed crystal oscillation external capacitor* Capacitor externally connected to AOUT pin – SPIN pin Capacitor externally connected to SG pin CGL 12 to 25 pF * CGH and CDH are built into, external capacity is unnecessary for CSTLS8M00G56-A0 (made by Murata Mfg.). 16/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 Flash Memory Operating Conditions Parameter Operating temperature Operating voltage Maximum rewrite count Data retention period 1 Symbol TOP DVDD VDDL VPP CEPP YDR (VSS = SPVSS = 0V) Range Unit 0 to +40 °C 2.7 to 5.5 V 2.5 to 2.75 7.7 to 8.3 80 times 10 years Condition At write/erase At write/erase *1 At write/erase 1 At write/erase ― ― * : At the writing of a flash ROM, it is necessary to supply voltage to VDDL pin within the limits of the above-mentioned regulation. Pulldown resistance is built in the VPP pin. DC Characteristics (1 of 6) (DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified) Measuring Parameter Symbol Condition Min. Typ. Max. Unit circuit High-speed crystal oscillation 2 20 ms TXTH ― ― start time Low-speed crystal oscillation ― ― 0.6 2 s TXTL 2 start time* Low-speed RC oscillator frequency fLCR ― PLL oscillation frequency fPLL LSCLK=32.768kHz 100 clock average Typ -5% 32.7k Typ -1% 8.192 Reset pulse width ― 100 ― PRST Reset noise rejection pulse PNRST ― ― ― width 1 * : Use 32.768KHz Crystal Oscillator DT-26 (Daishinku) with capacitance CGL/CDL＝12pF. Typ +5% Hz Typ +1% MHz 1 ― 0.4 μs Reset RESET_N VIL1 VIL1 PRST Reset by RESET_N pin 17/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 DC Characteristics (2 of 6) (DVDD= P5VDD=SPVDD= 4.5 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified) Measuring Parameter Symbol Condition Min. Typ. Max. Unit circuit LINE amplifier output At 10kΩ load for VSS SPVDD×1/6 ⎯ SPVDD×5/6 V VAD voltage range SG output voltage VSG ― 0.95 × SPVDD/2 SPVDD/2 1.05 × SPVDD/2 V SG output resistance SPM, SPP output load resistance RSG ― 57 96 135 kΩ RLSP ― ― 8 ― Ω Speaker amplifier output power PSPO1 Output offset voltage between SPM and SPP with no signal present VOF SPVDD = 5.0V, f = 1kHz, RSPO = 8Ω, THD ≥ 10% At SPIN Input SPVDD=5.0V, SPIN – SPM gain = +0dB With a load of 8Ω 1 — 0.6 — W −50 — +50 mV DC Characteristics (3 of 6) Parameter BLD threshold voltage (DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified) Meas Symbol Condition Min. Typ. Max. Unit uring circuit LD3 to 0 = 0H 2.35 LD3 to 0 = 3H Typ. Typ. 2.80 Ta = 25°C VBLD V 1 -2% +2% LD3 to 0 = 9H 3.70 LD3 to 0 = FH 4.60 DC Characteristics (4 of 6) (DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified) Meas Parameter Symbol Condition Min. Typ. Max. Unit uring circuit CPU: In STOP state Low-speed/high-speed oscillation: Stopped Supply current 1 IDD1 ― 0.7 22 DVDD=3.0V *2 CPU: In HALT state (LTBC,WBC: Operating ) μA High-speed oscillation: Stopped Supply current 2 IDD2 ― 2.0 24 DVDD=3.0V 1 1 CPU: Running at 32kHz* Supply current 3 High-speed oscillation: Stopped ― 13 42 IDD3 DVDD=3.0V CPU: Running at 8.192MHz Crystal/ceramic 2 Supply current 4 IDD4 oscillating mode* ― 5 8 mA DVDD = SPVDD = 5.0V 1 * : Case when the CPU operating rate is 100% (with no HALT state) 2 * : Significant bits of BLKCON0 to BLKCON4 registers are all “1”. 18/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 DC Characteristics (5 of 6) Parameter Output voltage 1 (P20 to P23) (P30 to P35) (P40 to P47) (P50 to P53) (PC0 to PC7) (PD0 to PD7) Output voltage 2 (P20–P23) Output voltage 3 (P40–P41) Output leakage current (P20 to P23) (P30 to P35) (P40 to P47) (P50 to P53) (PC0 to PC7) (PD0 to PD7) (DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified) Measuring Symbol Condition Min. Typ. Max. Unit circuit VOH1 IOH1 = −0.5mA DVDD −0.5 ― ― VOL1 IOL1 = +0.5mA ― ― 0.5 IOL2 = +10mA DVDD ≥ 4.5V ― ― 0.5 IOL3 = +3mA ― ― 0.4 ― ― 1 VOL2 VOL3 IOOH −1 ― ― VL3=3V、VOL=0.3V 15 40 ― VL3=5V、VOL=0.5V 100 200 ― VL3=3V、VOH=2.7V ― -30 -15 VL3=5V、VOH=4.5V ― -90 -45 VL3=3V、VOL=0.3V 15 30 ― VL3=5V、VOL=0.5V 70 150 ― VL3=3V、VOH=2.7V ― -13 -6 VL3=5V、VOH=4.5V ― -40 -20 IIH1 VIH1 = DVDD 0 ― 1 IIL1 VIL1 = VSS −1500 −300 −20 IIH2 VIH2 = DVDD (when pulled down) 2 30 250 IIL2 VIL2 = VSS (when pulled up) −250 −30 −2 IIH2Z VIH2 = DVDD (in high-impedance state) ― ― 1 IIL2Z VIL2 = VSS (in high-impedance state) -1 ― ― IIH3 VIH3 = DVDD 20 300 1500 IIL3 VIL3 = VSS -1 ― ― Output current 1 COM0 to COM3 IOH1 IOL2 Output current 2 SEG0 to SEG23 IOH2 Input current 3 (TEST0) VOH = DVDD (in high-impedance state) VOL = VSS (in high-impedance state) IOOL IOL1 Input current 1 (RESET_N) (TEST1_N) Input current 2 (NMI) (P00 to P03) (P10 to P11) (P30 to P35) (P40 to P47) (P50 to P53) (PC0 to PC7) (PD0 to PD7) When LED drive mode is selected 2 When I C mode is selected V 2 μA 3 μA 3 μA 4 19/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 DC Characteristics (6 of 6) Parameter (DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified) Measuring Symbol Condition Min. Typ. Max. Unit circuit Input voltage 1 (RESET_N) (TEST0) (TEST1_N) (NMI) (P00 to P03) (P10 to P11) (P30 to P35) (P40 to P43) (P50 to P53) (PC0 to PC7) (PD0 to PD7) Input pin capacitance (RESET_N) (TEST0) (TEST1_N) (NMI) (P00 to P03) (P10 to P11) (P30 to P35) (P40 to P43) (P50 to P53) (PC0 to PC7) (PD0 to PD7) VIH1 ― 0.7× DVDD ― DVDD VIL1 ― 0 ― 0.3× DVDD CIN f = 10kHz Vrms = 50mV Ta = 25°C ― ― 10 V 5 pF ― 20/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 Measuring Circuits Measuring circuit 1 CGL XT0 CDL CGH VL3 CL3 VL2 CL2 XT1 32.768kHz crystal OSC0 CL1 VL1 CDH OSC1 DVDD VREF SPVDD P5VDD※1 VDDLVDDR※2 SG VSS SPVSS 8MHz crystal A CV CL CV ：10μF CL ：10μF ：10μF CR CSG ：0.1μF ：12pF CGL CDL ：12pF ：47pF CGH CDH ：47pF CL1,C L2,C L3：0.22μF 32.768kHz Crystal oscillator (DMX-26S DAISHINKU Corp.) 8MHz Crystal oscillator CSTLS8M00G56-A0（MURATA Corp.）it has built-in CGH, and CDH CR CSG Measuring circuit 2 (*2) VIL Input pins (*1) Output pins VIH DVDD P5VDD※1 VDDR※2 VDDL VREF SPVDD VL1 VL2 V VL3 VSS SPVSS (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins. ※1. Only ML610Q380 is applied. ※2. Only ML610Q383/384/385 is applied. 21/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 Measuring circuit 3 (*2) VIL Input pins (*1) Output pins VIH DVDD P5VDD VDDR※ VDDL ※1 2 VREF SPVDD A VSS SPVSS *1: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins. Measuring circuit 4 Input pins Output pins (*3) A DVDDP5VDD※ VDDR※2 VDDL 1 VREF SPVDD VSS SPVSS *3: Measured at the specified input pins. VIL Input pins (*1) Output pins VIH DVDD P5VDD※1 VDDR※2 VDDL VREF SPVDD VSS Waveform monitoring Measuring circuit 5 SPVSS *1: Input logic circuit to determine the specified measuring conditions. ※1. Only ML610Q380 is applied. ※2. Only ML610Q383/384/385 is applied. 22/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 AC Characteristics (External Interrupt) (DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit External interrupt disable Interrupt: Enabled (MIE = 1), 2.5× 3.5× TNUL ― μs period CPU: NOP operation sysclk sysclk P00–P03 (Rising-edge interrupt) tNUL P00–P03 (Falling-edge interrupt) tNUL NMI, P00–P03 (Both-edge interrupt) tNUL 23/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 AC Characteristics (Synchronous Serial Port) (DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit High-speed oscillation stopped 10 ― ― μs SCK input cycle tSCYC (slave mode) 500 During high-speed oscillation ― ― ns SCK output cycle (master mode) ― ― SCK High-speed oscillation stopped 4 During high-speed oscillation 200 tSCYC SCK input pulse width (slave mode) tSW (*1) SCK output pulse width SCK ― tSW ×0.4 (master mode) SOUT output delay time ― ― tSD (slave mode) SOUT output delay time ― ― tSD (master mode) SIN input setup time ― 50 tSS (slave mode) SIN input hold time ― 50 tSH *1: Clock period selected by S0CK3–0 of the serial port 0 mode register (SIO0MOD1) (*1) ― sec ― ― μs ― ― ns (*1) SCK ×0.5 (*1) SCK ×0.6 sec ― 180 ns ― 80 ns ― ― ns ― ― ns tSCYC tSW tSW SCK0* tSD tSD SOUT0 tSS tSH SIN0* *: Indicates the secondary function of the corresponding port. 24/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 AC CHARACTERISTICS (I2C Bus Interface: Standard Mode 100kHz) (DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. SCL clock frequency fSCL ⎯ 0 ⎯ 100 kHz SCL hold time ⎯ 4.0 ⎯ ⎯ μs tHD:STA (start/restart condition) SCL ”L” level time tLOW ⎯ 4.7 ⎯ ⎯ μs SCL ”H” level time tHIGH ⎯ 4.0 ⎯ ⎯ μs SCL setup time tSU:STA ⎯ 4.7 ⎯ ⎯ μs (restart condition) SDA hold time ⎯ 0 ⎯ ⎯ μs tHD:DAT SDA setup time tSU:DAT ⎯ 0.25 ⎯ ⎯ μs SDA setup time tSU:STO ⎯ 4.0 ⎯ ⎯ μs (stop condition) Bus-free time tBUF ⎯ 4.7 ⎯ ⎯ μs AC CHARACTERISTICS (I2C Bus Interface: Fast Mode 400kHz) (DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. SCL clock frequency fSCL ⎯ 0 ⎯ 400 kHz SCL hold time tHD:STA ⎯ 0.6 ⎯ ⎯ μs (start/restart condition) SCL ”L” level time tLOW ⎯ 1.3 ⎯ ⎯ μs SCL ”H” level time tHIGH ⎯ 0.6 ⎯ ⎯ μs SCL setup time tSU:STA ⎯ 0.6 ⎯ ⎯ μs (restart condition) SDA hold time ⎯ 0 ⎯ ⎯ μs tHD:DAT SDA setup time tSU:DAT ⎯ 0.1 ⎯ ⎯ μs SDA setup time ⎯ 0.6 ⎯ ⎯ μs tSU:STO (stop condition) Bus-free time ⎯ 1.3 ⎯ ⎯ μs tBUF Start condition Restart condition Stop condition P40/SDA P41/SCL tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF 25/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 Electrical Characteristics of Successive Approximation Type A/D Converter (DVDD= P5VDD=SPVDD= 4.5 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Resolution n ― ― ― 10 bits Integral non-linearity error −4 ― +4 IDL 2.7V ≤ VREF ≤ 5.5V Differential non-linearity DNL 2.7V ≤ VREF ≤ 5.5V −3 ― +3 error LSB Zero-scale error VOFF ― −4 ― +4 Full-scale error FSE ― −4 ― +4 Input impedance RI ― ― ― 5k Ω Reference voltage VREF 4.5 ― DVDD V Conversion time HSCLK=3.0M to 8.4MHz tCONV ― 102 ― φ/CH φ: Period of high-speed clock (HSCLK) DVDD Reference voltage VREF VDDL 1μF 10μF A VDDR - 10μF Analog input RI≤5kΩ + 0.1μF 10μF AIN0 ～ AIN7 VSS 26/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact LAPIS SEMICONDUCTOR’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 27/29 FEDL610Q380FULL-01 ML610Q380/ML610Q383/ML610Q384/ML610Q385 REVISION HISTORY Document No. Date FEDL610Q380FULL-01 Mar 09, 2012 Page Previous Current Edition Edition – – Description Formal edition 1 28/29 FEDL610Q380FULL-01 ML610Q380/ML610Q385 NOTES No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from LAPIS Semiconductor upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties. LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Copyright 2011-2012 LAPIS Semiconductor Co., Ltd. 29/29