Samsung K6R1004C1A 256kx4 high speed static ram(5v operating), revolutionary pin out Datasheet

PRELIMINARY
K6R1004C1A-C
CMOS SRAM
Document Title
256Kx4 High Speed Static RAM(5V Operating), Revolutionary Pin out.
Revision History
Rev. No.
History
Draft Data
Remark
Rev. 0.0
Initial release with Preliminary.
Apr. 22th, 1995
Preliminary
Rev. 1.0
Release to final Data Sheet.
1.1. Delete Preliminary
Feb. 29th, 1996
Final
Rev. 2.0
Update D.C parameters.
2.1. Update D.C parameters.
Previous spec.
Items
(12/15/17/20ns part)
Icc
200/190/180/170mA
Isb
30mA
Isb1
10mA
Jul. 16th, 1996
Final
Updated spec.
(12/15/17/20ns part)
150/145/145/140mA
25mA
8mA
Rev. 3.0
Add Industrial Temperature Range parts.
3.1. Add Industrial Temperature Range parts with the same parameters as Commercial Temperature Range parts.
3.1.1. Add K6R1004C1A parts for Industrial Temperature Range.
3.1.2. Add ordering information.
3.1.3. Add the condition for operating at Industrial Temp. Range.
3.2. Add the test condition for VOH1 with VCC=5V±5% at 25°C
3.3. Add timing diagram to define tWP as ″(Timing Wave Form of
Write Cycle(CS=Controlled)″
Jun. 2nd, 1997
Final
Rev. 4.0
4.1. Delete Industrial Temperature Range Part
4.2. Delete TSOP2 Package
4.3. Delete 17ns Part
Feb. 25th, 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 4.0
February 1998
PRELIMINARY
K6R1004C1A-C
CMOS SRAM
256K x 4 Bit (with OE)High-Speed CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 12, 15, 20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 25mA(Max.)
(CMOS) : 8mA(Max.)
Operating K6R1004C1A-12 : 150mA(Max.)
K6R1004C1A-15 : 145mA(Max.)
K6R1004C1A-20 : 140mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R1004C1A-J : 32-SOJ-400
The K6R1004C1A is a 1,048,576-bit high-speed Static Random
Access Memory organized as 262,144 words by 4 bits. The
K6R1004C1A uses 4 common input and output lines and has
an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for highspeed circuit technology. It is particularly well suited for use in
high-density
high-speed
system
applications.
The
K6R1004C1A is packaged in a 400 mil 32-pin plastic SOJ.
PIN CONFIGURATION(Top View)
N.C
1
32 A17
A0
2
31 A16
A1
3
30 A15
A2
4
29 A14
A3
5
28 A13
CS
6
27
I/O1
7
26 I/O4
Vcc
8
Vss
9
24 Vcc
I/O2
10
23 I/O3
WE
11
22 A12
A4
12
21 A11
A7
A5
13
20 A10
A8
A6
14
19
A9
A7
15
18
A8
N.C
16
17 N.C
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
Pre-Charge Circuit
A0
A2
A3
A4
A5
A6
I/O1~I/O4
Row Select
A1
Memory Array
512 Rows
512x4 Columns
I/O Circuit &
Column Select
Data
Cont.
SOJ
OE
25 Vss
CLK
Gen.
A9
PIN FUNCTION
A10
A12
A14
A16
A11
A13
A15
A17
Pin Name
A0 - A17
CS
WE
OE
WE
Write Enable
CS
Chip Select
OE
Output Enable
I/O1~I/O4
-2-
Pin Function
Address Inputs
Data Inputs/Outputs
VCC
Power(+5.0V)
VSS
Ground
N.C
No Connection
Rev 4.0
February 1998
PRELIMINARY
K6R1004C1A-C
CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Voltage on Any Pin Relative to V SS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Storage Temperature
Rating
Unit
VIN, VOUT
-0.5 to 7.0
V
VCC
-0.5 to 7.0
V
PD
1.0
W
TSTG
-65 to 150
°C
TA
0 to 70
°C
Operating Temperature
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
4.5
5.0
5.5
V
Ground
VSS
0
0
0
V
Input High Voltage
VIH
2.2
-
VCC+0.5**
V
Input Low Voltage
VIL
-0.5*
-
0.8
V
* VIL(Min) = -2.0V a.c(Pulse Width ≤ 10ns) for I ≤ 20mA.
** VIH (Max) = VCC + 2.0V a.c (Pulse Width ≤ 10ns) for I ≤ 20mA.
DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Min
Max
Unit
Input Leakage Current
Parameter
Symbol
ILI
VIN = VSS to VCC
Test Conditions
-2
2
µA
Output Leakage Current
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT = VSS to VCC
-2
2
µA
Operating Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL,
IOUT=0mA
12ns
-
150
mA
15ns
-
145
20ns
-
140
ISB
Min. Cycle, CS=VIH
-
25
mA
ISB1
f=0MHz, CS≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V
-
8
mA
Output Low Voltage Level
VOL
IOL=8mA
-
0.4
V
Output High Voltage Level
VOH
IOH=-4mA
2.4
-
V
-
3.95
V
Standby Current
VOH1*
IOH1=-0.1mA
* VCC=5.0V±5%, Temp =25°C
CAPACITANCE*(TA=25°C, f=1.0MHz)
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
Item
CI/O
VI/O=0V
-
8
pF
Input Capacitance
CIN
VIN=0V
-
6
pF
* Capacitance is sampled and not 100% tested.
-3-
Rev 4.0
February 1998
PRELIMINARY
K6R1004C1A-C
CMOS SRAM
AC CHARACTERISTICS (TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
Output Loads(A)
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5.0V
+5.0V
480Ω
480Ω
DOUT
255Ω
DOUT
255Ω
30pF*
5pF*
* Including Scope and Jig Capacitance
READ CYCLE
Parameter
Symbol
K6R1004C1A-12
Min
K6R1004C1A-15
Max
Min
K6R1004C1A-20
Max
Min
Max
Unit
Read Cycle Time
tRC
12
-
15
-
20
-
ns
Address Access Time
tAA
-
12
-
15
-
20
ns
Chip Select to Output
tCO
-
12
-
15
-
20
ns
Output Enable to Valid Output
tOE
-
6
-
7
-
9
ns
Chip Enable to Low-Z Output
tLZ
3
-
3
-
3
-
ns
Output Enable to Low-Z Output
tOLZ
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
tHZ
0
6
0
7
0
9
ns
Output Disable to High-Z Output
tOHZ
0
6
0
7
0
9
ns
Output Hold from Address Change
tOH
3
-
3
-
3
-
ns
Chip Selection to Power Up Time
tPU
0
-
0
-
0
-
ns
Chip Selection to Power DownTime
tPD
-
12
-
15
-
20
ns
-4-
Rev 4.0
February 1998
PRELIMINARY
K6R1004C1A-C
CMOS SRAM
WRITE CYCLE
Parameter
K6R1004C1A-12
Symbol
K6R1004C1A-15
K6R1004C1A-20
Min
Max
Min
Max
Min
Max
Unit
Write Cycle Time
tWC
12
-
15
-
20
-
ns
Chip Select to End of Write
tCW
8
-
10
-
12
-
ns
Address Setup Time
tAS
0
-
0
-
0
-
ns
Address Valid to End of Write
tAW
8
-
10
-
12
-
ns
Write Pulse Width(OE High)
tWP
8
-
10
-
12
-
ns
Write Pulse Width(OE Low)
tWP1
12
-
15
-
20
-
ns
Write Recovery Time
tWR
0
-
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
6
0
7
0
9
ns
Data to Write Time Overlap
tDW
6
-
7
-
9
-
ns
Data Hold from Write Time
tDH
0
-
0
-
0
-
ns
End Write to Output Low-Z
tOW
3
-
3
-
3
-
ns
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled, CS=OE=VIL , WE=VIH)
tRC
Address
tAA
tOH
Data Out
Valid Data
Previous Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tCO
CS
tHZ(3,4,5)
tOHZ
tOE
OE
tOH
tOLZ
tLZ(4,5)
Data out
Valid Data
VCC
ICC
Current
ISB
tPU
tPD
50%
50%
-5-
Rev 4.0
February 1998
PRELIMINARY
K6R1004C1A-C
CMOS SRAM
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
tWR(5)
tAW
OE
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
Data in
High-Z
tDH
Valid Data
tOHZ(6)
High-Z(8)
Data out
TIMING WAVEFORM OF WRITE CYCLE(2)
(OE=Low Fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tAS(4)
tWP1(2)
WE
tDW
Data in
High-Z
tDH
Valid Data
tWHZ(6)
tOW
High-Z(8)
Data out
-6-
(10)
(9)
Rev 4.0
February 1998
PRELIMINARY
K6R1004C1A-C
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
High-Z
Data in
Valid Data
tLZ
High-Z
tWHZ(6)
High-Z(8)
High-Z
Data out
tDH
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
CS
WE
OE
Mode
I/O Pin
Supply Current
H
X
X*
Not Select
High-Z
ISB, ISB1
L
H
H
Output Disable
High-Z
ICC
L
H
L
Read
DOUT
ICC
L
L
X
Write
DIN
ICC
* X means Don′t Care.
-7-
Rev 4.0
February 1998
PRELIMINARY
K6R1004C1A-C
CMOS SRAM
Units:millimeters/Inches
PACKAGE DIMENSIONS
32-SOJ-400
#17
10.16
0.400
#32
11.18 ±0.12
0.440 ±0.005
9.40 ±0.25
0.370 ±0.010
0.20
#1
0.69
0.027 MIN
21.36 MAX
0.841
20.95 ±0.12
0.825 ±0.005
( 1.30 )
0.051
( 1.30 )
0.051
( 0.95 )
0.0375
0.43
+0.10
-0.05
0.017 +0.004
-0.002
1.27
0.050
+0.10
-0.05
0.008 +0.004
-0.002
#16
0.71
3.76 MAX
0.148
0.10
MAX
0.004
+0.10
-0.05
0.028 +0.004
-0.002
-8-
Rev 4.0
February 1998
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