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MB88154A
Spread Spectrum Clock Generator
MB88154A is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can
be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. It corresponds to both of
the center spread which modulates input frequency as Middle Centered and down spread which modulates so as not to exceed input
frequency.
Features
■
Input frequency : 16.6 MHz to 67 MHz
■
Output frequency: 16.6 MHz to 67 MHz (One time input frequency)
■
Modulation rate can select from ± 0.5%, ± 1.0%,
■
Equipped with crystal oscillation circuit: Range of oscillation 16.6 MHz to 48 MHz
■
The external clock can be input: 16.6 MHz to 67 MHz
■
Modulation clock output duty : 40% to 60%
■
Modulation clock cycle-cycle jitter : Less than 100 ps
■
Low current consumption by CMOS process : 5.0 mA (24 MHz : Typ-sample, no load)
■
Power supply voltage : 3.3 V ± 0.3 V
■
Operating temperature :
■
Package : SOP 8-pin
± 1.5% or − 1.0%, − 2.0%, − 3.0%. (For center spread / down spread.)
− 40 °C to +85 °C
Cypress Semiconductor Corporation
Document Number: 002-08252 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 12, 2017
MB88154A
Contents
PRODUCT LINEUP ................................................................. 3
OUTPUT CLOCK DUTY CYCLE (TDCC, TDCR = TB/TA) . 13
PIN ASSIGNMENT .................................................................. 3
INPUT FREQUENCY (FIN = 1/TIN) ..................................... 13
PIN DESCRIPTION ................................................................. 3
OUTPUT SLEW RATE (SR) ................................................ 13
I/O CIRCUIT TYPE .................................................................. 4
CYCLE-CYCLE JITTER (TJC = | TN − TN + 1 |) ................. 14
HANDLING DEVICES ............................................................. 5
Preventing Latch-up ......................................................... 5
Handling unused pins ....................................................... 5
The attention when the external clock is used ................. 5
Power supply pins ............................................................ 5
Oscillation circuit .............................................................. 5
MODULATION WAVEFORM ................................................ 15
BLOCK DIAGRAM .................................................................. 6
ORDERING INFORMATION ................................................. 20
PIN SETTING .......................................................................... 7
PACKAGE DIMENSION ....................................................... 21
Document History ................................................................ 22
Sales, Solutions, and Legal Information ........................... 23
ABSOLUTE MAXIMUM RATINGS ........................................ 9
RECOMMENDED OPERATING CONDITIONS .................... 10
LOCK-UP TIME ..................................................................... 16
OSCILLATION CIRCUIT ....................................................... 17
INTERCONNECTION CIRCUIT EXAMPLE .......................... 18
EXAMPLE CHARACTERISTICS .......................................... 19
ELECTRICAL CHARACTERISTICS .................................... 11
Document Number: 002-08252 Rev. *B
Page 2 of 23
MB88154A
1. Product Lineup
MB88154A has two kinds of input frequency, and three kinds of modulation type (center/down spread), total six line-ups.
Product
Input/Output Frequency
Modulation Type
MB88154A-103
16.6 MHz to 40 MHz
MB88154A-112
33 MHz to 67 MHz
MB88154A-113
16.6 MHz to 40 MHz
Down spread
Center spread
2. Pin Assignment
TOP VIEW
CKOUT 1
8 SEL1
VDD 2
VSS 3
7 REFOUT
MB88154A
XIN 4
6 SEL0
5 XOUT
SOB008
3. Pin Description
Pin Name
I/O
Pin No.
CKOUT
O
1
Modulated clock output pin
VDD
2
Power supply voltage pin
VSS
⎯
⎯
3
GND pin
XIN
I
4
Crystal resonator connection pin/clock input pin
XOUT
O
5
Crystal resonator connection pin
SEL0
I
6
Modulation rate setting pin
REFOUT
O
7
Non-modulated clock output pin
SEL1
I
8
Modulation rate setting pin
Document Number: 002-08252 Rev. *B
Description
Page 3 of 23
MB88154A
4. I/O Circuit Type
Pin
Circuit Type
Remarks
SEL0
SEL1
CMOS hysteresis input
CKOUT
REFOUT
■
CMOS output
■
IOL = 3 mA
Note : For XIN and XOUT pins, refer to “Oscillation Circuit”
Document Number: 002-08252 Rev. *B
Page 4 of 23
MB88154A
5. Handling Devices
5.1 Preventing Latch-up
A latch-up can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an input or output pin or
(b) a voltage higher than the rating is applied between VDD pin and VSS pin. The latch-up, if it occurs, significantly increases the power
supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the
maximum rating.
5.2 Handling Unused Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pull-down resistor.
Unused output pin should be opened.
5.3 The Attention When the External Clock is Used
Input the clock to XIN pin, and XOUT pin should be opened when you use the external clock.
Please pay attention so that an overshoot and an undershoot do not occur to an input clock of XIN pin.
5.4 Power Supply Pins
Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source.
We recommend connecting electrolytic capacitor (about 10 μF) and the ceramic capacitor (about 0.01 μF) in parallel between VSS
pin and VDD pin near the device, as a bypass capacitor.
5.5 Oscillation Circuit
Noise near the XIN and XOUT pins may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN
or XOUT pin and the resonator do not intersect other wiring.
Design the printed circuit board that surrounds the XIN and XOUT pins with ground.
Document Number: 002-08252 Rev. *B
Page 5 of 23
MB88154A
6. Block Diagram
VDD
2
SEL1
SEL0
XOUT
8
Modulation rate
setting
1
CKOUT
7
REFOUT
Modulation
clock output
6
PLL block
Reference
clock
5
Reference clock output
4
XIN
Rf = 1 MΩ
3
VSS
1
−
M
Phase
compare
Reference
clock
1
−
N
Charge
pump
V/I
conversion
IDAC
Modulation
logic
MB88154A PLL block
Modulation
Clock
output
Loop filter
1
−
L
ICO
Modulation
rate setting/
Modulation
enable setting
A glitchless IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing
EMI.
Document Number: 002-08252 Rev. *B
Page 6 of 23
MB88154A
7. Pin Setting
SEL 0, SEL 1 Modulation Rate Setting
Modulation Rate
SEL1
SEL0
MB88154A-103
MB88154A-112, MB88154A-113
Down Spread
Center Spread
± 0.5%
± 1.0%
± 1.5%
No spread
L
L
L
H
H
L
− 1.0%
− 2.0%
− 3.0%
H
H
No spread
Notes:
■
The modulation rate can be changed at the level of the pin. Spectrum does not spread when “H” level is set to SEL0 and SEL1 pins.
The clock with low jitter can be obtained.
■
When changing the modulation rate setting, the stabilization wait time for the modulation clock is required. The stabilization wait
time for the modulation clock take the maximum value of “ Electrical Characteristics AC Characteristics Lock-Up time”.
Center Spread
Spectrum is spread (modulated) by centering on the input frequency.
Modulation width 3.0%
Radiation level
−1.5%
+1.5%
Frequency
Input frequency
Modulation rate center spread example of
Document Number: 002-08252 Rev. *B
± 1.5%
Page 7 of 23
MB88154A
Down Spread
Spectrum is spread (modulated) below the input frequency.
Modulation width 3.0%
Radiation level
−3.0%
Frequency
Frequency in modulation off
Modulation width down spread example of
Document Number: 002-08252 Rev. *B
− 3.0%
Page 8 of 23
MB88154A
8. Absolute Maximum Ratings
Parameter
Rating
Symbol
Power supply voltage*
VDD
Input voltage*
VI
Output voltage*
VO
Storage temperature
TST
Operation junction
temperature
TJ
Output current
IO
VIOVER
VIUNDER
Overshoot
Undershoot
Unit
Min
Max
− 0.5
VSS − 0.5
VSS − 0.5
− 55
− 40
+ 4.0
VDD + 0.5
VDD + 0.5
+ 125
+ 125
°C
°C
− 14
⎯
+ 14
mA
VDD + 1.0 (tOVER ≤ 50 ns)
V
VSS − 1.0 (tUNDER ≤ 50 ns)
⎯
V
V
V
V
* : The parameter is based on VSS = 0.0 V.
WARNING:
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of absolute maximum ratings. Do not exceed these ratings.
Overshoot/Undershoot
tUNDER ≤ 50 ns
VIOVER ≤ VDD + 1.0 V
VDD
Input pin
VSS
tOVER ≤ 50 ns
Document Number: 002-08252 Rev. *B
VIUNDER ≤ VSS − 1.0 V
Page 9 of 23
MB88154A
9. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Symbol
Pin
Conditions
Power supply voltage
VDD
VDD
“H” level input voltage
VIH
“L” level input voltage
VIL
XIN,
SEL0,
SEL1
Input clock duty cycle
tDCI
Input clock through rate
Operating temperature
WARNING:
Value
Unit
Min
Typ
Max
⎯
3.0
3.3
3.6
V
⎯
VDD × 0.80
⎯
VDD + 0.3
V
⎯
VSS
⎯
VDD × 0.20
V
XIN
16.6 MHz to 67 MHz
40
50
60
%
SRIN
XIN
Input frequency
40 MHz to 67 MHz
0.0475 × fin −
1.75
⎯
⎯
V/ns
Ta
⎯
⎯
− 40
⎯
+ 85
°C
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Input clock duty cycle (tDCI = tb/ta)
ta
tb
1.5 V
XIN
Input clock through rate (SRIN)
VDD × 0.80
VDD × 0.20
XIN
trin
tfin
Note : SRIN = (VDD × 0.80 − VDD × 0.20) /trin, SRIN = (VDD × 0.80 − VDD × 0.20) /tfin
Document Number: 002-08252 Rev. *B
Page 10 of 23
MB88154A
10. Electrical Characteristics
■
DC Characteristics
Parameter
(Ta = −40 °C to
Symbol
Pin
Conditions
Power supply current
ICC
VDD
Output voltage
VOH
CKOUT,
REFOUT
VOL
+ 85 °C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V)
Value
Unit
Min
Typ
Max
no load capacitance at 24
MHz output
⎯
5.0
7.0
mA
“H” level output
IOH = − 3 mA
VDD − 0.5
⎯
VDD
V
“L” level output
IOL = 3 mA
VSS
⎯
0.4
V
Output impedance
ZO
CKOUT,
REFOUT
16.6 MHz to 67 MHz
⎯
70
⎯
Ω
Input capacitance
CIN
XIN,
SEL0,
SEL1
Ta = + 25 °C,
VDD = VI = 0.0 V,
f = 1 MHz
⎯
⎯
16
pF
Document Number: 002-08252 Rev. *B
Page 11 of 23
MB88154A
■
AC Characteristics
Parameter
Oscillation frequency
Input frequency
Output frequency
(Ta = −40 °C to
Symbol
Pin
Conditions
fx
XIN,
XOUT
fin
fOUT
+ 85 °C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V)
Value
Min
Typ
Max
Fundamental oscillation
16.6
40
3rd over-tone oscillation
40
MB88154A-103/113
16.6
MB88154A-112
33
CKOUT,
REFOUT
MB88154A-103/113
16.6
MB88154A-112
33
⎯
⎯
⎯
⎯
⎯
⎯
⎯
XIN
Output slew rate
SR
CKOUT,
REFOUT
0.4 V to 2.4 V
load capacitance 15 pF
0.3
Output clock duty cycle
tDCC
CKOUT
1.5 V
40
tDCR
REFOUT
1.5 V
fMOD (nMOD)
CKOUT
Modulation frequency
(Number of input clocks
per modulation)
Unit
MHz
48
40
MHz
67
40
MHz
67
2.0
V/ns
60
%
tDCI − 10*
⎯
⎯
tDCI + 10*
%
MB88154A-103/113
fin/2640
(2640)
fin/2280
(2280)
fin/1920
(1920)
kHz
(clks)
MB88154A-112
fin/4400
(4400)
fin/3800
(3800)
fin/3200
(3200)
⎯
⎯
2
5
ms
⎯
100
ps-rms
Lock-Up time
tLK
CKOUT
⎯
Cycle-cycle jitter
tJC
CKOUT
No load capacitance,
Ta = +25 °C, VDD = 3.3 V
* : Duty of the REFOUT output is guaranteed only for the following A and B because it depends on tDCI of input clock duty.
A. Resonator : When resonator is connected with XIN and XOUT and oscillates normally.
B. External clock input : The input level is Full - swing (VSS − VDD).
<Definition of modulation frequency and number of input clocks per modulation>
fout (Output frequency)
Modulation wave form
t
fMOD (Min)
Clock count
nMOD (Max)
fMOD (Max)
Clock count
nMOD (Min)
t
MB88154A contains the modulation period to realize the efficient EMI reduction.
The modulation period fMOD depends on the input frequency and changes between fMOD (Min) and fMOD (Max) .
Furthermore, the average value of fMOD equals the typical value of the electrical characteristics.
Document Number: 002-08252 Rev. *B
Page 12 of 23
MB88154A
11. Output Clock Duty Cycle (tDCC, tDCR = tb/ta)
ta
tb
1.5 V
CKOUT,
REFOUT
12. Input Frequency (fin = 1/tin)
tin
0.8 VDD
XIN
13. Output Slew Rate (SR)
2.4 V
CKOUT,
REFOUT
0.4 V
tr
tf
Note : SR = (2.4−0.4) /tr, SR = (2.4−0.4) /tf
Document Number: 002-08252 Rev. *B
Page 13 of 23
MB88154A
14. Cycle-cycle Jitter (tJC = | tn − tn + 1 |)
CKOUT
tn
tn+1
Note : Cycle-cycle jitter is defined the difference between a certain cycle and immediately after
(or, immediately before) .
Document Number: 002-08252 Rev. *B
Page 14 of 23
MB88154A
15. Modulation Waveform
■
±1.5% modulation rate, Example of center spread
CKOUT
output frequency
+ 1.5 %
Frequency at modulation OFF
Time
− 1.5 %
fMOD
■
−1.0% modulation rate, Example of down spread
CKOUT
output freqquency
Frequency at modulation OFF
Time
− 0.5 %
− 1.0 %
fMOD
Document Number: 002-08252 Rev. *B
Page 15 of 23
MB88154A
16. Lock-up Time
VDD
3.0 V
Internal clock
stabilization wait time
XIN
Setting pin
VIH
SEL0,
SEL1
tLK
(lock-up time )
CKOUT
If the setting pin is fixed at the “H” or “L” level, the maximum time after the power is turned on until the set clock signal is output from
CKOUT pin is (the stabilization wait time of input clock to XIN pin) + (the lock-up time “tLK”). For the input clock stabilization time,
check the characteristics of the resonator or oscillator used.
Note : When the pin setting is changed, the CKOUT pin output clock stabilization time is required. Until the output clock signal
becomes stable, the output frequency, output clock duty cycle, modulation period, and cycle-cycle jitter cannot be guaranteed.
It is therefore advisable to perform processing such as cancelling a reset of the device at the succeeding stage after
the lock-up time.
Document Number: 002-08252 Rev. *B
Page 16 of 23
MB88154A
17. Oscillation Circuit
The left side of figures below shows the connection example about general resonator. The oscillation circuit has the built-in feedback
resistance (Rf) . The value of capacity (C1 and C2) is required adjusting to the most suitable value of an individual resonator.
The right side of figures below shows the example of connecting for the 3rd over-tone resonator. The value of capacity (C1, C2 and
C3) and inductance (L1) is needed adjusting to the most suitable value of an individual resonator. The most suitable value is different
by individual resonator. Please refer to the resonator manufacturer which use for the most suitable value. When an external clock is
used (the resonator is not used) , input the clock to XIN pin and do not connect anything with XOUT.
■
When using a resonator
MB88154A LSI Internal
Rf (1 MΩ)
Rf (1 MΩ)
XIN Pin
XOUT Pin
XIN Pin
XOUT Pin
MB88154A LSI External
L1
C2
C1
Normal resonator
■
C2
C1
C3
3rd over-tone resonator
When using an external clock
MB88154A LSI Internal
Rf (1 MΩ)
XIN Pin
External clock
XOUT Pin
MB88154A LSI External
OPEN
Note : Note that a jitter characteristic of an input clock may cause an affect a cycle-cycle jitter characteristic.
Document Number: 002-08252 Rev. *B
Page 17 of 23
MB88154A
18. Interconnection Circuit Example
SEL1
R2
1
8
2
7
MB88154A
+
R1
3
6
4
5
SEL0
C3
C4
ENS
Xtal
C1
C2
C1, C2
: Oscillation stabilization capacitance (refer to “ Oscillation Circuit”.)
C3
: Capacitor of 10 μF or higher
C4
: Capacitor about 0.01 μF (connect a capacitor of good high frequency property
(ex. laminated ceramic capacitor) to close to this device.)
R1, R2
: Impedance matching resistor for board pattern
Document Number: 002-08252 Rev. *B
Page 18 of 23
MB88154A
19. Example Characteristics
The condition of the examples of the characteristic is shown as follows: Input frequency = 20 MHz (Output frequency = 20 MHz :
Using MB88154A-113), Power - supply voltage = 3.3 V, None load capacity.
Modulation rate = ± 1.5% (center spread)
Spectrum analyzer HP4396B is connected with CKOUT. The result of the measurement with RBW = 1 kHz (ATT use for − 6dB).
CH B Spectrum
10 dB /REF 0 dBm
No modulation
−6.18 dBm
Avg
4
modulation ± 1.5 %
−26.03 dBm
RBW# 1 kHZ
VBW 1 kHZ
CENTER 20 MHZ
Document Number: 002-08252 Rev. *B
ATT 6 dB
SWP 2.505 s
SPAN 4 MHZ
Page 19 of 23
MB88154A
20. Ordering Information
Input/Output frequency
Modulation
type
Package
MB88154APNF-G-112-JNE1
33 MHz to 67 MHz
Center
MB88154APNF-G-113-JNE1
16.6 MHz to 40 MHz
8-pin plastic SOP
(SOB008)
MB88154APNF-G-103-JNEFE1
16.6 MHz to 40 MHz
Down
MB88154APNF-G-112-JNEFE1
33 MHz to 67 MHz
Center
MB88154APNF-G-113-JNEFE1
16.6 MHz to 40 MHz
MB88154APNF-G-103-JNERE1
16.6 MHz to 40 MHz
Down
MB88154APNF-G-112-JNERE1
33 MHz to 67 MHz
Center
MB88154APNF-G-113-JNERE1
16.6 MHz to 40 MHz
Part number
Document Number: 002-08252 Rev. *B
Remarks
Emboss taping
(EF type)
Emboss taping
(ER type)
Page 20 of 23
MB88154A
21. Package Dimension
b
0.36
0.44
0.52
L
0.45
0.60
0.75
L 2
0.25 BSC
1.27 BSC.
h
0.40 BSC.
002-15856 **
11. JEDEC SPECIFICATION NO. REF : N/A
Page 21 of 23
Document Number: 002-08252 Rev. *B
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DETAIL A
MB88154A
Document History
Spansion Publication Number: DS04-29129-2E
Document Title: MB88154A Spread Spectrum Clock Generator
Document Number: 002-08252
Revision
ECN
Orig. of
Change
Submission
Date
**
–
TAOA
06/29/2009
Initial Release
*A
5563140
TAOA
12/22/2016
Updated to Cypress Template
*B
5991372
TAOA
12/12/2017
Deleated EOL part number: MB88154A-101/102/111
Updated Package Dimensions: Updated to Cypress format.
Changed the package name from FPT-8P-M02 to SOB008.
Document Number: 002-08252 Rev. *B
Description of Change
Page 22 of 23
MB88154A
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© Cypress Semiconductor Corporation, 2007-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
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Document Number: 002-08252 Rev. *B
Revised December 12, 2017
Page 23 of 23