ON FDMF5820DC Smart power stage (sps) module with integrated temperature monitor Datasheet

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FDMF5820DC – Smart Power Stage (SPS) Module
with Integrated Temperature Monitor
Features
 Ultra-Compact 5 mm x 5 mm PQFN Copper-Clip
Package with Flip Chip Low-Side MOSFET and
Dual Cool Architecture



High Current Handling: 60 A

Auto DCM (Low-Side Gate Turn Off) Using
ZCD# Input





Thermal Monitor for Module Temperature Reporting

Fairchild PowerTrench MOSFETs for Clean
Voltage Waveforms and Reduced Ringing

Fairchild SyncFET™ Technology (Integrated
Schottky Diode) in Low-Side MOSFET







Integrated Bootstrap Schottky Diode

Operating Junction Temperature Range:
-40°C to +125°C

Fairchild Green Packaging and RoHS Compliance
3-State 3.3 V PWM Input Gate Driver
Dynamic Resistance Mode for Low-Side Drive
(LDRV) Slows Low-Side MOSFET during Negative
Inductor Current Switching
Programmable Thermal Shutdown (P_THDN)
HS-Short Detect Fault# / Shutdown
Dual Mode Enable / Fault# Pin
Internal Pull-Up and Pull-Down for ZCD# and
EN Inputs, respectively
®
Optimized / Extremely Short Dead-Times
Under-Voltage Lockout (UVLO) on VCC
Optimized for Switching Frequencies up to 1.5 MHz
PWM Minimum Controllable On-Time: 30 ns
Low Shutdown Current: < 3 µA
Optimized FET Pair for Highest Efficiency:
10 ~ 15% Duty Cycle
Description
The SPS family is Fairchild’s next-generation, fully
optimized, ultra-compact, integrated MOSFET plus
driver power stage solution for high-current, highfrequency, synchronous buck, DC-DC applications. The
FDMF5820DC integrates a driver IC with a bootstrap
Schottky diode, two power MOSFETs, and a thermal
monitor into a thermally enhanced, ultra-compact, 5 mm
x 5 mm package.
With an integrated approach, the SPS switching power
stage is optimized for driver and MOSFET dynamic
performance, minimized system inductance, and power
MOSFET RDS(ON). The SPS family uses Fairchild's high®
performance PowerTrench
MOSFET technology,
which reduces switch ringing, eliminating the need for a
snubber circuit in most buck converter applications.
A driver IC with reduced dead times and propagation
delays further enhances the performance. A thermal
monitor function warns of a potential over-temperature
situation. A programmable thermal shutdown function
turns off the driver if an over-temperature condition
occurs. The FDMF5820DC incorporates an Auto-DCM
Mode (ZCD#) for improved light-load efficiency. The
FDMF5820DC also provides a 3-state 3.3 V PWM input
for compatibility with a wide range of PWM controllers.
Applications

Servers and Workstations, V-Core and Non-V-Core
DC-DC Converters

Desktop and All-in-One Computers, V-Core and
Non-V-Core DC-DC Converters



High-Performance Gaming Motherboards

Small Form-Factor Voltage Regulator Modules
High-Current DC-DC Point-of-Load Converters
Networking and Telecom Microprocessor Voltage
Regulators
Ordering Information
Part Number
Current Rating
Package
Top Mark
FDMF5820DC
60 A
31-Lead, Clip Bond PQFN SPS, 5.0 mm x 5.0 mm Package
5820DC
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
www.fairchildsemi.com
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
May 2016
V5V
VIN
RVCC
CPVCC
PVCC
EN
CVCC
VCC
CVIN
VIN
GL
EN/FAULT#
RBOOT
PWM Input
BOOT
PWM
FDMF5820DC
OFF
ON
CBOOT
ZCD#
PHASE
TMON
SW
LOUT
VTMON
RTMON
ITMON
AGND
Figure 1.
VOUT
PGND
COUT
Typical Application Diagram
Functional Block Diagram
EN/
FAULT#
VCC
BOOT
PVCC
VIN
ITMON
←
TMON
THERMAL
MONITOR
0.8V/2.0V
1.5V
FAULT
LATCH
FAULT
VCC
PHASE
LEVEL
SHIFT
EN/UVLO
HDRV
POR
RUP_ PWM
PWM
SW
PWM INPUT
PVCC
PWM CONTROL
LOGIC
RDN_ PWM
LDRV1
PVCC
POR
VCC
GL
LDRV2
↓
10uA
ZCD/CCM/DCM
LOGIC
ZCD#
0.8V/2.0V
AGND
Figure 2.
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
PGND
Functional Block Diagram
www.fairchildsemi.com
2
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Application Diagram
1
TMON
PVCC
PGND
12
27
PGND
12
GL
13
26
PGND
13
SW
14
25
PGND
14
SW
15
24
PGND
15
SW
31
VIN
10
30
VIN
10
EN/
FAULT#
9
9
31
2
30
3
29
4
28
5
27
6
26
7
25
8
24
PWM
1
ZCD#
2
VCC
3
AGND
4
BOOT
5
NC
6
PHASE
7
VIN
8
32
AGND
VIN
29
11
11
28
Figure 3.
23
SW
23
22
SW
22
21
SW
21
20
SW
20
19
SW
19
18
SW
18
17
SW
17
16
SW
16
33
GL
Pin Configuration - Top View and Transparent View
Pin Definitions
Pin #
Name
Description
1
PWM
PWM input to the gate driver IC
2
ZCD#
Enable input for the ZCD (Auto DCM) comparator
3
VCC
Power supply input for all analog control functions; this is the “quiet” VCC
4, 32
AGND
Analog ground for analog portions of the IC and for substrate, internally tied to PGND
5
BOOT
Supply for the high-side MOSFET gate driver. A capacitor from BOOT to PHASE supplies
the charge to turn on the N-channel high-side MOSFET
6
NC
7
PHASE
No connect
Return connection for the boot capacitor, internally tied to SW node
8~11
VIN
Power input for the power stage
12~15, 28
PGND
Power return for the power stage
16~26
SW
Switching node junction between high-side and low-side MOSFETs; also input to the gate
driver SW node comparator and input into the ZCD comparator
27, 33
GL
Gate Low, Low-side MOSFET gate monitor
29
PVCC
Power supply input for LS
30
TMON
Temperature monitoring & reporting / programmable thermal shutdown pin
31
EN /
FAULT#
(1)
gate driver and boot diode
Dual-functionality: enable input to the gate driver IC; FAULT# - internal pull-down
(2)
physically pulls this pin LOW upon detection of fault condition (HS MOSFET short or
TMON signal exceeding 1.5 V)
Notes:
1. LS = Low Side.
2. HS = High Side.
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
www.fairchildsemi.com
3
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Pin Configuration
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA = TJ = 25°C
Symbol
VCC
PVCC
VEN/FAULT#
Parameter
Min.
Max.
Unit
Supply Voltage
Referenced to AGND
-0.3
6.0
V
Drive Voltage
Referenced to AGND
-0.3
6.0
V
Output Enable / Disable
Referenced to AGND
-0.3
6.0
V
VPWM
PWM Signal Input
Referenced to AGND
-0.3
VCC+0.3
V
VZCD#
ZCD Mode Input
Referenced to AGND
-0.3
6.0
V
Low Gate Manufacturing Test
Pin
Referenced to AGND (DC only)
-0.3
6.0
Referenced to AGND, AC <20 nS
-3.0
6.0
Thermal Monitor
Referenced to AGND
-0.3
6.0
V
Power Input
Referenced to PGND, AGND
-0.3
25.0
V
Referenced to PGND, AGND (DC Only)
-0.3
25.0
Referenced to PGND, AC < 20 ns
-7.0
30.0
Referenced to PGND, AGND (DC Only)
-0.3
25.0
Referenced to PGND, AC < 20 ns
-7.0
30.0
Referenced to AGND (DC Only)
-0.3
30.0
Referenced to AGND, AC < 20 ns
-5.0
35.0
Referenced to PVCC
-0.3
6.0
VGL
VTMON
VIN
VPHASE
PHASE
VSW
Switch Node Input
VBOOT
Bootstrap Supply
VBOOT-PHASE Boot to PHASE Voltage
IO(AV)
(3)
IFAULT
θJ-A
θJ-PCB
Output Current
55
-0.1
V
V
V
V
A
7.0
mA
Junction-to-Ambient Thermal Resistance
12.4
°C/W
Junction-to-PCB Thermal Resistance (under Fairchild SPS Thermal Board)
1.8
°C/W
+125
°C
+150
°C
+150
°C
Ambient Temperature Range
TJ
Maximum Junction Temperature
ESD
60
fSW = 1 MHz, VIN=12 V, VOUT=1.8 V
EN / FAULT# Sink Current
TA
TSTG
fSW = 300 kHz, VIN=12 V, VOUT=1.8 V
V
-40
Storage Temperature Range
Electrostatic Discharge
Protection
-55
Human Body Model,
ANSI/ESDA/JEDEC JS-001-2012
3000
Charged Device Model, JESD22-C101
2500
V
Note:
3. IO(AV) is rated with testing Fairchild’s SPS evaluation board at TA = 25°C with natural convection cooling. This
rating is limited by the peak SPS temperature, TJ = 150°C, and varies depending on operating conditions and
PCB layout. This rating may be changed with different application settings.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
Operating Conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
PVCC
VIN
TJ
Notes:
4.
5.
Parameter
Control Circuit Supply Voltage
Gate Drive Circuit Supply Voltage
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
5.0
5.5
V
12.0
16.0
4.5
Output Stage Supply Voltage
4.5
Operating Junction Temperature
(4)
-40
(5)
+125
V
°C
3.0 V VIN is possible according to the application condition.
Operating at high VIN can create excessive AC voltage overshoots on the SW-to-GND and BOOT-to-GND nodes during
MOSFET switching transient. For reliable SPS operation, SW to GND and BOOT to GND must remain at or below the Absolute
Maximum Ratings in the table above.
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
www.fairchildsemi.com
4
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Absolute Maximum Ratings
Typical value is under VIN=12 V, VCC=PVCC=5 V and TA=TJ=+ 25°C unless otherwise noted. Minimum / Maximum
values are under VIN=12 V, VCC=PVCC=5 V ± 10% and TJ=TA=-40 ~ 125°C unless otherwise noted.
Symbol
Parameter
Condition
Min. Typ.
Max.
Unit
2
mA
Basic Operation
IQ
Quiescent Current
IQ=IVCC + IPVCC, EN=HIGH, PWM=LOW or
HIGH or Float (Non-Switching)
ISHDN
Shutdown Current
ISHDN=IVCC + IPVCC, EN=GND
VUVLO
UVLO Threshold
VCC Rising
VUVLO_HYST
UVLO Hysteresis
tD_POR
POR Delay to Enable IC
3.5
3.8
3
µA
4.1
V
20
µs
0.4
VCC UVLO Rising to Internal PWM Enable
V
EN Input
VIH_EN
High-Level Input Voltage
VIL_EN
Low-Level Input Voltage
RPLD_EN
2.0
V
0.8
Pull-Down Resistance
tPD_ENL
EN LOW Propagation Delay
PWM=GND, EN Going LOW to GL Going
LOW
tPD_ENH
EN HIGH Propagation Delay
PWM=GND, EN Going HIGH to GL
Going HIGH
V
250
kΩ
25
ns
20
µs
ZCD# Input
VIH_ZCD#
High-Level Input Voltage
VIL_ZCD#
Low-Level Input Voltage
IPLU_ZCD#
Pull-Up Current
tPD_ZLGLL
ZCD# LOW Propagation Delay
tPD_ZHGLH
ZCD# HIGH Propagation Delay
2.0
V
0.8
V
10
µA
PWM=GND, ZCD# Going LOW to GL
Going LOW (assume IL <=0)
10
ns
PWM=GND, ZCD# Going HIGH to GL
Going HIGH
10
ns
PWM Input
RUP_PWM
Pull-Up Impedance
23
kΩ
RDN_PWM
Pull-Down Impedance
10
kΩ
VIH_PWM
PWM High Level Voltage
VTRI_Window
VIL_PWM
3-State Window
PWM Low Level Voltage
tD_HOLD-OFF
3-State Shut-Off Time
VHIZ_PWM
3-State Open Voltage
Typical Values: TA=TJ=25°C,
VCC=PVCC=5 V,
Min. / Max. Values:
TA=TJ=-40°C to 125°C,
VCC=PVCC=5 V ±10%
2.2
V
1.2
1.3
1.8
V
0.8
V
90
130
ns
1.5
1.7
V
Minimum Controllable On-Time
tMIN_PWM_ON
PWM Minimum Controllable OnTime
Minimum PWM HIGH Pulse Required for
SW Node to Switch from GND to VIN
30
ns
Forced Minimum GL HIGH Time
tMIN_GL_HIGH
Forced Minimum GL HIGH
Minimum GL HIGH Time when LOW
VBOOT-SW detected and PWM
LOW=<100 ns
100
ns
PWM Propagation Delays & Dead Times (VIN=12 V, VCC=PVCC=5 V, fSW=1 MHz, IOUT=20 A, TA=25°C)
tPD_PHGLL
PWM HIGH Propagation Delay
PWM Going HIGH to GL Going LOW,
VIH_PWM to 90% GL
(6)
tPD_PLGHL
PWM LOW Propagation Delay
PWM Going LOW to GH
VIL_PWM to 90% GH
Going LOW,
tPD_PHGHH
PWM HIGH Propagation Delay
(ZCD# Held LOW)
PWM Going HIGH to GH Going HIGH,
VIH_PWM to 10% GH (ZCD#=LOW, IL=0,
Assumes DCM)
15
ns
30
ns
10
ns
Continued on the following page…
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
www.fairchildsemi.com
5
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Electrical Characteristics
Typical value is under VIN=12 V, VCC=PVCC=5 V and TA=TJ=+ 25°C unless otherwise noted. Minimum / Maximum
values are under VIN=12 V, VCC=PVCC=5 V ± 10% and TJ=TA=-40 ~ 125°C unless otherwise noted.
Symbol
Parameter
Condition
Min. Typ.
Max.
Unit
tD_DEADON
LS Off to HS On Dead Time
GL Going LOW to GH Going HIGH, 10%
GL to 10% GH, PWM Transition LOW to
HIGH – See Figure 27
10
ns
tD_DEADOFF
HS Off to LS On Dead Time
GH Going LOW to GL Going HIGH, 10%
GH to 10% GL, PWM Transition HIGH to
LOW – See Figure 27
5
ns
tR_GH_20A
GH Rise Time under 20 A IOUT
10% GH to 90% GH, IOUT=20 A
9
ns
tF_GH_20A
GH Fall Time under 20 A IOUT
90% GH to 10% GH, IOUT=20 A
9
ns
tR_GL_20A
GL Rise Time under 20 A IOUT
10% GL to 90% GL, IOUT=20 A
9
ns
tF_GL_20A
GL Fall Time under 20 A IOUT
90% GL to 10% GL, IOUT=20 A
6
ns
tPD_TSGHH
Exiting 3-State Propagation
Delay
PWM (from 3-State) Going HIGH to GH
Going HIGH, VIH_PWM to 10% GH
45
ns
tPD_TSGLH
Exiting 3-State Propagation
Delay
PWM (from 3-State) Going LOW to GL
Going HIGH, VIL_PWM to 10% GL
45
ns
High-Side Driver (HDRV, VCC = PVCC = 5 V)
RSOURCE_GH
Ω
Output Impedance, Sourcing
Source Current=100 mA
0.68
Output Impedance, Sinking
Sink Current=100 mA
0.9
Ω
tR_GH
GH Rise Time
10% GH to 90% GH, CLOAD=1.3 nF
4
ns
tF_GH
GH Fall Time
90% GH to 10% GH, CLOAD=1.3 nF
3
ns
0.82
Ω
RSINK_GH
Weak Low-Side Driver (LDRV2 Only under CCM2 Mode Operation, VCC = PVCC = 5 V)
RSOURCE_GL
Output Impedance, Sourcing
Source Current=100 mA
ISOURCE_GL
Output Sourcing Peak Current
GL=2.5 V
RSINK_GL
Output Impedance, Sinking
Sink Current=100 mA
ISINK_GL
Output Sinking Peak Current
GL=2.5 V
2
A
0.86
Ω
2
A
Low-Side Driver (Paralleled LDRV1 + LDRV2 under CCM1 Mode Operation, VCC = PVCC = 5 V)
0.47
Ω
4
A
0.29
Ω
RSOURCE_GL
Output Impedance, Sourcing
Source Current=100 mA
ISOURCE_GL
Output Sourcing Peak Current
GL=2.5 V
RSINK_GL
Output Impedance, Sinking
Sink Current=100 mA
ISINK_GL
Output Sinking Peak Current
GL=2.5 V
7
A
tR_GL
GL Rise Time
10% GL to 90% GL, CLOAD=7.0 nF
9
ns
tF_GL
GL Fall Time
90% GL to 10% GL, CLOAD=7.0 nF
6
ns
Thermal Monitor Current
ITMON_25
Thermal Monitor Current
TA=TJ=25°C
ITMON_150
Thermal Monitor Current
TA=TJ=150°C
Thermal Monitor Current Slope
TA=TJ=25 ~ 150°C
ITMON_SLOPE
39.3
40.2
41.0
µA
58
µA
0.144
µA/°C
Programmable Thermal Shutdown
VACT_PTHDN
Activation Voltage
RPLD_EN-PTHDN Pull-Down Resistance
TA=TJ=125 ~ 150°C, RTMON=25 kΩ
1.39
1.62
Ω
30
TA=TJ=25°C, IPLD_EN-PTHDN=5 mA
V
Catastrophic Fault (SW Monitor)
VSW_MON
SW Monitor Reference Voltage
1.3
2
V
tD_FAULT
Propagation Delay to Pull EN /
FAULT# Signal = LOW
20
ns
0.4
V
Boot Diode
VF
Forward-Voltage Drop
IF=10 mA
VR
Breakdown Voltage
IR=1 mA
30
V
Note:
6. GH = Gate High, internal gate pin of the high-side MOSFET.
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
www.fairchildsemi.com
6
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Electrical Characteristics
65
12
60
11
55
10
Module Power Loss, PL MOD [W]
Module Output Current, IOUT [A]
Test Conditions: VIN=12 V, VCC=PVCC=5 V, VOUT=1.8 V, LOUT=250 nH, TA=25°C and natural convection cooling,
unless otherwise noted.
50
FSW = 300kHz
45
40
35
FSW = 1000kHz
30
25
20
15
10
12Vin, 800kHz
9
12Vin, 1000kHz
8
7
6
5
4
3
2
0
0
0
25
50
75
100
PCB Temperature, T PCB [ C]
Figure 4.
125
0
150
Safe Operating Area
5
15 20 25 30 35 40 45
Module Output Current, IOUT [A]
50
55
60
Power Loss vs. Output Current
1.12
PVCC & VVCC = 5V, VOUT = 1.8V, FSW = 500kHz, IOUT = 30A
VIN = 12V, PVCC & VCC = 5V, VOUT = 1.8V, IOUT = 30A
1.10
Normalized Module Power Loss
1.4
Normalized Module Power Loss
10
Figure 5.
1.5
1.3
1.2
1.1
1.0
0.9
0.8
1.08
1.06
1.04
1.02
1.00
0.98
0.96
200
300
Figure 6.
400
500
600
700
800
900
Module Switching Frequency, F SW [kHz]
1000
1100
4
Power Loss vs. Switching Frequency
6
Figure 7.
1.12
8
10
12
14
Module Input Voltage, VIN [V]
16
18
Power Loss vs. Input Voltage
1.5
VIN = 12V, PVCC & VVCC = 5V, FSW = 500kHz, IOUT = 30A
VIN = 12V, VOUT = 1.8V, FSW = 500kHz, IOUT = 30A
Normalized Module Power Loss
1.10
Normalized Module Power Loss
PVCC & VCC = 5V, VOUT = 1.8V
12Vin, 500kHz
1
VIN = 12V, PVCC & VCC = 5V, VOUT = 1.8V
5
12Vin, 300kHz
1.08
1.06
1.04
1.02
1.00
0.98
0.96
1.4
1.3
1.2
1.1
1.0
0.9
4.0
Figure 8.
4.5
5.0
5.5
Driver Supply Voltage, PVCC & VCC [V]
6.0
0.5
Power Loss vs. Driver Supply Voltage
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
1.0
Figure 9.
1.5
2.0
2.5
Module Output Voltage, VOUT [V]
3.0
3.5
Power Loss vs. Output Voltage
www.fairchildsemi.com
7
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Typical Performance Characteristics
Test Conditions: VIN=12 V, VCC=PVCC=5 V, VOUT=1.8 V, LOUT=250 nH, TA=25°C and natural convection cooling,
unless otherwise noted.
1.01
0.07
VIN = 12V, PVCC & VCC = 5V, VOUT = 1.8V, IOUT = 0A
Driver Supply Current, IPVCC + IVCC [A]
Normalized Module Power Loss
VIN = 12V, PVCC & VVCC = 5V, FSW = 500kHz, VOUT = 1.8V, IOUT = 30A
1.00
0.99
0.98
0.97
0.06
0.05
0.04
0.03
0.02
0.01
200
250
Figure 10.
300
350
400
Output Inductor, LOUT [nH]
450
500
200
Power Loss vs. Output Inductor
Figure 11.
0.036
1000
1100
Driver Supply Current vs. Switching
Frequency
VIN = 12V, PVCC & VVCC = 5V, VOUT = 1.8V
1.04
0.034
Normalized Driver Supply Current
Driver Supply Current, IPVCC + IVCC [A]
400
500
600
700
800
900
Module Switching Frequency, F SW [kHz]
1.06
VIN = 12V, VOUT = 1.8V, FSW = 500kHz, IOUT = 0A
0.032
0.03
0.028
0.026
0.024
0.022
0.02
1.02
FSW = 1000kHz
1.00
0.98
0.96
FSW = 300kHz
0.94
0.92
0.90
0.88
4.0
4.5
5.0
5.5
Driver Supply Voltage, PVCC & VVCC [V]
Figure 12.
6.0
0
5
Driver Supply Current vs. Driver Supply Figure 13.
Voltage
4.0
10
15 20 25 30 35 40 45
Module Output Current, IOUT [A]
50
55
60
Driver Supply Current vs. Output Current
2.2
TA = 25°C
UVLOUP
PWM Threshold Voltage, VPWM [V]
3.9
Driver Supply Voltage, VCC [V]
300
3.8
3.7
3.6
3.5
UVLODN
3.4
VIH_PWM
2.0
VTRI_HI
1.8
VHIZ_PWM
1.6
1.4
1.2
VTRI_LO
1.0
VIL_PWM
0.8
3.3
-55
Figure 14.
0
25
55
100
Driver IC Junction Temperature, T J [oC]
UVLO Threshold vs. Temperature
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
4.50
125
Figure 15.
4.75
5.00
5.25
Driver Supply Voltage, VCC [V]
5.50
PWM Threshold vs. Driver Supply Voltage
www.fairchildsemi.com
8
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Typical Performance Characteristics
Test Conditions: VIN=12 V, VCC=PVCC=5 V, VOUT=1.8 V, LOUT=250 nH, TA=25°C and natural convection cooling,
unless otherwise noted.
2.2
1.8
VIH_PWM
TA = 25°C
1.7
2.0
ZCD# Threshold Voltage, VZCD# [V]
PWM Threshold Voltage, VPWM [V]
VCC = 5V
VTRI_HI
1.8
1.6
VHIZ_PWM
1.4
1.2
VTRI_LO
1.0
VIH_ZCD#
1.6
1.5
1.4
1.3
1.2
VIL_ZCD#
1.1
VIL_PWM
0.8
1.0
-55
0
25
55
100
Driver IC Junction Temperature, T J [oC]
Figure 16.
125
4.50
PWM Threshold vs. Temperature
Figure 17.
2
ZCD# Threshold vs. Driver Supply
Voltage
VCC = 5V
ZCD# Pull-Up Current, IPLU [uA]
1.9
1.8
1.7
1.6
1.5
VIH_ZCD#
1.4
1.3
1.2
0.2
0.18
0.16
0.14
0.12
VIL_ZCD#
1.1
0.1
1
-55
0
25
55
100
-55
125
Driver IC Junction Temperature, T J [oC]
Figure 18.
0
25
55
100
125
Driver IC Junction Temperature, T J [oC]
ZCD# Threshold vs. Temperature
Figure 19.
2.2
ZCD# Pull-Up Current vs. Temperature
2.0
VCC = 5V
TA = 25°C
1.9
2.0
VIH_EN
1.8
EN Threshold Voltage, VEN [V]
EN Threshold Voltage, VEN [V]
5.50
0.22
VCC = 5V
ZCD# Threshold Voltage, VZCD# [V]
4.75
5.00
5.25
Driver Supply Voltage, VCC [V]
1.8
1.6
1.4
VIL_EN
1.2
1.7
1.6
1.5
VIH_EN
1.4
1.3
1.2
VIL_EN
1.1
1.0
1.0
4.50
Figure 20.
4.75
5.00
5.25
Driver Supply Voltage, VCC [V]
5.50
-55
EN Threshold vs. Driver Supply Voltage
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
Figure 21.
0
25
55
100
Driver IC Junction Temperature, T J [oC]
125
EN Threshold vs. Temperature
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9
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Typical Performance Characteristics
Test Conditions: VIN=12 V, VCC=PVCC=5 V, VOUT=1.8 V, LOUT=250 nH, TA=25°C and natural convection cooling,
unless otherwise noted.
0.43
500
IF = 10mA
Boot Diode Forward Voltage, V F [mV]
EN Pull-Down Current, IPLD [uA]
VCC = 5V
0.42
0.41
0.4
0.39
0.38
450
400
350
300
0.37
-55
Figure 22.
0
25
55
100
Driver IC Junction Temperature, T J [oC]
-55
125
EN Pull-Down Current vs. Temperature
Figure 23.
2.5
125
Boot Diode Forward Voltage
vs. Temperature
1.25
PVCC & VCC = 5V, PWM = 0V, ZCD# = 0V, EN = 0V
PVCC & VCC = 5V, ZCD# = 5V, EN = 5V
Driver Quiescent Current, IQ [mA]
Driver Shut-Down Current, ISHDN [uA]
0
25
55
100
Driver IC Junction Temperature, T J [oC]
2
1.5
1
0.5
0
-0.5
-1
PWM = 0V
1.2
1.15
PWM = Float
1.1
PWM = 5V
1.05
1
0.95
0.9
-55
0
25
55
100
Driver IC Junction Temperature, T J [oC]
Figure 24.
Driver Shutdown Current
vs. Temperature
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
125
-55
Figure 25.
0
25
55
100
Driver IC Junction Temperature, T J [oC]
125
Driver Quiescent Current vs. Temperature
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10
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Typical Performance Characteristics
The SPS FDMF5820DC is a driver-plus-MOSFET
module optimized for the synchronous buck converter
topology. A PWM input signal is required to properly
drive the high-side and the low-side MOSFETs. The part
is capable of driving speed up to 1.5 MHz.
EN / FAULT# (Enable / Fault Flag)
The driver can be disabled by pulling the EN / FAULT#
pin LOW (EN < VIL_EN), which holds both GL and GH
LOW regardless of the PWM input state. The driver can
be enabled by raising the EN / FAULT# pin voltage
HIGH (EN > VIH_EN). The driver IC has less than 3 µA
shutdown current when it is disabled. Once the driver is
re-enabled, it takes a maximum of 20 µs startup time.
Power-On Reset (POR)
The PWM input stage should incorporate a POR feature
to ensure both LDRV and HDRV are forced inactive
(LDRV = HDRV = 0) until UVLO > ~ 3.8 V (rising
threshold). After all gate drive blocks are fully powered
on and have finished the startup sequence, the internal
driver IC EN_PWM signal is released HIGH, enabling
the driver outputs. Once the driver POR has finished
(<20 µs maximum), the driver follows the state of the
PWM signal (it is assumed that at startup the controller
is either in a high-impedance state or forcing the PWM
signal to be within the driver 3-state window).
EN / FAULT# pin is an open-drain output for fault flag
with an internal 250 kΩ pull-down resistor. Logic HIGH
signal from PWM controller or a ~ 10 kΩ external pull-up
resistor from EN / FAULT# pin to VCC is required to
start driver operation.
Table 1.
Three conditions below must be supported for normal
startup / power-up.



VCC rises to 5 V, then EN goes HIGH;
EN pin is tied to the VCC pin;
UVLO and Enable Logic
UVLO
EN
Driver State
0
X
Disabled (GH & GL = 0)
1
0
Disabled (GH & GL = 0)
1
1
Enabled (see Table 2)
1
Open
Disabled (GH & GL = 0)
EN is commanded HIGH prior to 5 V VCC reaching
the UVLO rising threshold.
The POR method is to increase the VCC over than UVLO
> rising threshold and EN = HIGH.
The EN / FAULT# pin has two functions: enabling /
disabling driver and fault flag. The fault flag signal is
active LOW. When the driver detects a fault condition
during operation, it turns on the open-drain on the EN /
FAULT# pin and the pin voltage is pulled LOW. The
fault conditions are:
Under-Voltage Lockout (UVLO)

UVLO is performed on VCC only, not on PVCC or VIN.
When the EN is set HIGH and VCC is rising over the
UVLO threshold level (3.8 V), the part starts switching
operation after a maximum 20 µs POR delay. The delay
is implemented to ensure the internal circuitry is biased,
stable, and ready to operate. Two VCC pins are
provided: PVCC and VCC. The gate driver circuitry is
powered from the PVCC rail. The user connects PVCC
to VCC through a low-pass R-C filter. This provides a
filtered 5 V bias to the analog circuitry on the IC.
High-side MOSFET false turn-on or VIN ~ SW short
during low-side MOSFET turn on;

P-THDN by exceeding 1.5 V on TMON pin.
When the driver detects a fault condition and disables
itself, a POR event on VCC is required to restart the
driver operation.
3-State PWM Input
The FDMF5820DC incorporates a 3-state 3.3 V PWM
input gate drive design. The 3-state gate drive has both
logic HIGH and LOW levels, along with a 3-state
shutdown window. When the PWM input signal enters
and remains within the 3-state window for a defined
hold-off time (tD_HOLD-OFF), both GL and GH are pulled
LOW. This feature enables the gate drive to shut down
both the high-side and the low-side MOSFETs to
support features such as phase shedding, a common
feature on multi-phase voltage regulators.
Driver
State
Enable
Disable
Table 2.
3.4
3.8
VCC [V]
* EN pin keeps HIGH
Figure 26.
UVLO on VCC
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
EN / PWM / 3-State / ZCD# Logic States
EN
PWM
ZCD#
GH
GL
0
X
X
0
0
1
3-State
X
0
0
1
0
0
0
1 (IL > 0), 0 (IL < 0)
1
1
0
1
0
1
0
1
0
1
1
1
1
1
0
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11
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Functional Description
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
VIH_PWM
VIL_PWM
PWM
GL
90%
90%
10%
10%
GH-PHASE
(internal)
90%
90%
10%
10%
BOOT-GND
PVCC - VF_DBOOT - 1V
90%
SW
tPD_PHGLL tD_DEADON tRISE_GH
tFALL_GL
tPD_PLGHL tD_DEADOFF
tFALL_GH
tRISE_GL
tPD_PHGLL = PWM HI to GL LO, VIH_PWM to 90% GL
tPD_PLGLH
tFALL_GL = 90% GL to 10% GL
tD_DEADON = LS Off to HS On Dead Time, 10% GL to VBOOT-GND <= PVCC - VF_DBOOT - 1V or BOOT-GND dip start point
tRISE_GH = 10% GH to 90% GH, VBOOT-GND <= PVCC - VF_DBOOT - 1V or BOOT-GND dip start point to GL bounce start point
tPD_PLGHL = PWM LO to GH LO, VIL_PWM to 90% GH or BOOT-GND decrease start point, tPD_PLGLH - tD_DEADOFF - tFALL_GH
tFALL_GH = 90% GH to 10% GH, BOOT-GND decrease start point to 90% VSW or GL dip start point
tD_DEADOFF = HS Off to LS On Dead Time, 90% VSW or GL dip start point to 10% GL
tRISE_GL = 10% GL to 90% GL
tPD_PLGLH = PWM LO to GL HI, VIL_PWM to 10% GL
Figure 27.
PWM Timing Diagram
(7)
(7)
VIH_PWM(11)
VIH_PWM
VTRI_HI
VTRI_HI(9)
VTRI_LO(10)
VTRI_LO
VIL_PWM(12)
VIL_PWM
PWM
3-State
Window
3-State
Window
(8)
(8)
GH-PHASE
GL
Figure 28.
PWM Threshold Definition
Notes:
7. The timing diagram in Figure 28 assumes very slow ramp on PWM.
8. Slow ramp of PWM implies the PWM signal remains within the 3-state window for a time >>> tD_HOLD-OFF.
9. VTRI_HI = PWM trip level to enter 3-state on PWM falling edge.
10. VTRI_LO = PWM trip level to enter 3-state on PWM rising edge.
11. VIH_PWM = PWM trip level to exit 3-state on PWM rising edge and enter the PWM HIGH logic state.
12. VIL_PWM = PWM trip level to exit 3-state on PWM falling edge and enter the PWM LOW logic state.
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
www.fairchildsemi.com
12
SPS FDMF5820DC requires four (4) input signals to
conduct normal switching operation: VIN, VCC / PVCC,
PWM, and EN. PWM should not be applied before VCC
and the amplitude of PWM should not be higher than
VCC. All other combinations of their power sequences
are allowed. The below example of a power sequence
is for a reference application design:
The MOSFET gate driver in SPS FDMF5820DC
operates in one of three modes, described below.

Continuous Current Mode 1 (CCM1) with Positive
Inductor Current
In this mode, inductor current is always flowing towards
the output capacitor, typical of a heavily loaded power
stage. The high-side MOSFET turns on with the lowside body diode conducting inductor current and SW is
approximately a VF below ground, meaning hardswitched turn-on and turn-off of the high-side MOSFET.
From no input signals
-> VIN On: Typical 12 VDC
-> VCC / PVCC On: Typical 5 VDC
-> EN HIGH: Typical 5 VDC
-> PWM Signaling: 3.3 V HIGH / 0 V LOW
The VIN pins are tied to the system main DC power rail.
PVCC and VCC pins are tied together to supply gate
driving and logic circuit powers from the system VCC
rail. Or the PVCC pin can be directly tied to the system
VCC rail, and the VCC pin is powered by PVCC pin
through a filter resistor located between PVCC pin and
VCC pin. The filter resistor reduces switching noise
impact from PVCC to VCC.
The EN pin can be tied to the VCC rail with an external
pull-up resistor and it will maintain HIGH once the VCC
rail turns on. Or the EN pin can be directly tied to the
PWM controller for other purposes.
Discontinuous Current Mode (DCM)
Typical of lightly loaded power stage; the high-side
MOSFET turns on with zero inductor current, ramps the
inductor current, then returns to zero every switching
cycle. When the high-side MOSFET turns on under
DCM operation, the SW node may be at any voltage
from a VF below ground to a VF above VIN. This is
because after the low-side MOSFET turns off, the SW
node capacitance resonates with the inductor current.
The level shifter in driver IC should be able to turn on
the high-side MOSFET regardless of the SW node
voltage. In this case, the high-side MOSFET turns off a
positive current.
High-Side Driver
The high-side driver (HDRV) is designed to drive a
floating N-channel MOSFET (Q1). The bias voltage for
the high-side driver is developed by a bootstrap supply
circuit, consisting of the internal Schottky diode and
external bootstrap capacitor (CBOOT). During startup, the
SW node is held at PGND, allowing CBOOT to charge to
PVCC through the internal bootstrap diode. When the
PWM input goes HIGH, HDRV begins to charge the
gate of the high-side MOSFET (internal GH pin). During
this transition, the charge is removed from the CBOOT
and delivered to the gate of Q1. As Q1 turns on, SW
rises to VIN, forcing the BOOT pin to VIN + VBOOT, which
provides sufficient VGS enhancement for Q1. To
complete the switching cycle, Q1 is turned off by pulling
HDRV to SW. CBOOT is then recharged to PVCC when
the SW falls to PGND. HDRV output is in phase with
the PWM input. The high-side gate is held LOW when
the driver is disabled or the PWM signal is held within
the 3-state window for longer than the 3-state hold-off
time, tD_HOLD-OFF.
During this mode, both LDRV1 and LDRV2 operate in
parallel and the low-side gate driver pull-up and pulldown resistors are operating at full strength.
Continuous Current Mode 2 (CCM2) with Negative
Inductor Current
This mode is typical in a synchronous buck converter
pulling energy from the output capacitors and delivering
the energy to the input capacitors (Boost Mode). In this
mode, the inductor current is negative (meaning
towards the MOSFETs) when the low-side MOSFET is
turned off (may be negative when the high-side
MOSFET turns on as well). This situation causes the
low-side MOSFET to hard switch while the high-side
MOSFET acts as a synchronous rectifier (temporarily
operated in synchronous Boost Mode).
During this mode, only the “weak” LDRV2 is used for
low-side MOSFET turn-on and turn-off. The intention is
to slow down the low-side MOSFET switching speed
when it is hard switching to reduce peak VDS stress.
Low-Side Driver
The low-side driver (LDRV) is designed to drive the
gate-source of a ground-referenced low RDS(ON),
N-channel MOSFET (Q2). The bias for LDRV is
internally connected between the PVCC and AGND.
When the driver is enabled, the driver output is 180° out
of phase with the PWM input. When the driver is
disabled (EN = 0 V), LDRV is held LOW.
Continuous Current Mode 2 (CCM2) Operation
A main feature of the low-side driver design in SPS
FMDF5820DC is the ability to control the part of the
low-side gate driver upon detection of negative
inductor current, called CCM2 operation. This is
accomplished by using the ZCD comparator signal.
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
Dead-Times in CCM1 / DCM / CCM2
The driver IC design ensures minimum MOSFET dead
times, while eliminating potential shoot-through (crossconduction) currents. To ensure optimal module
efficiency, body diode conduction times must be
reduced to the low nano-second range during CCM1
and DCM operation. CCM2 alters the gate drive
impedance while operating the power MOSFETs in a
different mode versus CCM1 / DCM. Altered dead-time
operation must be considered.
www.fairchildsemi.com
13
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
The primary reason for scaling back on the drive
strength is to limit the peak V DS stress when the lowside MOSFET hard-switches inductor current. This
peak V DS stress has been an issue with applications
with large amounts of load transient and fast and
wide output voltage regulation.
Power Sequence
High-Side MOSFET Off to Low-Side MOSFET On
Dead Time in CCM1 / DCM
To get very short dead time during high-side MOSFET
off to low-side MOSFET on transition, a fixed-dead-time
method is implemented in the SPS gate driver. The
fixed-dead-time circuitry monitors the internal HS signal
and adds a fixed delay long enough to gate on GL after
a desired tD_DEADOFF (~ 5 ns, tD_DEADOFF = tFD_OFF1),
regardless of SW node state.
Some situations where the ZCD# rising-edge signal
leads the PWM rising edge by tens of nanoseconds,
can cause GH and GL overlap. This event can occur
when the PWM controller sends PWM and ZCD#
signals that lead, lag, or are synchronized. To avoid this
phenomenon, a secondary fixed propagation delay
(tFD_ON1) is added to ensure there is always a minimum
delay between low-side MOSFET off to high-side
MOSFET on.
Exiting 3-State Condition
When exiting a valid 3-state condition, the gate driver of
the FDMF5820DC follows the PWM input command. If
the PWM input goes from 3-state to LOW, the low-side
MOSFET is turned on. If the PWM input goes from 3state to HIGH, the high-side MOSFET is turned on. This
is illustrated in Figure 29 below.
Low-Side MOSFET Off to High-Side MOSFET On
Dead Time in CCM2
As noted in the CCM2 Operation section, the low-side
driver strength is scale-able upon detection of CCM2.
CCM2 feature slows the charge and discharge of the
low-side MOSFET gate to minimize peak switching
voltage overshoots during low-side MOSFET hardVIH_PWM
VIH_PWM
PWM
VTRI_HI
VTRI_LO
VIL_PWM
VIH_PWM
VTRI_HI
VTRI_HI
VTRI_LO
3-State
Window
VIL_PWM
VIL_PWM
90%
GH to SW
90%
10%
10%
90%
90%
GL
10%
tPD_PHGLL
tD_DEADON
10%
10%
10%
tPD_PLGHL
tPD_THGHH
tPD_PHGLL
tD_DEADON2
tD_DEADOFF
10%
tD_HOLD-OFF
tPD_TLGLH
tD_HOLD-OFF
SW
Less than
tD_HOLD-OFF
Inductor
Current
Less than
tD_HOLD-OFF
3-State
GL / GH
tHOLD_OFF
off
Window
3-State
GL / GH
tHOLD_OFF
off
Window
NOTES:
tPD_XXX = propagation delay from external signal (PWM, ZCD#, etc.) to IC generated signal. Example : tPD_PHGLL – PWM going HIGH to low-side MOSFET VGS (GL) going LOW
tD_XXX = delay from IC generated signal to IC generated signal. Example : tD_DEADON – low-side MOSFET VGS LOW to high-side MOSFET VGS HIGH
PWM
tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS
tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS
tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (ZCD# held LOW)
Exiting 3-State
tPD_TSGHH = PWM 3-State to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS
tPD_TSGLH = PWM 3-State to LOW to LS VGS rise, VIL_PWM to 10% LS VGS
ZCD#
tPD_ZLGLL = ZCD# fall to LS VGS fall, VIL_ZCD# to 90% LS VGS
tPD_ZHGLH = ZCD# rise to LS VGS rise, VIH_ZCD# to 10% LS VGS
Dead Times
tD_DEADON = LS VGS fall to HS VGS rise, LS-Comp trip value to 10% HS VGS
tD_DEADOFF = SW fall to LS VGS rise, SW-Comp trip value to 10% LS VGS
Figure 29.
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
PWM HIGH / LOW / 3-State Timing Diagram
www.fairchildsemi.com
14
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
switching (negative inductor current). To avoid crossconduction, the slowing of the low-side gate also
requires an adjustment (increase) of the dead time
between low-side MOSFET off to high-side MOSFET
on. A fairly long fixed dead time (tFD_ON2) is
implemented to ensure there is no cross conduction
during this CCM2 operation.
Low-Side MOSFET Off to High-Side MOSFET On
Dead Time in CCM1 / DCM
To prevent overlap during the low-side MOSFET off to
high-side MOSFET on switching transition, adaptive
circuitry monitors the voltage at the GL pin. When the
PWM signal goes HIGH, GL goes LOW after a
propagation delay (tPD_PHGLL). Once the GL pin is
discharged below ~ 1 – 2 V, GH is pulled HIGH after an
adaptive delay, tD_DEADON.
VIH_PWM
The SPS module is used in multi-phase VR topologies
requiring the module to wait in 3-state condition for an
indefinite time. These long idle times can bleed the boot
capacitor down until eventual clamping occurs based
on PVCC and VOUT. Low BOOT-SW can cause
increased propagation delays in the level-shift circuit as
well as all HDRV floating circuitry, which is biased from
the BOOT-SW rail. Another issue with a depleted
BOOT-SW capacitor voltage is the voltage applied to
the HS MOSFET gate during turn-on. A low BOOT-SW
voltage results in a very weak HS gate drive, hence,
much larger HS RDS(ON) and increased risk for
unreliable operation since the HS MOSFET may not
turn-on if BOOT-SW falls too low.
PWM
GH to
PHASE
GL
GL / GH
off
LOW
BOOT-SW
detect
Low BOOT-SW voltage detected
Figure 30.

Low BOOT-SW Voltage Detected and
PWM from 3-State to HIGH
PWM LOW
> 100 ns
To address this issue, the SPS monitors for a low
BOOT-SW voltage when the module is in 3-state
condition. When the module exits 3-state condition with
a low BOOT-SW voltage, a 100 ns minimum GL on
time is output regardless of the PWM input. This
ensures the boot capacitor is adequately charged to a
safe operating level and has minimal impact on
transient response of the system. Scenarios of exiting
3-state condition are listed below.

100 ns
GL pulse
VIL_PWM
PWM
GH to
PHASE
GL
GL / GH
off
LOW
BOOT-SW
detect
If the part exits 3-state with a low BOOT-SW voltage
condition and the controller commands PWM=HIGH,
the SPS outputs a 100 ns GL pulse and follows the
PWM=HIGH command (see Figure 30).
> 100 ns
GL pulse
Low BOOT-SW voltage detected
Figure 31. Low BOOT-SW Voltage Detected and
PWM from 3-State to LOW for more than 100 ns
If the part exits 3-state with a low BOOT-SW
voltage condition and the controller commands
PWM=LOW for 100 ns or more, the SPS follows
the PWM input. If PWM=LOW for less than 100 ns,
GL remains on for 100 ns then follows the PWM
input (see Figure 31 and Figure 32).
PWM LOW
< 100 ns
VIL_PWM
PWM
GH to
PHASE

If no low BOOT-SW condition is detected, the SPS
follows the PWM command when exiting 3-state
(see Figure 33).
The SPS momentarily stays in an adaptive dead time
mode when exiting 3-state condition or at initial powerup. This adaptive dead time mode lasts for no more
than two (2) consecutive switching cycles, giving the
boot capacitor ample time to recharge to a safe level.
The module switches back to fixed dead time control for
maximum efficiency.
GL
GL / GH
off
LOW
BOOT-SW
detect
100 ns
GL pulse
Low BOOT-SW voltage detected
Figure 32. Low BOOT-SW voltage Detected and
PWM from 3-State to LOW for Less than 100 ns
VIH_PWM
VIL_PWM
PWM
GH to
PHASE
GL
GL / GH
off
GL / GH
off
LOW
BOOT-SW
detect
Low BOOT-SW voltage NOT detected
Figure 33. Low BOOT-SW Voltage NOT Detected
and PWM from 3-State to HIGH or LOW
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
www.fairchildsemi.com
15
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Exiting 3-State with Low BOOT-SW Voltage
The ZCD control block houses the circuitry that
determines when the inductor current reverses direction
and controls when to turn off the low-side MOSFET. A
low offset comparator monitors the SW-to-PGND
voltage of the low-side MOSFET during the LS
MOSFET on-time. When the sensed voltage switches
polarity from negative to positive, the comparator
changes state and reverse current has been detected.
This comparator offset must sense the negative VSW
The comparator is switched on after the rising edge of
the low-side gate drive and turned off by the signal at
the input to the low-side gate driver. In this way, the
zero-current comparator is connected with a breakbefore-make connection, allowing the comparator to be
designed with low-voltage transistors.
VIH_ZCD#
ZCD#
VIL_ZCD#
VIH_PWM
VIH_PWM
PWM
VIH_PWM
VIL_PWM
90%
GH to
SW
10%
10%
90%
GL
90%
10%
tPD_PHGLL
90%
90%
10%
10%
tPD_PLGHL
tD_DEADON
SW
10%
tPD_PHGLL
tPD_ZCD
tD_DEADON2
tD_DEADOFF
CCM
(Negative inductor current)
CCM
tPD_PHGHH
tPD_ZHGLH
Delay from PWM going
HIGH to HS VGS HIGH
(HS turn-on in DCM)
DCM
tPD_ZLGLL
Delay from ZCD# going Delay from ZCD# going
HIGH to LS VGS HIGH
LOW to LS VGS LOW
VIN
DCM
VOUT
Inductor
Current
(simplified
slopes)
SW
(zoom)
VZCD_OFF :
-0.5mV
CCM operation with
positive inductor current
DCM operation: Diode
Emulation using the GL (LS
MOSFET VGS) to eliminate
negative inductor current
CCM operation with
negative inductor current
Figure 34.
ZCD# used to
control negative
inductor current
(fault condition)
ZCD# & PWM Timing Diagram
driver temperature versus TMON pin voltage with 25 kΩ
RTMON and 0.1 µF CTMON.
Temperature Monitor (TMON)
The FDMF5820DC provides a temperature monitor
(TMON) to warn of over-temperature conditions. The
gate driver uses the TMON pin to source an analog
current proportional to absolute temperature (PTAT). It is
expected that the analog current will be used with a
properly chosen external resistor to AGND to develop a
voltage across TMON (VTMON) proportional to the
temperature. A filter capacitance may be needed to
minimize noise spikes in the analog current, ITMON. Noise
spikes are generated from power MOSFET switching
dv / dt and di / dt coupling back into the driver VCC pin.
VTMON
[V]
1.45
1.0
25
150
TJ [°C]
* RTMON = 25 kW, CTMON = 0.1 µF
The TMON pin needs a pull-down resistor (RTMON) and
filter capacitor (CTMON) to AGND. With 25 kΩ RTMON and
0.1 µF CTMON, the TMON voltage is around 1 V at 25°C
of gate driver TJ, and 1.5 V when the driver temperature
reaches 150°C. The VTMON signal can be connected to
PWM controller or MCU in system to indicate the
thermal status of the gate driver. Figure 35 shows gate
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
DCM operation: Diode
Emulation using the GL (LS
MOSFET VGS) to eliminate
negative inductor current
Figure 35.
Gate Driver TJ vs. VTMON
The TMON voltage is defined by following equation:
(1)
www.fairchildsemi.com
16
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
within a 0.5 mV worst-case range. The negative offset
is to ensure the inductor current never reverses; some
small body-diode conduction is preferable to having
negative current.
Zero Cross Detect (ZCD) Operation
When the TMON pin voltage exceeds 1.5 V, the internal
comparator shuts down the driver (EN pin goes LOW).
The programmable thermal shutdown temperature
range can be adjusted by RTMON so that the shutdown
temperature can be customized. The equation below
shows the relationship between RTMON value in design
and desirable thermal shutdown temperature.
200
150
100
23
(2)
25.9
29.5 RTMON [kW]
* VTMON = 1.5 V, CTMON = 0.1 µF
Figure 36.
Figure 36 shows the relationship between RTMON and PTHDN temperature. Increasing the RTMON value results
in a lower P-THDN temperature. The system designer
can define the shutdown temperature of FDMF5820DC
based on the system thermal design.
RTMON vs. P-THDN Temperature
Catastrophic Fault
SPS FDMF5820DC includes a catastrophic fault
feature. If a HS MOSFET short is detected, the driver
internally pulls the EN / FAULT# pin LOW and shuts
down the SPS driver. The intention is to implement a
basic circuit to test the HS MOSFET short by monitoring
LDRV and the state of SW node.
The P-THDN is a latch-off shutdown, so the (POR) on
VCC is needs to re-enable the gate driver. If not using
TMON / P-THDN features, tie the TMON pin to AGND.
If a HS short fault is detected, the SPS module clocks
the fault latch shutting down the module. The module
requires a VCC POR event to restart.
PWM
LDRV
(internal)
HS FET short during
LS FET turning on
SW
Potential noise from
adjacent phases switching
SW-Fault
(internal)
false trigger
FAULT
(internal)
EN/FAULT#
Normal switching operation
Figure 37.
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
EN/FAULT#
pulled LOW and
driver IC disabled
Catastrophic Fault Waveform
www.fairchildsemi.com
17
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
P-THDN
Temp. [°C]
Programmable Thermal Shutdown (P-THDN)
PWM (Input)
Decoupling Capacitor for PVCC & VCC
The PWM pin recognizes three different logic levels
from PWM controller: HIGH, LOW, and 3-state. When
the PWM pin receives a HIGH command, the gate
driver turns on the high-side MOSFET. When the PWM
pin receives a LOW command, the gate driver turns on
the low-side MOSFET. When the PWM pin receives a
voltage signal inside of the 3-state window (VTRI_Window)
and exceeds the 3-state hold-off time, the gate driver
turns off both high-side and low-side MOSFETs. To
recognize the high-impedance 3-state signal from the
controller, the PWM pin has an internal resistor divider
from VCC to PWM to AGND. The resistor divider sets
a voltage level on the PWM pin inside the 3-state
window when the PWM signal from the controller is
high-impedance.
For the supply inputs (PVCC and VCC pins), local
decoupling capacitors are required to supply the peak
driving current and to reduce noise during switching
operation. Use at least 0.68 ~ 1 µF / 0402 ~ 0603 / X5R
~ X7R multi-layer ceramic capacitors for both power
rails. Keep these capacitors close to the PVCC and
VCC pins and PGND and AGND copper planes. If they
need to be located on the bottom side of board, put
through-hole vias on each pads of the decoupling
capacitors to connect the capacitor pads on bottom with
PVCC and VCC pins on top.
The supply voltage range on PVCC and VCC is 4.5 V ~
5.5 V, typically 5 V for normal applications.
R-C Filter on VCC
ZCD# (Input)
The PVCC pin provides power to the gate drive of the
high-side and low-side power MOSFETs. In most cases,
PVCC can be connected directly to VCC, which is the
pin that provides power to the analog and logic blocks of
the driver. To avoid switching noise injection from PVCC
into VCC, a filter resistor can be inserted between
PVCC and VCC decoupling capacitors.
When the ZCD# pin sets HIGH, the ZCD function is
disabled and high-side and low-side MOSFETs switch in
CCM (or FCCM, Forced CCM) by PWM signal. When
the ZCD# pin is LOW, the low-side MOSFET turns off
when the SPS driver detects negative inductor current
during the low-side MOSFET turn-on period. This ZCD
feature allows higher converter efficiency under lightload condition and PFM / DCM operation.
Recommended filter resistor value range is 0 ~ 10 Ω,
typically 0 Ω for most applications.
The ZCD# pin has an internal current source from VCC,
so it may not need an external pull-up resistor. Once
VCC is supplied and the driver is enabled, the ZCD# pin
holds logic HIGH without external components and the
driver operates switching in CCM or FCCM. The ZCD#
pin can be grounded for automatic diode emulation in
DCM by the SPS itself, or it can be connected to the
controller or system to follow the command from them.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBOOT). A bootstrap capacitor of 0.1 ~ 0.22 µF / 0402 ~
0603 / X5R ~ X7R is usually appropriate for most
switching applications. A series bootstrap resistor may
be needed for specific applications to lower high-side
MOSFET switching speed. The boot resistor is required
when the SPS is switching above 15 V VIN; when it is
effective at controlling VSW overshoot. RBOOT value from
zero to 6 Ω is typically recommended to reduce
excessive voltage spike and ringing on the SW node. A
higher RBOOT value can cause lower efficiency due to
high switching loss of high-side MOSFET.
The typical pull-up resistor value on ZCD# ~ VCC is
10 kΩ for stable ZCD# HIGH level. If not using the ZCD
feature, tie the ZCD# pin to VCC with a pull-up resistor.
Do not add any noise filter capacitor on the ZCD# pin.
TMON (Output) / P-THDN
During normal operation (no fault detected), the TMON
pin sources an analog current proportional to the
absolute temperature of the gate driver. With 25 kΩ
RTMON and 0.1 µF CTMON on TMON pin to AGND, it
outputs 1 V at 25°C driver TJ and 1.5 V at 150°C driver
TJ. The CTMON is a filter capacitor to minimize switching
noise injection onto the TMON pin. The TMON pin can
be connected to a PWM controller or system controller
and used to monitor the SPS module temperature.
Do not add a capacitor or resistor between the BOOT
pin and GND.
EN / FAULT# (Input / Output)
The driver in SPS is enabled by pulling the EN pin
HIGH. The EN pin has internal 250 kΩ pull-down
resistor, so it needs to be pulled-up to VCC with an
external resistor or connected to the controller or system
to follow up the command from them. If the EN pin is
floated, it cannot turn on the driver.
If the TMON pin voltage exceeds 1.5 V with 25 kΩ
RTMON, the driver temperature is over 150°C and the
driver is shut down by the P-THDN feature. The 150°C
thermal shutdown temperature can be adjusted by the
RTMON value to define the THDN temperature for the
application. Refer to the P-THDN section to define
thermal shutdown temperature and RTMON value.
The fault flag LOW signal is asserted on the EN /
FAULT# pin when the driver temperature reaches PTHDN temperature or a high-side MOSFET fault occurs.
Then the driver shuts down.
The typical pull-up resistor value on EN ~ VCC is 10 kΩ.
Do not add a noise filter capacitor on the EN pin.
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
If not using the TMON / P-THDN features, tie the TMON
pin to GND.
www.fairchildsemi.com
18
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Application Information
Figure 38 shows an example diagram for power loss
and efficiency measurement.
Power loss calculation and equation examples:
PIN = (VIN  IIN) + (VCC  ICC)
PSW = VSW  IOUT
POUT = VOUT  IOUT
PLOSS_MODULE = PIN – PSW
PLOSS_TOTAL = PIN – POUT
EFFIMODULE = (PSW / PIN)  100
EFFITOTAL = (POUT / PIN)  100
[W]
[W]
[W]
[W]
[W]
[%]
[%]
Pulse
Generator
PWM
Power
Supply 1
Power
Supply 2
VIN / IIN
VIN
HS
VCC / ICC
GD
PVCC
LS
VCC
Figure 38.
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
Electronic
Load
VOUT
VSW / IOUT
VOUT / IOUT
Fairchild SPS
Evaluation Board
Power Loss and Efficiency Measurement Diagram
www.fairchildsemi.com
19
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Power Loss and Efficiency
Figure 39 through Figure 42 provide examples of singlephase and multi-phase layouts for the FDMF5820DC
and critical components. All of the high-current paths;
such as VIN, SW, VOUT, and GND coppers; should be
short and wide for low parasitic inductance and
resistance. This helps achieve a more stable and evenly
distributed current flow, along with enhanced heat
radiation and system performance.
A boot resistor may be required when the SPS is
operating above 15 V VIN and it is effective to control the
high-side MOSFET turn-on slew rate and SW voltage
overshoot. RBOOT can improve noise operating margin in
synchronous buck designs that may have noise issues
due to ground bounce or high positive and negative VSW
ringing. Inserting a boot resistance lowers the SPS
module efficiency. Efficiency versus switching noise
must be considered. RBOOT values from 0.5 W to 6.0 W
are typically effective in reducing VSW overshoot.
Input ceramic bypass capacitors must be close to the
VIN and PGND pins. This reduces the high-current
power loop inductance and the input current ripple
induced by the power MOSFET switching operation.
The VIN and PGND pins handle large current transients
with frequency components greater than 100 MHz. If
possible, these pins should be connected directly to the
VIN and board GND planes. The use of thermal relief
traces in series with these pins is not recommended
since this adds extra parasitic inductance to the power
path. This added inductance in series with either the
VIN or PGND pin degrades system noise immunity by
increasing positive and negative VSW ringing.
The SW copper trace serves two purposes. In addition
to being the high-frequency current path from the SPS
package to the output inductor, it serves as a heat sink
for the low-side MOSFET. The trace should be short
and wide enough to present a low-impedance path for
the high-frequency, high-current flow between the SPS
and the inductor. The short and wide trace minimizes
electrical losses and SPS temperature rise. The SW
node is a high-voltage and high-frequency switching
node with high noise potential. Care should be taken to
minimize coupling to adjacent traces. Since this copper
trace acts as a heat sink for the low-side MOSFET,
balance using the largest area possible to improve SPS
cooling while maintaining acceptable noise emission.
PGND pad and pins should be connected to the GND
copper plane with multiple vias for stable grounding.
Poor grounding can create a noisy and transient offset
voltage level between PGND and AGND. This could
lead to faulty operation of gate driver and MOSFETs.
Ringing at the BOOT pin is most effectively controlled
by close placement of the boot capacitor. Do not add
any additional capacitors between BOOT to PGND. This
may lead to excess current flow through the BOOT
diode, causing high power dissipation.
An output inductor should be located close to the
FDMF5820DC to minimize the power loss due to the
SW copper trace. Care should also be taken so the
inductor dissipation does not heat the SPS.
The ZCD# and EN pins have weak internal pull-up and
pull-down current sources, respectively. These pins
should not have any noise filter capacitors. Do not float
these pins unless absolutely necessary.
®
PowerTrench MOSFETs are used in the output stage
and are effective at minimizing ringing due to fast
switching. In most cases, no RC snubber on SW node is
required. If a snubber is used, it should be placed close
to the SW and PGND pins. The resistor and capacitor of
the snubber must be sized properly to not generate
excessive heating due to high power dissipation.
Put multiple vias on the VIN and VOUT copper areas to
interconnect top, inner, and bottom layers to evenly
distribute current flow and heat conduction. Do not put
too many vias on the SW copper to avoid extra parasitic
inductance and noise on the switching waveform. As
long as efficiency and thermal performance are
acceptable, place only one SW node copper on the top
layer and put no vias on the SW copper to minimize
switch node parasitic noise. Vias should be relatively
large and of reasonably low inductance. Critical highfrequency components; such as RBOOT, CBOOT, RC
snubber, and bypass capacitors; should be located as
close to the respective SPS module pins as possible on
the top layer of the PCB. If this is not feasible, they can
be placed on the board bottom side and their pins
connected from bottom to top through a network of lowinductance vias.
Decoupling capacitors on PVCC, VCC, and BOOT
capacitors should be placed as close as possible to the
PVCC ~ PGND, VCC ~ AGND, and BOOT ~ PHASE pin
pairs to ensure clean and stable power supply. Their
routing traces should be wide and short to minimize
parasitic PCB resistance and inductance.
The board layout should include a placeholder for smallvalue series boot resistor on BOOT ~ PHASE. The bootloop size, including series RBOOT and CBOOT, should be
as small as possible.
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
www.fairchildsemi.com
20
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
PCB Layout Guideline
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
PCB Layout Guideline (Continued)
Figure 39.
Figure 40.
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
Single-Phase Board Layout Example – Top View
Single-Phase Board Layout Example – Bottom View (Mirrored)
www.fairchildsemi.com
21
FDMF5820DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
PCB Layout Guideline (Continued)
Figure 41.
Figure 42.
6-Phase Board Layout Example with 6 mm x 6 mm Inductor – Top View
6-Phase Board Layout Example with 6 mm x 6 mm Inductor – Bottom View (Mirrored)
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.7
www.fairchildsemi.com
22
3.80±0.10
(0.85)
C.L.
0.50 (2X)
0.30
16
0.40
1.03
1.92±0.10
17 18 19
20
15
24
14
25
13
26
12
33
0.45
11
0.55
0.30
27
0.30
28
0.55 (0.22)
29
32
10
30 1.03±0.10
9
0.40
C A B
C
0.35
0.15
0.85
21 22 23
C.L.
1.03±0.10
0.10
0.05
0.40
31
7
8
6
5
4
3
2
1
0.50
0.30
PIN #1 INDICATOR
0.30
0.20 (31X)
0.50
(0.38)
1.98±0.10
1.32±0.10
0.50
B
0.10 C
5.00±0.10
2X
SEE
DETAIL 'A'
A
C.L.
8
PIN#1
INDICATOR
1
31
9
NOTES: UNLESS OTHERWISE SPECIFIED
C.L.
5.00±0.10
1.63
(0.82) 15
24
16
(0.68)
0.10 C
23
2X
3.53
0.10 C
0.80
0.70
0.08 C
0.05 MAX
0.30
0.20
SCALE: 2:1
0.05
0.00
C
SEATING
PLANE
A) DOES NOT FULLY CONFORM TO JEDEC
REGISTRATION MO-220, DATED
MAY/2005.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) DRAWING FILE NAME: MKT-PQFN31AREV4
F) FAIRCHILDSEMICONDUCTOR
1.90
2.10
2.15
2.70
0.00
0.90
1.37
2.70
2.10
1.95
1.90
1.75
C.L.
23
16
2.70
0.60
26
0.40
27
0.05
0.00
C.L.
28
29
0.50 TYP
30
1.90
12
33
11
2.10
1.90
1.75
0.10
0.27
0.62
32
31
9
0.60(13X)
1
2
3
4
5
6
7
8
0.20
0.30 (13X)
LAND PATTERN
RECOMMENDATION
2.10
0.07
0.34
0.50 TYP
1.76
5.40
15
24
1.90
1.75
1.90
2.10
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