MB95F613H/F613K/F614H
MB95F614K/F616H/F616K
PRELIMINARY
New 8FX MB95610H Series
8-bit Microcontrollers
The MB95610H Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the
microcontrollers of these series contain a variety of peripheral resources.
Features
F2MC-8FX CPU core
■
Instruction set optimized for controllers
■
Multiplication and division instructions
■
16-bit arithmetic operations
■
Bit test branch instructions
■
Bit manipulation instructions, etc.
I2C bus interface 1 channel
Built-in wake-up function
External interrupt 8 channels
Clock
■
■
Capable of clock asynchronous (UART) serial data transfer and
clock synchronous (SIO) serial data transfer
Selectable main clock source
❐ Main oscillation clock (up to 16.25 MHz, maximum machine
clock frequency: 8.125 MHz)
❐ External clock (up to 32.5 MHz, maximum machine clock
frequency: 16.25 MHz)
❐ Main CR clock (4 MHz 2%)
❐ Main PLL clock / Main CR PLL clock (Main oscillation clock
= 4 MHz, Main CR clock = 4 MHz)
• Both main oscillation clock and main CR clock can be multiplied by a PLL multiplication rate.
• The frequency of the main PLL clock / main CR PLL clock
becomes 8 MHz when the PLL multiplication rate is 2.
• he frequency of the main PLL clock / main CR PLL clock
becomes 10 MHz when the PLL multiplication rate is 2.5.
• he frequency of the main PLL clock / main CR PLL clock
becomes 12 MHz when the PLL multiplication rate is 3.
• he frequency of the main PLL clock / main CR PLL clock
becomes 16 MHz when the PLL multiplication rate is 4.
Selectable subclock source
❐ Suboscillation clock (32.768 kHz)
❐ External clock (32.768 kHz)
❐ Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz)
■
Interrupt by edge detection (rising edge, falling edge, and both
edges can be selected)
■
Can be used to wake up the device from different low power
consumption (standby) modes
8/10-bit A/D converter 4 channels
8-bit or 10-bit resolution can be selected.
LCD controller (LCDC)
■
LCD output can be selected from 52 SEG 4 COM or 48 SEG
8 COM.
■
Internal divider resistor whose resistance value can be selected
from 10 k or 100 k through software
■
Interrupt in sync with the LCD module frame frequency
■
Blinking function
■
Inverted display function
Low power consumption (standby) modes
There are four standby modes as follows:
■
Stop mode
■
Sleep mode
■
Watch mode
■
Time-base timer mode
In standby mode, two further options can be selected: normal
standby mode and deep standby mode.
Timer
■
8/16-bit composite timer 2 channels
I/O port
■
8/16-bit PPG 2 channels
■
■
16-bit reload timer 1 channel
■
Event counter 1 channel
MB95F613H/F614H/F616H (no. of I/O ports: 40)
❐ General-purpose I/O ports (CMOS I/O): 39
❐ General-purpose I/O ports (N-ch open drain): 1
Time-base timer 1 channel
■
■
■
Watch counter 1 channel
MB95F613K/F614K/F616K (no. of I/O ports: 41)
❐ General-purpose I/O ports (CMOS I/O): 39
❐ General-purpose I/O ports (N-ch open drain): 2
■
Watch prescaler 1 channel
On-chip debug
UART/SIO 2 channels
■
Full duplex double buffer
Cypress Semiconductor Corporation
Document Number: 002-04698 Rev. *A
•
■
1-wire serial control
■
Serial writing supported (asynchronous mode)
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 8, 2016
PRELIMINARY
Hardware/software watchdog timer
MB95610H Series
Clock supervisor counter
■
Built-in hardware watchdog timer
Built-in clock supervisor counter
■
Built-in software watchdog timer
Dual operation Flash memory
Power-on reset
A power-on reset is generated when the power is switched on.
Low-voltage detection (LVD) reset circuit (only
available on MB95F613K/F614K/F616K)
Built-in low-voltage detection function (The combination of
detection voltage and release voltage can be selected from four
options.)
Document Number: 002-04698 Rev. *A
The program/erase operation and the read operation can be
executed in different banks (upper bank/lower bank) simultaneously.
Flash memory security function
Protects the content of the Flash memory.
Page 2 of 110
PRELIMINARY
MB95610H Series
Contents
Product Line-up ................................................................ 5
Packages and Corresponding Products ........................ 8
Differences Among Products and Notes
On Product Selection ....................................................... 8
Pin Assignment ................................................................ 9
Pin Functions .................................................................. 10
I/O Circuit Type ............................................................... 14
Handling Precautions ..................................................... 18
Precautions for Product Design ................................. 18
Precautions for Package Mounting ........................... 19
Precautions for Use Environment .............................. 21
Notes on Device Handling ......................................... 22
Pin Connection .......................................................... 22
Block Diagram ........................................................... 24
CPU Core .................................................................. 25
Memory Space .......................................................... 26
Areas for Specific Applications .................................. 28
I/O Map ...................................................................... 29
I/O Ports .................................................................... 34
Port 0 ......................................................................... 34
Port 0 configuration ................................................... 34
Block diagrams of port 0 ............................................ 35
Port 0 registers .......................................................... 38
Port 0 operations ....................................................... 38
Port 1 ......................................................................... 40
Port 1 configuration ................................................... 40
Block diagrams of port 1 ............................................ 40
Port 1 registers .......................................................... 44
Port 1 operations ....................................................... 45
Port 2 ......................................................................... 46
Port 2 configuration ................................................... 46
Block diagrams of port 2 ............................................ 46
Port 2 registers .......................................................... 49
Port 2 operations ....................................................... 50
Port 3 ......................................................................... 51
Port 3 configuration ................................................... 51
Block diagrams of port 3 ............................................ 51
Port 3 registers .......................................................... 54
Port 3 operations ....................................................... 54
Port 5 ......................................................................... 57
Port 5 configuration ................................................... 57
Block diagrams of port 5 ............................................ 57
Document Number: 002-04698 Rev. *A
Port 5 registers .......................................................... 59
Port 5 operations ....................................................... 59
Port 9 ......................................................................... 61
Port 9 configuration ................................................... 61
Block diagrams of port 9 ............................................ 61
Port 9 registers .......................................................... 62
Port 9 operations ....................................................... 63
Port F ......................................................................... 64
Port F configuration ................................................... 64
Block diagrams of port F ........................................... 64
Port F registers .......................................................... 66
Port F operations ....................................................... 67
Port G ........................................................................ 68
Port G configuration .................................................. 68
Block diagram of port G ............................................. 68
Port G registers ......................................................... 69
Port G operations ...................................................... 69
Interrupt Source Table ................................................... 70
Pin States in Each Mode ................................................ 71
Electrical Characteristics ............................................... 76
Absolute Maximum Ratings ....................................... 76
Recommended Operating Conditions ....................... 78
DC Characteristics .................................................... 79
AC Characteristics ..................................................... 83
Clock Timing .............................................................. 83
Source Clock/Machine Clock .................................... 89
External Reset ........................................................... 91
Power-on Reset ......................................................... 92
Peripheral Input Timing ............................................. 92
Low-voltage Detection ............................................... 93
I2C Bus Interface Timing ........................................... 95
UART/SIO, Serial I/O Timing ..................................... 99
A/D Converter .......................................................... 101
A/D Converter Electrical Characteristics ................. 101
Notes on Using A/D Converter ................................ 102
Definitions of A/D Converter Terms ......................... 104
Flash Memory Program/Erase Characteristics ........ 106
MASK Options .............................................................. 107
Ordering Information .................................................... 108
Package Dimension ...................................................... 109
Major Changes ...............................................................110
Page 3 of 110
PRELIMINARY
MB95610H Series
1. Product Line-up
Part number
MB95F613H
MB95F614H
MB95F616H
MB95F613K
MB95F614K
MB95F616K
12 Kbyte
20 Kbyte
36 Kbyte
512 bytes
1024 bytes
1024 bytes
Parameter
Type
Flash memory product
Clock
It supervises the main clock oscillation and the subclock oscillation.
supervisor counter
Flash memory
capacity
12 Kbyte
20 Kbyte
36 Kbyte
RAM capacity
512 bytes
1024 bytes
1024 bytes
Power-on reset
Yes
Low-voltage
detection reset
No
Reset input
Yes
With dedicated reset input
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Interrupt processing time
Selected through software
CPU functions
•
•
•
•
•
•
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8 and 16 bits
: 61.5 ns (machine clock frequency = 16.25 MHz)
: 0.6 µs (machine clock frequency = 16.25 MHz)
General-purpose
I/O
• I/O port
• CMOS I/O
• N-ch open drain
Time-base timer
Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)
: 40
: 39
: 1
• I/O port
• CMOS I/O
• N-ch open drain
: 41
: 39
: 2
• Reset generation cycle
Hardware/
Main oscillation clock at 10 MHz: 105 ms (Min)
software watchdog
• The sub-CR clock can be used as the source clock of the software watchdog timer.
timer
Wild register
It can be used to replace 3 bytes of data.
8/10-bit
A/D converter
4 channels
8-bit or 10-bit resolution can be selected.
2 channels
8/16-bit
composite timer
•
•
•
•
The timer can be configured as an “8-bit timer × 2 channels” or a “16-bit timer × 1 channel”.
It has the following functions: interval timer function, PWC function, PWM function and input capture function.
Count clock: it can be selected from internal clocks (seven types) and external clocks.
It can output square wave.
8 channels
External interrupt
On-chip debug
• Interrupt by edge detection (The rising edge, falling edge, and both edges can be selected.)
• It can be used to wake up the device from different standby modes.
• 1-wire serial control
• It supports serial writing (asynchronous mode).
(Continued)
Document Number: 002-04698 Rev. *A
Page 4 of 110
PRELIMINARY
MB95610H Series
Part number
MB95F613H
MB95F614H
MB95F616H
MB95F613K
MB95F614K
MB95F616K
Parameter
2 channels
UART/SIO
• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate generator and an error
detection function.
• It uses the NRZ type transfer format.
• LSB-first data transfer and MSB-first data transfer are available to use.
• Both clock asynchronous (UART) serial data transfer and clock synchronous (SIO) serial data transfer are enabled.
1 channel
I2C bus
interface
• Master/slave transmission and receiving
• It has the following functions: bus error function, arbitration function, transmission direction detection function,
wake-up function, and functions of generating and detecting repeated START conditions.
2 channels
8/16-bit PPG
• Each channel can be used as an “8-bit timer 2 channels” or a “16-bit timer 1 channel”.
• The counter operating clock can be selected from eight clock sources.
1 channel
16-bit reload timer
Event counter
LCDC controller
(LCDC)
•
•
•
•
Two clock modes and two counter operating modes are available to use.
It can output square wave.
Count clock: it can be selected from internal clocks (seven types) and external clocks.
Two counter operating modes: reload mode and one-shot mode
By configuring the 16-bit reload timer and 8/16-bit composite timer ch. 1, the event count function can be
implemented. When the event counter function is used, the 16-bit reload timer and 8/16-bit composite timer ch. 1
become unavailable.
• COM output: 4 or 8 (max) (selectable)
• SEG output: 48 or 52 (max) (selectable)
- If the number of COM outputs is 4, the maximum number of SEG outputs is 52, and the maximum number of
pixels that can be displayed 208 (4 52).
- If the number of COM outputs is 8, the maximum number of SEG outputs is 48, and the maximum number of
pixels that can be displayed 384 (8 48).
•
•
•
•
•
•
Duty LCD mode
LCD standby mode
Blinking function
Internal divider resistor whose resistance value can be selected from 10 k or 100 k through software
Interrupt in sync with the LCD module frame frequency
Inverted display function
Watch counter
• Count clock: four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s)
• The counter value can be selected from 0 to 63. (The watch counter can count for one minute when the clock
source is one second and the counter value is set to 60.)
Watch prescaler
Eight different time intervals can be selected.
(Continued)
Document Number: 002-04698 Rev. *A
Page 5 of 110
PRELIMINARY
MB95610H Series
(Continued)
Part number
MB95F613H
MB95F614H
MB95F616H
MB95F613K
MB95F614K
MB95F616K
Parameter
Flash memory
• It supports automatic programming (Embedded Algorithm), and program/erase/erase-suspend/erase-resume
commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
• Flash security feature for protecting the content of the Flash memory
Number of program/erase cycles
Data retention time
Standby mode
1000
10000
100000
20 years
10 years
5 years
There are four standby modes as follows:
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
In standby mode, two further options can be selected: normal standby mode and deep standby mode.
Package
Document Number: 002-04698 Rev. *A
FPT-80P-M37
Page 6 of 110
PRELIMINARY
MB95610H Series
2. Packages and Corresponding Products
Part number
MB95F613H
MB95F614H
MB95F616H
MB95F613K
MB95F614K
MB95F616K
Package
FPT-80P-M37
: Available
3. Differences Among Products and Notes On Product Selection
■
Current consumption
When using the on-chip debug function, take account of the current consumption of Flash program/erase.
For details of current consumption, see “Electrical Characteristics”.
■
Package
For details of information on each package, see “Packages and Corresponding Products” and “Package Dimension”.
■
Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of operating voltage, see “Electrical Characteristics”.
■
On-chip debug function
The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool. For details of the connection
method, refer to “CHAPTER 25 EXAMPLE OF SERIAL PROGRAMMING CONNECTION” in “New 8FX MB95610H Series Hardware
Manual”.
Document Number: 002-04698 Rev. *A
Page 7 of 110
PRELIMINARY
MB95610H Series
P04/SEG32
P05/SEG33/ADTG
P06/SEG34/PPG10
P07/SEG35/PPG11
P30/SEG36/INT04
P31/SEG37/INT05
P32/SEG38/INT06
P33/SEG39/INT07
P34/SEG40/TO11
P35/SEG41/TO10
P36/SEG42/EC1
P37/SEG43/TO0
P20/SEG44/TI0
P21/SEG45/UO1
P22/SEG46/UCK1
P23/SEG47/UI1
P24/SEG48/PPG00
P25/SEG49/PPG01
P26/SEG50/SCL
P27/SEG51/SDA
4. Pin Assignment
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P12/DBG
1
60
SEG31
P13/UO0
2
59
SEG30
P14/UCK0
3
58
SEG29
P15/UI0
4
57
SEG28
P52/TO00
5
56
SEG27
P51/EC0
6
55
SEG26
P50/TO01
7
54
SEG25
PF2/RST
8
53
SEG24
P94/V0
9
52
SEG23
P93/V1
10
51
SEG22
P92/V2
11
50
SEG21
(TOP VIEW)
LQFP80
FPT-80P-M37
P91/V3
12
49
SEG20
P90/V4
13
48
SEG19
VCC
14
47
SEG18
PG1/X0A
15
46
SEG17
PG2/X1A
16
45
SEG16
C
17
44
SEG15
PF0/X0
18
43
SEG14
PF1/X1
19
42
SEG13
VSS
20
41
SEG12
Document Number: 002-04698 Rev. *A
SEG11
SEG10
SEG09
SEG08
SEG07
SEG06
SEG05
SEG04
COM7/SEG03
COM6/SEG02
COM5/SEG01
COM4/SEG00
COM3
COM2
COM1
COM0
P03/INT03/AN03
P02/INT02/AN02
P01/INT01/AN01
P00/INT00/AN00
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Page 8 of 110
PRELIMINARY
MB95610H Series
5. Pin Functions
Pin no. Pin name I/O circuit type*1
1
2
3
4
5
6
7
P12
DBG
P13
UO0
P14
UCK0
P15
UI0
P52
TO00
P51
EC0
P50
TO01
A
B
B
B
B
B
B
PF2
8
9
10
11
12
13
14
15
16
17
18
19
20
RST
P94
V0
P93
V1
P92
V2
P91
V3
P90
V4
VCC
PG1
X0A
PG2
X1A
C
PF0
X0
PF1
X1
VSS
Function
General-purpose I/O port
DBG input pin
General-purpose I/O port
UART/SIO ch. 0 data output pin
General-purpose I/O port
UART/SIO ch. 0 clock I/O pin
General-purpose I/O port
UART/SIO ch. 0 data input pin
General-purpose I/O port
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
8/16-bit composite timer ch. 0 clock input pin
General-purpose I/O port
8/16-bit composite timer ch. 0 output pin
I/O type
Input
Output OD*2 PU*3
Hysteresis
CMOS
—
Hysteresis
CMOS
—
Hysteresis
CMOS
—
Hysteresis
CMOS
—
Hysteresis
CMOS
—
Hysteresis
CMOS
—
Hysteresis
CMOS
—
Hysteresis
CMOS
—
Hysteresis
CMOS
—
—
Hysteresis
CMOS
—
—
Hysteresis
CMOS
—
—
Hysteresis
CMOS
—
—
Hysteresis
CMOS
—
—
—
—
—
—
Hysteresis
CMOS
—
Hysteresis
CMOS
—
—
—
—
—
Hysteresis
CMOS
—
—
Hysteresis
CMOS
—
—
—
—
—
—
General-purpose I/O port
C
D
D
D
D
D
—
E
E
—
F
F
—
Reset pin
Dedicated reset pin on MB95F613H/F614H/F616H
General-purpose I/O port
LCD drive power supply pin
General-purpose I/O port
LCD drive power supply pin
General-purpose I/O port
LCD drive power supply pin
General-purpose I/O port
LCD drive power supply pin
General-purpose I/O port
LCD drive power supply pin
Power supply pin
General-purpose I/O port
Subclock input oscillation pin (32 kHz)
General-purpose I/O port
Subclock I/O oscillation pin (32 kHz)
Decoupling capacitor connection pin
General-purpose I/O port
Main clock input oscillation pin
General-purpose I/O port
Main clock I/O oscillation pin
Power supply pin (GND)
(Continued)
Document Number: 002-04698 Rev. *A
Page 9 of 110
PRELIMINARY
Pin no. Pin name I/O circuit type*1
P00
21
INT00
G
CMOS
—
—
External interrupt input pin
Hysteresis/
analog
CMOS
—
—
External interrupt input pin
Hysteresis/
analog
CMOS
—
—
Hysteresis/
analog
CMOS
—
—
8/10-bit A/D converter analog input pin
P03
INT03
Hysteresis/
analog
General-purpose I/O port
G
AN02
24
External interrupt input pin
8/10-bit A/D converter analog input pin
P02
INT02
Output OD*2 PU*3
General-purpose I/O port
AN01
23
Input
8/10-bit A/D converter analog input pin
P01
INT01
I/O type
General-purpose I/O port
G
AN00
22
Function
MB95610H Series
General-purpose I/O port
G
AN03
External interrupt input pin
8/10-bit A/D converter analog input pin
25
COM0
H
LCDC COM0 output pin
Hysteresis
LCD
—
—
26
COM1
H
LCDC COM1 output pin
Hysteresis
LCD
—
—
27
COM2
H
LCDC COM2 output pin
Hysteresis
LCD
—
—
28
COM3
H
LCDC COM3 output pin
Hysteresis
LCD
—
—
Hysteresis
LCD
—
—
Hysteresis
LCD
—
—
Hysteresis
LCD
—
—
Hysteresis
LCD
—
—
29
30
31
32
COM4
SEG00
COM5
SEG01
COM6
SEG02
COM7
SEG03
H
H
H
H
LCDC COM4 output pin
LCDC SEG00 output pin
LCDC COM5 output pin
LCDC SEG01 output pin
LCDC COM6 output pin
LCDC SEG02 output pin
LCDC COM7 output pin
LCDC SEG03 output pin
33
SEG04
H
LCDC SEG04 output pin
Hysteresis
LCD
—
—
34
SEG05
H
LCDC SEG05 output pin
Hysteresis
LCD
—
—
35
SEG06
H
LCDC SEG06 output pin
Hysteresis
LCD
—
—
36
SEG07
H
LCDC SEG07 output pin
Hysteresis
LCD
—
—
37
SEG08
H
LCDC SEG08 output pin
Hysteresis
LCD
—
—
38
SEG09
H
LCDC SEG09 output pin
Hysteresis
LCD
—
—
39
SEG10
H
LCDC SEG10 output pin
Hysteresis
LCD
—
—
40
SEG11
H
LCDC SEG11 output pin
Hysteresis
LCD
—
—
41
SEG12
H
LCDC SEG12 output pin
Hysteresis
LCD
—
—
42
SEG13
H
LCDC SEG13 output pin
Hysteresis
LCD
—
—
43
SEG14
H
LCDC SEG14 output pin
Hysteresis
LCD
—
—
44
SEG15
H
LCDC SEG15 output pin
Hysteresis
LCD
—
—
45
SEG16
H
LCDC SEG16 output pin
Hysteresis
LCD
—
—
46
SEG17
H
LCDC SEG17 output pin
Hysteresis
LCD
—
—
47
SEG18
H
LCDC SEG18 output pin
Hysteresis
LCD
—
—
48
SEG19
H
LCDC SEG19 output pin
Hysteresis
LCD
—
—
(Continued)
Document Number: 002-04698 Rev. *A
Page 10 of 110
PRELIMINARY
Pin no. Pin name I/O circuit type*1
Function
MB95610H Series
I/O type
Input
Output OD*2 PU*3
49
SEG20
H
LCDC SEG20 output pin
Hysteresis
LCD
—
—
50
SEG21
H
LCDC SEG21 output pin
Hysteresis
LCD
—
—
51
SEG22
H
LCDC SEG22 output pin
Hysteresis
LCD
—
—
52
SEG23
H
LCDC SEG23 output pin
Hysteresis
LCD
—
—
53
SEG24
H
LCDC SEG24 output pin
Hysteresis
LCD
—
—
54
SEG25
H
LCDC SEG25 output pin
Hysteresis
LCD
—
—
55
SEG26
H
LCDC SEG26 output pin
Hysteresis
LCD
—
—
56
SEG27
H
LCDC SEG27 output pin
Hysteresis
LCD
—
—
57
SEG28
H
LCDC SEG28 output pin
Hysteresis
LCD
—
—
58
SEG29
H
LCDC SEG29 output pin
Hysteresis
LCD
—
—
59
SEG30
H
LCDC SEG30 output pin
Hysteresis
LCD
—
—
60
SEG31
H
LCDC SEG31 output pin
Hysteresis
LCD
—
—
Hysteresis
CMOS/LC
D
—
—
Hysteresis
CMOS/LC
D
—
—
Hysteresis
CMOS/LC
D
—
—
Hysteresis
CMOS/LC
D
—
—
Hysteresis
CMOS/LC
D
—
—
Hysteresis
CMOS/LC
D
—
—
Hysteresis
CMOS/LC
D
—
—
Hysteresis
CMOS/LC
D
—
—
Hysteresis
CMOS/LC
D
—
—
61
P04
SEG32
I
P05
62
SEG33
General-purpose I/O port
I
ADTG
SEG34
General-purpose I/O port
I
PPG10
SEG35
General-purpose I/O port
I
PPG11
SEG36
General-purpose I/O port
I
INT04
67
SEG37
General-purpose I/O port
I
External interrupt input pin
P32
General-purpose I/O port
SEG38
I
SEG39
LCDC SEG38 output pin
External interrupt input pin
P33
69
LCDC SEG37 output pin
INT05
INT06
68
LCDC SEG36 output pin
External interrupt input pin
P31
66
LCDC SEG35 output pin
8/16-bit PPG ch. 1 output pin
P30
65
LCDC SEG34 output pin
8/16-bit PPG ch. 1 output pin
P07
64
LCDC SEG33 output pin
8/10-bit A/D converter trigger input pin
P06
63
General-purpose I/O port
LCDC SEG32 output pin
General-purpose I/O port
I
LCDC SEG39 output pin
INT07
External interrupt input pin
P34
General-purpose I/O port
SEG40
I
TO11
LCDC SEG40 output pin
8/16-bit composite timer ch. 1 output pin
(Continued)
Document Number: 002-04698 Rev. *A
Page 11 of 110
PRELIMINARY
MB95610H Series
(Continued)
Pin no. Pin name I/O circuit type*1
P35
70
SEG41
I
73
16-bit reload timer ch. 0 output pin
General-purpose I/O port
I
SEG45
UART/SIO ch. 1 data output pin
General-purpose I/O port
I
UART/SIO ch. 1 data input pin
General-purpose I/O port
I
—
Hysteresis
CMOS/LC
D
—
—
Hysteresis
CMOS/LC
D
—
—
Hysteresis
CMOS/LC
D
—
—
Hysteresis
CMOS/LC
D
—
—
Hysteresis
CMOS/LC
D
—
—
LCDC SEG48 output pin
Hysteresis
CMOS/LC
D
—
—
LCDC SEG49 output pin
Hysteresis
CMOS/LC
D
—
—
Hysteresis
CMOS/LC
D
—
—
Hysteresis
CMOS/LC
D
—
—
8/16-bit PPG ch. 0 output pin
General-purpose I/O port
I
LCDC SEG50 output pin
I2
SCL
P27
SEG51
—
General-purpose I/O port
I
P26
SEG50
CMOS/LC
D
8/16-bit PPG ch. 0 output pin
PPG01
80
LCDC SEG47 output pin
UI1
SEG49
Hysteresis
General-purpose I/O port
I
P25
79
LCDC SEG46 output pin
P24
SEG48
—
UART/SIO ch. 1 clock I/O pin
PPG00
78
LCDC SEG45 output pin
P22
SEG47
—
General-purpose I/O port
I
P23
77
LCDC SEG44 output pin
UO1
SEG46
CMOS/LC
D
16-bit reload timer ch. 0 input pin
UCK1
76
LCDC SEG43 output pin
P20
P21
75
LCDC SEG42 output pin
TO0
SEG44
Hysteresis
General-purpose I/O port
I
TI0
74
LCDC SEG41 output pin
8/16-bit composite timer ch. 1 clock input pin
P37
SEG43
Output OD*2 PU*3
General-purpose I/O port
EC1
72
Input
8/16-bit composite timer ch. 1 output pin
P36
SEG42
I/O type
General-purpose I/O port
I
TO10
71
Function
C bus interface ch. 0 clock I/O pin
General-purpose I/O port
I
SDA
LCDC SEG51 output pin
I2
C bus interface ch. 0 data I/O pin
: Available
1:For the I/O circuit types, see “I/O Circuit Type”.
2:N-ch open drain
3:Pull-up
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PRELIMINARY
MB95610H Series
6. I/O Circuit Type
Type
Circuit
Remarks
A
Standby control
• N-ch open drain output
• Hysteresis input
Hysteresis input
Digital output
N-ch
B
• CMOS output
• Hysteresis input
• Pull-up control
R
Pull-up control
P-ch
Digital output
Digital output
N-ch
Standby control
Hysteresis input
C
Reset input / Hysteresis input
• N-ch open drain output
• Hysteresis input
• Reset output
Reset output / Digital output
N-ch
D
P-ch
Digital output
• CMOS output
• LCD power supply
• Hysteresis input
Digital output
N-ch
LCD internal divider
resistor I/O
LCD control
Standby control
Hysteresis input
Document Number: 002-04698 Rev. *A
Page 13 of 110
PRELIMINARY
Type
Circuit
Remarks
E
P-ch
Port select
Digital output
N-ch
MB95610H Series
Digital output
Standby control
Hysteresis input
• Oscillation circuit
• High-speed side
Feedback resistance:
approx. 1 M
• CMOS output
• Hysteresis input
Clock input
X1
X0
Standby control / Port select
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
Document Number: 002-04698 Rev. *A
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PRELIMINARY
MB95610H Series
(Continued)
Type
Circuit
Remarks
F
Port select
R
Pull-up control
P-ch
P-ch
Digital output
N-ch
Digital output
• Oscillation circuit
• Low-speed side
Feedback resistance:
approx. 10 M
• CMOS output
• Hysteresis input
• Pull-up control
Standby control
Hysteresis input
Clock input
X1A
X0A
Standby control / Port select
Port select
R
Pull-up control
Digital output
P-ch
Digital output
N-ch
Digital output
Standby control
Hysteresis input
G
P-ch
Digital output
• CMOS output
• Hysteresis input
• Analog input
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
H
LCD output
LCD output
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Page 15 of 110
PRELIMINARY
Type
Circuit
MB95610H Series
Remarks
I
P-ch
Digital output
• CMOS output
• LCD output
• Hysteresis input
Digital output
N-ch
LCD output
LCD control
Standby control
Hysteresis input
Document Number: 002-04698 Rev. *A
Page 16 of 110
PRELIMINARY
MB95610H Series
7. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
7.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
■
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain
established limits, called absolute maximum ratings. Do not exceed these ratings.
■
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering
application outside the listed conditions are advised to contact their sales representative beforehand.
■
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions
at the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
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Page 17 of 110
PRELIMINARY
■
MB95610H Series
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high
heat, smoke or flame. To prevent this from happening, do the following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
■
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference,
etc. Customers are requested to observe applicable regulations and standards in the design of products.
■
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
■
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human
lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace
systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested
to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without
prior approval.
7.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress’s recommended conditions. For detailed information about mount conditions, contact your sales
representative.
■
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified
before mounting.
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PRELIMINARY
■
MB95610H Series
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with FUJITSU SEMICONDUCTOR ranking
of recommended conditions.
■
Lead-Free Packaging
When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be
reduced under some conditions of use.
■
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations
where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 C
and 30C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
■
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the FUJITSU SEMICONDUCTOR
recommended conditions for baking.
Condition: 125C/24 h
■
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%.
Use of an apparatus for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 M).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
Document Number: 002-04698 Rev. *A
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MB95610H Series
7.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with
sales representatives.
Document Number: 002-04698 Rev. *A
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PRELIMINARY
MB95610H Series
8. Notes on Device Handling
■
Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither a
medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned
in “18.1 Absolute Maximum Ratings” of “Electrical Characteristics” is applied to the VCC pin or the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed.
■
Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating
range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the commercial
frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/ms
at a momentary fluctuation such as switching the power supply.
■
Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop
mode.
9. Pin Connection
■
Treatment of unused pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. Always pull
up or pull down an unused input pin through a resistor of at least 2 k. Set an unused input/output pin to the output state and leave
it unconnected, or set it to the input state and treat it the same as an unused input pin. If there is an unused output pin, leave it
unconnected.
■
Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the ground level, and
conform to the total output current standard, always connect the VCC pin and the VSS pin to the power supply and ground outside the
device. In addition, connect the current supply source to the VCC pin and the VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a decoupling capacitor between the VCC pin and the
VSS pin at a location close to this device.
■
DBG pin
Connect the DBG pin to an external pull-up resistor of 2 k or above.
After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released.
The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the
interconnection length, refer to the tool document when selecting a pull-up resistor.
■
RST pin
Connect the RST pin to an external pull-up resistor of 2 k or above.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the interconnection length between a pull-up
resistor and the RST pin and that between a pull-up resistor and the VCC pin when designing the layout of the printed circuit board.
The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the reset output of the PF2/RST pin can be enabled
by the RSTOE bit in the SYSC register, and the reset input function and the general purpose I/O function can be selected by the
RSTEN bit in the SYSC register.
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Page 21 of 110
PRELIMINARY
■
MB95610H Series
C pin
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The decoupling capacitor for the VCC pin must have
a capacitance equal to or larger than the capacitance of CS. For the connection to a decoupling capacitor CS, see the diagram below.
To prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, minimize the distance
between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board.
■
DBG/RST/C pins connection diagram
DBG
C
RST
Cs
■
Note on serial communication
In serial communication, reception of wrong data may occur due to noise or other causes. Therefore, design a printed circuit board
to prevent noise from occurring. Taking account of the reception of wrong data, take measures such as adding a checksum to the end
of data in order to detect errors. If an error is detected, retransmit the data.
Document Number: 002-04698 Rev. *A
Page 22 of 110
PRELIMINARY
MB95610H Series
10. Block Diagram
F2MC-8FX CPU
PF2*1/RST*2
PF0/X0
Reset with LVD
Dual operation Flash with
security function
(36/20/12 Kbyte)
*2
PF1/X1*2
PG1/X0A*2
Oscillator
circuit
CR oscillator
RAM (1024/512 bytes)
PG2/X1A*2
Interrupt controller
P52/TO00
PLL
8/16-bit composite timer ch. 0
P50/TO01
P51/EC0
Clock control
C
On-chip debug
Wild register
P00/INT00 to P03/INT03,
P30/INT04 to P33/INT07
External interrupt
Internal bus
P12*1/DBG
P00/AN00 to P03/AN03
8/10-bit A/D converter
Watch counter
P05/ADTG
4 COM mode:
LCDC
(4 COM or 8 COM)
P14/UCK0
P13/UO0
16-bit reload timer ch. 0
P07/PPG11
SEG04 to SEG31
P04/SEG32 to P07/SEG35
P04/SEG32 to P07/SEG35
P30/SEG36 to P37/SEG43
P30/SEG36 to P37/SEG43
P20/SEG44 to P27/SEG51
P20/SEG44 to P27/SEG51
P20/TI0
P37/TO0
P34/TO11
8/16-bit composite timer ch. 1
P06/PPG10
SEG00 to SEG31
UART/SIO ch. 1
P23/UI1
P25/PPG01
COM0 to COM7
*3
P22/UCK1
P24/PPG00
P90/V4 to P94/V0
COM0 to COM3
UART/SIO ch. 0
P15/UI0
P21/UO1
8 COM mode:
P90/V4 to P94/V0
P36/EC1
8/16-bit PPG ch. 0
I2C bus interface ch. 0
8/16-bit PPG ch. 1
Port
P35/TO10
P27/SDA
P26/SCL
Port
Vcc
Vss
*1: P12 and PF2 are N-ch open drain pins.
*2: Software select
*3: When the event counter operating mode is enabled, 8/16-bit composite timer ch. 1 and the 16-bit reload timer ch. 0 can function as an event counter.
Document Number: 002-04698 Rev. *A
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PRELIMINARY
MB95610H Series
11. CPU Core
■
Memory space
The memory space of the MB95610H Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area, a data area, and
a program area. The memory space includes areas intended for specific purposes such as general-purpose registers and a vector
table. The memory maps of the MB95610H Series are shown below.
■
Memory maps
MB95F613H/F613K
0x0000
0x0080
0x0090
0x0100
0x0200
I/O area
Access prohibited
RAM 512 bytes
Registers
MB95F614H/F614K
0x0000
0x0080
0x0090
0x0100
0x0200
I/O area
Access prohibited
RAM 1024 bytes
Registers
MB95F616H/F616K
0x0000
0x0080
0x0090
0x0100
0x0200
I/O area
Access prohibited
RAM 1024 bytes
Registers
0x0290
Access prohibited
0x0490
0x0490
Access prohibited
0x0F80
0x0F80
0x0F80
Extended I/O area
Extended I/O area
Flash memory 4 Kbyte
Flash memory 4 Kbyte
Flash memory 4 Kbyte
0x2000
0x2000
0x2000
Extended I/O area
0x1000
0x1000
0x1000
Access prohibited
Access prohibited
Access prohibited
0x8000
Access prohibited
0xC000
Flash memory 32 Kbyte
Flash memory 16 Kbyte
0xE000
Flash memory 8 Kbyte
0xFFFF
Document Number: 002-04698 Rev. *A
0xFFFF
0xFFFF
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PRELIMINARY
MB95610H Series
12. Memory Space
The memory space of the MB95610H Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area, a data area, and
a program area. The memory space includes areas for specific applications such as general-purpose registers and a vector table.
■
I/O area (addresses: 0x0000 to 0x007F)
❐ This area contains the control registers and data registers for built-in peripheral functions.
❐ As the I/O area forms part of the memory space, it can be accessed in the same way as the memory. It can also be accessed at
high-speed by using direct addressing instructions.
■
Extended I/O area (addresses: 0x0F80 to 0x0FFF)
❐ This area contains the control registers and data registers for built-in peripheral functions.
❐ As the extended I/O area forms part of the memory space, it can be accessed in the same way as the memory.
■
Data area
❐ Static RAM is incorporated in the data area as the internal data area.
❐ The internal RAM size varies according to product.
❐ The RAM area from 0x0090 to 0x00FF can be accessed at high-speed by using direct addressing instructions.
❐ In MB95F614H/F614K/F616H/F616K, the area from 0x0090 to 0x047F is an extended direct addressing area. It can be accessed
at high-speed by direct addressing instructions with a direct bank pointer set.
❐ In MB95F613H/F613K, the area from 0x0090 to 0x028F is an extended direct addressing area. It can be accessed at high-speed
by direct addressing instructions with a direct bank pointer set.
❐ The area from 0x0100 to 0x01FF can be used as a general-purpose register area.
■
Program area
❐ The Flash memory is incorporated in the program area as the internal program area.
❐ The Flash memory size varies according to product.
❐ The area from 0xFFC0 to 0xFFFF is used as the vector table.
❐ The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register.
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PRELIMINARY
■
MB95610H Series
Memory space map
0x0000
0x0080
0x0090
0x0100
I/O area
Direct addressing area
Access prohibited
Registers
(General-purpose register area)
Extended direct addressing area
0x0200
Data area
0x047F
0x048F
0x0490
Access prohibited
0x0F80
0x0FFF
0x1000
Extended I/O area
Program area
0xFFC0
0xFFFF
Document Number: 002-04698 Rev. *A
Vector table area
Page 26 of 110
PRELIMINARY
MB95610H Series
13. Areas for Specific Applications
The general-purpose register area and vector table area are used for the specific applications.
■
General-purpose register area (Addresses: 0x0100 to 0x01FF*)
❐ This area contains the auxiliary registers used for 8-bit arithmetic operations, transfer, etc.
❐ As this area forms part of the RAM area, it can also be used as conventional RAM.
❐ When the area is used as general-purpose registers, general-purpose register addressing enables high-speed access with short
instructions.
■
Non-volatile register data area (Addresses: 0xFFBB to 0xFFBF)
❐ The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register. For details, refer to “CHAPTER 27 NON-VOLATILE REGISTER (NVR) INTERFACE” in “New 8FX MB95610H Series Hardware Manual”.
■
Vector table area (Addresses: 0xFFC0 to 0xFFFF)
❐ This area is used as the vector table for vector call instructions (CALLV), interrupts, and resets.
❐ The top of the Flash memory area is allocated to the vector table area. The start address of a service routine is set to an address
in the vector table in the form of data.
“■ Interrupt Source Table” lists the vector table addresses corresponding to vector call instructions, interrupts, and resets.
For details, refer to “CHAPTER 4 RESET”, “CHAPTER 5 INTERRUPTS”, and “A.2 Special Instruction ■ Special Instruction ● CALLV
#vct” in “APPENDIX” in “New 8FX MB95610H Series Hardware Manual”.
■
Direct bank pointer and access area
Direct bank pointer (DP[2:0])
Operand-specified dir
Access area
0bXXX (It does not affect mapping.)
0x0000 to 0x007F
0x0000 to 0x007F
0b000 (initial value)
0x0090 to 0x00FF
0x0090 to 0x00FF
0b001
0x0100 to 0x017F
0b010
0x0180 to 0x01FF
0b011
0b100
0x0200 to 0x027F
0x0080 to 0x00FF
0x0280 to 0x02FF*
0b101
0x0300 to 0x037F
0b110
0x0380 to 0x03FF
0b111
0x0400 to 0x047F
*: Due to the memory size limit, the available access area is up to “0x028F” in MB95F613H/F613K.
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PRELIMINARY
MB95610H Series
14. I/O Map
Address
Register
abbreviation
0x0000
PDR0
Port 0 data register
0x0001
DDR0
Port 0 direction register
R/W
0b00000000
0x0002
PDR1
Port 1 data register
R/W
0b00000000
0x0003
DDR1
Port 1 direction register
R/W
0b00000000
0x0004
—
—
—
0x0005
WATR
Oscillation stabilization wait time setting register
R/W
0b11111111
0x0006
PLLC
PLL control register
R/W
0b000X0000
0x0007
SYCC
System clock control register
R/W
0bXXX11011
0x0008
STBC
Standby control register
R/W
0b00000000
Register name
(Disabled)
R/W
Initial value
R/W
0b00000000
0x0009
RSRR
Reset source register
R/W
0b000XXXXX
0x000A
TBTC
Time-base timer control register
R/W
0b00000000
0x000B
WPCR
Watch prescaler control register
R/W
0b00000000
0x000C
WDTC
Watchdog timer control register
R/W
0b00XX0000
0x000D
SYCC2
System clock control register 2
R/W
0bXXXX0011
0x000E
PDR2
Port 2 data register
R/W
0b00000000
0x000F
DDR2
Port 2 direction register
R/W
0b00000000
0x0010
PDR3
Port 3 data register
R/W
0b00000000
Port 3 direction register
R/W
0b00000000
—
—
0x0011
DDR3
0x0012,
0x0013
—
0x0014
PDR5
Port 5 data register
R/W
0b00000000
0x0015
DDR5
Port 5 direction register
R/W
0b00000000
0x0016
to
0x001B
—
—
—
(Disabled)
(Disabled)
0x001C
PDR9
Port 9 data register
R/W
0b00000000
0x001D
DDR9
Port 9 direction register
R/W
0b00000000
0x001E
STBC2
Standby control register 2
R/W
0b00000000
0x001F
to
0x0027
—
—
—
(Disabled)
0x0028
PDRF
Port F data register
R/W
0b00000000
0x0029
DDRF
Port F direction register
R/W
0b00000000
0x002A
PDRG
Port G data register
R/W
0b00000000
0x002B
DDRG
Port G direction register
R/W
0b00000000
0x002C
—
0x002D
PUL1
0x002E
to
0x0030
—
0x0031
PUL5
(Disabled)
Port 1 pull-up register
(Disabled)
Port 5 pull-up register
—
—
R/W
0b00000000
—
—
R/W
0b00000000
(Continued)
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Page 28 of 110
PRELIMINARY
MB95610H Series
Address
Register
abbreviation
Register name
R/W
Initial value
0x0032
to
0x0034
—
(Disabled)
—
—
0x0035
PULG
Port G pull-up register
R/W
0b00000000
0x0036
T01CR1
8/16-bit composite timer 01 status control register 1
R/W
0b00000000
0x0037
T00CR1
8/16-bit composite timer 00 status control register 1
R/W
0b00000000
0x0038
T11CR1
8/16-bit composite timer 11 status control register 1
R/W
0b00000000
0x0039
T10CR1
8/16-bit composite timer 10 status control register 1
R/W
0b00000000
0x003A
PC01
8/16-bit PPG timer 01 control register
R/W
0b00000000
0x003B
PC00
8/16-bit PPG timer 00 control register
R/W
0b00000000
0x003C
PC11
8/16-bit PPG timer 11 control register
R/W
0b00000000
0x003D
PC10
8/16-bit PPG timer 10 control register
R/W
0b00000000
0x003E
TMCSRH0
16-bit reload timer control status register (upper) ch. 0
R/W
0b00000000
0x003F
TMCSRL0
16-bit reload timer control status register (lower) ch. 0
R/W
0b00000000
0x0040
to
0x0047
—
—
—
0x0048
EIC00
External interrupt circuit control register ch. 0/ch. 1
R/W
0b00000000
(Disabled)
0x0049
EIC10
External interrupt circuit control register ch. 2/ch. 3
R/W
0b00000000
0x004A
EIC20
External interrupt circuit control register ch. 4/ch. 5
R/W
0b00000000
External interrupt circuit control register ch. 6/ch. 7
R/W
0b00000000
—
—
LVD reset voltage selection ID register
R/W
0b00000000
LCDC control register 2
R/W
0b00010100
—
—
0x004B
EIC30
0x004C,
0x004D
—
0x004E
LVDR
0x004F
LCDCC2
0x0050
to
0x0055
—
0x0056
SMC10
UART/SIO serial mode control register 1 ch. 0
R/W
0b00000000
0x0057
SMC20
UART/SIO serial mode control register 2 ch. 0
R/W
0b00100000
0x0058
SSR0
UART/SIO serial status and data register ch. 0
R/W
0b00000001
0x0059
TDR0
UART/SIO serial output data register ch. 0
R/W
0b00000000
R
0b00000000
R/W
0b00000000
(Disabled)
(Disabled)
0x005A
RDR0
UART/SIO serial input data register ch. 0
0x005B
SMC11
UART/SIO serial mode control register 1 ch. 1
0x005C
SMC21
UART/SIO serial mode control register 2 ch. 1
R/W
0b00100000
0x005D
SSR1
UART/SIO serial status and data register ch. 1
R/W
0b00000001
R/W
0b00000000
R
0b00000000
0x005E
TDR1
UART/SIO serial output data register ch. 1
0x005F
RDR1
UART/SIO serial input data register ch. 1
0x0060
IBCR00
I2C bus control register 0 ch. 0
R/W
0b00000000
0x0061
IBCR10
I2C bus control register 1 ch. 0
R/W
0b00000000
(Continued)
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PRELIMINARY
Address
Register
abbreviation
0x0062
IBSR0
0x0063
IDDR0
Register name
MB95610H Series
R/W
Initial value
I2C bus status register ch. 0
R/W
0b00000000
I2C data register ch. 0
R/W
0b00000000
2
0x0064
IAAR0
I C address register ch. 0
R/W
0b00000000
0x0065
ICCR0
I2C clock control register ch. 0
R/W
0b00000000
0x0066
to
0x006B
—
—
—
0x006C
ADC1
8/10-bit A/D converter control register 1
R/W
0b00000000
0x006D
ADC2
8/10-bit A/D converter control register 2
R/W
0b00000000
0x006E
ADDH
8/10-bit A/D converter data register (upper)
R/W
0b00000000
(Disabled)
0x006F
ADDL
8/10-bit A/D converter data register (lower)
R/W
0b00000000
0x0070
WCSR
Watch counter status register
R/W
0b00000000
0x0071
FSR2
Flash memory status register 2
R/W
0b00000000
0x0072
FSR
Flash memory status register
R/W
0b000X0000
0x0073
SWRE0
Flash memory sector write control register 0
R/W
0b00000000
0x0074
FSR3
R
0b000XXXXX
Flash memory status register 3
0x0075
FSR4
Flash memory status register 4
R/W
0b00000000
0x0076
WREN
Wild register address compare enable register
R/W
0b00000000
0x0077
WROR
Wild register data test setting register
R/W
0b00000000
0x0078
—
—
—
0x0079
ILR0
Interrupt level setting register 0
R/W
0b11111111
0x007A
ILR1
Interrupt level setting register 1
R/W
0b11111111
Mirror of register bank pointer (RP) and direct bank pointer (DP)
0x007B
ILR2
Interrupt level setting register 2
R/W
0b11111111
0x007C
ILR3
Interrupt level setting register 3
R/W
0b11111111
0x007D
ILR4
Interrupt level setting register 4
R/W
0b11111111
0x007E
ILR5
Interrupt level setting register 5
R/W
0b11111111
0x007F
—
0x0F80
WRARH0
—
—
Wild register address setting register (upper) ch. 0
0x0F81
0x0F82
0x0F83
0x0F84
(Disabled)
R/W
0b00000000
WRARL0
Wild register address setting register (lower) ch. 0
R/W
0b00000000
WRDR0
Wild register data setting register ch. 0
R/W
0b00000000
WRARH1
Wild register address setting register (upper) ch. 1
R/W
0b00000000
WRARL1
Wild register address setting register (lower) ch. 1
R/W
0b00000000
0x0F85
WRDR1
Wild register data setting register ch. 1
R/W
0b00000000
0x0F86
WRARH2
Wild register address setting register (upper) ch. 2
R/W
0b00000000
0x0F87
WRARL2
Wild register address setting register (lower) ch. 2
R/W
0b00000000
0x0F88
WRDR2
Wild register data setting register ch. 2
R/W
0b00000000
0x0F89
to
0x0F91
—
—
—
0x0F92
T01CR0
8/16-bit composite timer 01 status control register 0
R/W
0b00000000
0x0F93
T00CR0
8/16-bit composite timer 00 status control register 0
R/W
0b00000000
(Disabled)
(Continued)
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PRELIMINARY
MB95610H Series
Address
Register
abbreviation
0x0F94
T01DR
0x0F95
T00DR
0x0F96
0x0F97
0x0F98
T10CR0
8/16-bit composite timer 10 status control register 0
R/W
0b00000000
0x0F99
T11DR
8/16-bit composite timer 11 data register
R/W
0b00000000
0x0F9A
T10DR
8/16-bit composite timer 10 data register
R/W
0b00000000
0x0F9B
TMCR1
8/16-bit composite timer 10/11 timer mode control register
R/W
0b00000000
0x0F9C
PPS01
8/16-bit PPG01 cycle setting buffer register
R/W
0b11111111
0x0F9D
PPS00
8/16-bit PPG00 cycle setting buffer register
R/W
0b11111111
0x0F9E
PDS01
8/16-bit PPG01 duty setting buffer register
R/W
0b11111111
0x0F9F
PDS00
8/16-bit PPG00 duty setting buffer register
R/W
0b11111111
0x0FA0
PPS11
8/16-bit PPG11 cycle setting buffer register
R/W
0b11111111
0x0FA1
PPS10
8/16-bit PPG10 cycle setting buffer register
R/W
0b11111111
Register name
R/W
Initial value
8/16-bit composite timer 01 data register
R/W
0b00000000
8/16-bit composite timer 00 data register
R/W
0b00000000
TMCR0
8/16-bit composite timer 00/01 timer mode control register
R/W
0b00000000
T11CR0
8/16-bit composite timer 11 status control register 0
R/W
0b00000000
0x0FA2
PDS11
8/16-bit PPG11 duty setting buffer register
R/W
0b11111111
0x0FA3
PDS10
8/16-bit PPG10 duty setting buffer register
R/W
0b11111111
0x0FA4
PPGS
8/16-bit PPG start register
R/W
0b00000000
0x0FA5
REVC
8/16-bit PPG output inversion register
R/W
0b00000000
R/W
0b00000000
R/W
0b00000000
0x0FA6
0x0FA7
0x0FA8
TMRH0
16-bit reload timer timer register (upper) ch. 0
TMRLRH0
16-bit reload timer reload register (upper) ch. 0
TMRL0
16-bit reload timer timer register (lower) ch. 0
TMRLRL0
16-bit reload timer reload register (lower) ch. 0
PSSR0
UART/SIO dedicated baud rate generator prescaler select register ch. 0
R/W
0b00000000
0x0FA9
BRSR0
UART/SIO dedicated baud rate generator baud rate setting register ch.
0
R/W
0b00000000
0x0FAA
PSSR1
UART/SIO dedicated baud rate generator prescaler select register ch. 1
R/W
0b00000000
0x0FAB
BRSR1
UART/SIO dedicated baud rate generator baud rate setting register ch.
1
R/W
0b00000000
0x0FAC
to
0x0FAE
—
(Disabled)
—
—
0x0FAF
AIDRL
A/D input disable register (lower)
R/W
0b00000000
0x0FB0
LCDCC1
LCDC control register 1
R/W
0b00000000
0x0FB1
—
—
—
(Disabled)
0x0FB2
LCDCE1
LCDC enable register 1
R/W
0b00111110
0x0FB3
LCDCE2
LCDC enable register 2
R/W
0b00000000
0x0FB4
LCDCE3
LCDC enable register 3
R/W
0b00000000
0x0FB5
LCDCE4
LCDC enable register 4
R/W
0b00000000
0x0FB6
LCDCE5
LCDC enable register 5
R/W
0b00000000
(Continued)
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PRELIMINARY
MB95610H Series
(Continued)
Address
Register
abbreviation
0x0FB7
LCDCE6
0x0FB8
LCDCE7
0x0FB9
0x0FBA
Register name
R/W
Initial value
LCDC enable register 6
R/W
0b00000000
LCDC enable register 7
R/W
0b00000000
LCDCE8
LCDC enable register 8
R/W
0b00000000
LCDCE9
LCDC enable register 9
R/W
0b00000000
0x0FBB
LCDCB1
LCDC blinking setting register 1
R/W
0b00000000
0x0FBC
LCDCB2
LCDC blinking setting register 2
R/W
0b00000000
0x0FBD
to
0x0FE0
LCDRAM
LCDC display RAM
4 COM mode: 0x0FBD to 0x0FD6 (26 bytes)
8 COM mode: 0x0FC1 to 0x0FE0 (32 bytes)
R/W
0b00000000
0x0FE1
—
—
—
(Disabled)
0x0FE2
EVCR
Event counter control register
R/W
0bXXXXXXX0
0x0FE3
WCDR
Watch counter data register
R/W
0b00111111
0x0FE4
CRTH
Main CR clock trimming register (upper)
R/W
0b000XXXXX
0x0FE5
CRTL
Main CR clock trimming register (lower)
R/W
0b000XXXXX
0x0FE6
—
0x0FE7
CRTDA
—
—
Main CR clock temperature dependent adjustment register
(Disabled)
R/W
0b000XXXXX
0x0FE8
SYSC
System configuration register
R/W
0b11000011
0x0FE9
CMCR
Clock monitoring control register
R/W
0b00000000
0x0FEA
CMDR
Clock monitoring data register
R
0b00000000
0x0FEB
WDTH
Watchdog timer selection ID register (upper)
R
0bXXXXXXXX
Watchdog timer selection ID register (lower)
R
0bXXXXXXXX
—
—
0x0FEC
WDTL
0x0FED,
0x0FEE
—
0x0FEF
WICR
Interrupt pin selection circuit control register
R/W
0b01000000
0x0FF0
to
0x0FFF
LCDRAM
LCDC display RAM
4 COM mode: Unused
8 COM mode: 0x0FF0 to 0x0FFF (16 bytes)
R/W
0b00000000
(Disabled)
■
R/W access symbols
R/W
: Readable/Writable
R
: Read only
■
Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned.
Document Number: 002-04698 Rev. *A
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PRELIMINARY
MB95610H Series
15. I/O Ports
■
List of port registers
Register name
Read/Write
Initial value
Port 0 data register
PDR0
R, RM/W
0b00000000
Port 0 direction register
DDR0
R/W
0b00000000
Port 1 data register
PDR1
R, RM/W
0b00000000
Port 1 direction register
DDR1
R/W
0b00000000
Port 2 data register
PDR2
R, RM/W
0b00000000
Port 2 direction register
DDR2
R/W
0b00000000
Port 3 data register
PDR3
R, RM/W
0b00000000
Port 3 direction register
DDR3
R/W
0b00000000
Port 5 data register
PDR5
R, RM/W
0b00000000
Port 5 direction register
DDR5
R/W
0b00000000
Port 9 data register
PDR9
R, RM/W
0b00000000
Port 9 direction register
DDR9
R/W
0b00000000
Port F data register
PDRF
R, RM/W
0b00000000
Port F direction register
DDRF
R/W
0b00000000
Port G data register
PDRG
R, RM/W
0b00000000
Port G direction register
DDRG
R/W
0b00000000
Port 1 pull-up register
PUL1
R/W
0b00000000
Port 5 pull-up register
PUL5
R/W
0b00000000
Port G pull-up register
PULG
R/W
0b00000000
A/D input disable register (lower)
AIDRL
R/W
0b00000000
R/W
: Readable/writable (The read value is the same as the write value.)
R, RM/W : Readable/writable (The read value is different from the write value. The write value is read by the read-modify-write
(RMW) type of instruction.)
15.1 Port 0
Port 0 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral
functions, refer to their respective chapters in “New 8FX MB95610H Series Hardware Manual”.
15.1.1 Port 0 configuration
Port 0 is made up of the following elements.
■
General-purpose I/O pins/peripheral function I/O pins
■
Port 0 data register (PDR0)
■
Port 0 direction register (DDR0)
■
A/D input disable register (lower) (AIDRL)
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PRELIMINARY
MB95610H Series
15.1.2 Block diagrams of port 0
■
P00/INT00/AN00 pin
This pin has the following peripheral functions:
❐ External interrupt circuit input pin (INT00)
❐ 8/10-bit A/D converter analog input pin (AN00)
■
P01/INT01/AN01 pin
This pin has the following peripheral functions:
❐ External interrupt circuit input pin (INT01)
❐ 8/10-bit A/D converter analog input pin (AN01)
■
P02/INT02/AN02 pin
This pin has the following peripheral functions:
❐ External interrupt circuit input pin (INT02)
❐ 8/10-bit A/D converter analog input pin (AN02)
■
P03/INT03/AN03 pin
This pin has the following peripheral functions:
❐ External interrupt circuit input pin (INT03)
❐ 8/10-bit A/D converter analog input pin (AN03)
■
Block diagram of P00/INT00/AN00, P01/INT01/AN01, P02/INT02/AN02 and P03/INT03/AN03
Peripheral function input
A/D analog input
Peripheral function input enable
(INT00, INT01, INT02 and INT03)
0
1
PDR0 read
PDR0
Pin
PDR0 write
Internal bus
Executing bit manipulation instruction
DDR0 read
DDR0
DDR0 write
Stop mode, watch mode (SPL = 1)
AIDRL read
AIDRL
AIDRL write
■
P04/SEG32 pin
This pin has the following peripheral function:
❐ LCDC SEG32 output pin (SEG32)
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PRELIMINARY
■
MB95610H Series
Block diagram of P04/SEG32
LCD output
LCD output enable
0
1
PDR0 read
Pin
Internal bus
PDR0
PDR0 write
Executing bit manipulation instruction
DDR0 read
DDR0
DDR0 write
■
Stop mode, watch mode (SPL = 1)
P05/SEG33/ADTG pin
This pin has the following peripheral functions:
❐ LCDC SEG33 output pin (SEG33)
❐ 8/10-bit A/D converter trigger input pin (ADTG)
■
Block diagram of P05/SEG33/ADTG
Peripheral function input
Peripheral function input enable
LCD output
LCD output enable
0
1
PDR0 read
Internal bus
PDR0
Pin
PDR0 write
Executing bit manipulation instruction
DDR0 read
DDR0
DDR0 write
■
Stop mode, watch mode (SPL = 1)
P06/SEG34/PPG10 pin
This pin has the following peripheral functions:
❐ LCDC SEG34 output pin (SEG34)
❐ 8/16-bit PPG ch. 1 output pin (PPG10)
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PRELIMINARY
■
MB95610H Series
P07/SEG35/PPG11 pin
This pin has the following peripheral functions:
❐ LCDC SEG35 output pin (SEG35)
❐ 8/16-bit PPG ch. 1 output pin (PPG11)
■
Block diagram of P06/SEG34/PPG10 and P07/SEG35/PPG11
Peripheral function output enable
Peripheral function output
LCD output
LCD output enable
0
1
PDR0 read
1
Internal bus
PDR0
0
Pin
PDR0 write
Executing bit manipulation instruction
DDR0 read
DDR0
DDR0 write
Stop mode, watch mode (SPL = 1)
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PRELIMINARY
MB95610H Series
15.1.3 Port 0 registers
■
Port 0 register functions
Register
abbreviation
PDR0
DDR0
AIDRL
■
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR0 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR0 value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
0
Analog input enabled
1
Port input enabled
Correspondence between registers and pins for port 0
Correspondence between related register bits and pins
Pin name
PDR0
DDR0
AIDRL
P07
P06
P05
P04
bit7
bit6
bit5
bit4
-
-
-
-
P03
P02
P01
P00
bit3
bit2
bit1
bit0
15.1.4 Port 0 operations
■
Operation as an output port
❐ A pin becomes an output port if the bit in the DDR0 register corresponding to that pin is set to “1”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ When a pin is used as an output port, it outputs the value of the PDR0 register to external pins.
❐ If data is written to the PDR0 register, the value is stored in the output latch and is output to the pin set as an output port as it is.
❐ Reading the PDR0 register returns the PDR0 register value.
❐ To use a pin shared with the LCDC as an output port, set a corresponding function select bit (SEG[35:32]) in the LCDC enable
register 7 (LCDCE7) to “0” to select the general-purpose I/O port function, and then set the port input control bit (PICTL) in the
LCDC enable register 1 (LCDCE1) to “1”.
■
Operation as an input port
❐ A pin becomes an input port if the bit in the DDR0 register corresponding to that pin is set to “0”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ When using an analog input shared pin as an input port, set the corresponding bit in the A/D input disable register (lower) (AIDRL)
to “1”.
❐ If data is written to the PDR0 register, the value is stored in the output latch but is not output to the pin set as an input port.
❐ Reading the PDR0 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the
PDR0 register, the PDR0 register value is returned.
❐ To use a pin shared with the LCDC as an input port, set a corresponding function select bit (SEG[35:32]) in the LCDCE7 register
to “0” to select the general-purpose I/O port function, and then set the PICTL bit in the LCDCE1 register to “1”.
■
Operation as a peripheral function output pin
❐ A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a
peripheral function corresponding to that pin.
❐ The pin value can be read from the PDR0 register even if the peripheral function output is enabled. Therefore, the output value
of a peripheral function can be read by the read operation on the PDR0 register. However, if the read-modify-write (RMW) type
of instruction is used to read the PDR0 register, the PDR0 register value is returned.
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■
Operation as a peripheral function input pin
❐ To set a pin as an input port, set the bit in the DDR0 register corresponding to the input pin of a peripheral function to “0”.
❐ When using the analog input shared pin as another peripheral function input pin, configure it as an input port, which is the same
as the operation as an input port.
❐ Reading the PDR0 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin.
However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned.
■
Operation as an LCDC segment output pin
❐ Set the bit in the DDR0 register corresponding to a desired LCDC segment output pin to “0”.
❐ Select the segment pin by setting a corresponding function select bit (SEG[35:32]) in the LCDCE7 register to “1”, and then set
the PICTL bit in the LCDCE1 register to “1”.
■
Operation at reset
If the CPU is reset, all bits in the DDR0 register are initialized to “0” and port input is enabled. As for a pin shared with analog input,
its port input is disabled because the AIDRL register is initialized to “0”.
■
Operation in stop mode and watch mode
❐ If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch
mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR0 register value. The input of that
pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the
external interrupt (INT00 to INT03), the input is enabled and not blocked.
❐ If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output
level is maintained.
■
Operation as an analog input pin
❐ Set the bit in the DDR0 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin in the AIDRL
register to “0”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
■
Operation as an external interrupt input pin
❐ Set the bit in the DDR0 register corresponding to the external interrupt input pin to “0”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the
external interrupt function corresponding to that pin.
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MB95610H Series
15.2 Port 1
Port 1 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral
functions, refer to their respective chapters in “New 8FX MB95610H Series Hardware Manual”.
15.2.1 Port 1 configuration
Port 1 is made up of the following elements.
■
General-purpose I/O pins/peripheral function I/O pins
■
Port 1 data register (PDR1)
■
Port 1 direction register (DDR1)
■
Port 1 pull-up register (PUL1)
15.2.2 Block diagrams of port 1
■
P12/DBG pin
This pin has the following peripheral function:
❐ DBG input pin (DBG)
■
Block diagram of P12/DBG
0
1
PDR1 read
Internal bus
PDR1
Pin
OD
PDR1 write
Executing bit manipulation instruction
DDR1 read
DDR1
DDR1 write
Stop mode, watch mode (SPL = 1)
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MB95610H Series
P13/UO0 pin
This pin has the following peripheral function:
❐ UART/SIO ch. 0 data output pin (UO0)
■
Block diagram of P13/UO0
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR1 read
1
PDR1
0
Pin
PDR1 write
Internal bus
Executing bit manipulation instruction
DDR1 read
DDR1
DDR1 write
Stop mode, watch mode (SPL = 1)
PUL1 read
PUL1
PUL1 write
■
P14/UCK0 pin
This pin has the following peripheral function:
❐ UART/SIO ch. 0 clock I/O pin (UCK0)
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MB95610H Series
Block diagram of P14/UCK0
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR1 read
1
PDR1
0
Pin
PDR1 write
Internal bus
Executing bit manipulation instruction
DDR1 read
DDR1
DDR1 write
Stop mode, watch mode (SPL = 1)
PUL1 read
PUL1
PUL1 write
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MB95610H Series
P15/UI0 pin
This pin has the following peripheral function:
❐ UART/SIO ch. 0 data input pin (UI0)
■
Block diagram of P15/UI0
Peripheral function input
Peripheral function input enable
CMOS
0
Pull-up
1
PDR1 read
PDR1
Pin
PDR1 write
Internal bus
Executing bit manipulation instruction
DDR1 read
DDR1
DDR1 write
Stop mode, watch mode (SPL = 1)
PUL1 read
PUL1
PUL1 write
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15.2.3 Port 1 registers
■
Port 1 register functions
Register
abbreviation
PDR1
DDR1
PUL1
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR1 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR1 value is “1”.
As output port, outputs “H” level.*
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.
■
Correspondence between registers and pins for port 1
Correspondence between related register bits and pins
Pin name
-
-
P15
P14
P13
P12
-
-
-
-
bit5
bit4
bit3
bit2*
-
-
PDR1
DDR1
PUL1
*: Though P12 has no pull-up function, bit2 in the PUL1 register can still be accessed. The operation of P12 is not affected by the
setting of bit2 in the PUL1 register.
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15.2.4 Port 1 operations
■
Operation as an output port
❐ A pin becomes an output port if the bit in the DDR1 register corresponding to that pin is set to “1”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ When a pin is used as an output port, it outputs the value of the PDR1 register to external pins.
❐ If data is written to the PDR1 register, the value is stored in the output latch and is output to the pin set as an output port as it is.
❐ Reading the PDR1 register returns the PDR1 register value.
■
Operation as an input port
❐ A pin becomes an input port if the bit in the DDR1 register corresponding to that pin is set to “0”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ If data is written to the PDR1 register, the value is stored in the output latch but is not output to the pin set as an input port.
❐ Reading the PDR1 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the
PDR1 register, the PDR1 register value is returned.
■
Operation as a peripheral function output pin
❐ A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a
peripheral function corresponding to that pin.
❐ The pin value can be read from the PDR1 register even if the peripheral function output is enabled. Therefore, the output value
of a peripheral function can be read by the read operation on the PDR1 register. However, if the read-modify-write (RMW) type
of instruction is used to read the PDR1 register, the PDR1 register value is returned.
■
Operation as a peripheral function input pin
❐ To set a pin as an input port, set the bit in the DDR1 register corresponding to the input pin of a peripheral function to “0”.
❐ Reading the PDR1 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin.
However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned.
■
Operation at reset
If the CPU is reset, all bits in the DDR1 register are initialized to “0” and port input is enabled.
■
Operation in stop mode and watch mode
❐ If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch
mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR1 register value. The input of that
pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P14/UCK0 and
P15/UI0 is enabled by the external interrupt control register ch. 0 (EIC00) of the external interrupt circuit and the interrupt pin
selection circuit control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked.
❐ If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output
level is maintained.
■
Operation of the pull-up register
Setting the bit in the PUL1 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level,
the pull-up resistor is disconnected regardless of the value of the PUL1 register.
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MB95610H Series
15.3 Port 2
Port 2 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral
functions, refer to their respective chapters in “New 8FX MB95610H Series Hardware Manual”.
15.3.1 Port 2 configuration
Port 2 is made up of the following elements.
■
General-purpose I/O pins/peripheral function I/O pins
■
Port 2 data register (PDR2)
■
Port 2 direction register (DDR2)
15.3.2 Block diagrams of port 2
■
P20/SEG44/TI0 pin
This pin has the following peripheral functions:
❐ LCDC SEG44 output pin (SEG44)
❐ 16-bit reload timer ch. 0 input pin (TI0)
■
P23/SEG47/UI1 pin
This pin has the following peripheral functions:
❐ LCDC SEG47 output pin (SEG47)
❐ UART/SIO ch. 1 data input pin (UI1)
■
Block diagram of P20/SEG44/TI0 and P23/SEG47/UI1
Peripheral function input
Peripheral function input enable
LCD output
LCD output enable
0
1
PDR2 read
Internal bus
PDR2
Pin
PDR2 write
Executing bit manipulation instruction
DDR2 read
DDR2
DDR2 write
Stop mode, watch mode (SPL = 1)
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MB95610H Series
P21/SEG45/UO1 pin
This pin has the following peripheral functions:
❐ LCDC SEG45 output pin (SEG45)
❐ UART/SIO ch. 1 data output pin (UO1)
■
P24/SEG48/PPG00 pin
This pin has the following peripheral functions:
❐ LCDC SEG48 output pin (SEG48)
❐ 8/16-bit PPG ch. 0 output pin (PPG00)
■
P25/SEG49/PPG01 pin
This pin has the following peripheral functions:
❐ LCDC SEG49 output pin (SEG49)
❐ 8/16-bit PPG ch. 0 output pin (PPG01)
■
Block diagram of P21/SEG45/UO1, P24/SEG48/PPG00 and P25/SEG49/PPG01
Peripheral function output enable
Peripheral function output
LCD output
LCD output enable
0
1
PDR2 read
1
Internal bus
PDR2
0
Pin
PDR2 write
Executing bit manipulation instruction
DDR2 read
DDR2
DDR2 write
Stop mode, watch mode (SPL = 1)
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MB95610H Series
P22/SEG46/UCK1 pin
This pin has the following peripheral functions:
❐ LCDC SEG46 output pin (SEG46)
❐ UART/SIO ch. 1 clock I/O pin (UCK1)
■
P26/SEG50/SCL pin
This pin has the following peripheral functions:
❐ LCDC SEG50 output pin (SEG50)
2
❐ I C bus interface ch. 0 clock I/O pin (SCL)
■
P27/SEG51/SDA pin
This pin has the following peripheral functions:
❐ LCDC SEG51 output pin (SEG51)
2
❐ I C bus interface ch. 0 data I/O pin (SDA)
■
Block diagram of P22/SEG46/UCK1, P26/SEG50/SCL and P27/SEG51/SDA
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
LCD output
LCD output enable
0
1
PDR2 read
1
Internal bus
PDR2
0
Pin
PDR2 write
Executing bit manipulation instruction
DDR2 read
DDR2
DDR2 write
Stop mode, watch mode (SPL = 1)
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15.3.3 Port 2 registers
■
Port 2 register functions
Register
abbreviation
PDR2
DDR2
■
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR2 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR2 value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
Correspondence between registers and pins for port 2
Correspondence between related register bits and pins
Pin name
PDR2
DDR2
P27
P26
P25
P24
P23
P22
P21
P20
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
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15.3.4 Port 2 operations
■
Operation as an output port
❐ A pin becomes an output port if the bit in the DDR2 register corresponding to that pin is set to “1”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ When a pin is used as an output port, it outputs the value of the PDR2 register to external pins.
❐ If data is written to the PDR2 register, the value is stored in the output latch and is output to the pin set as an output port as it is.
❐ Reading the PDR2 register returns the PDR2 register value.
❐ To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 9
(LCDCE9:SEG[51:48]) or in the LCDC enable register 8 (LCDCE8:SEG[47:44]) to “0” to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1 (LCDCE1) to “1”.
■
Operation as an input port
❐ A pin becomes an input port if the bit in the DDR2 register corresponding to that pin is set to “0”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ If data is written to the PDR2 register, the value is stored in the output latch but is not output to the pin set as an input port.
❐ Reading the PDR2 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the
PDR2 register, the PDR2 register value is returned.
❐ To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 9
(LCDCE9:SEG[51:48]) or in the LCDC enable register 8 (LCDCE8:SEG[47:44]) to “0” to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1 (LCDCE1) to “1”.
■
Operation as a peripheral function output pin
❐ A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a
peripheral function corresponding to that pin.
❐ The pin value can be read from the PDR2 register even if the peripheral function output is enabled. Therefore, the output value
of a peripheral function can be read by the read operation on the PDR2 register. However, if the read-modify-write (RMW) type
of instruction is used to read the PDR2 register, the PDR2 register value is returned.
■
Operation as a peripheral function input pin
❐ To set a pin as an input port, set the bit in the DDR2 register corresponding to the input pin of a peripheral function to “0”.
❐ Reading the PDR2 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin.
However, if the read-modify-write (RMW) type of instruction is used to read the PDR2 register, the PDR2 register value is returned.
■
Operation as an LCDC segment output pin
❐ Set the bit in the DDR2 register corresponding to a desired LCDC segment output pin to “0”.
❐ Select the segment pin by setting a corresponding function select bit in the LCDC enable register 9 (LCDCE9:SEG[51:48]) or in
the LCDC enable register 8 (LCDCE8:SEG[47:44]) to “1”, and then set the PICTL bit in the LCDCE1 register to “1”.
■
Operation at reset
If the CPU is reset, all bits in the DDR2 register are initialized to “0” and port input is enabled.
■
Operation in stop mode and watch mode
❐ If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch
mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR2 register value. The input of that
pin is locked to “L” level and blocked in order to prevent leaks due to input open.
❐ If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output
level is maintained.
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MB95610H Series
15.4 Port 3
Port 3 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral
functions, refer to their respective chapters in “New 8FX MB95610H Series Hardware Manual”.
15.4.1 Port 3 configuration
Port 3 is made up of the following elements.
❐ General-purpose I/O pins/peripheral function I/O pins
❐ Port 3 data register (PDR3)
❐ Port 3 direction register (DDR3)
15.4.2 Block diagrams of port 3
■
P30/SEG36/INT04 pin
This pin has the following peripheral functions:
❐ LCDC SEG36 output pin (SEG36)
❐ External interrupt input pin (INT04)
■
P31/SEG37/INT05 pin
This pin has the following peripheral functions:
❐ LCDC SEG37 output pin (SEG37)
❐ External interrupt input pin (INT05)
■
P32/SEG38/INT06 pin
This pin has the following peripheral functions:
❐ LCDC SEG38 output pin (SEG38)
❐ External interrupt input pin (INT06)
■
P33/SEG39/INT07 pin
This pin has the following peripheral functions:
❐ LCDC SEG39 output pin (SEG39)
❐ External interrupt input pin (INT07)
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MB95610H Series
Block diagram of P30/SEG36/INT04, P31/SEG37/INT05, P32/SEG38/INT06 and P33/SEG39/INT07
Peripheral function input
LCD output
Peripheral function input enable
(INT04, INT05, INT06 and INT07)
LCD output enable
0
1
PDR3 read
Internal bus
PDR3
Pin
PDR3 write
Executing bit manipulation instruction
DDR3 read
DDR3
DDR3 write
Stop mode, watch mode (SPL = 1)
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MB95610H Series
P34/SEG40/TO11 pin
This pin has the following peripheral functions:
❐ LCDC SEG40 output pin (SEG40)
❐ 8/16-bit composite timer ch. 1 output pin (TO11)
■
P35/SEG41/TO10 pin
This pin has the following peripheral functions:
❐ LCDC SEG41 output pin (SEG41)
❐ 8/16-bit composite timer ch. 1 output pin (TO10)
■
P37/SEG43/TO0 pin
This pin has the following peripheral functions:
❐ LCDC SEG43 output pin (SEG43)
❐ 16-bit reload timer ch. 0 output pin (TO0)
■
Block diagram of P34/SEG40/TO11, P35/SEG41/TO11 and P37/SEG43/TO0
Peripheral function output enable
Peripheral function output
LCD output
LCD output enable
0
1
PDR3 read
1
Internal bus
PDR3
0
Pin
PDR3 write
Executing bit manipulation instruction
DDR3 read
DDR3
DDR3 write
Stop mode, watch mode (SPL = 1)
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MB95610H Series
P36/SEG42/EC1 pin
This pin has the following peripheral functions:
❐ LCDC SEG42 output pin (SEG42)
❐ 8/16-bit composite timer ch. 1 clock input pin (EC1)
■
Block diagram of P36/SEG42/EC1
Peripheral function input
Peripheral function input enable
LCD output
LCD output enable
0
1
PDR3 read
Pin
Internal bus
PDR3
PDR3 write
Executing bit manipulation instruction
DDR3 read
DDR3
DDR3 write
Stop mode, watch mode (SPL = 1)
15.4.3 Port 3 registers
■
Port 3 register functions
Register
abbreviation
PDR3
DDR3
■
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR3 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR3 value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
Correspondence between registers and pins for port 3
Correspondence between related register bits and pins
Pin name
PDR3
DDR3
P37
P36
P35
P34
P33
P32
P31
P30
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
15.4.4 Port 3 operations
■
Operation as an output port
❐ A pin becomes an output port if the bit in the DDR3 register corresponding to that pin is set to “1”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ When a pin is used as an output port, it outputs the value of the PDR3 register to external pins.
❐ If data is written to the PDR3 register, the value is stored in the output latch and is output to the pin set as an output port as it is.
❐ Reading the PDR3 register returns the PDR3 register value.
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❐
MB95610H Series
To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 8
(LCDCE8:SEG[43:40]) or in the LCDC enable register 7 (LCDCE7:SEG[39:36]) to “0” to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1 (LCDCE1) to “1”.
■
Operation as an input port
❐ A pin becomes an input port if the bit in the DDR3 register corresponding to that pin is set to “0”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ If data is written to the PDR3 register, the value is stored in the output latch but is not output to the pin set as an input port.
❐ Reading the PDR3 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the
PDR3 register, the PDR3 register value is returned.
❐ To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 8
(LCDCE8:SEG[43:40]) or in the LCDC enable register 7 (LCDCE7:SEG[39:36]) to “0” to select the general-purpose I/O port
function, and then set the port input control bit (PICTL) in the LCDC enable register 1 (LCDCE1) to “1”.
■
Operation as a peripheral function output pin
❐ A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a
peripheral function corresponding to that pin.
❐ The pin value can be read from the PDR3 register even if the peripheral function output is enabled. Therefore, the output value
of a peripheral function can be read by the read operation on the PDR3 register. However, if the read-modify-write (RMW) type
of instruction is used to read the PDR3 register, the PDR3 register value is returned.
■
Operation as a peripheral function input pin
❐ To set a pin as an input port, set the bit in the DDR3 register corresponding to the input pin of a peripheral function to “0”.
❐ Reading the PDR3 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin.
However, if the read-modify-write (RMW) type of instruction is used to read the PDR3 register, the PDR3 register value is returned.
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■
Operation as an LCDC segment output pin
❐ Set the bit in the DDR3 register corresponding to a desired LCDC segment output pin to “0”.
❐ Select the segment pin by setting a corresponding function select bit in the LCDC enable register 8 (LCDCE8:SEG[43:40]) or in
the LCDC enable register 7 (LCDCE7:SEG[39:36]) to “1”, and then set the PICTL bit in the LCDCE1 register to “1”.
■
Operation at reset
If the CPU is reset, all bits in the DDR3 register are initialized to “0” and port input is enabled.
■
Operation in stop mode and watch mode
❐ If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch
mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR3 register value. The input of that
pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the
external interrupt (INT04 to INT07), the input is enabled and not blocked.
❐ If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output
level is maintained.
■
Operation as an external interrupt input pin
❐ Set the bit in the DDR3 register corresponding to the external interrupt input pin to “0”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the
external interrupt function corresponding to that pin.
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PRELIMINARY
MB95610H Series
15.5 Port 5
Port 5 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral
functions, refer to their respective chapters in “New 8FX MB95610H Series Hardware Manual”.
15.5.1 Port 5 configuration
Port 5 is made up of the following elements.
■
General-purpose I/O pins/peripheral function I/O pins
■
Port 5 data register (PDR5)
■
Port 5 direction register (DDR5)
■
Port 5 pull-up register (PUL5)
15.5.2 Block diagrams of port 5
■
P50/TO01 pin
This pin has the following peripheral function:
❐ 8/16-bit composite time ch. 0 output pin (TO01)
■
P52/TO00 pin
This pin has the following peripheral function:
❐ 8/16-bit composite time ch. 0 output pin (TO00)
■
Block diagram of P50/TO01 and P52/TO00
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR5 read
1
PDR5
0
Pin
PDR5 write
Internal bus
Executing bit manipulation instruction
DDR5 read
DDR5
DDR5 write
Stop mode, watch mode (SPL = 1)
PUL5 read
PUL5
PUL5 write
■
P51/EC0 pin
This pin has the following peripheral function:
❐ 8/16-bit composite time ch. 0 clock input pin (EC0)
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PRELIMINARY
■
MB95610H Series
Block diagram of P51/EC0
Peripheral function input
Peripheral function input enable
Hysteresis
0
Pull-up
1
PDR5 read
PDR5
Pin
PDR5 write
Internal bus
Executing bit manipulation instruction
DDR5 read
DDR5
DDR5 write
Stop mode, watch mode (SPL = 1)
PUL5 read
PUL5
PUL5 write
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PRELIMINARY
MB95610H Series
15.5.3 Port 5 registers
■
Port 5 register functions
Register
abbreviation
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR5 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR5 value is “1”.
As output port, outputs “H” level.
PDR5
DDR5
PUL5
■
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
Correspondence between registers and pins for port 5
Correspondence between related register bits and pins
Pin name
-
-
-
-
-
P52
P51
P50
-
-
-
-
-
bit2
bit1
bit0
PDR5
DDR5
PUL5
15.5.4 Port 5 operations
■
Operation as an output port
❐ A pin becomes an output port if the bit in the DDR5 register corresponding to that pin is set to “1”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ When a pin is used as an output port, it outputs the value of the PDR5 register to external pins.
❐ If data is written to the PDR5 register, the value is stored in the output latch and is output to the pin set as an output port as it is.
❐ Reading the PDR5 register returns the PDR5 register value.
■
Operation as an input port
❐ A pin becomes an input port if the bit in the DDR5 register corresponding to that pin is set to “0”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ If data is written to the PDR5 register, the value is stored in the output latch but is not output to the pin set as an input port.
❐ Reading the PDR5 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the
PDR5 register, the PDR5 register value is returned.
■
Operation as a peripheral function output pin
❐ A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a
peripheral function corresponding to that pin.
❐ The pin value can be read from the PDR5 register even if the peripheral function output is enabled. Therefore, the output value
of a peripheral function can be read by the read operation on the PDR5 register. However, if the read-modify-write (RMW) type
of instruction is used to read the PDR5 register, the PDR5 register value is returned.
■
Operation as a peripheral function input pin
❐ To set a pin as an input port, set the bit in the DDR5 register corresponding to the input pin of a peripheral function to “0”.
❐ Reading the PDR5 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin.
However, if the read-modify-write (RMW) type of instruction is used to read the PDR5 register, the PDR5 register value is returned.
■
Operation at reset
If the CPU is reset, all bits in the DDR5 register are initialized to “0” and port input is enabled.
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PRELIMINARY
MB95610H Series
■
Operation in stop mode and watch mode
❐ If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch
mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR5 register value. The input of that
pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P51/EC0 is
enabled by the external interrupt control register ch. 0 (EIC00) of the external interrupt circuit and the interrupt pin selection circuit
control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked.
❐ If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output
level is maintained.
■
Operation of the pull-up register
Setting the bit in the PUL5 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level,
the pull-up resistor is disconnected regardless of the value of the PUL5 register.
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PRELIMINARY
MB95610H Series
15.6 Port 9
Port 9 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral
functions, refer to their respective chapters in “New 8FX MB95610H Series Hardware Manual”.
15.6.1 Port 9 configuration
Port 9 is made up of the following elements.
■
General-purpose I/O pins/peripheral function I/O pins
■
Port 9 data register (PDR9)
■
Port 9 direction register (DDR9)
15.6.2 Block diagrams of port 9
■
P90/V4 pin
This pin has the following peripheral function:
❐ LCDC drive power supply pin (V4)
■
P91/V3 pin
This pin has the following peripheral function:
❐ LCDC drive power supply pin (V3)
■
P92/V2 pin
This pin has the following peripheral function:
❐ LCDC drive power supply pin (V2)
■
P93/V1 pin
This pin has the following peripheral function:
❐ LCDC drive power supply pin (V1)
■
P94/V0 pin
This pin has the following peripheral function:
❐ LCDC drive power supply pin (V0)
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PRELIMINARY
■
MB95610H Series
Block diagram of P90/V4, P91/V3, P92/V2, P93/V1 and P94/V0
LCD power supply
LCD power supply enable
0
1
PDR9 read
Pin
Internal bus
PDR9
PDR9 write
Executing bit manipulation instruction
DDR9 read
DDR9
DDR9 write
Stop mode, watch mode (SPL = 1)
15.6.3 Port 9 registers
■
Port 9 register functions
Register
abbreviation
PDR9
DDR9
■
Read
Read by read-modify-write
(RMW) instruction
0
Pin state is “L” level.
PDR9 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR9 value is “1”.
As output port, outputs “H” level.
Data
0
Port input enabled
1
Port output enabled
Write
Correspondence between registers and pins for port 9
Correspondence between related register bits and pins
Pin name
PDR9
DDR9
-
-
-
P94
P93
P92
P91
P90
-
-
-
bit4
bit3
bit2
bit1
bit0
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PRELIMINARY
MB95610H Series
15.6.4 Port 9 operations
■
Operation as an output port
❐ A pin becomes an output port if the bit in the DDR9 register corresponding to that pin is set to “1”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ When a pin is used as an output port, it outputs the value of the PDR9 register to external pins.
❐ If data is written to the PDR9 register, the value is stored in the output latch and is output to the pin set as an output port as it is.
❐ Reading the PDR9 register returns the PDR9 register value.
❐ To use a pin shared with the LCDC as an output port, set the bit corresponding to that pin in the VE[4:0] bits in the LCDC enable
register 1 (LCDCE1) to “0”.
■
Operation as an input port
❐ A pin becomes an input port if the bit in the DDR9 register corresponding to that pin is set to “0”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ If data is written to the PDR9 register, the value is stored in the output latch but is not output to the pin set as an input port.
❐ Reading the PDR9 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the
PDR9 register, the PDR9 register value is returned.
❐ To use a pin shared with the LCDC as an input port, set the bit (VE[4:0]) corresponding to that pin in the LCDCE1 register to “0”.
■
Operation at reset
If the CPU is reset, all bits in the DDR9 register are initialized to “0” and port input is enabled.
■
Operation in stop mode and watch mode
❐ If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch
mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR9 register value. The input of that
pin is locked to “L” level and blocked in order to prevent leaks due to input open.
❐ If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output
level is maintained.
■
Operation as an LCDC drive power supply pin
❐ Set the bit in the DDR9 register corresponding to a desired LCDC drive power supply pin to “0”.
❐ Select the LCDC drive power supply pin by setting the bit corresponding to that pin in the VE[4:0] bits in the LCDCE1 register to “1”.
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PRELIMINARY
MB95610H Series
15.7 Port F
Port F is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral
functions, refer to their respective chapters in “New 8FX MB95610H Series Hardware Manual”.
15.7.1 Port F configuration
Port F is made up of the following elements.
❐ General-purpose I/O pins/peripheral function I/O pins
❐ Port F data register (PDRF)
❐ Port F direction register (DDRF)
15.7.2 Block diagrams of port F
■
PF0/X0 pin
This pin has the following peripheral function:
❐ Main clock input oscillation pin (X0)
■
PF1/X1 pin
This pin has the following peripheral function:
❐ Main clock I/O oscillation pin (X1)
■
Block diagram of PF0/X0 and PF1/X1
Hysteresis
0
1
PDRF read
Internal bus
PDRF
Pin
PDRF write
Executing bit manipulation instruction
DDRF read
DDRF
DDRF write
Stop mode, watch mode (SPL = 1)
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PRELIMINARY
■
MB95610H Series
PF2/RST pin
This pin has the following peripheral function:
❐ Reset pin (RST)
■
Block diagram of PF2/RST
Reset input
Reset input enable
Reset output enable
Reset output
Hysteresis
0
1
PDRF read
PDRF
Internal bus
Pin
1
0
OD
PDRF write
Executing bit manipulation instruction
DDRF read
DDRF
DDRF write
Stop mode, watch mode (SPL = 1)
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PRELIMINARY
MB95610H Series
15.7.3 Port F registers
■
Port F register functions
Register
abbreviation
PDRF
DDRF
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDRF value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDRF value is “1”.
As output port, outputs “H” level.*
0
Port input enabled
1
Port output enabled
*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.
■
Correspondence between registers and pins for port F
Correspondence between related register bits and pins
Pin name
PDRF
DDRF
-
-
-
-
-
PF2*
PF1
PF0
-
-
-
-
-
bit2
bit1
bit0
*: PF2/RST is the dedicated reset pin on MB95F613H/F614H/F616H.
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PRELIMINARY
MB95610H Series
15.7.4 Port F operations
■
Operation as an output port
❐ A pin becomes an output port if the bit in the DDRF register corresponding to that pin is set to “1”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ When a pin is used as an output port, it outputs the value of the PDRF register to external pins.
❐ If data is written to the PDRF register, the value is stored in the output latch and is output to the pin set as an output port as it is.
❐ Reading the PDRF register returns the PDRF register value.
■
Operation as an input port
❐ A pin becomes an input port if the bit in the DDRF register corresponding to that pin is set to “0”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ If data is written to the PDRF register, the value is stored in the output latch but is not output to the pin set as an input port.
❐ Reading the PDRF register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the
PDRF register, the PDRF register value is returned.
■
Operation at reset
If the CPU is reset, all bits in the DDRF register are initialized to “0” and port input is enabled.
■
Operation in stop mode and watch mode
❐ If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch
mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRF register value. The input of that
pin is locked to “L” level and blocked in order to prevent leaks due to input open.
❐ If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output
level is maintained.
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PRELIMINARY
MB95610H Series
15.8 Port G
Port G is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral
functions, refer to their respective chapters in “New 8FX MB95610H Series Hardware Manual”.
15.8.1 Port G configuration
Port G is made up of the following elements.
■
General-purpose I/O pins/peripheral function I/O pins
■
Port G data register (PDRG)
■
Port G direction register (DDRG)
■
Port G pull-up register (PULG)
15.8.2 Block diagram of port G
■
PG1/X0A pin
This pin has the following peripheral function:
■
Subclock input oscillation pin (X0A)
■
PG2/X1A pin
This pin has the following peripheral function:
❐ Subclock I/O oscillation pin (X1A)
■
Block diagram of PG1/X0A and PG2/X1A
Hysteresis
0
Pull-up
1
PDRG read
PDRG
Pin
PDRG write
Internal bus
Executing bit manipulation instruction
DDRG read
DDRG
DDRG write
Stop mode, watch mode (SPL = 1)
PULG read
PULG
PULG write
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PRELIMINARY
MB95610H Series
15.8.3 Port G registers
■
Port G register functions
Register
abbreviation
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDRG value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDRG value is “1”.
As output port, outputs “H” level.
PDRG
DDRG
PULG
■
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
Correspondence between registers and pins for port G
Correspondence between related register bits and pins
Pin name
-
-
-
-
-
PG2
PG1
-
-
-
-
-
-
bit2
bit1
-
PDRG
DDRG
PULG
15.8.4 Port G operations
■
Operation as an output port
❐ A pin becomes an output port if the bit in the DDRG register corresponding to that pin is set to “1”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ When a pin is used as an output port, it outputs the value of the PDRG register to external pins.
❐ If data is written to the PDRG register, the value is stored in the output latch and is output to the pin set as an output port as it is.
❐ Reading the PDRG register returns the PDRG register value.
■
Operation as an input port
❐ A pin becomes an input port if the bit in the DDRG register corresponding to that pin is set to “0”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ If data is written to the PDRG register, the value is stored in the output latch but is not output to the pin set as an input port.
❐ Reading the PDRG register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the
PDRG register, the PDRG register value is returned.
■
Operation as a peripheral function input pin
❐ To set a pin as an input port, set the bit in the DDRG register corresponding to the input pin of a peripheral function to “0”.
❐ Reading the PDRG register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin.
However, if the read-modify-write (RMW) type of instruction is used to read the PDRG register, the PDRG register value is returned.
■
Operation at reset
If the CPU is reset, all bits in the DDRG register are initialized to “0” and port input is enabled.
■
Operation in stop mode and watch mode
❐ If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch
mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRG register value. The input of that
pin is locked to “L” level and blocked in order to prevent leaks due to input open.
❐ If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output
level is maintained.
■
Operation of the pull-up register
Setting the bit in the PULG register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level,
the pull-up resistor is disconnected regardless of the value of the PULG register.
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PRELIMINARY
MB95610H Series
16. Interrupt Source Table
Vector table
address
Interrupt level setting
Priority order of
register
interrupt sources of
the same level
(occurring
Register
Bit
simultaneously)
Interrupt
request
number
Upper
Lower
IRQ00
0xFFFA
0xFFFB
ILR0
L00 [1:0]
IRQ01
0xFFF8
0xFFF9
ILR0
L01 [1:0]
IRQ02
0xFFF6
0xFFF7
ILR0
L02 [1:0]
IRQ03
0xFFF4
0xFFF5
ILR0
L03 [1:0]
UART/SIO ch. 0
IRQ04
0xFFF2
0xFFF3
ILR1
L04 [1:0]
8/16-bit composite timer ch. 0 (lower)
IRQ05
0xFFF0
0xFFF1
ILR1
L05 [1:0]
8/16-bit composite timer ch. 0 (upper)
IRQ06
0xFFEE
0xFFEF
ILR1
L06 [1:0]
IRQ07
0xFFEC
0xFFED
ILR1
L07 [1:0]
IRQ08
0xFFEA
0xFFEB
ILR2
L08 [1:0]
IRQ09
0xFFE8
0xFFE9
ILR2
L09 [1:0]
8/16-bit PPG ch. 1 (upper)
IRQ10
0xFFE6
0xFFE7
ILR2
L10 [1:0]
16-bit reload timer ch. 0
IRQ11
0xFFE4
0xFFE5
ILR2
L11 [1:0]
Interrupt source
External interrupt ch. 0
External interrupt ch. 4
External interrupt ch. 1
External interrupt ch. 5
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
—
LCDC
8/16-bit PPG ch. 1 (lower)
UART/SIO ch. 1
8/16-bit PPG ch. 0 (upper)
IRQ12
0xFFE2
0xFFE3
ILR3
L12 [1:0]
8/16-bit PPG ch. 0 (lower)
IRQ13
0xFFE0
0xFFE1
ILR3
L13 [1:0]
8/16-bit composite timer ch. 1 (upper)
IRQ14
0xFFDE
0xFFDF
ILR3
L14 [1:0]
IRQ15
0xFFDC
0xFFDD
ILR3
L15 [1:0]
IRQ16
0xFFDA
0xFFDB
ILR4
L16 [1:0]
IRQ17
0xFFD8
0xFFD9
ILR4
L17 [1:0]
—
I
2C
bus interface ch. 0
—
8/10-bit A/D converter
IRQ18
0xFFD6
0xFFD7
ILR4
L18 [1:0]
Time-base timer
IRQ19
0xFFD4
0xFFD5
ILR4
L19 [1:0]
IRQ20
0xFFD2
0xFFD3
ILR5
L20 [1:0]
Watch prescaler
Watch counter
IRQ21
0xFFD0
0xFFD1
ILR5
L21 [1:0]
8/16-bit composite timer ch. 1 (lower)
—
IRQ22
0xFFCE
0xFFCF
ILR5
L22 [1:0]
Flash memory
IRQ23
0xFFCC
0xFFCD
ILR5
L23 [1:0]
High
Low
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PRELIMINARY
MB95610H Series
17. Pin States in Each Mode
Pin name
Normal
operation
Sleep mode
Oscillation input Oscillation input
PF0/X0
I/O port*
1
I/O
port*1
Oscillation input Oscillation input
PF1/X1
PF2/RST
I/O port*1
I/O port*1
Reset input
Reset input
I/O port*1
I/O port*1
Oscillation input Oscillation input
PG1/X0A
I/O port*1
I/O port*1
Oscillation input Oscillation input
PG2/X1A
I/O port*
1
Stop mode
SPL=0
SPL=1
Hi-Z
Hi-Z
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
1,
2
blocked* *
Hi-Z
Hi-Z
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
1,
2
blocked* *
Reset input
Reset input
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
1,
2
blocked* *
Hi-Z
Hi-Z
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
1,
2
blocked* *
Hi-Z
Hi-Z
Watch mode
SPL=0
SPL=1
Hi-Z
Hi-Z
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
1,
2
blocked* *
Hi-Z
Hi-Z
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
1,
2
blocked* *
Reset input
Reset input
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
1,
2
blocked* *
Hi-Z
Hi-Z
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
1,
2
blocked* *
Hi-Z
Hi-Z
On reset
—
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
—
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
Reset input*4
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
—
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
—
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
1, 2
blocked* *
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1, *2
1, 2
blocked* *
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
I/O port/
peripheral
function I/O/
analog input
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*2, *5
blocked*2, *5
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*2, *5
blocked*2, *5
- Hi-Z
- Input
blocked*2
I/O port/
peripheral
function I/O/
analog input
- Previous state
- Previous state
- Hi-Z
- Hi-Z
- Hi-Z
kept
2 kept
2 - Input
Input
blocked*
Input
blocked*
- Input blocked*2
- Input blocked*2
blocked*2
I/O port*
1
P00/INT00/
AN00
P01/INT01/ I/O port/
AN01
peripheral
P02/INT02/ function I/O/
analog input
AN02
P03/INT03/
AN03
P04/SEG32
P05/SEG33/ I/O port/
ADTG
peripheral
P06/SEG34/ function I/O/
analog input
PPG10
P07/SEG35/
PPG11
(Continued)
Document Number: 002-04698 Rev. *A
Page 70 of 110
PRELIMINARY
Pin name
P12/DBG
Normal
operation
I/O port/
peripheral
function I/O
Sleep mode
I/O port/
peripheral
function I/O
Watch mode
SPL=0
SPL=1
On reset
I/O port/
peripheral
function I/O
- Hi-Z
- Input
- Previous state
- Previous state
enabled*3
- Hi-Z
- Hi-Z
kept
2 kept
2
Input
blocked*
Input
blocked*
(However,
it
- Input blocked*2
- Input blocked*2
does not
function.)
I/O port/
peripheral
function I/O
- Hi-Z
- Input
- Previous state
- Previous state
enabled*3
- Hi-Z*6
- Hi-Z*6
kept
kept
2
2
- Input blocked*
- Input blocked* (However, it
- Input blocked*2
- Input blocked*2
does not
function.)
I/O port/
peripheral
function I/O
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*2, *7
blocked*2, *7
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*2, *7
blocked*2, *7
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
I/O port/
peripheral
function I/O
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*2*5
blocked*2*5
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*2*5
blocked*2*5
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
I/O port/
peripheral
function I/O
- Previous state
- Previous state
- Hi-Z
- Hi-Z
kept
kept
2
- Input blocked*
- Input blocked*2
- Input blocked*2
- Input blocked*2
I/O port/
peripheral
function I/O
- Hi-Z
- Input
- Previous state
- Previous state
enabled*3
- Hi-Z*6
- Hi-Z*6
kept
kept
2
2
- Input blocked*
- Input blocked* (However, it
- Input blocked*2
- Input blocked*2
does not
function.)
P13/UO0
P14/UCK0
Stop mode
SPL=0
SPL=1
MB95610H Series
P15/UI0
P20/SEG44/
TI0
P21/SEG45/
UO1
P22/SEG46/
UCK1
P23/SEG47/
I/O port/
UI1
peripheral
P24/SEG48/ function I/O
PPG00
P25/SEG49/
PPG01
P26/SEG50/
SCL
P27/SEG51/
SDA
P30/SEG36/
INT04
P31/SEG37/
I/O port/
INT05
peripheral
P32/SEG38/ function I/O
INT06
P33/SEG39/
INT07
P34/SEG40/
TO11
P35/SEG41/
I/O port/
TO10
peripheral
P36/SEG42/ function I/O
EC1
P37/SEG43/
TO0
P50/TO01
P51/EC0
I/O port/
peripheral
function I/O
P52/TO00
Document Number: 002-04698 Rev. *A
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
Page 71 of 110
PRELIMINARY
Pin name
P90/V4
P91/V3
P92/V2
P93/V1
Normal
operation
I/O port/
peripheral
function I/O
Sleep mode
I/O port/
peripheral
function I/O
Stop mode
SPL=0
SPL=1
MB95610H Series
Watch mode
SPL=0
SPL=1
On reset
- Previous state
- Previous state
- Hi-Z
- Hi-Z
- Hi-Z
kept
kept
- Input
2
2
- Input blocked*
- Input blocked*
- Input blocked*2
- Input blocked*2
blocked*2
(Continued)
Document Number: 002-04698 Rev. *A
Page 72 of 110
PRELIMINARY
MB95610H Series
(Continued)
Pin name
Stop mode
SPL=0
SPL=1
Watch mode
SPL=0
SPL=1
Normal
operation
Sleep mode
Analog output
Analog output
- Previous state
- Hi-Z
- Previous state
- Hi-Z
- Hi-Z
kept
- Input
kept
2
2
- Input blocked*
- Input blocked*
- Input blocked*2
blocked*2
- Input blocked*2
Analog output
Analog output
- Previous state
- Hi-Z
- Previous state
- Hi-Z
- Hi-Z
kept
- Input
kept
2
2
- Input blocked*
- Input blocked*
- Input blocked*2
blocked*2
- Input blocked*2
On reset
COM0
COM1
COM2
COM3
COM4/
SEG00
COM5/
SEG01
COM6/
SEG02
COM7/
SEG03
SEG04
SEG05
SEG06
SEG07
SEG08
SEG09
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SPL: Pin state setting bit in the standby control register (STBC:SPL)
Hi-Z: High impedance
*1: The pin stays at the state shown when configured as a general-purpose I/O port.
*2: “Input blocked” means direct input gate operation from the pin is disabled.
*3: “Input enabled” means that the input function is enabled. While the input function is enabled, execute a pull-up or pull-down operation to prevent leaks due to external input. If a pin is used as an output port, its pin state is the same as that of other ports.
*4: The PF2/RST pin stays at the state shown when configured as a reset pin.
*5: Though input is blocked, an external interrupt can be input when the external interrupt request is enabled.
*6: The pull-up control setting is still effective.
*7: The I2C bus interface can wake up the MCU in stop mode or watch mode when its MCU standby mode wakeup function is enabled.
Document Number: 002-04698 Rev. *A
Page 73 of 110
PRELIMINARY
MB95610H Series
For details of the MCU standby mode wakeup function, refer to “CHAPTER 23 I2C BUS INTERFACE” in “New 8FX MB95610H
Series Hardware Manual”.
Document Number: 002-04698 Rev. *A
Page 74 of 110
PRELIMINARY
MB95610H Series
18. Electrical Characteristics
18.1 Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS 0.3
VSS 6
V
Input voltage*
VI
VSS 0.3
VSS 6
V
*2
Output voltage*1
VO
VSS 0.3
VSS 6
V
*2
ICLAMP
2
2
mA
Applicable to specific pins*3
|ICLAMP|
—
20
mA
Applicable to specific pins*3
“L” level maximum output
current
IOL
—
15
mA
“L” level average current
IOLAV
—
4
mA
“L” level total maximum output
current
IOL
—
100
mA
“L” level total average output
current
IOLAV
—
50
mA
“H” level maximum output
current
IOH
—
15
mA
“H” level average current
IOHAV
—
4
mA
“H” level total maximum output
current
IOH
—
100
mA
“H” level total average output
current
IOHAV
—
50
mA
Power supply voltage*1
1
Maximum clamp current
Total maximum clamp current
Power consumption
Pd
—
320
mW
Operating temperature
TA
40
85
C
Storage temperature
Tstg
55
150
C
Average output current =
operating current operating ratio (1 pin)
Total average output current =
operating current operating ratio
(Total number of pins)
Average output current =
operating current operating ratio (1 pin)
Total average output current =
operating current operating ratio
(Total number of pins)
(Continued)
Document Number: 002-04698 Rev. *A
Page 75 of 110
PRELIMINARY
MB95610H Series
(Continued)
*1: These parameters are based on the condition that VSS is 0.0 V.
*2: V1 and V0 must not exceed VCC 0.3 V. V1 must not exceed the rated voltage. However, if the maximum current to/from an input
is limited by means of an external component, the ICLAMP rating is used instead of the VI rating
*3: Specific pins: P00 to P07, P12 to P15, P20 to P27, P30 to P37, P50 to P52, P90 to P94
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between the HV
(High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when the HV
(High Voltage) signal is input is below the standard value, irrespective of whether the current is transient current or stationary
current.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage) input potential
may pass through the protective diode to increase the potential of the VCC pin, affecting other devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power is supplied
from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may
not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit:
• Input/Output equivalent circuit
Protective diode
VCC
P-ch
Limiting
resistor
HV(High Voltage) input (0 V to 16 V)
N-ch
R
WARNING:
Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
Document Number: 002-04698 Rev. *A
Page 76 of 110
PRELIMINARY
MB95610H Series
18.2 Recommended Operating Conditions
Parameter
Symbol
Power supply voltage
VCC
Decoupling capacitor
CS
Operating temperature
TA
(VSS = 0.0 V)
Value
Min
Max
2.4*1
5.5
Unit
Remarks
V
In normal operation
2.3
5.5
V
Hold condition in stop mode
0.022
1
µF
*2
40
85
5
35
C
Not in on-chip debug mode
In on-chip debug mode
*1: The minimum power supply voltage becomes 2.88 V when a product with the low-voltage detection reset is used or when the
on-chip debug mode is used.
*2: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The decoupling capacitor for the VCC pin must
have a capacitance equal to or larger than the capacitance of CS. For the connection to a decoupling capacitor CS, see the diagram
below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the C
pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board.
• DBG / RST / C pins connection diagram
*
DBG
C
RST
Cs
*: Connect the DBG pin to an external pull-up resistor of 2 k or above. After power-on, ensure that the
DBG pin does not stay at “L” level until the reset output is released. The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the
interconnection length, refer to the tool document when selecting a pull-up resistor.
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and could result
in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet.
If you are considering application under any conditions other than listed herein, please contact sales representatives
beforehand.
Document Number: 002-04698 Rev. *A
Page 77 of 110
PRELIMINARY
18.3 DC Characteristics
Parameter
“H” level input
voltage
“L” level input
voltage
Open-drain
output
application
voltage
“H” level output
voltage
“L” level output
voltage
MB95610H Series
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 C to 85 °C)
Symbol
Pin name
Condition
VIHI
P15, P23, P26, P27
Value
Unit
Remarks
Min
Typ
Max
—
0.7 VCC
—
VCC 0.3
V
Hysteresis input
VIHS
P00 to P07,
P12 to P14,
P20 to P22,
P24, P25,
P30 to P37,
P50 to P52,
P90 to P94,
PF0 to PF2,
PG1, PG2
—
0.8 VCC
—
VCC 0.3
V
Hysteresis input
VILI
P15, P23, P26, P27
—
VSS 0.3
—
0.3 VCC
V
Hysteresis input
VILS
P00 to P07,
P12 to P14,
P20 to P22,
P24, P25,
P30 to P37,
P50 to P52,
P90 to P94,
PF0 to PF2,
PG1, PG2,
—
VSS 0.3
—
0.2 VCC
V
Hysteresis input
P12, PF2
—
VSS 0.3
—
Vss 5.5
V
VCC 0.5
—
—
V
—
—
0.4
V
VD
VOH
P00 to P07,
P13 to P15,
P20 to P27,
P30 to P37,
P50 to P52,
P90 to P94,
PF0, PF1,
PG1, PG2
IOH = 4 mA
VOL
P00 to P07,
P12 to P15,
P20 to P27,
P30 to P37,
P50 to P52,
P90 to P94,
PF0 to PF2,
PG1, PG2
IOL = 4 mA
(Continued)
Document Number: 002-04698 Rev. *A
Page 78 of 110
PRELIMINARY
MB95610H Series
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 C to 85 °C)
Parameter
Input leak
current (Hi-Z
output leak
current)
Internal
pull-up resistor
Input
capacitance
Symbol
Pin name
Condition
Value
Min
Typ
Max
Unit
Remarks
ILI
P00 to P07,
P12 to P15,
P20 to P27,
P30 to P37,
P50 to P52,
P90 to P94,
PF0 to PF2
PG1, PG2
0.0 V < VI < VCC
5
—
5
µA
When the internal
pull-up resistor is
disabled
RPULL
P13 to P15,
P50 to P52,
PG1, PG2*1
VI = 0 V
25
50
100
k
When the internal
pull-up resistor is
enabled
Other than VCC
and VSS
f = 1 MHz
—
5
15
pF
—
4.5
5.8
mA
Except during Flash
memory programming
and erasing
—
10.0
13.8
mA
During Flash memory
programming and
erasing
At A/D conversion
CIN
ICC
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
—
6.3
9.1
mA
ICCS
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
—
2.0
3.0
mA
FCL = 32 kHz
FMPL = 16 kHz
Subclock mode
(divided by 2)
TA = 25 °C
—
60
100
µA
FCL = 32 kHz
FMPL = 16 kHz
Subsleep mode
(divided by 2)
TA = 25 °C
—
10
15
µA
FCL = 32 kHz
Watch mode
Main stop mode
TA = 25 °C
—
8
13
µA
Power supply
current*1
ICCL
VCC
(External clock
operation)
ICCLS*2
2
ICCT*
(Continued)
Document Number: 002-04698 Rev. *A
Page 79 of 110
PRELIMINARY
MB95610H Series
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 C to 85 °C)
Parameter
Symbol
Pin name
Value
Unit
Min
Typ
Max
FMCRPLL = 16 MHz
FMP = 16 MHz
Main CR PLL clock
mode
(multiplied by 4)
TA = 25 °C
—
5.5
6.8
mA
ICCMCR
FCRH = 4 MHz
FMP = 4 MHz
Main CR clock mode
—
1.4
2.0
mA
ICCSCR
Sub-CR clock mode
(divided by 2)
TA = 25 °C
—
70
150
µA
ICCTS
FCH = 32 MHz
Time-base timer mode
TA = 25 °C
—
360
410
µA
Substop mode
TA = 25 °C
—
7
11
µA
ICCMPLL
VCC
Power supply
current*1
Condition
ICCH
VCC
(External clock
operation)
ILVD
Current consumption
of the low-voltage
detection reset circuit
—
4
7
µA
ICRH
Current consumption
of the main CR
oscillator
—
240
320
µA
Current consumption
of the sub-CR
oscillator oscillating at
100 kHz
—
7
20
µA
Current consumption
difference between
normal standby mode
and deep standby
mode
TA = 25 °C
—
20
30
µA
ICRL
VCC
INSTBY
Remarks
The low-voltage
detection reset circuit
operates only in
on-chip debug mode.
(Continued)
Document Number: 002-04698 Rev. *A
Page 80 of 110
PRELIMINARY
(Continued)
Parameter
LCD internal
division
resistance
MB95610H Series
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 C to 85 °C)
Symbol
RLCD
Pin name
—
COM0 to COM7
output
impedance
RVCOM
SEG00 to
SEG51 output
impedance
RVSEG
SEG00 to SEG51
LCD leakage
current
ILCDL
V0 to V4, COM0 to
COM7, SEG00 to
SEG51
Condition
Between V4 and VSS
COM0 to COM7
Value
Unit
Remarks
—
k
1/2 bias, 10 k resistor
200
—
k
1/2 bias, 100 k
resistor
—
40
—
k
1/4 bias, 10 k resistor
—
400
—
k
1/4 bias, 100 k
resistor
—
—
5
k
—
—
7
k
1
—
1
k
Min
Typ
Max
—
20
—
V1 to V4 = 4.1 V
—
*1: • The power supply current is determined by the external clock. When the low-voltage detection reset circuit is selected, the power
supply current is the sum of adding the current consumption of the low-voltage detection reset circuit (ILVD) to one of the values
from ICC to ICCH. When both the low-voltage detection reset circuit and a CR oscillator are selected, the power supply current
is the sum of adding up the current consumption of the low-voltage detection reset circuit (ILVD), the current consumption of the
CR oscillator (ICRH or ICRL) and one of the values from ICC to ICCH. In on-chip debug mode, the main CR oscillator (ICRH) and
the low-voltage detection reset circuit are always in operation, and current consumption therefore increases accordingly.
• See “4. AC Characteristics (1) Clock Timing” for FCH, FCL, FCRH and FMCRPLL.
• See “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.
• The power supply current value in standby mode is measured in deep standby mode. The current consumption in normal standby is higher than that in deep standby mode. The power supply current value in normal standby can be found by adding the
current consumption difference between normal standby mode and deep standby mode (INSTBY) to the power supply current
value in deep standby mode. For details of normal standby and deep standby mode, refer to “CHAPTER 3 CLOCK CONTROLLER” in “New 8FX MB95610H Series Hardware Manual”.
*2: In sub-CR clock mode, the power supply current is the sum of adding ICCLS or ICCT to ICRH.
Document Number: 002-04698 Rev. *A
Page 81 of 110
PRELIMINARY
MB95610H Series
18.4 AC Characteristics
18.4.1 Clock Timing
Parameter
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C)
Symbol
Pin name
X0, X1
X0
Condition
—
X1: open
X0, X1
*
FCH
X0, X1
—
Unit
Remarks
Min
Typ
Max
1
—
16.25
MHz
1
—
12
MHz
1
—
32.5
MHz
4
—
8.13
Operating conditions
MHz • The main clock is used.
• PLL multiplication rate: 2
4
—
6.5
Operating conditions
MHz • The main clock is used.
• PLL multiplication rate: 2.5
4
—
5.41
Operating conditions
MHz • The main clock is used.
• PLL multiplication rate: 3
4
—
4.06
Operating conditions
MHz • The main clock is used.
• PLL multiplication rate: 4
3.92
4
4.08
Operating conditions
MHz • The main CR clock is used.
• 0 C TA 70 C
4.1
Operating conditions
• The main CR clock is used.
MHz
• 40 C TA 0 C,
70 C TA 85 C
—
Clock frequency
FCRH
Value
—
3.9
4
When the main oscillation circuit is
used
When the main external clock is used
(Continued)
Document Number: 002-04698 Rev. *A
Page 82 of 110
PRELIMINARY
MB95610H Series
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C)
Parameter
Symbol
FMCRPLL
Pin name
—
Condition
Value
FCRL
X0A, X1A
Max
7.84
8
8.16
Operating conditions
MHz • PLL multiplication rate: 2
• 0 C TA 70 C
7.6
8
8.4
Operating conditions
• PLL multiplication rate: 2
MHz
• 40 C TA 0 C,
70 C TA 85 C
9.8
10
10.2
Operating conditions
MHz • PLL multiplication rate: 2.5
• 0 C TA 70 C
9.5
10
10.5
Operating conditions
• PLL multiplication rate: 2.5
MHz
• 40 C TA 0 C,
70 C TA 85 C
11.76
12
12.24
Operating conditions
MHz • PLL multiplication rate: 3
• 0 C TA 70 C
—
—
—
—
Remarks
Typ
Clock frequency
FCL
Unit
Min
11.4
12
12.6
Operating conditions
• PLL multiplication rate: 3
MHz
• 40 C TA 0 C,
70 C TA 85 C
15.68
16
16.32
Operating conditions
MHz • PLL multiplication rate: 4
• 0 C TA 70 C
Operating conditions
• PLL multiplication rate: 4
MHz
• 40 C TA 0 C,
70 C TA 85 C
15.2
16
16.8
—
32.768
—
kHz
When the suboscillation circuit is
used
—
32.768
—
kHz
When the sub-external clock is used
50
100
150
kHz
When the sub-CR clock is used
(Continued)
Document Number: 002-04698 Rev. *A
Page 83 of 110
PRELIMINARY
(Continued)
Parameter
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C)
Symbol
Pin name
X0, X1
Clock cycle time
Input clock
pulse width
Input clock
rising time and
falling time
MB95610H Series
tHCYL
X0
Condition
—
X1: open
Value
Unit
Remarks
1000
ns
When the main oscillation circuit
is used
—
1000
ns
Min
Typ
Max
61.5
—
83.4
X0, X1
*
30.8
—
1000
ns
tLCYL
X0A, X1A
—
—
30.5
—
µs
tWH1,
tWL1
X0
tWH2,
tWL2
tCR,
tCF
X1: open
X0, X1
X0A
X0, X0A
X0, X1,
X0A, X1A
33.4
—
—
ns
*
14.4
15.2
—
ns
—
—
30.5
—
µs
—
—
5
ns
*
—
—
5
ns
X1: open
When an external clock is used
When the subclock is used
When an external clock is used,
the duty ratio should range
between 40% and 60%.
When an external clock is used
CR oscillation
start time
tCRHWK
—
—
—
—
50
µs
tCRLWK
—
—
—
—
30
µs
When the sub-CR clock is used
PLL oscillation
start time
tMCRPLLW
µs
When the main CR PLL clock is
used
K
—
—
—
—
100
When the main CR clock is used
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
Document Number: 002-04698 Rev. *A
Page 84 of 110
PRELIMINARY
MB95610H Series
• Input waveform generated when an external clock (main clock) is used
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0, X1
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0
When an external clock is used When an external clock
(X1 is open)
is used
X0
X1
X1
X0
X1
Open
FCH
FCH
FCH
• Input waveform generated when an external clock (subclock) is used
tLCYL
tWH2
tCR
tWL2
tCF
0.8 VCC 0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0A
X1A
FCL
When an external clock
is used
X0A
X1A
Open
FCL
Document Number: 002-04698 Rev. *A
Page 85 of 110
PRELIMINARY
MB95610H Series
• Input waveform generated when an internal clock (main CR clock) is used
tCRHWK
1/FCRH
Main CR clock
Oscillation starts
Document Number: 002-04698 Rev. *A
Oscillation stabilizes
Page 86 of 110
PRELIMINARY
MB95610H Series
• Input waveform generated when an internal clock (sub-CR clock) is used
tCRLWK
1/FCRL
Sub-CR clock
Oscillation starts
Oscillation stabilizes
• Input waveform generated when an internal clock (main CR PLL clock) is used
1/FMCRPLL
tMCRPLLWK
Main CR PLL clock
Oscillation starts
Document Number: 002-04698 Rev. *A
Oscillation stabilizes
Page 87 of 110
PRELIMINARY
18.4.2 Source Clock/Machine Clock
Parameter
Source clock
cycle time*1
Symbol
tSCLK
Pin
name
—
FSP
Source clock
frequency
Machine clock
cycle time*2
(minimum
instruction
execution time)
—
FSPL
tMCLK
Machine clock
frequency
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Value
Unit
—
FMPL
Remarks
Min
Typ
Max
61.5
—
2000
ns
When the main external clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
62.5
—
1000
ns
When the main CR clock is used
Min: FCRH = 4 MHz, multiplied by 4
Max: FCRH = 4 MHz, divided by 4
—
61
—
µs
When the suboscillation clock is used
FCL = 32.768 kHz, divided by 2
—
20
—
µs
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
0.5
—
16.25
MHz When the main oscillation clock is used
—
4
12.5
MHz When the main CR clock is used
—
16.384
—
kHz When the suboscillation clock is used
—
50
—
kHz
61.5
—
32000
ns
When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
250
—
4000
ns
When the main CR clock is used
Min: FSP = 4 MHz, no division
Max: FSP = 4 MHz, divided by 16
61
—
976.5
µs
When the suboscillation clock is used
Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
20
—
320
µs
When the sub-CR clock is used
Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
0.031
—
16.25
0.25
—
16
1.024
—
16.384
3.125
—
50
—
FMP
MB95610H Series
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
MHz When the main oscillation clock is used
MHz When the main CR clock is used
kHz When the suboscillation clock is used
kHz
When the sub-CR clock is used
FCRL = 100 kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits
(SYCC:DIV[1:0]). This source clock is divided to become a machine clock according to the division ratio set by the machine clock
division ratio select bits (SYCC:DIV[1:0]). In addition, a source clock can be selected from the following.
• Main clock divided by 2
• Main CR clock
• PLL multiplication of main clock or main CR clock (Select a multiplication rate from 2, 2.5, 3 and 4.)
• Subclock divided by 2
• Sub-CR clock divided by 2
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
Document Number: 002-04698 Rev. *A
Page 88 of 110
PRELIMINARY
MB95610H Series
• Schematic diagram of the clock generation block
FCH
(Main oscillation clock)
Divided by 2
FMCRPLL
(Main PLL clock,
main CR PLL clock)
SCLK
(Source clock)
FCRH
(Main CR clock)
FCL
(Suboscillation clock)
Division circuit
×
1
× 1/4
× 1/8
× 1/16
MCLK
(Machine clock)
Divided by 2
Machine clock divide ratio select bits
(SYCC:DIV[1:0])
FCRL
(Sub-CR clock)
Divided by 2
Clock mode select bits
(SYCC:SCS[2:0])
• Operating voltage - Operating frequency (TA = 40 °C to 85 °C)
5.5
Operating voltage (V)
5.0
A/D converter operation range
4.0
3.5
3.0
2.7
2.4
16 kHz
3 MHz
10 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
Document Number: 002-04698 Rev. *A
Page 89 of 110
PRELIMINARY
18.4.3 External Reset
Parameter
MB95610H Series
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Symbol
RST “L” level
pulse width
tRSTL
Value
Min
Max
2 tMCLK*
—
Unit
Remarks
ns
*: See “Source Clock/Machine Clock” for tMCLK.
tRSTL
RST
0.2 VCC
Document Number: 002-04698 Rev. *A
0.2 VCC
Page 90 of 110
PRELIMINARY
MB95610H Series
18.4.4 Power-on Reset
Parameter
(VSS = 0.0 V, TA = 40 °C to 85 °C)
Symbol
Condition
Power supply rising time
tR
Power supply cutoff time
tOFF
Value
Unit
Min
Max
50
ms
1
ms
Remarks
Wait time until power-on
tOFF
tR
2.5 V
0.2 V
VCC
0.2 V
0.2 V
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage
during the operation, set the slope of rising to a value below within 30 mV/ms as shown below.
VCC
Set the slope of rising to
a value below 30 mV/ms.
2.3 V
Hold condition in stop mode
VSS
18.4.5 Peripheral Input Timing
Parameter
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Symbol
Peripheral input “H” pulse width
tILIH
Peripheral input “L” pulse width
tIHIL
Value
Pin name
INT00 to INT07, EC0, EC1, ADTG, TI0
Unit
Min
Max
2 tMCLK*
ns
2 tMCLK*
ns
*: See “Source Clock/Machine Clock” for tMCLK.
tILIH
INT00 to INT07,
EC0, EC1, ADTG,
TI0
Document Number: 002-04698 Rev. *A
0.8 VCC
tIHIL
0.8 VCC
0.2 VCC
0.2 VCC
Page 91 of 110
PRELIMINARY
MB95610H Series
18.4.6 Low-voltage Detection
Parameter
Release voltage*
Detection voltage*
(VSS = 0.0 V, TA = 40 °C to 85 °C)
Symbol
VDL
VDL
Value
Min
Typ
Max
2.52
2.7
2.88
2.61
2.8
2.99
2.89
3.1
3.31
3.08
3.3
3.52
2.43
2.6
2.77
2.52
2.7
2.88
2.80
3
3.20
2.99
3.2
3.41
Unit
V
At power supply rise
V
At power supply fall
VHYS
—
—
100
mV
Power supply start voltage
Voff
—
—
2.3
V
Power supply end voltage
Hysteresis width
Remarks
Von
4.9
—
—
V
Power supply voltage change
time
(at power supply rise)
tr
650
—
—
µs
Slope of power supply that the reset release
signal generates within the rating (VDL+)
Power supply voltage change
time
(at power supply fall)
tf
650
—
—
µs
Slope of power supply that the reset release
signal generates within the rating (VDL-)
Reset release delay time
td1
—
—
30
µs
Reset detection delay time
td2
—
—
30
µs
LVD reset threshold voltage
transition stabilization time
tstb
10
—
—
µs
*: The release voltage and the detection voltage can be selected by using the LVD reset voltage selection ID register (LVDR) in the
low-voltage detection reset circuit. For details of the LVDR register, refer to “CHAPTER 16 LOW-VOLTAGE DETECTION RESET
CIRCUIT” in “New 8FX MB95610H Series Hardware Manual”.
(Continued)
Document Number: 002-04698 Rev. *A
Page 92 of 110
PRELIMINARY
MB95610H Series
(Continued)
VCC
Von
Voff
time
tf
tr
VDL+
VHYS
VDL-
Internal reset signal
time
td2
Document Number: 002-04698 Rev. *A
td1
Page 93 of 110
PRELIMINARY
18.4.7 I2C Bus Interface Timing
MB95610H Series
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Value
Parameter
SCL clock frequency
(Repeated) START condition hold time
SDA SCL
Symbol
fSCL
tHD;STA
Pin name
Condition
Standard-mod
e
Fast-mode
Unit
Min
Max
Min
Max
0
100
0
400
kHz
SCL, SDA
4.0
—
0.6
—
µs
SCL
SCL clock “L” width
tLOW
SCL
4.7
—
1.3
—
µs
SCL clock “H” width
tHIGH
SCL
4.0
—
0.6
—
µs
4.7
—
0.6
—
µs
0
3.45*2
0
0.9*3
µs
(Repeated) START condition setup time
SCL SDA
tSU;STA
SCL, SDA
Data hold time
SCL SDA
tHD;DAT
SCL, SDA
Data setup time
SDA SCL
tSU;DAT
SCL, SDA
0.25
—
0.1
—
µs
STOP condition setup time
SCL SDA
tSU;STO
SCL, SDA
4
—
0.6
—
µs
tBUF
SCL, SDA
4.7
—
1.3
—
µs
Bus free time between STOP condition and
START condition
R = 1.7 k,
C = 50 pF*1
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
*2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding the SCL signal
at “L” (tLOW) does not extend.
*3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition of tSU;DAT 250 ns is
fulfilled.
Document Number: 002-04698 Rev. *A
Page 94 of 110
PRELIMINARY
MB95610H Series
tWAKEUP
SDA
tLOW
tHD;DAT
tHD;STA
tHIGH
tBUF
SCL
tHD;STA
tSU;DAT
fSCL
tSU;STO
tSU;STA
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Parameter
Pin
Symbol name
Condition
Value*2
Min
Max
Unit
Remarks
SCL clock “L”
width
tLOW
SCL
(2 nm/2)tMCLK 20
—
ns
Master mode
SCL clock “H”
width
tHIGH
SCL
(nm/2)tMCLK 20
(nm/2)tMCLK 20
ns
Master mode
START
condition hold
time
tHD;STA
SCL,
SDA
(-1 nm/2)tMCLK 20
(-1 nm)tMCLK 20
ns
Master mode
Maximum value is applied when
m, n = 1, 8.
Otherwise, the minimum value is
applied.
STOP condition
setup time
tSU;STO
SCL,
SDA
(1 nm/2)tMCLK 20
(1 nm/2)tMCLK 20
ns
Master mode
START
condition setup
time
tSU;STA
SCL,
SDA
(1 nm/2)tMCLK 20
(1 nm/2)tMCLK 20
ns
Master mode
Bus free time
between STOP
condition and
START
condition
tBUF
SCL,
SDA
(2 nm 4) tMCLK 20
—
ns
Data hold time
tHD;DAT
SCL,
SDA
3 tMCLK 20
—
ns
Master mode
ns
Master mode
It is assumed that “L” of SCL is
not extended. The minimum
value is applied to the first bit of
continuous data. Otherwise, the
maximum value is applied.
Data setup time
tSU;DAT
R = 1.7 k,
C = 50 pF*1
SCL,
SDA
(-2 nm/2) tMCLK 20
(-1 nm/2) tMCLK 20
Setup time
between
clearing
interrupt and
SCL rising
tSU;INT
SCL
(nm/2) tMCLK 20
(1 nm/2) tMCLK 20
ns
The minimum value is applied to
the interrupt at the ninth SCL.
The maximum value is applied to
the interrupt at the eighth SCL.
SCL clock “L”
width
tLOW
SCL
4 tMCLK 20
—
ns
At reception
SCL clock “H”
width
tHIGH
SCL
4 tMCLK 20
—
ns
At reception
Document Number: 002-04698 Rev. *A
Page 95 of 110
PRELIMINARY
(Continued)
Parameter
MB95610H Series
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Symbol
Pin
name
Condition
Value*2
Min
Max
Unit
Remarks
START condition
detection
tHD;STA
SCL,
SDA
2 tMCLK 20
—
ns
No START condition is detected
when 1 tMCLK is used at reception.
STOP condition
detection
tSU;STO
SCL,
SDA
2 tMCLK 20
—
ns
No STOP condition is detected when
1 tMCLK is used at reception.
RESTART condition
detection condition
tSU;STA
SCL,
SDA
2 tMCLK 20
—
ns
No RESTART condition is detected
when 1 tMCLK is used at reception.
Bus free time
tBUF
SCL,
SDA
2 tMCLK 20
—
ns
At reception
Data hold time
tHD;DAT
SCL,
SDA
2 tMCLK 20
—
ns
At slave transmission mode
Data setup time
tSU;DAT
SCL,
SDA
tLOW 3 tMCLK 20
—
ns
At slave transmission mode
Data hold time
tHD;DAT
SCL,
SDA
0
—
ns
At reception
Data setup time
tSU;DAT
SCL,
SDA
tMCLK 20
—
ns
At reception
SDA SCL
(with wakeup function
in use)
tWAKEUP
SCL,
SDA
Oscillation stabilization wait
time
2 tMCLK 20
—
ns
R = 1.7 k,
C = 50 pF*1
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
*2: • See “(2) Source Clock/Machine Clock” for tMCLK.
• m represents the CS[4:3] bits in the I2C clock control register ch. 0 (ICCR0).
• n represents the CS[2:0] bits in the I2C clock control register ch. 0 (ICCR0).
• The actual timing of the I2C bus interface is determined by the values of m and n set by the machine clock (tMCLK) and the
CS[4:0] bits in the ICCR0 register.
• Standard-mode:
m and n can be set to values in the following range: 0.9 MHz tMCLK (machine clock) 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK 1 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4)
: 0.9 MHz < tMCLK 2 MHz
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8)
: 0.9 MHz < tMCLK 4 MHz
(m, n) = (1, 98), (5, 22), (6, 22), (7, 22)
: 0.9 MHz < tMCLK 10 MHz
(m, n) = (8, 22)
: 0.9 MHz < tMCLK 16.25 MHz
• Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK 4 MHz
(m, n) = (1, 22), (5, 4)
: 3.3 MHz < tMCLK 8 MHz
(m, n) = (1, 38), (6, 4), (7, 4), (8, 4)
: 3.3 MHz < tMCLK 10 MHz
(m, n) = (5, 8)
: 3.3 MHz < tMCLK 16.25 MHz
Document Number: 002-04698 Rev. *A
Page 96 of 110
PRELIMINARY
18.4.8 UART/SIO, Serial I/O Timing
Parameter
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Symbol
Serial clock cycle time
UCK UO time
MB95610H Series
Pin name
Value
Condition
tSCYC
UCK0, UCK1
tSLOV
UCK0, UCK1, UO0,
UO1
Internal clock operation:
CL = 80 pF + 1 TTL
Unit
Min
Max
4 tMCLK*
—
ns
190
190
ns
2 tMCLK*
—
ns
Valid UI UCK
tIVSH
UCK0, UCK1, UI0,
UI1
UCK valid UI hold time
tSHIX
UCK0, UCK1, UI0,
UI1
2 tMCLK*
—
ns
Serial clock “H” pulse width
tSHSL
UCK0, UCK1
4 tMCLK*
—
ns
Serial clock “L” pulse width
tSLSH
UCK0, UCK1
4 tMCLK*
—
ns
UCK UO time
tSLOV
UCK0, UCK1, UO0,
UO1
—
190
ns
Valid UI UCK
tIVSH
UCK0, UCK1, UI0,
UI1
2 tMCLK*
—
ns
UCK valid UI hold time
tSHIX
UCK0, UCK1, UI0,
UI1
2 tMCLK*
—
ns
External clock operation:
CL = 80 pF + 1 TTL
*: See “Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
UCK0,
UCK1
tSCYC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
UO0,
UO1
0.8 VCC
0.2 VCC
tIVSH
UI0,
UI1
Document Number: 002-04698 Rev. *A
tSHIX
0.7 VCC 0.7 VCC
0.3 VCC 0.3 VCC
Page 97 of 110
PRELIMINARY
MB95610H Series
• External shift clock mode
tSLSH
UCK0,
UCK1
tSHSL
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLOV
UO0,
UO1
0.8 VCC
0.2 VCC
tIVSH
UI0,
UI1
Document Number: 002-04698 Rev. *A
tSHIX
0.7 VCC 0.7 VCC
0.3 VCC 0.3 VCC
Page 98 of 110
PRELIMINARY
MB95610H Series
18.5 A/D Converter
18.5.1 A/D Converter Electrical Characteristics
Parameter
Value
Symbol
Resolution
Total error
Linearity error
(VCC = 2.7 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C)
—
Differential linearity error
Unit
Min
Typ
Max
—
—
10
bit
3
—
3
LSB
2.5
—
2.5
LSB
1.9
—
1.9
LSB
Remarks
Zero transition
voltage
V0T
VSS 7.2 LSB
VSS 0.5 LSB
VSS 8.2 LSB
V
Full-scale transition
voltage
VFST
VCC 6.2 LSB
VCC 1.5 LSB
VCC 9.2 LSB
V
—
3
—
10
µs
2.7 V VCC 5.5 V
2.7 V VCC 5.5 V,
with external impedance
3.3 k and external
capacitance = 10 pF
Compare time
—
0.941
—
µs
Analog input current
IAIN
0.3
—
0.3
µA
Analog input voltage
VAIN
VSS
—
VCC
V
Sampling time
Document Number: 002-04698 Rev. *A
Page 99 of 110
PRELIMINARY
MB95610H Series
18.5.2 Notes on Using A/D Converter
■
External impedance of analog input and its sampling time
The A/D converter of the MB95610H Series has a sample and hold circuit. If the external impedance is too high to keep sufficient
sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, considering the relationship between the
external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the external
impedance so that the sampling time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured,
connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling: ON
VCC
R
C
4.5 V ≤ VCC ≤ 5.5 V
1.45 kΩ (Max)
14.89 pF (Max)
2.7 V ≤ VCC < 4.5 V
2.7 kΩ (Max)
14.89 pF (Max)
Note: The values are reference values.
Document Number: 002-04698 Rev. *A
Page 100 of 110
PRELIMINARY
MB95610H Series
• Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 100 kΩ]
100
External impedance [kΩ]
80
60
40
20
0
0
2
4
6
8
10
12
14
16
18
20
Minimum sampling time [μs]
[External impedance = 0 kΩ to 20 kΩ]
External impedance [kΩ]
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Minimum sampling time [μs]
Note: External capacitance = 10 pF
■
A/D conversion error
As |VCC VSS| decreases, the A/D conversion error increases proportionately.
Document Number: 002-04698 Rev. *A
Page 101 of 110
PRELIMINARY
MB95610H Series
18.5.3 Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (“0000000000”
“0000000001”) of a device to the full-scale transition point (“1111111111” “1111111110”) of the same device.
• Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero transition error, a
full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
Total error
VFST
0x3FF
0x3FF
2 LSB
0x3FD
Digital output
Digital output
0x004
0x003
Actual conversion
characteristic
0x3FE
0x3FE
0x3FD
V0T
{1 LSB × (N - 1) + 0.5 LSB}
0x004
VNT
0x003
1 LSB
0x002
0x002
0x001
Actual conversion
characteristic
Ideal characteristic
0x001
0.5 LSB
VSS
Analog input
1 LSB =
VCC
VCC - VSS
(V)
1024
N
VSS
Analog input
Total error of digital output N =
VCC
VNT - {1 LSB × (N - 1) + 0.5 LSB}
[LSB]
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from 0x(N - 1) to 0xN
(Continued)
Document Number: 002-04698 Rev. *A
Page 102 of 110
PRELIMINARY
MB95610H Series
(Continued)
Zero transition error
Full-scale transition error
0x004
Ideal characteristic
Actual conversion
characteristic
0x3FF
Actual conversion
characteristic
0x002
Ideal
characteristic
Digital output
Digital output
0x003
Actual conversion
characteristic
0x3FE
VFST
(measurement
value)
0x3FD
Actual conversion
characteristic
0x001
0x3FC
V0T (measurement value)
VSS
Analog input
VCC
VSS
Linearity error
0x3FF
0x3FE
Ideal characteristic
0x(N+1)
Actual conversion
characteristic
{1 LSB × N + V0T}
VFST
Digital output
Digital output
0x3FD
(measurement
value)
VNT
0x004
0x002
VCC
Differential linearity error
Actual conversion
characteristic
Actual conversion
characteristic
0x003
Analog input
V(N+1)T
0xN
VNT
0x(N-1)
Ideal
characteristic
Actual conversion
characteristic
0x(N-2)
0x001
V0T (measurement value)
VSS
Analog input
VCC
Linearity error of digital output N =
VSS
VCC
VNT - {1 LSB × N + V0T}
1 LSB
Differential linearity error of digital output N =
N
Analog input
V(N+1)T - VNT
- 1
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from 0x(N - 1) to 0xN
V0T (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC - 2 LSB [V]
Document Number: 002-04698 Rev. *A
Page 103 of 110
PRELIMINARY
MB95610H Series
18.6 Flash Memory Program/Erase Characteristics
Parameter
Value
Unit
Remarks
Min
Typ
Max
Sector erase time
(2 Kbyte sector)
—
0.3*1
1.6*2
s
The time of writing “0x00” prior to erasure is excluded.
Sector erase time
(32 Kbyte sector)
—
0.6*1
3.1*2
s
The time of writing “0x00” prior to erasure is excluded.
Byte writing time
—
17
272
µs
System-level overhead is excluded.
100000
—
—
cycle
2.4
—
5.5
V
20*3
—
—
10*3
—
—
5*3
—
—
Program/erase cycle
Power supply voltage at
program/erase
Flash memory data
retention time
Average TA = 85 °C
Number of program/erase cycles: 1000 or below
year
Average TA = 85 °C
Number of program/erase cycles: 1001 to 10000 inclusive
Average TA = 85 °C
Number of program/erase cycles: 10001 or above
*1: VCC = 5.5 V, TA = 25 °C, 0 cycle
*2: VCC = 2.4 V, TA = 85 °C, 100000 cycles
*3: These values were converted from the result of a technology reliability assessment. (These values were converted from the result
of a high temperature accelerated test using the Arrhenius equation with the average temperature being 85 °C.)
Document Number: 002-04698 Rev. *A
Page 104 of 110
PRELIMINARY
MB95610H Series
19. MASK Options
Part number
No.
MB95F613H
MB95F614H
MB95F616H
Selectable/Fixed
MB95F613K
MB95F614K
MB95F616K
Fixed
1
Low-voltage detection reset
Without low-voltage detection reset
With low-voltage detection reset
2
Reset
With dedicated reset input
Without dedicated reset input
Document Number: 002-04698 Rev. *A
Page 105 of 110
PRELIMINARY
MB95610H Series
20. Ordering Information
Part number
MB95F613HPMC-G-SNE2
MB95F613KPMC-G-SNE2
MB95F614HPMC-G-SNE2
MB95F614KPMC-G-SNE2
MB95F616HPMC-G-SNE2
MB95F616KPMC-G-SNE2
Document Number: 002-04698 Rev. *A
Package
80-pin plastic LQFP
(FPT-80P-M37)
Page 106 of 110
PRELIMINARY
MB95610H Series
21. Package Dimension
80-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
(FPT-80P-M37)
80-pin plastic LQFP
(FPT-80P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
0.145±0.055
(.006±.002)
*12.00±0.10(.472±.004)SQ
60
41
Details of "A" part
61
40
+0.20
1.50 –0.10
(Mounting height)
+.008
.059 –.004
0.25(.010)
0~8°
0.08(.003)
INDEX
80
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
(Stand off)
21
"A"
1
20
0.50(.020)
C
0.22±0.05
(.009±.002)
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2
Document Number: 002-04698 Rev. *A
0.08(.003)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Page 107 of 110
PRELIMINARY
MB95610H Series
22. Major Changes
Spansion Publication Number: DS702–00017–0v02-E.
Page
19
Section
Pin Connection
• DBG pin
Details
Revised details of “• DBG pin”.
• RST pin
Revised details of “• RST pin”.
20
• C pin
Corrected the following statement.
The decoupling capacitor for the VCC pin must have a capacitance
larger than CS.
The decoupling capacitor for the VCC pin must have a capacitance
equal to or larger than the capacitance of CS.
75
Electrical Characteristics
Recommended Operating Conditions
Revised remark *1.
The minimum value becomes 2.88 V when the low-voltage
detection reset is used or in on-chip debug mode.
The minimum power supply voltage becomes 2.88 V when a
product with the low-voltage detection reset is used or when the
on-chip debug mode is used.
Corrected the following statement in remark *2.
The decoupling capacitor for the VCC pin must have a capacitance
larger than CS.
The decoupling capacitor for the VCC pin must have a capacitance
equal to or larger than the capacitance of CS.
Revised the remark in “• DBG/RST/C pins connection diagram”.
77
DC Characteristics
Revised the remark of the parameter “Input leak current (Hi-Z
output leak current)”.
When pull-up resistance is disabled
When the internal pull-up resistor is disabled
Rename the parameter “Pull-up resistance” to “Internal pull-up
resistor”.
Revised the remark of the parameter “Internal pull-up resistor”.
When pull-up resistance is enabled
When the internal pull-up resistor is enabled
82
AC Characteristics
Clock Timing
Corrected the pin names of the parameter “Input clock rising time
and falling time”.
X0 X0, X0A
X0, X1 X0, X1, X0A, X1A
NOTE: Please see “Document History” about later revised information.
Document Number: 002-04698 Rev. *A
Page 108 of 110
PRELIMINARY
MB95610H Series
Document History
Document Title: MB95F613H/F613K/F614H, MB95F614K/F616H/F616K New 8FX MB95610H Series 8-bit Microcontrollers
Document Number: 002-04698
Revision
ECN
**
*A
5211405
Orig. of
Change
Submission
Date
AKIH
06/14/2013
Migrated to Cypress and assigned document number 002-04698.
No change to document contents or format.
AKIH
04/08/2016
Updated to Cypress template
Document Number: 002-04698 Rev. *A
Description of Change
Page 109 of 110
PRELIMINARY
MB95610H Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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cypress.com/powerpsoc
cypress.com/memory
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Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
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© Cypress Semiconductor Corporation, 2012-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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Document Number: 002-04698 Rev. *A
Revised April 8, 2016
Page 110 of 110