STMicroelectronics L4988D Low drop voltage regulator Datasheet

L4988
Low drop voltage regulator
Datasheet  production data
Features
Max DC supply voltage
VS
40V
Max output voltage tolerance
V0
+/-2%
Max dropout voltage
Vdp
500 mV
Output current
I0
200 mA
Quiescent current
Iqn
75 µA(1)
'!0'#&4
SO-8
'!0'#&4
SO-20
1. Typical value with watchdog disabled.
Description
■
Operating DC supply voltage range 5.6V to
31V
■
Reset circuit sensing the output voltage down
to 1V
■
Programmable reset pulse delay with external
capacitor
■
Watchdog
■
Programmable watchdog timer with external
capacitor
■
Enable input for enabling/disabling the
watchdog functionality
■
Thermal shutdown and short circuit protection
■
Wide temperature range (Tj = -40°C to 150°C)
Table 1.
The L4988 is a monolithic integrated 5V voltage
regulator with a low drop voltage at currents up to
200mA. The output voltage regulating element
consists in a p-channel MOS and the regulation is
performed regardless of input voltage transients
up to 40V. The high precision of the output voltage
is obtained with a pre-trimmed reference voltage.
The L4988 is protected against short circuit and
an over-temperature protection switches off the
device in case of extremely high power dissipation. The L4988 is active when the Enable is high.
State of the art features like reset and watchdog
make this device particularly suitable to supply
microprocessor systems in automotive
applications.
Device summary
Order codes
Package
Tube
Tape & reel
SO8
L4988D
L4988DTR
SO20 (16+2+2)
L4988MD
L4988MDTR
September 2013
This is information on a product in full production.
Doc ID 13617 Rev 6
1/32
www.st.com
1
Contents
L4988
Contents
1
Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5
Test circuit and waveforms plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.1
3
4
5
6
2/32
Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1
SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2
SO-20 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2
SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3
SO-20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4
SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5
SO-20 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 13617 Rev 6
L4988
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Watchdog Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SO-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SO-20 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SO-20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 13617 Rev 6
3/32
List of figures
L4988
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
4/32
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output voltage vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output voltage vs. Vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Drop Voltage vs. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current consumption vs. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current consumption vs. Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current limitation vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current limitation vs. Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Short Circuit Current vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Short Circuit Current vs. Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VWEn_high vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VWEN_LOW vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Vrhth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Vrlth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Vwhth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Vwlth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Icr & Icwc vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Idr & Icwd vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Twop vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Load regulation test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Maximum load variation response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
L4988 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Behavior of output current versus regulated voltage Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SO-8 Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . 19
SO-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SO-8 thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SO-20 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SO-20 Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . 22
SO-20 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 23
SO-20 thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SO-20 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SO-20 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SO-20 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 13617 Rev 6
L4988
1
Block diagram and pin configuration
Block diagram and pin configuration
Figure 1.
Block diagram
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Doc ID 13617 Rev 6
5/32
Block diagram and pin configuration
Table 2.
Pin
L4988
Pins description
SO8(D)
S020(MD)
WEn
1
1
Watchdog Enable input
If high watchdog functionality is active
Gnd
2
4
Ground reference
name
Gnd
5, 6, 15, 16
Function
Ground.
Connected these pins to a heat spreader ground
Res
3
7
Reset output.
It is pulled down when output voltage goes below Vo_th
or frequency at Wi is too low.
Vcr
4
10
Reset timing adjust.
A capacitor between Vcr pin and gnd, sets the reset
delay time (trd)
Vcw
5
11
Watchdog timer adjust
A capacitor between Vcw pin and gnd, sets the time
response of the watchdog monitor.
Wi
6
14
Watchdog input.
If the frequency at this input pin is too low, the Reset
output is activated.
Vo
7
17
Voltage regulator output
Block to ground with a capacitor >100nF (needed for
regulator stability)
Vs
8
20
Supply voltage
Block to ground directly at IC pin with a capacitor
2, 3, 8, 9, 12,
13, 18, 19
N.C.
Figure 2.
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Pins configuration
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6CW
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6/32
Doc ID 13617 Rev 6
L4988
Electrical specifications
2
Electrical specifications
2.1
Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
-0.3 to 40
V
VVsdc
DC supply voltage
IVsdc
Input current
VVo
DC output voltage
-0.3 to 6(1)
IVo
DC output current
Internally limited
VWi
Watchdog input voltage
-0.3 to VVo + 0.3
V
Vod
Open Drain output voltage
-0.3 to VVo + 0.3
V
Iod
Open Drain output current
Internally limited
Vcr
Reset delay voltage
-0.3 to VVo + 0.3
V
Vcw
Watchdog delay voltage
-0.3 to VVo + 0.3
V
Watchdog Enable input voltage
-0.3 to VVo +0.3
V
-40 to 150
“C
VWEn
Tj
Internally limited
Junction temperature
V
VESD
ESD voltage level (HBM-MIL STD 883C)
±2
kV
VESD
ESD voltage level (CDM AEC-Q100-011)
750
V
1. Using the typical application schematic with Cout= 10 µF and Iout=0 A, when the regulator is switched-on,
an overshoot exceeding 6 V could occur.This behavior does not impact the reliability of the regulator.
2.2
Thermal data
Table 4.
Thermal data
Symbol
Rth-jamb
Parameter
Thermal resistance junction to ambient
S08
S016+2+2
Unit
130(1)
51(2)
°C/W
2
1. With copper area 2 cm ; for details see Figure 29.
2. With copper area 6 cm2 ; for details see Figure 33.
Doc ID 13617 Rev 6
7/32
Electrical specifications
2.3
L4988
Electrical characteristics
Vs =5.6V to 31V, Tj= -40°C to +150°C unless otherwise specified.
Table 5.
General
Pin
Symbol
Vo
Vo_ref
Output voltage
Vo
Ishort
Short circuit current
Vo
Ilim(2)
Output current limitation
Vs = 13.5V
Vs, Vo
Vline
Line regulation voltage
Vo
Vload
Vs, Vo
Vdp(3)
Vs, Vo
Vdp(3)
Vs, Vo
SVR
Vs, Vo
Parameter
Test condition
Min.
Typ.
Vs = 6 to 31V
Io = 1 to 200mA
4.9
5.0
5.1
V
Vs = 13.5V(1)
200
280
500
mA
(1)
200
350
600
mA
Vs = 6 to 31V
Io = 1 to 200mA
25
mV
Load regulation voltage
Io = 1 to 200mA
25
mV
Drop voltage
Io = 200mA
270
500
mV
Drop voltage
Io = 150mA
200
400
mV
Hz(4)
Max. Unit
Ripple rejection
fr = 100
Iqn_200
Quiescent current
Vs=13.5V,
Io=200mA,
WEn = high
1.9
2.5
mA
Vs, Vo
Iqn_50
Quiescent current
Vs=13.5V,
Io= 50mA,
WEn = high
500
700
µA
Vs, Vo
Iq_1_we
Quiescent current
Vs=13.5V,
Io< 1mA,
WEn = high
93
200
µA
Iq_1_wd
Quiescent current
Vs=13.5V,
Io< 1mA,
WEn = low
75
150
µA
Tw
Thermal protection
temperature
190
°C
Vs, Vo
Tw_hy
Thermal protection
temperature hysteresis
60
150
dB
10
1. See Figure 3.
2. Measured output current when the output voltage has dropped 100mV from its nominal value obtained at
Vs=13.5V and Io= 75mA.
3. Vs-Vo measured when the output voltage has dropped 100mV from its nominal value obtained at
Vs=13.5V and Io= 75mA.
4. Guaranteed by design.
8/32
Doc ID 13617 Rev 6
°C
L4988
Electrical specifications
Table 6.
Reset
Pin
Symbol
Res
Vres_l
Reset output low voltage
Rext = 5k to Vo,
Vo > 1V
Res
IRes_h
Reset output high leakage
current
VRes = 5V
Res
R_p_u
Pull up internal resistance
With respect to Vo
12
Res
Vo_th
Vo out of regulation
threshold
Vs = 6 to 31V,
Io = 1 to 200mA
Vcr
Vrlth
Reset timing low threshold
Vcr
Vrhth
Vcr
Icr
Charge current
Vcr
Idr
Discharge current
Res
Trr_2
Res
Trd
Parameter
Test condition
Min.
Typ.
Max. Unit
0.4
V
1
µA
25
50
k
6%
8%
10%
Below
Vo_ref
Vs = 13.5V
10%
13%
16% Vo_ref
Reset timing high threshold Vs =13.5V
44%
47%
50% Vo_ref
Vs = 13.5V
8
17.6
30
µA
Vs = 13.5V
8
17.6
30
µA
Vo = Vo_th -100mV
100
275
1000
µs
Vs = 13.5V,
Ctr = 1nF
65
150
ms
Reset reaction
time(1)
Reset delay time
1. When Vo becomes lower than 4V, the reset reaction time decreases down to 2µs assuring a faster reset
condition in this particular case.
Table 7.
Watchdog
Pin
Symbol
Parameter
Test condition
Wi
Vih
Input high voltage
Vs = 13.5V
Wi
Vil
Input low voltage
Vs = 13.5V
Wi
Vih
Input hysteresis
Vs = 13.5V
500
Wi
Ii
Pull down current
Vs = 13.5V
10
Vcw
Vwhth
High threshold
Vs = 13.5V
44%
47%
50% Vo_ref
Vcw
Vwlth
Low threshold
Vs = 13.5V
10%
13%
16% Vo_ref
Vcw
Icwc
Charge current
Vs = 13.5V,
Vcw = 0.1V
4
8
14
µA
Vcw
Icwd
Discharge current
Vs = 13.5V,
Vcw = 2.5V
1.0
2.1
4.5
µA
Vcw
Twop
Watchdog period
Vs = 13.5V,
Ctw = 47nF
25
50
90
ms
Res
twol
Watchdog output low time
Vs = 13.5V,
Ctw = 47nF
6
10.5
22
ms
Doc ID 13617 Rev 6
Min.
Typ.
Max. Unit
3.5
V
1.5
V
mV
20
µA
9/32
Electrical specifications
Table 8.
10/32
L4988
Watchdog Enable
Pin
Symbol
Parameter
WEn
VEn_l
Enable input low voltage
WEn
VEn_h
Enable input high voltage
WEn
VEn_hy
Enable input hysteresis
WEn
I_leak
Pull down current
Test condition
Min.
Typ.
Max. Unit
1
3
WEn = 5V
Doc ID 13617 Rev 6
V
V
500
800
1100
mV
2
8
20
µA
L4988
Electrical specifications
2.4
Electrical characteristics curves
Figure 3.
Output voltage vs. Tj
Figure 4.
Vo_ref (V)
Output voltage vs. Vs
Vo_ref (V)
10
5,5
Vs= 13.5V
I0 = 75mA
5,4
9
5,3
8
5,2
7
5,1
6
5
5
4,9
4
4,8
3
4,7
2
4,6
1
4,5
0
-50
-25
0
25
50
75
100
125
150
I0 = 75 mA
Tj = 25 °C
0
5
10
15
Tj(°C )
Figure 5.
20
25
30
35
Vs (V )
Drop Voltage vs. Output Current
Figure 6.
Current consumption vs. Output
Current
Vdp (V)
Iqn (µA)
0,35
1800
0,3
1500
Vs= 13.5 V
Tj= 25 °C
WEn= High
0,25
1200
Tj= 125 °C
0,2
900
0,15
Tj= 25 °C
600
0,1
300
0,05
0
0
0
50
100
150
200
250
0
40
80
Io (mA)
Figure 7.
120
160
200
240
Io (mA)
Current consumption vs. Input
Voltage
Figure 8.
Current limitation vs. Tj
Ilim (mA)
Iqn(µA )
600
2400
Tj = 25 °C
WEn = High
500
2000
Io= 200mA
400
1600
Vs= 13.5V
300
1200
Io= 100mA
200
800
Io = 50mA
100
400
Io = 1mA
0
0
0
5
10
15
20
25
30
35
-50
-25
0
25
50
75
100
125
150
Tj(°C )
Vs (V )
Doc ID 13617 Rev 6
11/32
Electrical specifications
Figure 9.
L4988
Current limitation vs. Input Voltage
Figure 10. Short Circuit Current vs. Tj
Ilim (mA)
Ishort (mA)
400
600
375
500
Tj = 25 °C
350
Vs= 13.5V
400
325
300
Tj = 125 °C
300
200
275
100
250
0
0
5
10
15
20
25
30
35
-50
-25
0
25
Vs (V )
50
75
100
125
150
125
150
Tj(°C )
Figure 11. Short Circuit Current vs. Input
Voltage
Figure 12. VWEn_high vs. Tj
Vwen_high (V)
Ishort (mA )
4
360
3,5
330
Vs= 5.6V to 31V
3
Tj = 25 °C
300
2,5
270
Tj = 150 °C
2
240
1,5
1
210
0
5
10
15
20
25
30
-50
35
-25
0
25
Figure 13. VWEN_LOW vs. Tj
75
100
Figure 14. Vrhth vs. Tj
Vwen_low (V)
Vrhth (% Vo_ref )
2
60
1,9
55
1,8
Vs= 5.6V to 31V
50
Vs= 5.6V to 31V
1,7
45
1,6
40
1,5
35
1,4
30
-50
-25
0
25
50
75
100
125
150
-50
Tj(°C )
12/32
50
Tj(°C )
Vs (V )
-25
0
25
50
Tj(°C )
Doc ID 13617 Rev 6
75
100
125
150
L4988
Electrical specifications
Figure 15. Vrlth vs. Tj
Figure 16. Vwhth vs. Tj
Vrlth (% Vo_ref)
Vwhth (% Vo_ref )
50
60
55
Vs= 5.6V to 31V
40
Vs= 5.6V to 31V
50
30
45
20
40
10
35
0
30
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
Tj(°C )
50
75
100
125
150
Tj(°C )
Figure 17. Vwlth vs. Tj
Figure 18. Icr & Icwc vs. Tj
Vwlth (% Vo_ref)
Icr & Icwc (µA)
50
30
Vs= 5.6V to 31V
25
Vs= 5.6V to 31V
40
20
Icr
30
15
20
10
10
Icwc
5
0
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
Tj(°C )
50
75
100
125
150
Tj(°C )
Figure 19. Idr & Icwd vs. Tj
Figure 20. Twop vs. Tj
Idr & Icwd (µA)
Twop (ms)
30
80
Vs= 5.6V to 31V
25
70
20
Vs= 5.6V to 31V
Ctw= 47nF
60
Idr
15
50
10
40
5
30
Icwd
0
20
-50
-25
0
25
50
75
100
125
150
-50
Tj(°C )
-25
0
25
50
75
100
125
150
Tj(°C )
Doc ID 13617 Rev 6
13/32
Electrical specifications
L4988
Figure 21. PSRR
C0 = 4.7µF
PSRR [dB]
80
70
60
50
40
30
20
10
0,1
1
10
100
1000
0
10000
FREQUENCY [KHz]
2.5
Test circuit and waveforms plot
2.5.1
Load regulation
Figure 22. Load regulation test circuit
'!0'2)
14/32
Doc ID 13617 Rev 6
L4988
Electrical specifications
Figure 23. Maximum load variation response
V 0 [1
[1V / div]
d
I 0 [50
50mA / div]
di
0,00E+00
5,00E-05
1,00
00E-04
1,50E-04
2,00E-04
2,50E-04
3,00E-04
3,50E-04
4,00E-04
Time [s]
GAPGRI00073
Doc ID 13617 Rev 6
15/32
Application information
3
L4988
Application information
Figure 24. L4988 application schematic
6O
6S
6I
#
7KHUPDO
SURWHFWLRQ
#S
6CW
#TW
7I
#
:DWFKGRJ
9ROWDJHUHIHUHQFH
7%N
2ES
6CR
5HVHW
#TR
'ND
'!0'2)
Note:
The input capacitor Cs > 200nF is necessary for the smoothing of line disturbances. The
output capacitor C01 > 100nF is necessary for the stability of the regulation loop. In order to
damp output voltage oscillations during high load current surges, it is recommended to put
an additional electrolytic capacitor C02 > 10µF at the output pin.
3.1
Voltage regulator
Voltage regulator uses a p-channel mos transistor as a regulating element. With this
structure a very low dropout voltage at currents up to 200mA is obtained. The output voltage
is regulated up to transient input supply voltage of 40V. No functional interruption due to
over-voltage pulses is generated. A short circuit protection to GND is provided. The high
precision of the output voltage is obtained with a pre-trimmed reference voltage.
16/32
Doc ID 13617 Rev 6
L4988
Application information
Figure 25. Behavior of output current versus regulated voltage Vo
6O
6O?REF
)SHORT )LIM
)OUT
("1($'5
3.2
Reset
The reset circuit supervises the output voltage Vo. The Vo_th reset threshold is defined with
the in-ternal reference voltage and a resistor output divider. If the output voltage becomes
lower than Vo_th then Res goes low with a reaction time trr. The reset low signal is
guaranteed for an output voltage Vo greater than 1V.
When the output voltage becomes higher than Vo_th then Res goes high with a delay trd.
This delay is obtained by an internal oscillator.
The oscillator period is given by:
Tosc = [(Vrhth-Vrlth) x Ctr] / Icr + [(Vrhth-Vrlth) x Ctr] / Idr
where:
Icr:
is an internally generated charge current
Idr:
is an internally generated discharge current
Vrhth, Vrlth:
are two voltages defined with the output voltage and a resistor output
divider
Ctr:
is an external capacitance.
trd is given by:
trd = 512 x Tosc
Reset is active when En is high.
Doc ID 13617 Rev 6
17/32
Application information
L4988
Figure 26. Reset timing diagram
7I
6 OUT?TH
TRR
6O
4 OSC
TRR
6 CR
6 RHTH
6 RLTH
TRD 4 OSC
2ES
'!0'#&4
3.3
Watchdog
A connected microcontroller is monitored by the watchdog input Wi. If pulses are missing,
the Reset output pin is set to low. The pulse sequence time can be set within a wide range
with the external capacitor, Ctw. The watchdog circuit discharges the capacitor Ctw, with the
constant current Icwd. If the lower threshold Vwlth is reached, a watchdog reset is
generated. To prevent this the microcontroller must generate a positive edge during the
discharge of the capacitor before the voltage has reached the threshold Vwlth. In order to
calculate the minimum time t, during which the micro-controller must output the positive
edge, the following equation can be used:
(Vwhth-Vwlth) x Ctw = Icwd x t
Every Wi positive edge switches the current source from discharging to charging. The same
happens when the lower threshold is reached. When the voltage reaches the upper
threshold, Vwhth, the current switches from charging to discharging. The result is a
saw-tooth voltage at the watchdog timer capacitor Ctw.
Figure 27. Watchdog timing diagram
7I
4WO P
6WHTH
6WLTH
6WLTH
6CW
TWOL
2ES
'!0'2)
18/32
Doc ID 13617 Rev 6
L4988
Package and PCB thermal data
4
Package and PCB thermal data
4.1
SO-8 thermal data
Figure 28. SO-8 PC board
*$3*&)7
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB
thickness = 2mm, Cu thickness = 35µm , Copper areas: from minimum pad lay-out to 8cm2)
Figure 29. SO-8 Rthj-amb Vs. PCB copper area in open box free air condition
24(J?AMB VS #U HEATSINK AREA
24(JAMB
24(J?AMB #7
Note:
0#" #U HEATSINK AREA CM>
'!0'#&4
Doc ID 13617 Rev 6
19/32
Package
and PCB thermal data
,
L4988
0ACKAGE AND 0#" THERMAL DATA
Figure 30. SO-8 thermal impedance junction ambient single pulse
=7+ ƒ&:
&OOTPRINT
CM
7LPH V
'!0'2)
Equation 1: pulse calculation formula
Z
TH
= R
TH
+Z
THtp
1 – 
where  = tP/T
Figure 31. SO-8 thermal fitting model of a single channel
*$3*&)7
20/32
Doc ID 13617 Rev 6
L4988
Package and PCB thermal data
Table 9.
SO-8 thermal parameter
Area/island (cm2)
Footprint
R1 (°C/W)
4.21
R2 (°C/W)
2.11
R3 (°C/W)
2
R4 (°C/W)
41
R5 (°C/W)
40
R6 (°C/W)
58
C1 (W.s/°C)
0.00029
C2 (W.s/°C)
0.0024
C3 (W.s/°C)
0.03
C4 (W.s/°C)
0.04
C5 (W.s/°C)
0.1
C6 (W.s/°C)
1.05
Doc ID 13617 Rev 6
2
40
2
21/32
Package and PCB thermal data
4.2
L4988
SO-20 thermal data
Figure 32. SO-20 PC board
.
*$3*&)7
Note:
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm,PCB
thickness = 2mm, Cu thickness=35m , Copper areas: from minimum pad lay-out to 8cm2).
Figure 33. SO-20 Rthj-amb Vs. PCB copper area in open box free air condition
57+MBDPEYV&XKHDWVLQNDUHD
57+MBDPE ƒ&:
57+MDPE
22/32
3&%&XKHDWVLQNDUHD FPA
Doc ID 13617 Rev 6
("1($'5
L4988
Package and PCB thermal data
Figure 34. SO-20 thermal impedance junction ambient single pulse
=7+ ƒ&:
&X FP
&X IRRWSULQW
7LPH V
("1($'5
Equation 2: pulse calculation formula
Z
TH
= R
TH
+Z
THtp
1 – 
where  = tP/T
Figure 35. SO-20 thermal fitting model of a single channel
*$3*&)7
Doc ID 13617 Rev 6
23/32
Package and PCB thermal data
Table 10.
24/32
L4988
SO-20 thermal parameter
Area/island (cm2)
Footprint
R1 (°C/W)
4.21
R2 (°C/W)
2.11
R3 (°C/W)
2.2
R4 (°C/W)
10
R5 (°C/W)
15
R6 (°C/W)
35
C1 (W.s/°C)
0.00029
C2 (W.s/°C)
0.0024
C3 (W.s/°C)
0.015
C4 (W.s/°C)
0.15
C5 (W.s/°C)
1.5
C6 (W.s/°C)
4
Doc ID 13617 Rev 6
2
18
7
L4988
Package and packing information
5
Package and packing information
5.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
SO-8 package information
Figure 36. SO-8 package dimensions
'!0'#&4
Doc ID 13617 Rev 6
25/32
Package and packing information
L4988
SO-8 mechanical data
Table 11.
Millimeters
Symbol
Min.
Typ.
A
Max.
1.75
A1
0.10
A2
1.25
b
0.28
0.48
c
0.17
0.23
D(1)
4.80
4.90
5.00
E
5.80
6.00
6.20
E1(2)
3.80
3.90
4.00
e
0.25
1.27
h
0.25
0.50
L
0.40
1.27
L1
k
1.04
0°
ccc
8°
0.10
1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs
shall not exceed 0.15mm in total (both side).
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25mm per side.
26/32
Doc ID 13617 Rev 6
L4988
5.3
Package and packing information
SO-20 package information
Figure 37. SO-20 package dimensions
("1($'5
SO-20 mechanical data
Table 12.
Millimeters
Symbol
Min.
Typ.
Max.
A
2.35
2.65
A1
0.10
0.30
B
0.33
0.51
C
0.23
0.32
D(1)
12.60
13.00
E
7.40
7.60
e
1.27
H
10.0
10.65
h
0.25
0.75
L
0.40
1.27
Doc ID 13617 Rev 6
27/32
Package and packing information
L4988
SO-20 mechanical data (continued)
Table 12.
Millimeters
Symbol
Min.
k
Typ.
Max.
0°
8°
ddd
0.10
1. “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs
shall not exceed 0.15mm per side.
5.4
SO-8 packing information
Figure 38. SO-8 tube shipment (no suffix)
"
#
!
Base q.ty
Bulk q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
All dimensions are in mm.
'!0'2)
28/32
Doc ID 13617 Rev 6
100
2000
532
3.2
6
0.6
L4988
Package and packing information
Figure 39. SO-8 tape and reel shipment (suffix “TR”)
Doc ID 13617 Rev 6
29/32
Package and packing information
5.5
L4988
SO-20 packing information
Figure 40. SO-20 tube shipment (no suffix)
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
#
"
40
800
532
3.5
13.8
0.6
All dimensions are in mm.
!
'!0'2)
Figure 41. SO-20 tape and reel shipment (suffix “TR”)
Reel dimensions
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
D
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
60
30.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (+ 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
24
4
12
1.5
1.5
11.5
6.5
2
All dimensions are in mm.
End
Start
Top
cover
tape
No components
Components
No components
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
GAPGRI00080
30/32
Doc ID 13617 Rev 6
L4988
6
Revision history
Revision history
01
Table 13.
Document revision history
Date
Revision
Changes
01-Jun-2007
1
Initial release
30-Aug-2007
2
Added features table.
Added list of tables and figures.
Updated Section 2.3: Electrical characteristics.
Added Section 4: Package and PCB thermal data.
Added SO-8 packing information and SO-20 packing information.
13-Feb-2008
3
Update Section 2.3: Electrical characteristics.
04-Jun-2008
4
Document restructured.
Changed Figure 1: Block diagram.
Updated features table on cover page: changed quiescent current
value from 80 to 75 µA.
Updated Table 5: General:
– changed Ishort typical value from 250 to 280 mA
– changed Iqn_50 typical value from 550 to 500 µA
– changed Iq_1_we typical value from 130 to 93 µA
– changed Iq_1_wd typical value from 80 to 75 µA.
Updated Table 7: Watchdog:
– changed Vwlth values in Vo_ref percentages
– changed Vwhth values in Vo_ref percentages.
Added Figure 24: L4988 application schematic.
Added Section 2.4: Electrical characteristics curves.
Added Section 2.5: Test circuit and waveforms plot.
05-Apr-2012
5
Update Table 3: Absolute maximum ratings.
20-Sep-2013
6
Updated disclaimer.
Doc ID 13617 Rev 6
31/32
L4988
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