TI OPA355-Q1 200-mhz cmos operational amplifier with shutdown Datasheet

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OPA355-Q1
SLOS868B – DECEMBER 2013 – REVISED JUNE 2014
OPA355-Q1 200-MHz CMOS Operational Amplifier With Shutdown
1 Features
3 Description
•
•
The OPA355-Q1 device is a high-speed, voltagefeedback CMOS operational amplifier designed for
applications requiring wide bandwidth. The OPA355Q1 device is unity-gain stable and can drive large
output currents. In addition, the OPA355-Q1 device
has a digital shutdown (enable) function. This feature
provides power saving during idle periods and places
the output in a high-impedance state to support
output multiplexing. The differential gain is 0.02% and
the differential phase is 0.05°. The quiescent current
is 8.3 mA per channel.
1
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•
•
•
•
•
•
•
•
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
Unity-Gain Bandwidth: 450 MHz
Wide Bandwidth: 200 MHz GBW
High Slew Rate: 360 V/μs
Low Noise: 5.8 nV/√Hz
Excellent Video Performance:
– Differential Gain: 0.02%
– Differential Phase: 0.05° 0.1 dB
– Gain Flatness: 75 MHz
Input Range Includes Ground
Rail-to-Rail Output (within 100 mV)
Low Input Bias Current: 3 pA
Low Shutdown Current: 3.4 μA
Enable and Disable Time: 100 ns and 30 ns
Thermal Shutdown
Single-Supply Operating Range: 2.5 to 5.5 V
MicroSIZE Packages
The OPA355-Q1 device is optimized for operation on
single supply or dual supplies as low as 2.5 V (±1.25
V) and up to 5.5 V (±2.75 V). The common-mode
input range for the OPA355-Q1 device extends 100
mV below ground and up to 1.5 V from V+. The
output swing is within 100 mV of the rails, supporting
wide dynamic range.
The OPA355-Q1 device is available in a single
SOT23-6 package and is specified over the extended
–40°C to 125°C range.
Device Information(1)
PART NUMBER
OPA355-Q1
PACKAGE
SOT-23 (6)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
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Automotive
Active Filters
High-Speed Integrators
Analog-to-Digital Converter (ADC) Input Buffers
Digital-to-Analog Converter (DAC) Output
Amplifiers
V+
–VIN
OPA355-Q1
Out
+VIN
V– Enable
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA355-Q1
SLOS868B – DECEMBER 2013 – REVISED JUNE 2014
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
3
7.1
7.2
7.3
7.4
7.5
3
3
4
4
6
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
8
Detailed Description ............................................ 11
9
Application and Implementation ........................ 12
8.1 Feature Description................................................. 11
9.1 Application Information............................................ 12
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................. 12
11 Device and Documentation Support ................. 13
11.1 Trademarks ........................................................... 13
11.2 Electrostatic Discharge Caution ............................ 13
11.3 Glossary ................................................................ 13
12 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
Changes from Revision A (December 2013) to Revision B
•
2
Page
Changed device status from Product Preview to Production Data ....................................................................................... 1
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5 Device Comparison Table
OPA355-Q1 RELATED
PRODUCTS
FEATURES
OPA356
200-MHz, Rail-to-Rail Output, CMOS, No Shutdown
OPAx350
38-MHz, Rail-to-Rail Input and Output, CMOS
OPAx631
75-MHz, Rail-to-Rail Output
OPAx634
150-MHz, Rail-to-Rail Output
THS412x
Differential Input and Output, 3.3-V Supply
6 Pin Configuration and Functions
6-Pin SOT-23
DBV Package
Top View
(1)
C55
6
V+
V– 2
5
Enable
+In 3
4
–In
Out 1
Pin 1 of the SOT23-6 is determined by orienting the package marking as indicated in the diagram.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage
V+ to V–
Voltage
(V–) – 0.5
Signal input terminals
MAX
UNIT
7.5
V
(V+) +
0.5
V
10
mA
Current
Output short circuit (2)
Continuous
Operating temperature
150
°C
Junction Temperature
160
°C
Lead temperature (soldering, 10 seconds)
300
°C
(1)
(2)
–55
Stresses above absolute maximum ratings may cause permanent damage. Exposure to absolute maximum conditions for extended
periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those specified is not implied.
Short-circuit to ground, one amplifier per package.
7.2 Handling Ratings
Tstg
Storage temperature range
Human body model (HBM), per AEC Q100-002
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per
AEC Q100-011
MIN
MAX
UNIT
–65
150
°C
(1)
2000
Corner pins (1, 3, 4,
and 6)
750
Other pins
500
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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7.3 Thermal Information
DBV
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
187.3
RθJC(top)
Junction-to-case (top) thermal resistance
126.5
RθJB
Junction-to-board thermal resistance
32.6
ψJT
Junction-to-top characterization parameter
24.1
ψJB
Junction-to-board characterization parameter
32.1
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
(1)
UNIT
6 PINS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.4 Electrical Characteristics
VS = 2.7 V to 5.5 V single supply. At TA = 25°C, RF = 604 Ω, RL = 150Ω, and connected to VS / 2, unless otherwise noted.
PARAMETER
TA = 25°C
TEST CONDITIONS
MIN
TA = –40°C to 125°C
TYP
MAX
±2
±9
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
DVOS/dT
Input offset voltage versus temperature
VS = 5 V
PSRR
Input offset voltage versus power supply
±15
±7
VS = 2.7 to 5.5 V, VCM = VS / 2 – 0.15 V
mV
µV/°C
±80
±350
µV/V
3
±50
pA
±1
±50
pA
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
NOISE
en
Input noise voltage density
ƒ = 1 MHz
5.8
nV/√Hz
in
Current noise density
ƒ = 1 MHz
50
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
(V–) – 0.1
VS = 5.5 V, –0.1 V < VCM < 4 V
(V+) – 1.5
66
80
V
66
dB
INPUT IMPEDANCE
Differential
Ω || pF
1013 || 1.5
Common-mode
13
10
Ω || pF
|| 1.5
OPEN-LOOP GAIN
Open-loop gain
VS = 5 V, 0.3 V < VO < 4.7 V
84
92
80
dB
FREQUENCY RESPONSE
ƒ–3dB
Small-signal bandwidth
G = 1, VO = 100 mVp-p, RF = 0 Ω
450
MHz
G = 2, VO = 100 mVp-p, RL = 50 Ω
100
MHz
G = 2, VO = 100 mVp-p, RL = 150 Ω
170
MHz
G = 2, VO = 100 mVp-p, RL = 1 kΩ
200
MHz
200
MHz
75
MHz
300 / –360
V/µs
GBW
Gain-bandwidth product
G = 10, RL = 1 kΩ
ƒ0.1dB
Bandwidth for 0.1-db gain flatness
G = 2, VO = 100 mVp-p, RF = 560 Ω
SR
Slew rate
VS = 5 V, G = 2, 4-V output step
G = 2, VO = 200 mVp-p, 10% to 90%
2.4
ns
G = 2, VO = 2 Vp-p, 10% to 90%
8
ns
0.1%
VS = 5 V, G = 2, 2-V output step
30
ns
0.01%
VS = 5 V, G = 2, 2-V output step
120
ns
Rise and fall time
Settling time
Overload recovery time
VI × G = VS
Second harmonic
G = 2, ƒ = 1 MHz, VO = 2 Vp-p, RL = 200 Ω
Third harmonic
G = 2, ƒ = 1 MHz, VO = 2 Vp-p, RL = 200 Ω
Harmonic distortion
4
8
dBc
–93
dBc
Differential gain error
NTSC, RL = 150 Ω
0.02%
Differential phase error
NTSC, RL = 150 Ω
0.05
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ns
–81
degrees
(°)
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Electrical Characteristics (continued)
VS = 2.7 V to 5.5 V single supply. At TA = 25°C, RF = 604 Ω, RL = 150Ω, and connected to VS / 2, unless otherwise noted.
PARAMETER
TA = 25°C
TEST CONDITIONS
MIN
TA = –40°C to 125°C
TYP
MAX
MIN
TYP
MAX
UNIT
VS = 5 V, RL = 150 Ω, AOL > 84 dB
0.2
0.3
VS = 5 V, RL = 1 kΩ
0.1
V
±60
mA
VS = 5 V
±100
mA
VS = 3 V
±80
mA
ƒ < 100 kHz
0.02
Ω
OUTPUT
Voltage output swing from rail
Continuous
Output current (1)
IO
Peak
Closed-loop output
impedance
V
POWER SUPPLY
VS
Specified voltage range
2.7
Operating voltage range
IQ
5.5
V
2.5 to 5.5
Quiescent current (per amplifier)
VS = 5 V, enabled; IO = 0
8.3
V
11
14
mA
SHUTDOWN
Disabled
Logic-LOW
threshold (2)
Enabled
Logic-HIGH
threshold (2)
0.8
2
V
V
Enable time
100
Disable time
30
ns
3.4
µA
Shutdown
160
°C
Reset from
Shutdown
140
°C
Shutdown current (per amplifier)
VS = 5 V, disabled
ns
THERMAL SHUTDOWN
Junction Temperature
TEMPERATURE RANGE
(1)
(2)
Specified Range
–40
125
°C
Operating Range
–55
150
°C
Storage Range
–65
150
°C
See the Output Voltage Swing vs Output Current (Figure 21 and Figure 23) in the Typical Characteristics section.
Logic LOW and HIGH levels are CMOS logic compatible. They are referenced to V–.
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7.5 Typical Characteristics
At TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2, unless otherwise noted.
6
3
G=1
RF = 0
0
Normalized Gain (dB)
Normalized Gain (dB)
3
0
–3
G=2
–6
G=5
–9
G = 10
1M
10M
Frequency (Hz)
–3
G = –5
–6
G =–15
–10
–9
100M
1G
100k
VO = 0.1 VP-P
1M
10M
Frequency (Hz)
100M
1G
VO = 0.1 VP-P
Figure 2. Inverting Small-Signal Frequency Response
Output Voltage (50 mV/div)
Output Voltage (500 mV/div)
Figure 1. Non-Inverting Small-Signal Frequency Response
Time (20 ns/div)
Time (20 ns/div)
G=2
G=2
Figure 3. Non-Inverting Small-Signal Step Response
0.5
RF = 604
0.3
3.5
2.5
1.5
Disabled
0.4
Normalized Gain (dB)
Output Voltage (500 mV/div)
fIN = 5 MHz
Figure 4. Non-Inverting Large-Signal Step Response
4.5
Disable Voltage (V)
Enabled
0.2
0.1
0
–0.1
RF = 560
–0.2
–0.3
RF = 500
–0.4
VO
0.5
–0.5
1
10
Frequency (MHz)
Time (200 ns/div)
CL = 0 pF
Figure 5. Large-Signal Disable and Enable Response
6
G = –2
–12
–12
–15
100k
G = –1
100
VO = 0.1 VP-P
Figure 6. 0.1 dB Gain Flatness for Various RF
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Typical Characteristics (continued)
–50
–50
–60
–60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
At TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2, unless otherwise noted.
–70
2nd Harmonic
–80
3rd Harmonic
–90
–100
–70
2nd-Harmonic
–80
3rd-Harmonic
–90
–100
0
RL = 200
1
2
Output Voltage (Vp-p)
3
4
1
ƒ = 1 MHz
RL = 200
Figure 7. Harmonic Distortion vs Output Voltage
VO = 2 VP-P
–50
Harmonic Distortion (dBc)
–60
–70
2nd-Harmonic
–80
3rd-Harmonic
–90
–100
1
10
–60
2nd-Harmonic
–70
–80
3rd-Harmonic
–90
–100
100k
1M
Frequency (Hz)
Gain (V/V)
RL = 200
VO = 2 VP-P
ƒ = 1 MHz
RL = 200
–60
–70
–80
2nd-Harmonic
–90
3rd-Harmonic
–100
100
VO = 2 VP-P
1k
10k
1k
Voltage Noise
Current Noise
100
10
1
10
RL (Ω)
ƒ = 1 MHz
10M
Figure 10. Harmonic Distortion vs Frequency
Voltage Noise (nV/√Hz), Current Noise (fA/√Hz)
Figure 9. Harmonic Distortion vs Inverting Gain
–50
Harmonic Distortion (dBc)
ƒ = 1 MHz
Figure 8. Harmonic Distortion vs Non-Inverting Gain
–50
Harmonic Distortion (dBc)
10
Gain (V/V)
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
VO = 2 VP-P
Figure 11. Harmonic Distortion vs Load Resistance
Figure 12. Input Voltage and Current Noise Spectral Density
vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2, unless otherwise noted.
3
9
RL = 10k
–3
RL = 50
–6
RL = 150
–9
RL = 1k
–12
CL = 47 pF
3
Normalized Gain (dB)
Normalized Gain (dB)
CL = 100 pF
6
0
0
–3
CL = 5.6 pF
–6
–9
–12
–15
100k
1M
10M
Frequency (Hz)
CL = 0 pF
100M
–15
100k
1G
VO = 0.1 VP-P
Figure 13. Frequency Response for Various RL
Normalized Gain (dB)
0
RS (Ω)
100
80
RS
VO
OPA355-Q1
40
CL
1k
604
20
0
D3
VI
D6
RS
VO
OPA355-Q1
CL
D9
10
Capacitive Load (pF)
100
CL = 47 pF
RS = 36
1k
604
(1k is
Optional)
604
1M
Figure 15. Recommended RS vs Capacitive Load
10M
100M
Frequency (Hz)
1G
Figure 16. Frequency Response vs Capacitive Load
180
100
90
160
Open-Loop Phase (degrees)
Open-Loop Gain (dB)
DPSRR
80
CMRR, PSRR (dB)
CL = 5.6 pF
RS = 80
D15
1
+PSRR
70
60
CMRR
50
40
30
20
140
120
Phase
100
80
60
Gain
40
20
RL = 1 kW
RL = 150 kW
0
10
–20
0
10k
100k
1M
10M
Frequency (Hz)
100M
1G
1k
Figure 17. Common-Mode Rejection Ratio and PowerSupply Rejection Ratio vs Frequency
8
1G
VO = 0.1 VP-P
CL = 100 pF
RS = 24
D12
(1k is
Optional)
604
100M
Figure 14. Frequency Response for Various CL
3
VI
10M
Frequency (Hz)
RS = 0
120
60
1M
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10k
100k
1M
10M
Frequency (Hz)
100M
1G
Figure 18. Open-Loop Gain and Phase
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Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2, unless otherwise noted.
0.40
10n
Input Bias Current (pA)
dG/dP (%/degrees)
0.35
0.30
0.25
0.20
dP
0.15
0.10
1n
100
10
dG
0.05
1
0
1
2
3
Number of 150 Loads
–55
4
Figure 19. Composite Video Differential Gain and Phase
–35
–15
5
85
105 125 135
Figure 20. Input Bias Current vs Temperature
3
14
12
25°C
VS = 5.5 V
Supply Current (mA)
–55°C
Output Voltage (V)
25
45
65
Temperature (°C)
2
125°C
125°C
1
–55°C
25°C
10
8
6
VS = 2.5 V
VS = 3 V
4
VS = 5 V
2
0
0
0
30
60
90
Output Current (mA)
120
150
–55
–35
–15
5
25
45
65
Temperature (°C)
85
105 125 135
Continuous currents above 60 mA are not recommended
Figure 21. Output Voltage Swing vs Output Current
for VS = 3 V
Figure 22. Supply Current vs Temperature
5
4.5
25°C
Shutdown Current (A)
Output Voltage (V)
4
125°C
3
2
125°C
1
–55°C
25°C
VS = 5.5 V
4.0
–55°C
3.5
VS = 5 V
3.0
2.5
2.0
1.5
VS = 3 V
1.0
VS = 2.5 V
0.5
0
0
0
50
100
150
Output Current (mA)
200
250
–55
–35
–15
5
25
45
65
Temperature (°C)
85
105 125 135
Continuous currents above 60 mA are not recommended
Figure 23. Output Voltage Swing vs Output Current
for VS = 5 V
Figure 24. Shutdown Current vs Temperature
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Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2, unless otherwise noted.
6
100
VS = 5.5 V
5
Output Voltage (Vp-p)
Output Impedance (Ω)
10
1
OPA355-Q1
0.1
ZO
604
0.01
4
3
VS = 2.7 V
2
1
604
0
0.001
10k
100k
1M
10M
Frequency (Hz)
100M
1
1G
10
Frequency (MHz)
100
Maximum output voltage without slew-rate induced distortion
Figure 25. Closed-Loop Output Impedance vs Frequency
Figure 26. Maximum Output Voltage vs Frequency
0.2
110
RL = 1k
100
Open-Loop Gain (dB)
Output Error (%)
0.1
0
–0.1
–0.2
–0.3
–0.4
0
5
10
15
20 25
30
Time (ns)
35
40
45
90
RL = 150
80
70
60
50
–55
–35
–15
5
25
45
65
Temperature (°C)
85
105 125 135
VO = 2 VP-P
Figure 27. Output Settling Time to 0.1%
Figure 28. Open-Loop Gain vs Temperature
20
100
Power-Supply Rejection Ratio
16
90
14
CMRR, PSRR (dB)
Percent of Amplifiers (%)
18
12
10
8
6
4
80
Common-Mode Rejection Ratio
70
60
2
0
50
–9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9
Offset Voltage (mV)
Figure 29. Offset Voltage Production Distribution
10
–55
–35
–15
5
25
45
65
Temperature (°C)
85
105 125 135
Figure 30. Common-Mode Rejection Ratio and PowerSupply Rejection Ratio vs Temperature
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8 Detailed Description
8.1 Feature Description
8.1.1 Operating Voltage
The OPA355-Q1 device is specified over a power-supply range of 2.7 to 5.5 V (±1.35 to ±2.75 V). However, the
supply voltage can range from 2.5 to 5.5 V (±1.25 to ±2.75 V). Supply voltages higher than 7.5 V (absolute
maximum) can permanently damage the amplifier.
Parameters that vary significantly over supply voltage or temperature are shown in the Typical Characteristics
section of this data sheet.
8.1.2 Enable Function
The OPA355-Q1 device is enabled by applying a TTL HIGH-voltage level to the Enable pin. Conversely, a TTL
LOW-voltage level disables the amplifier which reduces the supply current from 8.3 mA to only 3.4 μA per
amplifier. This pin voltage is referenced to a single-supply ground. When using a split-supply, such as ±2.5 V, the
enable and disable voltage levels are referenced to V–. Independent Enable pins are available for each channel,
providing maximum design flexibility. For portable battery-operated applications, this feature can be used to
greatly reduce the average current and thereby extend battery life.
The Enable input can be modeled as a CMOS input gate with a 100-kΩ pullup resistor to V+. Left open, the
Enable pin assumes a logic HIGH, and the amplifier turns on.
The Enable time is 100 ns and the disable time is 30 ns which allows the OPA355-Q1 device to operate as a
gated amplifier, or to have the output multiplexed onto a common output bus. When disabled, the output
assumes a high-impedance state.
8.1.3 Output Drive
The output stage supplies a high short-circuit current (typically over 200 mA). Therefore, an on-chip thermal
shutdown circuit is provided to protect the OPA355-Q1 device from dangerously-high junction temperatures. At
160°C, the protection circuit shuts down the amplifier. Normal operation resumes when the junction temperature
cools to below 140°C.
NOTE
Running a continuous DC current in excess of ±60 mA is not recommended. Refer to the
Output Voltage Swing vs Output Current graphs (Figure 21 and Figure 22) in the Typical
Characteristics section.
8.1.4 Input and ESD Protection
All OPA355-Q1 pins are static protected with internal ESD protection diodes tied to the supplies (see Figure 31).
If the current is externally limited to 10 mA by the source or by a resistor, these diodes provide overdrive
protection.
+V CC
External
Pin
Internal
Circuitry
–V CC
Figure 31. Internal ESD Protection
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11
OPA355-Q1
SLOS868B – DECEMBER 2013 – REVISED JUNE 2014
www.ti.com
9 Application and Implementation
9.1 Application Information
The OPA355-Q1 device is a CMOS, high-speed, voltage-feedback, operational amplifier (op-amp) designed for
general-purpose applications.
The amplifier features a 200-MHz gain bandwidth and 360-V/μs slew rate, but the device is unity-gain stable and
can operate as a 1-V/V voltage follower.
The input common-mode voltage range of the device includes ground which allows the OPA355-Q1 to be used in
virtually any single-supply application up to a supply voltage of +5.5 V.
10 Layout
10.1 Layout Guidelines
Good high-frequency printed-circuit board (PCB) layout techniques must be used for the OPA355-Q1. Generous
use of ground planes, short direct-signal traces, and a suitable bypass capacitor located at the V+ pin will assure
clean and stable operation. Large areas of copper also help dissipate heat generated within the amplifier in
normal operation.
Sockets are not recommended for use with any high-speed amplifier.
A 10-nF ceramic bypass capacitor is the minimum recommended value; adding a 1-μF or larger tantalum
capacitor in parallel can be beneficial when driving a low-resistance load. Providing adequate bypass
capacitance is essential to achieving very low harmonic and intermodulation distortion.
12
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OPA355-Q1
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SLOS868B – DECEMBER 2013 – REVISED JUNE 2014
11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
OPA355QDBVRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOT-23
DBV
6
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
SLN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jun-2014
OTHER QUALIFIED VERSIONS OF OPA355-Q1 :
• Catalog: OPA355
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
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