CD54ACT174, CD74ACT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCHS344 – APRIL 2003 D D D D D D D D D CD54ACT174 . . . F PACKAGE CD74ACT174 . . . E OR M PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible Contain Six Flip-Flops With Single-Rail Outputs Buffered Inputs Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 Applications Include: – Buffer/Storage Registers – Shift Registers CLR 1Q 1D 2D 2Q 3D 3Q GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 6Q 6D 5D 5Q 4D 4Q CLK description/ordering information The ’ACT174 devices are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input and are designed for 4.5-V to 5.5-V VCC operation. Information at the data (D) inputs that meets the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output. ORDERING INFORMATION PDIP – E 55°C to 125°C –55°C ORDERABLE PART NUMBER PACKAGE† TA SOIC – M Tube CD74ACT174E Tube CD74ACT174M Tape and reel CD74ACT174M96 TOP-SIDE MARKING CD74ACT174E ACT174M CDIP – F Tube CD54ACT174F3A CD54ACT174F3A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each flip-flop) INPUTS CLR CLK D OUTPUT Q L X X L H ↑ H H H ↑ L L H L X Q0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD54ACT174, CD74ACT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCHS344 – APRIL 2003 logic diagram (positive logic) CLR CLK 1D 1 9 3 1D 2 C1 1Q R To Five Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input clamp current, IIK (VI < 0 V or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 V or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO > 0 V or VO < VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±150 mA Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) TA = 25°C –40°C to 85°C UNIT MIN MAX MIN MAX MIN MAX 4.5 5.5 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 High-level output current –24 IOL ∆t/∆v Low-level output current 24 Input transition rise or fall rate 10 High-level input voltage –55°C to 125°C 2 2 0.8 VCC VCC 2 0.8 0 0 V V 0.8 V VCC VCC V –24 –24 mA 24 24 mA 10 10 ns/V VCC VCC 0 0 V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD54ACT174, CD74ACT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCHS344 – APRIL 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VOH VOL II ICC DICC‡ VI = VIH or VIL VI = VIH or VIL VI = VCC or GND VI = VCC or GND, –55°C to 125°C TA = 25°C VCC MAX MIN –40°C to 85°C MAX MIN UNIT MAX IOH = –50 µA IOH = –24 mA 4.5 V 4.4 4.5 V 3.94 IOH = –50 mA† IOH = –75 mA† 5.5 V IOL = 50 µA IOL = 24 mA IOL = 50 mA† 4.5 V 0.1 0.1 0.1 4.5 V 0.36 0.5 0.44 IOL = 75 mA† 5.5 V 4.4 4.4 3.7 3.8 5.5 V 3.85 5.5 V IO = 0 VI = VCC – 2.1 V V 3.85 1.65 V 1.65 5.5 V ±0.1 ±1 ±1 µA 5.5 V 8 160 80 µA 2.4 3 2.8 mA 4.5 V to 5.5 V Ci 10 10 10 pF † Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C. ‡ Additional quiescent supply current per input pin, TTL inputs high, 1 unit load ACT INPUT LOAD TABLE INPUT UNIT LOAD Data 0.5 CLR 0.5 CLK 0.83 Unit Load is ∆ICC limit specified in electrical characteristics table (e.g., 2.4 mA at 25°C). timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) –55°C to 125°C MIN fclock Clock frequency tw Pulse duration tsu th Setup time before CLK↑ trec Recovery time, before CLK↑ –40°C to 85°C MAX MIN 80 CLR low CLK high or low Data Hold time, data after CLK↑ CLR↑ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MAX 91 MHz 4 3.5 6.2 5.4 2 2 ns 2.5 2.2 ns 1.5 1.5 ns ns 3 CD54ACT174, CD74ACT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCHS344 – APRIL 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) –55°C to 125°C MIN –40°C to 85°C MAX 80 CLK Any Q CLR Any Q MIN UNIT MAX 91 MHz 3.5 14 3.6 12.6 3.5 14 3.6 12.6 3.9 15.5 4 14.1 3.9 15.5 4 14.1 ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP UNIT 37 pF CD54ACT174, CD74ACT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCHS344 – APRIL 2003 PARAMETER MEASUREMENT INFORMATION S1 R1 = 500 Ω From Output Under Test 2 × VCC Open GND CL = 50 pF (see Note A) R2 = 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw 3V 1.5 V Input LOAD CIRCUIT 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION CLR Input 3V Reference Input 3V 1.5 V 1.5 V 0V 0V trec Data Input 3V 1.5 V CLK th tsu 1.5 V 10% 90% 90% tr 0V VOLTAGE WAVEFORMS RECOVERY TIME 3V 1.5 V 10% 0 V tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 3V Input 1.5 V 1.5 V 0V tPLH In-Phase Output 50% 10% 90% 90% tr 90% 1.5 V 1.5 V 0V tPHL tPHL Out-of-Phase Output 3V Output Control VOH 50% VCC 10% VOL tf tPLH 50% VCC 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ tPZL 20% VCC tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) ≈VCC 20% VCC VOL 80% VCC VOH 80% VCC ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. I. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CD54ACT174F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54ACT174F3A CD74ACT174E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74ACT174E CD74ACT174EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74ACT174E CD74ACT174M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT174M CD74ACT174M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT174M CD74ACT174M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT174M CD74ACT174M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT174M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF CD54ACT174, CD74ACT174 : • Catalog: CD74ACT174 • Military: CD54ACT174 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74ACT174M96 Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74ACT174M96 SOIC D 16 2500 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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