LM5017 www.ti.com SNVS783D – JANUARY 2012 – REVISED MAY 2013 LM5017 100V, 600mA Constant On-Time Synchronous Buck Regulator Check for Samples: LM5017 FEATURES PACKAGES • • • • • • • • • • • • • • • • 1 2 Wide 9V to 100V Input Range Integrated 100V, High and Low Side Switches No Schottky Required Constant On-time Control No Loop Compensation Required Ultra-Fast Transient Response Nearly Constant Operating Frequency Intelligent Peak Current Limit Adjustable Output Voltage from 1.225V Precision 2% Feedback Reference Frequency Adjustable to 1MHz Adjustable Undervoltage Lockout (UVLO) Remote Shutdown Thermal Shutdown DESCRIPTION The LM5017 is a 100V, 600mA synchronous stepdown regulator with integrated high side and low side MOSFETs. The constant-on-time (COT) control scheme employed in the LM5017 requires no loop compensation, provides excellent transient response, and enables very low step-down ratios. The on-time varies inversely with the input voltage resulting in nearly constant frequency over the input voltage range. A high voltage startup regulator provides bias power for internal operation of the IC and for integrated gate drivers. A peak current limit circuit protects against overload conditions. The undervoltage lockout (UVLO) circuit allows the input undervoltage threshold and hysteresis to be independently programmed. Other protection features include thermal shutdown and bias supply undervoltage lockout (VCC UVLO). APPLICATIONS • • • • WSON-8 SO PowerPAD-8 Smart Power Meters Telecommunication Systems Automotive Electronics Isolated Bias Supply The LM5017 is available in WSON-8 and SO PowerPAD-8 plastic packages. Typical Application LM5017 CIN 2 + 4 RUV2 RON SD 3 BST VIN SW RON + 8 CBST L1 VOUT CVCC VCC UVLO FB RUV1 7 RTN 1 + 9V-100V VIN 6 RFB2 5 RC + RFB1 COUT 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated LM5017 SNVS783D – JANUARY 2012 – REVISED MAY 2013 www.ti.com Connection Diagram RTN 1 VIN 2 UVLO 3 RON 4 SO PowerPAD8 Exp Pad 8 SW 7 BST 6 VCC 5 FB Figure 1. Top View (Connect Exposed Pad to RTN) RTN 1 VIN 2 UVLO 3 RON 4 8 SW WSON-8 Exp Pad 7 BST 6 VCC 5 FB Figure 2. Top View (Connect Exposed Pad to RTN) Pin Descriptions Pin Name 1 RTN 2 VIN 3 UVLO 4 Description Application Information Ground Ground connection of the integrated circuit. Input Voltage Operating input range is 9V to 100V. Input Pin of Undervoltage Comparator Resistor divider from VIN to UVLO to GND programs the undervoltage detection threshold. An internal current source is enabled when UVLO is above 1.225V to provide hysteresis. When UVLO pin is pulled below 0.66V externally, the parts goes in shutdown mode. RON On-Time Control A resistor between this pin and VIN sets the switch ontime as a function of VIN. Minimum recommended ontime is 100ns at max input voltage. 5 FB Feedback This pin is connected to the inverting input of the internal regulation comparator. The regulation level is 1.225V. 6 VCC Output from the Internal High Voltage Series Pass Regulator. Regulated at 7.6V The internal VCC regulator provides bias supply for the gate drivers and other internal circuitry. A 1.0μF decoupling capacitor is recommended. 7 BST Bootstrap Capacitor An external capacitor is required between the BST and SW pins (0.01μF ceramic). The BST pin capacitor is charged by the VCC regulator through an internal diode when the SW pin is low. 8 SW Switching Node Power switching node. Connect to the output inductor and bootstrap capacitor. EP Exposed Pad Exposed pad must be connected to RTN pin. Connect to system ground plane on application board for reduced thermal resistance. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM5017 LM5017 www.ti.com SNVS783D – JANUARY 2012 – REVISED MAY 2013 Absolute Maximum Ratings (1) (2) VIN, UVLO to RTN -0.3V to 100V SW to RTN -1.5V to VIN +0.3V BST to VCC 100V BST to SW 13V RON to RTN -0.3V to 100V VCC to RTN -0.3V to 13V FB to RTN -0.3V to 5V ESD Rating (Human Body Model Lead Temperature (3) 2kV (4) 200°C Storage Temperature Range (1) (2) (3) (4) -55°C to +150°C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics. The RTN pin is the GND reference electrically connected to the substrate. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. For detailed information on soldering plastic SO PowerPAD package, refer to the SNOA549 available from Texas Instruments. Max solder time not to exceed 4 seconds. Operating Ratings (1) VIN Voltage 9V to 100V −40°C to +125°C Operating Junction Temperature (1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics. The RTN pin is the GND reference electrically connected to the substrate. Thermal Characteristics (1) WSON-8 SO PowerPAD-8 UNIT θJA Junction-to-ambient thermal resistance 41.3 41.1 °C/W θJCbot Junction-to-case (bottom) thermal resistance 3.2 2.4 °C/W ΨJB Junction-to-board thermal characteristic parameter 19.2 24.4 °C/W θJB Junction-to-board thermal resistance 19.1 30.6 °C/W θJCtop Junction-to-case (top) thermal resistance 34.7 37.3 °C/W ΨJT Junction-to-top thermal characteristic parameter 0.3 6.7 °C/W (1) The package thermal impedance is calculated in accordance with JESD 51. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM5017 3 LM5017 SNVS783D – JANUARY 2012 – REVISED MAY 2013 www.ti.com Electrical Characteristics Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, unless otherwise stated. See (1). Symbol Parameter Conditions Min Typ Max 6.25 7.6 8.55 Units VCC Supply VCC Reg VCC Regulator Output VIN = 48V, ICC = 20mA VCC Current Limit VIN = 48V (2) VCC Undervoltage Lockout Voltage (VCC increasing) 26 V mA 4.15 VCC Undervoltage Hysteresis 4.5 4.9 300 V mV VCC Drop Out Voltage VIN = 9V, ICC = 20mA 2.3 V IIN Operating Current Non-Switching, FB = 3V 1.75 mA IIN Shutdown Current UVLO = 0V 50 225 µA Buck Switch RDS(ON) ITEST = 200mA, BST-SW = 7V 0.8 1.8 Ω Synchronous RDS(ON) ITEST = 200mA 0.45 1 Ω Gate Drive UVLO VBST − VSW Rising 3 3.6 Switch Characteristics 2.4 Gate Drive UVLO Hysteresis 260 V mV Current Limit Current Limit Threshold 0.7 Current Limit Response Time Time to Switch Off OFF-Time Generator (Test 1) OFF-Time Generator (Test 2) 1.02 1.3 A 150 ns FB = 0.1V, VIN = 48V 12 µs FB = 1.0V, VIN = 48V 2.5 µs On-Time Generator TON Test 1 VIN = 32V, RON = 100k 270 350 460 ns TON Test 2 VIN = 48V, RON = 100k 188 250 336 ns TON Test 3 VIN = 75V, RON = 250k 250 370 500 ns TON Test 4 VIN = 10V, RON = 250k 1880 3200 4425 ns Minimum Off-Time Minimum Off-Timer FB = 0V 144 ns Regulation and Overvoltage Comparators FB Regulation Level Internal Reference Trip Point for Switch ON FB Overvoltage Threshold Trip Point for Switch OFF 1.2 1.225 FB Bias Current 1.25 V 1.62 V 60 nA Undervoltage Sensing Function UV Threshold UV Rising 1.19 1.225 1.26 V UV Hysteresis Input Current UV = 2.5V -10 -20 -29 µA Remote Shutdown Threshold Voltage at UVLO Falling 0.32 0.66 V 110 mV Thermal Shutdown Temperature 165 °C Thermal Shutdown Hysteresis 20 °C Remote Shutdown Hysteresis Thermal Shutdown Tsd (1) (2) 4 All limits are specified by design. All electrical characteristics having room temperature limits are tested during production at TA = 25°C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM5017 LM5017 www.ti.com SNVS783D – JANUARY 2012 – REVISED MAY 2013 Typical Performance Characteristics Efficiency at 200kHz, 10V VCC vs VIN Figure 3. Figure 4. VCC vs ICC ICC vs External VCC Figure 5. Figure 6. TON vs VIN and RON TOFF (ILIM) vs VFB and VIN Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM5017 5 LM5017 SNVS783D – JANUARY 2012 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) IIN vs VIN (Operating, Non Switching) IIN vs VIN (Shutdown) Figure 9. Figure 10. Switching Frequency vs VIN Figure 11. 6 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM5017 LM5017 www.ti.com SNVS783D – JANUARY 2012 – REVISED MAY 2013 Block Diagram LM5017 START-UP REGULATOR VIN VCC V UVLO 20 µA 4.5V UVLO THERMAL SHUTDOWN UVLO 1.225V SD VDD REG BST 0.66V SHUTDOWN BG REF VIN DISABLE ON/OFF TIMERS RON 1.225V SW COT CONTROL LOGIC FEEDBACK FB ILIM COMPARATOR OVER-VOLTAGE 1.62V CURRENT LIMIT ONE-SHOT RTN + VILIM Figure 12. Functional Block Diagram Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM5017 7 LM5017 SNVS783D – JANUARY 2012 – REVISED MAY 2013 www.ti.com Functional Description The LM5017 step-down switching regulator features all the functions needed to implement a low cost, efficient, buck converter capable of supplying up to 0.6A to the load. This high voltage regulator contains 100V, N-channel buck and synchronous switches, is easy to implement, and is provided in thermally enhanced SO PowerPAD-8 and WSON-8 packages. The regulator operation is based on a constant on-time control scheme using an ontime inversely proportional to VIN. This control scheme does not require loop compensation. The current limit is implemented with a forced off-time inversely proportional to VOUT. This scheme ensures short circuit protection while providing minimum foldback. The simplified block diagram of the LM5017 is shown in Figure 12, Functional Block Diagram. The LM5017 can be applied in numerous applications to efficiently regulate down higher voltages. This regulator is well suited for 48V telecom and 42V automotive power bus ranges. Protection features include: thermal shutdown, Undervoltage Lockout (UVLO), minimum forced off-time, and an intelligent current limit. Control Overview The LM5017 buck regulator employs a control principle based on a comparator and a one-shot on-timer, with the output voltage feedback (FB) compared to an internal reference (1.225V). If the FB voltage is below the reference the internal buck switch is turned on for the one-shot timer period, which is a function of the input voltage and the programming resistor (RON). Following the on-time the switch remains off until the FB voltage falls below the reference, but never before the minimum off-time forced by the minimum off-time one-shot timer. When the FB pin voltage falls below the reference and the minimum off-time one-shot period expires, the buck switch is turned on for another on-time one-shot period. This will continue until regulation is achieved and the FB voltage is approximately equal to 1.225V (typ). In a synchronous buck converter, the low side (sync) FET is ‘on’ when the high side (buck) FET is ‘off’. The inductor current ramps up when the high side switch is ‘on’ and ramps down when the high side switch is ‘off’. There is no diode emulation feature in this IC, and therefore, the inductor current may ramp in the negative direction at light load. This causes the converter to operate in continuous conduction mode (CCM) regardless of the output loading. The operating frequency remains relatively constant with load and line variations. The operating frequency can be calculated as follows: VOUT gsw = -10 10 x RON The output voltage (VOUT) is set by two external resistors (RFB1, RFB2). The regulated output voltage is calculated as follows: RFB2 + RFB1 VOUT = 1.225V x RFB1 RFB2 VOUT - 1.225V = 1.225V RFB1 This regulator regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum amount of ESR for the output capacitor (COUT). A minimum of 25mV of ripple voltage at the feedback pin (FB) is required for the LM5017. In cases where the capacitor ESR is too small, additional series resistance may be required (RC in Figure 13 Low Ripple Output Configuration). For applications where lower output voltage ripple is required the output can be taken directly from a low ESR output capacitor, as shown in Figure 13 Low Ripple Output Configuration. However, RC slightly degrades the load regulation. VCC Regulator The LM5017 contains an internal high voltage linear regulator with a nominal output of 7.6V. The input pin (VIN) can be connected directly to the line voltages up to 100V. The VCC regulator is internally current limited to 30mA. The regulator sources current into the external capacitor at VCC. This regulator supplies current to internal circuit blocks including the synchronous MOSFET driver and the logic circuits. When the voltage on the VCC pin reaches the undervoltage lockout (VCC UVLO) threshold of 4.5V, the IC is enabled. The VCC regulator contains an internal diode connection to the BST pin to replenish the charge in the gate drive boot capacitor when SW pin is low. 8 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM5017 LM5017 www.ti.com SNVS783D – JANUARY 2012 – REVISED MAY 2013 At high input voltages, the power dissipated in the high voltage regulator is significant and can limit the overall achievable output power. As an example, with the input at 48V and switching at high frequency, the VCC regulator may supply up to 7mA of current resulting in 48V x 7mA = 336mW of power dissipation. If the VCC voltage is driven externally by an alternate voltage source, between 8V and 13V, the internal regulator is disabled. This reduces the power dissipation in the IC. L1 VOUT SW LM5017 RFB2 FB RC + RFB1 COUT VOUT (low ripple) Figure 13. Low Ripple Output Configuration Regulation Comparator The feedback voltage at FB is compared to an internal 1.225V reference. In normal operation, when the output voltage is in regulation, an on-time period is initiated when the voltage at FB falls below 1.225V. The high side switch will stay on for the on-time, causing the FB voltage to rise above 1.225V. After the on-time period, the high side switch will stay off until the FB voltage again falls below 1.225V. During start-up, the FB voltage will be below 1.225V at the end of each on-time, causing the high side switch to turn on immediately after the minimum forced off-time of 144ns. The high side switch can be turned off before the on-time is over, if the peak current in the inductor reaches the current limit threshold. Overvoltage Comparator The feedback voltage at FB is compared to an internal 1.62V reference. If the voltage at FB rises above 1.62V the on-time pulse is immediately terminated. This condition can occur if the input voltage and/or the output load changes suddenly. The high side switch will not turn on again until the voltage at FB falls below 1.225V. On-Time Generator The on-time for the LM5017 is determined by the RON resistor, and is inversely proportional to the input voltage (VIN), resulting in a nearly constant frequency as VIN is varied over its range. The on-time equation for the LM5017 is: 10-10 x RON TON = VIN See figure “TON vs VIN and RON” in the section “ Performance Curves”. RON should be selected for a minimum ontime (at maximum VIN) greater than 100ns, for proper operation. This requirement limits the maximum switching frequency for high VIN. Current Limit The LM5017 contains an intelligent current limit off-timer. If the current in the buck switch exceeds 1.02A the present cycle is immediately terminated, and a non-resetable off-timer is initiated. The length of off-time is controlled by the FB voltage and the input voltage VIN. As an example, when FB = 0V and VIN = 48V, the maximum off-time is set to 16μs. This condition occurs when the output is shorted, and during the initial part of start-up. This amount of time ensures safe short circuit operation up to the maximum input voltage of 100V. In cases of overload where the FB voltage is above zero volts (not a short circuit) the current limit off-time is reduced. Reducing the off-time during less severe overloads reduces the amount of foldback, recovery time, and start-up time. The off-time is calculated from the following equation: 0.07 x VIN Ps TOFF(ILIM) = VFB + 0.2V The current limit protection feature is peak limited. The maximum average output will be less than the peak. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM5017 9 LM5017 SNVS783D – JANUARY 2012 – REVISED MAY 2013 www.ti.com N-Channel Buck Switch and Driver The LM5017 integrates an N-Channel Buck switch and associated floating high voltage gate driver. The gate driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A 0.01uF ceramic capacitor connected between the BST pin and the SW pin provides the voltage to the driver during the on-time. During each off-time, the SW pin is at approximately 0V, and the bootstrap capacitor charges from VCC through the internal diode. The minimum off-timer, set to 144ns , ensures a minimum time each cycle to recharge the bootstrap capacitor. Synchronous Rectifier The LM5017 provides an internal synchronous N-Channel MOSFET rectifier. This MOSFET provides a path for the inductor current to flow when the high-side MOSFET is turned off. The synchronous rectifier has no diode emulation mode, and is designed to keep the regulator in continuous conduction mode even during light loads which would otherwise result in discontinuous operation. Undervoltage Detector The LM5017 contains a dual level undervoltage lockout (UVLO) circuit. When the UVLO pin voltage is below 0.66V, the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.66V but less than 1.225V, the controller is in standby mode. In standby mode the VCC bias regulator is active while the regulator output is disabled. When the VCC pin exceeds the VCC undervoltage threshold and the UVLO pin voltage is greater than 1.225V, normal operation begins. An external set-point voltage divider from VIN to GND can be used to set the minimum operating voltage of the regulator. UVLO hysteresis is accomplished with an internal 20μA current source that is switched on or off into the impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to quickly raise the voltage at the UVLO pin. The hysteresis is equal to the value of this current times the resistance RUV2. UVLO Mode Description <0.66V VCC Shutdown VCC regulator disabled. Switcher disabled. 0.66V – 1.225V Standby VCC regulator enabled Switcher disabled. VCC <4.5V Standby VCC regulator enabled. Switcher disabled. VCC >4.5V Operating VCC enabled. Switcher enabled. >1.225V If the UVLO pin is wired directly to the VIN pin, the regulator will begin operation once the VCC undervoltage is satisfied. VIN CIN 2 VIN + RUV2 LM5017 3 UVLO RUV1 Figure 14. UVLO Resistor Setting 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM5017 LM5017 www.ti.com SNVS783D – JANUARY 2012 – REVISED MAY 2013 Thermal Protection The LM5017 should be operated so the junction temperature does not exceed 150°C during normal operation. An internal Thermal Shutdown circuit is provided to protect the LM5017 in the event of a higher than normal junction temperature. When activated, typically at 165°C, the controller is forced into a low power reset state, disabling the buck switch and the VCC regulator. This feature prevents catastrophic failures from accidental device overheating. When the junction temperature reduces below 145°C (typical hysteresis = 20°C), the VCC regulator is enabled, and normal operation is resumed. APPLICATION INFORMATION SELECTION OF EXTERNAL COMPONENTS Selection of external components is illustrated through a design example. The design example specifications are as follows: Buck Converter Design Specifications Input voltage range 12.5V to 95V Output voltage 10V Maximum Load current 500mA Switching Frequency 200kHz RFB1, RFB2: VOUT = VFB x (RFB2/RFB1 + 1), and since VFB = 1.225V, the ratio of RFB2 to RFB1 calculates as 7:1. Standard values of 6.98kΩ and 1.00kΩ are chosen. Other values could be used as long as the 7:1 ratio is maintained. Frequency Selection: At the minimum input voltage, the maximum switching frequency of LM5017 is restricted by the forced minimum off-time (TOFF(MIN)) as given by: 1 - DMAX 1 - 10/12.5 = = 1 MHz gSW(MAX) = 200 ns TOFF(MIN) Similarly, at maximum input voltage, the maximum switching frequency of LM5017 is restricted by the minimum TON as given by: DMIN 10/95 gSW(MAX) = = = 1.05 MHz TON(MIN) 100 ns Resistor RON sets the nominal switching frequency based on the following equations: VOUT gSW = K x RON (1) –10 where K = 1 x 10 . Operation at high switching frequency results in lower efficiency while providing the smallest solution. For this example a conservative 200kHz was selected, resulting in RON = 504kΩ. Selecting a standard value for RON = 499kΩ results in a nominal frequency of 202kHz. Inductor Selection: The minimum inductance is selected to limit the output ripple to 20 to 40 percent of the maximum load current. In addition, the peak inductor current at maximum load should be smaller than the minimum current limit as given in Electrical Characteristics table. The inductor current ripple is given by: VIN - VOUT VOUT x ûIL = VIN L1 x gSW The maximum ripple is observed at maximum input voltage. Substituting VIN = 95V and ΔIL = 40 percent x IOUT (max) results in L1 = 198.4μH. The next higher standard value of 220μH is chosen. The peak-to-peak minimum and maximum inductor current ripples of 35mA and 204mA are given at minimum and maximum input voltages respectively. The peak inductor and switch current is given by Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM5017 11 LM5017 SNVS783D – JANUARY 2012 – REVISED MAY 2013 ILI(peak) = IOUT + www.ti.com ûIL(MAX) = 602 mA 2 which is smaller than the minimum current limit. The inductor should be able to withstand the maximum current limit of 1.3A, which can be reached during startup and overload conditions. LM5017 CIN 2 + + 4 CBYP RUV2 Shutdown RON 3 BST VIN SW RON + 8 CBST L1 VOUT CVCC VCC UVLO FB RUV1 7 RTN 1 + 9V-100V VIN 6 RC RFB2 5 RFB1 + COUT Figure 15. Reference Schematic for Selection of External Components Output Capacitor: The output capacitor is selected to minimize the capacitive ripple across it. The maximum ripple is observed at maximum input voltage and is given by: ûIL COUT = 8 x gsw x ûVripple where ΔVripple is the voltage ripple across the capacitor. Substituting ΔVripple = 10mV gives COUT = 12.64μF. A 22μF standard value is selected. An X5R or X7R type capacitor with a voltage rating 16V or higher should be selected. Series Ripple Resistor RC: The series resistor should be selected to produce sufficient ripple at the feedback node. The ripple produced by RC is proportional to the inductor current ripple, and therefore RC should be chosen for minimum inductor current ripple which occurs at minimum input voltage. The RC is calculated by the equation: 25 mV VOUT x RC > ûIL(MIN) VREF This gives an RC of greater than or equal to 5.15Ω. Selecting RC = 5.23Ω results in ~1V of maximum output voltage ripple. For applications requiring lower output voltage ripple, Type II or Type III ripple injection circuits should be used as described in the section “ Ripple Configuration”. VCC and Bootstrap Capacitor: The VCC capacitor provides charge to bootstrap capacitor as well as internal circuitry and low side gate driver. The Bootstrap capacitor provides charge to high side gate driver. A good value for CVCC is 1μF. A good value for CBST is 0.01μF. Input Capacitor: Input capacitor should be large enough to limit the input voltage ripple: IOUT(MAX) CIN > 8 x gSW x ûVIN choosing a ΔVIN = 0.5V gives a minimum CIN = 1.24μF. A standard value of 2.2μF is selected. The input capacitor should be rated for the maximum input voltage under all conditions. A 100V, X7R dielectric should be selected for this design. Input capacitor should be placed directly across VIN and RTN (pin 2 and 1) of the IC. If it is not possible to place all of the input capacitor close to the IC, a 0.47μF capacitor should be placed near the IC to provide a bypass path for the high frequency component of the switching current. This helps limit the switching noise. 12 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM5017 LM5017 www.ti.com SNVS783D – JANUARY 2012 – REVISED MAY 2013 UVLO Resistors: The UVLO resistors RFB1 and RFB2 set the UVLO threshold and hysteresis according to the following relationship: VIN(HYS) = IHYS x RUV2 and VIN (UVLO,rising) = 1.225V x ( RUV2 + 1) RUV1 where IHYS = 20μA. Setting UVLO hysteresis of 2.5V and UVLO rising threshold of 12V results in RUV1 = 14.53kΩ and RUV2 = 125kΩ. Selecting standard value of RUV1 = 14kΩ and RUV2 = 125kΩ results in UVLO thresholds and hysteresis of 12.4V and 2.5V respectively. APPLICATION CIRCUIT: 12V TO 95V INPUT AND 10V, 500mA OUTPUT BUCK CONVERTER The application schematic of a buck supply is shown in Figure 16 below. For output voltage (VOUT) above the maximum regulation threshold of VCC (8.55V, see Electrical Characteristics), the VCC pin can be connected to VOUT through a diode (D2), as shown below, for higher efficiency and lower power dissipation in the IC. 12V-95V VIN (TP1) 30177733 BST 2 C4 2.2 F + C5 + R5 0.47 F 127 NŸ GND (TP2) (TP4) UVLO/SD SW (TP6) LM5017 VIN 4 SW RON R3 499 NŸ 3 7 0.01 F + C1 8 R4 46.4 NŸ UVLO VCC R7 14 NŸ FB EXP 220 H L1 RTN 1 6 0Ÿ R8 C6 C8 0.1 F 5 + (TP3) R2 0Ÿ 3300 pF D2 U1 VOUT R1 6.98 NŸ + R6 1 NŸ C7 1 F C9 22 F GND (TP5) Figure 16. Final Schematic for 12V to 95V Input, and 10V, 500mA Output Buck Converter ISOLATED DC-DC CONVERTER USING LM5017 An isolated supply using LM5017 is shown in Figure 17 below. Inductor (L) in a typical buck circuit is replaced with a coupled inductor (X1). A diode (D1) is used to rectify the voltage on a secondary output. The nominal voltage at the secondary output (VOUT2) is given by: N VOUT2 = VOUT1 x S - VF NP where VF is the forward voltage drop of D1, and NP, NS are the number of turns on the primary and secondary of coupled inductor X1. For output voltage (VOUT1) above the maximum VCC (8.55V), the VCC pin can be diode connected to VOUT1 for higher effiicency and low dissipation in the IC. See AN-2204 (SNVA611) for a complete isolated bias design with LM5017. VOUT2 D1 + NS LM5017 VIN 20V-100V BST CIN + X1 CBST SW VIN COUT2 VOUT1 Rr NP + + RON RUV2 RON Cac RFB2 VCC UVLO COUT1 Cr D2 RUV1 RTN FB + CVCC RFB1 Figure 17. Typical Isolated Application Schematic Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM5017 13 LM5017 SNVS783D – JANUARY 2012 – REVISED MAY 2013 www.ti.com RIPPLE CONFIGURATION LM5017 uses Constant-On-Time (COT) control scheme, in which the on-time is terminated by an on-timer, and the off-time is terminated by the feedback voltage (VFB) falling below the reference voltage (VREF). Therefore, for stable operation, the feedback voltage must decrease monotonically, in phase with the inductor current during the off-time. Furthermore, this change in feedback voltage (VFB) during off-time must be large enough to suppress any noise component present at the feedback node. Table 1 shows three different methods for generating appropriate voltage ripple at the feedback node. Type 1 and Type 2 ripple circuits couple the ripple at the output of the converter to the feedback node (FB). The output voltage ripple has two components: 1. Capacitive ripple caused by the inductor current ripple charging/discharging the output capacitor. 2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor. The capacitive ripple is not in phase with the inductor current. As a result, the capacitive ripple does not decrease monotonically during the off-time. The resistive ripple is in phase with the inductor current and decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at the output node (VOUT) for stable operation. If this condition is not satisfied unstable switching behavior is observed in COT converters, with multiple on-time bursts in close succession followed by a long off-time. Type 3 ripple method uses Rr and Cr and the switch node (SW) voltage to generate a triangular ramp. This triangular ramp is ac coupled using Cac to the feedback node (FB). Since this circuit does not use the output voltage ripple, it is ideally suited for applications where low output voltage ripple is required. See application note AN-1481 (SNVA166) for more details for each ripple generation method. Table 1. Type 1 Lowest Cost Configuration Type 2 Reduced Ripple Configuration VOUT Type 3 Minimum Ripple Configuration VOUT L1 VOUT L1 L1 R FB2 Cac R FB2 RC To FB C OUT COUT R FB2 GND R FB1 GND 25 mV VOUT x ûIL(MIN) VREF Cr Cac To FB R FB1 RC > Rr RC C OUT To FB R FB1 GND C> 5 gsw (RFB2||RFB1) 25 mV RC > ûIL(MIN) Cr = 3300 pF Cac = 100 nF (VIN(MIN) - VOUT) x TON RrCr < 25 mV SOFT START A soft-start feature can be implemented to the LM5017 using an external circuit. As shown in Figure 18, the softstart circuit consists of one capacitor, C1, two resistors, R1 and R2, and a diode, D. During the initial start-up, the VCC voltage is established prior to the VOUT voltage. D is thereby forward biased and the FB voltage is pulled up above the reference voltage (1.225V). The switcher is disabled. With the charging of the capacitor C1, the voltage at node B gradually decreases. Due to the action of the control circuit, VOUT will gradually rise to maintain the FB voltage at the reference voltage. Once the voltage at node B is lower than the FB voltage, plus the voltage drop of D, the soft-start is finished and D is reverse biased. During the initial part of the start-up, the FB voltage can be approximated as follows. Please note that the effect of R1 has been ignored to simplify the calculation: RFB1 x RFB2 VFB = (VCC - VD) x R2 x (RFB1 + RFB2) + RFB1 x RFB2 14 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM5017 LM5017 www.ti.com SNVS783D – JANUARY 2012 – REVISED MAY 2013 To achieve the desired soft-start, the following design guidance is recommended: (1) R2 is selected so that VFB is higher than 1.225V for a VCC of 4.5V, but is lower than 5V when VCC is 8.55V. If an external VCC is used, VFB should not exceed 5V at maximum VCC. (2) C1 is selected to achieve the desired start-up time that can be determined as follows: RFB1 x RFB2 ) tS = C1 x (R2 + RFB1 + RFB2 (3) R1 is used to maintain the node B voltage at zero after the soft-start is finished. A value larger than the feedback resistor divider is preferred. Based on the schematic shown in Figure 16, selecting C1=1uF, R2=1kΩ, R1=30kΩ results in a soft-start time of about 2ms. VCC VOUT C1 RFB2 R2 To FB D B RFB1 R1 Figure 18. Soft-Start Circuit LAYOUT RECOMMENDATION A proper layout is essential for optimum performance of the circuit. In particular, the following guidelines should be observed: 1. CIN: The loop consisting of input capacitor (CIN), VIN pin, and RTN pin carries switching currents. Therefore, the input capacitor should be placed close to the IC, directly across VIN and RTN pins and the connections to these two pins should be direct to minimize the loop area. In general it is not possible to accommodate all of input capacitance near the IC. A good practice is to use a 0.1μF or 0.47μF capacitor directly across the VIN and RTN pins close to the IC, and the remaining bulk capacitor as close as possible (Refer to Figure 19 Placement of Bypass Capacitors). 2. CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high and low side gate drivers. These two capacitors should also be placed as close to the IC as possible, and the connecting trace length and loop area should be minimized (See Figure 19 Placement of Bypass Capacitors). 3. The Feedback trace carries the output voltage information and a small ripple component that is necessary for proper operation of LM5017. Therefore, care should be taken while routing the feedback trace to avoid coupling any noise to this pin. In particular, feedback trace should not run close to magnetic components, or parallel to any other switching trace. 4. SW trace: The SW node switches rapidly between VIN and GND every cycle and is therefore a possible source of noise. The SW node area should be minimized. In particular, the SW node should not be inadvertently connected to a copper plane or pour. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM5017 15 LM5017 SNVS783D – JANUARY 2012 – REVISED MAY 2013 www.ti.com RTN 1 VIN 2 UVLO 3 RON 4 8 SW 7 BST 6 VCC 5 FB CIN SO PowerPAD8 CVCC Figure 19. Placement of Bypass Capacitors 16 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM5017 PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5017MRE/NOPB SO Power PAD DDA 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5017MRX/NOPB SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5017SD/NOPB WSON NGU 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5017SDX/NOPB WSON NGU 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5017MRE/NOPB SO PowerPAD DDA LM5017MRX/NOPB SO PowerPAD DDA 8 250 213.0 191.0 55.0 8 2500 367.0 367.0 35.0 LM5017SD/NOPB WSON LM5017SDX/NOPB WSON NGU 8 1000 203.0 190.0 41.0 NGU 8 4500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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