INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4724B MSI 8-bit addressable latch Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4724B MSI 8-bit addressable latch selected output (O0 to O7; determined by A0 to A2) follows D. When E goes HIGH, the contents of the latch are stored. When operating in the addressable latch mode (E = CL = LOW), changing more than one bit of A0 to A2 could impose a transient wrong address. Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW). DESCRIPTION The HEF4724B is an 8-bit addressable latch with three address inputs (A0 to A2), a data input (D), an active LOW enable input (E), an active HIGH clear input (CL), and eight parallel latch outputs (O0 to O7). When E and CL are HIGH, all outputs (O0 to O7) are LOW. Eight-channel demultiplexing or active HIGH 1-of-8 decoding with output enable operation occurs when CL is HIGH and E is LOW. When CL and E are LOW, the Fig.2 Pinning diagram. HEF4724BP(N): 16-lead DIL; plastic (SOT38-1) HEF4724BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4724BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING Fig.1 Functional diagram. A0 to A2 address inputs A data input E enable input (active LOW) CL clear input (active HIGH) O0 to O7 parallel latch outputs FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors 8-bit addressable latch January 1995 3 Fig.3 Logic diagram. Product specification HEF4724B MSI Fig.4 Logic diagram (one latch). Philips Semiconductors Product specification HEF4724B MSI 8-bit addressable latch MODE SELECTION E CL MODE L L addressable latch H L memory L H active HIGH 8-channel demultiplexer H H clear FUNCTION TABLE CL E D A0 A1 A2 O0 O1 O2 O3 O4 O5 O6 O7 H H X X X X L L L L L L L L H L D1 L L L D1 L L L L L L L H L D1 H L L L D1 L L L L L L H L D1 L H L L L D1 L L L L L H L D1 H H L L L L D1 L L L L H L D1 L L H L L L L D1 L L L H L D1 H L H L L L L L D1 L L H L D1 L H H L L L L L L D1 L H L D1 H H H L L L L L L L D1 MODE clear demultiplexer; unaddressed latch is cleared L H X X X X On-1 On-1 On-1 On-1 On-1 On-1 On-1 On-1 memory L L D1 L L L D1 On-1 On-1 On-1 On-1 On-1 On-1 On-1 L L D1 H L L On-1 D1 On-1 On-1 On-1 On-1 On-1 On-1 L L D1 L H L On-1 On-1 D1 On-1 On-1 L L D1 H H L On-1 On-1 On-1 D1 On-1 L L D1 L L H On-1 On-1 On-1 On-1 D1 L L D1 H L H On-1 On-1 On-1 On-1 On-1 L L D1 L H H On-1 On-1 On-1 On-1 On-1 addressable On-1 On-1 On-1 latch; On-1 On-1 On-1 unaddressed On-1 On-1 On-1 latch holds D1 On-1 On-1 previous state On-1 D1 On-1 L L D1 H H H On-1 On-1 On-1 On-1 On-1 On-1 On-1 Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial On-1 = state before the positive transition of E D1 = either HIGH or LOW January 1995 4 D1 Philips Semiconductors Product specification HEF4724B MSI 8-bit addressable latch AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns VDD V Dynamic power TYPICAL FORMULA FOR P (µW) 700 fi + ∑ (foCL) × VDD2 5 dissipation per 10 3700 fi + ∑ (foCL) × package (P) 15 10 800 fi + ∑ (foCL) × where VDD2 VDD2 fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYP. TYPICAL EXTRAPOLATION FORMULA MAX. Propagation delays E → On HIGH to LOW LOW to HIGH D → On HIGH to LOW LOW to HIGH An → On HIGH to LOW LOW to HIGH CL → On HIGH to LOW 5 230 ns 88 ns + (0,55 ns/pF) CL 50 95 ns 39 ns + (0,23 ns/pF) CL 15 35 70 ns 27 ns + (0,16 ns/pF) CL 5 95 195 ns 68 ns + (0,55 ns/pF) CL 10 tPHL 40 80 ns 29 ns + (0,23 ns/pF) CL 15 30 55 ns 22 ns + (0,16 ns/pF) CL 5 95 190 ns 68 ns + (0,55 ns/pF) CL 10 tPLH 35 75 ns 24 ns + (0,23 ns/pF) CL 15 25 55 ns 17 ns + (0,16 ns/pF) CL 5 85 170 ns 58 ns + (0,55 ns/pF) CL 35 75 ns 24 ns + (0,23 ns/pF) CL 10 10 tPHL tPLH 15 25 55 ns 17 ns + (0,16 ns/pF) CL 5 110 225 ns 83 ns + (0,55 ns/pF) CL 45 95 ns 34 ns + (0,23 ns/pF) CL 10 tPHL 15 35 70 ns 27 ns + (0,16 ns/pF) CL 5 95 190 ns 68 ns + (0,55 ns/pF) CL 40 80 ns 29 ns + (0,23 ns/pF) CL 10 tPLH 15 30 55 ns 22 ns + (0,16 ns/pF) CL 5 85 165 ns 58 ns + (0,55 ns/pF) CL 35 70 ns 24 ns + (0,23 ns/pF) CL 25 50 ns 17 ns + (0,16 ns/pF) CL 10 tPHL 15 January 1995 115 5 Philips Semiconductors Product specification HEF4724B MSI 8-bit addressable latch VDD V Set-up times D→E An → E SYMBOL MIN. 5 10 TYPICAL EXTRAPOLATION FORMULA MAX. 40 20 ns 15 5 ns 15 10 0 ns 5 40 20 ns 20 10 ns 15 15 5 ns Hold times 5 20 0 ns D→E 10 15 5 ns An → E Minimum E pulse width; LOW Minimum CL pulse width; HIGH 10 tsu TYP. tsu thold 15 15 5 ns 5 50 25 ns 20 10 ns 10 thold 15 15 5 ns 5 75 35 ns 30 15 ns 15 20 10 ns 5 70 35 ns 30 15 ns 20 10 ns 10 10 tWEL tWCLH 15 see also waveforms Fig.5 AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Output transition times HIGH to LOW LOW to HIGH 5 120 ns 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 tTHL tTLH 15 January 1995 10 ns + (1,0 ns/pF) CL 60 30 10 6 10 ns + (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL Philips Semiconductors Product specification HEF4724B MSI 8-bit addressable latch (1) The address to enable set-up time is the time before the HIGH to LOW enable transition that the address must be stable so that the correct latch is addressed and the other latches are not affected. Fig.5 Waveforms showing minimum E and CL pulse widths, set-up times, hold times. Set-up and hold times are shown as positive values but may be specified as negative values. January 1995 7