CAB4A www.ti.com SNAS630B – JULY 2013 – REVISED OCTOBER 2013 CAB4A - DDR4 Register 32-Bit 1:2 Command/Address/Control Buffer and 1:4 Differential Clock Buffer Check for Samples: CAB4A FEATURES DESCRIPTION • • • • • • • • • • • • • • • • The CAB4 is 32-bit 1:2 Command/Address/Control Buffer and 1:4 differential Clock Buffer designed for operation on DDR4 registered DIMMs with a 1.2 V VDD mode. 1 23 • DDR4RCD01 JEDEC Compliant DDR4 RDIMM and LRDIMM up to DDR4-2400 32 Bits 1-to-2 Register Outputs 1-to-4 Differential Clock Buffer 1.2V Operation PLL with Internal Feedback Configurable Driver Strength Scalable Weak Driver Programmable Latency Output Driver Calibration Address Mirroring and Inversion DDR4 Full-Parity Operation On-Chip Programmable VREF Generation CA Bus Training Mode I2C™ Interface Support Up to 16-Logical Ranks Support for 3DS RDIMMs and LRDIMMs Up to 4 Physical Ranks Support for RDIMMs and LRDIMMs All inputs are pseudo-differential using external or internal voltage reference. All outputs are full swing CMOS drivers optimized to drive 15 to 50 Ω effective terminated traces in DDR4 RDIMM, LRDIMM and 3DStacked DIMM applications. The clock outputs, command/address outputs, control outputs, data buffer control outputs can be enabled in groups, and independently driven with different strengths to compensate for different DIMM net topologies. The DDR4 Register operates from a differential clock (CK_t and CK_c). Inputs are registered at the crossing of CK_t going HIGH, and CK_c going LOW. The input signals could be either re-driven to the outputs if one of the input signals DCS[n:0]_n is driven LOW or it could be used to access device internal control registers when certain input conditions are met. The device is characterized in the temperature range from -40°C to 95°C. PLL Data Clock Command Address Clock MEMORY MODULE DRAM CAB4A operating Data MEMORY CONTROLLER (MCH) CPU / DSP / Ethernet MCU DDR4 ² Memory Subsystem Figure 1. DDR4 - RDIMM Memory Subsystem 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners. 2 2 3 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated CAB4A SNAS630B – JULY 2013 – REVISED OCTOBER 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM QVREFCA VrefCA Vref Generation and Control Vref for Input Receivers BVREFCA DA17, DRAS_n/A16, DCAS_n/A15, DWE_n/A14, DA[13:0], DBA[1:0], DBG[1:0], DACT_n DPAR QxRAS_n/QxA16, QxCAS_n/QxA15, QxWE_n/QxA14, QAA[13:0], QABA[1:0] QABG[1:0], QxACT_n QBA12, QBA10,QAA17 QBA[2:0], QAPAR CW Table D Q R CE Control Word State Machine and Control Logic Parity Logic DA17,DRAS_n/A16, DCAS_n/A15, DWE_n/A14 DA[13:0], DBA[1:0], DBG[1:0], DACT_n,DPAR Output-Enable Y0..Y3, BCKEnable ALERT_n 4 DCS[1:0]_n, DCS2_n/DC0, DCS3_n/DC1, DC2 D Q R QACS[1:0]_n, QACS2_n/C0, QACS3_n/C1, QAC2 QBCS[1:0]_n, QBCS2_n/C0, QBCS3_n/C1, QBC2 QRST_n CS Logic and Decoder DCKE0, DCKE1 QBA17, QBA13, QBA11, QBA[9,3], QBBG[1:0], QBBA[1;0] QBPAR (cond.) ERROR_IN_n QACKE[1:0] D Q R DODT0, DODT1 QBCKE[1:0] QAODT[1:0] D Q R QBODT[1:0] DRST_n Y0_t Y0_c Y1_t Y1_c CK_t CK_c Y2_t 10k:100k: Y2_c PLL Y3_t Y3_c VDDSPD SCL SDA SA[2:0] 2 I C BCK_t Feedback BFUNC BCK_c 120k: ZQCal ZQCal BCOM[3:0] DQB Interface Command Decoder BCKE BODT 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CAB4A x CAB4A www.ti.com SNAS630B – JULY 2013 – REVISED OCTOBER 2013 Table 1. TERMINAL FUNCTIONS SIGNAL GROUP TYPE NAME DCKE0/1 DODT0/1 DRAM corresponding register function pins not associated with Chip Select. DCS0_n..DCS1_ n Input Control bus DCS2_n..DCS3_ n or DC0..DC1 DRAM corresponding register Chip Select signals. CMOS (1) VREF based DRAM corresponding register Chip Select signals. These pins initiate DRAM address/command decodes, and as such exactly one will be LOW when a valid address/command is present which should be re-driven. Some of these have alternative functions: • • DC2 DCS2_n ↔ DC0 DCS3_n ↔ DC1 DRAM corresponding register Chip ID 2 signal. DRAM corresponding register inputs. In case of an ACT command some of these terminals have an alternative function: DRAM corresponding register command signals DA0..DA13, DA17 DBA0..DBA1, DBG0..DBG1 CMOS (1) VREF based Input Address and Command bus DESCRIPTION • • • DA14 ↔ DWE_n DA15 ↔ DCAS_n DA16 ↔ DRAS_n DA14..DA16 or DWE_n, DCAS_n, DRAS_n DACT_n DRAM corresponding register DACT_n signal. Differential master clock input pair to the PLL with a 10 kΩ ~ 100 kΩ pull-down resistor. Clock inputs CK_t, CK_c CMOS differential Reset input DRST_n CMOS input Active LOW asynchronous reset input. When LOW, it causes a reset of the internal latches and disables the outputs, thereby forcing the outputs to float. Parity input DPAR CMOS (2) VREF based Input parity is received on pin DPAR and should maintain even parity across the address and command inputs (see above), at the rising edge of the input clock. Error Input ERROR_IN_n CMOS input DRAM address parity and CRC Alert is connected to this input pin, which in turn is buffered and re-driven to the ALERT_n output of the register. Requires external pull-up resistor. (3) BODT BCKE Data buffer control and communication outputs (1) (2) (3) Data buffer on-die termination signal. CMOS (3) Data buffer clock enable signal for PLL power management. Register communication bus for data buffer programming and control access. BCOM[3:0] BCK_t, BCK_c CMOS differential BVREFCA VDD/2Reference Voltage Differential clock output pair to the data buffer Output reference voltage for data buffer control bus receivers. These receivers use VREFCA as the switching point reference. These receivers use VREFCA as the switching point reference. CMOS: These outputs with rail to rail signal swing and programmable impedance are optimized for memory applications to drive DRAM inputs over a terminated transmission line. Error_In_n: Internal Pull-up resistor can be turned on. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CAB4A 3 CAB4A SNAS630B – JULY 2013 – REVISED OCTOBER 2013 www.ti.com Table 1. TERMINAL FUNCTIONS (continued) SIGNAL GROUP NAME TYPE QACKE0/1, QAODT0/1, QBCKE0/1, QBODT0/1 Register output CKE and ODT signals. QACS0_n..QACS 1_n, QBCS0_n..QBCS 1_n Register output Chip Select signals. Output Control Bus Register output Chip Select signals. These pins initiate DRAM address/command decodes, and as such exactly one will be LOW when a valid address/command is present which should be re-driven. Some of these have alternative functions (Chip ID): QACS2_n..QACS 3_n, QBCS2_n..QBCS 3_n or QAC0..QAC1, QBC0..QBC1 • • QAC2, QBC2 QAA0..QAA13, QAA17, QBA0..QBA13, QBA17, QABA0..QABA1, QBBA0..QBBA1, QAG0..QAG1, QBG0..QBG1 Output Address and Command bus DESCRIPTION QxCS2_n ↔ QxC0 QxCS2_n ↔ QxC0 Register output Chip ID2 signals. CMOS Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock. QAA14..QAA16, QBA14..QBA16 or QAWE_n, QACAS_n, QARAS_n, QBWE_n, QBCAS_n, QBRAS_n Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock. In case of an ACT command some of these terminals have an alternative function: QAACT-n, QBACT_n Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock. • • • Vref output QVREFCA VDD/2 Reference voltage Clock outputs Y0_t..Y3_t, Y0_c..Y3_c CMOS differential Reset output QRST_n Parity outputs QAPAR, QBPAR CMOS QxA14 ↔ QxWE_n QxA15 ↔ QxCAS_n QxA16 ↔ QxRAS_n Output reference voltage for DRAM receivers Re-driven clocks Re-driven reset. This is not an asynchronous output. Re-driven parity (4) Error out ALERT_n Open drain When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs when parity checking is enabled or that the ERROR_IN_n input was asserted, regardless of whether parity checking is enabled or not. I2C pins SDA SCL SA[2:0] BFUNC VDDSPD Open drain I/O CMOS input CMOS input CMOS input Power input I2C Data I2C Clock I2C Address signals Reserved (5) I2C power input (4) (5) 4 I2C inputs: These inputs are 2.5V inputs, except BFUNC which is a 1.2V input. BFUNC has an internal pull-down resistor of 120 kΩ to V. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CAB4A CAB4A www.ti.com SNAS630B – JULY 2013 – REVISED OCTOBER 2013 Table 1. TERMINAL FUNCTIONS (continued) SIGNAL GROUP Miscellaneous pins NAME TYPE DESCRIPTION VREFCA VCC/2Reference voltage VDD Power input Power supply voltage VSS Ground input Ground AVDD Analog power Analog supply voltage PVDD Clock power Clock logic and clock output driver power supply. PVSS Clock ground Clock logic and clock output driver ground. ZQCAL Reference NU Mechanical ball RFU[3:0] I/O Input reference voltage for the CMOS inputs. Needs a calibration resistor of 240Ω ±1% to VSS. Do not connect on PCB. Reserved; must be left floating on DIMM and in DDR4 register. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CAB4A 5 CAB4A SNAS630B – JULY 2013 – REVISED OCTOBER 2013 www.ti.com REVISION HISTORY Change document to production data. 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CAB4A PACKAGE OPTION ADDENDUM www.ti.com 19-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) CAB4AZNRR ACTIVE Package Type Package Pins Package Drawing Qty NFBGA ZNR 253 2000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR Op Temp (°C) Device Marking (4/5) -40 to 95 CAB4A6 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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